Semiconductor device and method for manufacturing a semiconductor device
By forming p-type layers with hydrogen-containing materials and exposing them during annealing, and using hydrogen-free n-type layer formation, the method addresses the low activation rate issue, achieving efficient hydrogen removal and improved semiconductor device performance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- TOYODA GOSEI CO LTD
- Filing Date
- 2024-11-20
- Publication Date
- 2026-06-01
AI Technical Summary
Existing methods for forming p-type group III nitride semiconductors face challenges in achieving high activation rates of p-type impurities due to hydrogen bonding, especially when an n-type layer is stacked on top, as the surface of the p-type layer is covered, inhibiting hydrogen emission.
A method involving the formation of a p-type layer using hydrogen-containing materials and carrier gases, followed by an annealing treatment with the p-type layer's operation region exposed, and forming n-type layers without hydrogen in the raw materials or carrier gases, ensuring efficient hydrogen removal and suppression of re-contamination.
This approach enhances the activation rate of p-type impurities by effectively removing hydrogen and preventing re-contamination, even when an n-type layer is formed on top, resulting in improved semiconductor device performance.
Smart Images
Figure 2026089519000001_ABST
Abstract
Description
[Technical Field]
[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]
[0002] It is widely known that magnesium (Mg) is used as the p-type impurity in group III nitride semiconductors. However, simply forming a Mg-doped group III nitride semiconductor does not result in a p-type semiconductor, as the Mg atoms bond with hydrogen atoms, inhibiting the activation of Mg. Therefore, after forming the Mg-doped group III nitride semiconductor, an annealing treatment is performed to separate the Mg-H bond and remove hydrogen from the semiconductor layer, thereby achieving p-type formation.
[0003] In this p-type conversion method, it is difficult to convert the p-type layer to p-type when an n-type layer is stacked on top of a p-type layer. This is because the surface of the p-type layer is covered by the n-type layer, which inhibits the emission of hydrogen from the p-type semiconductor layer.
[0004] Patent Document 1 describes forming a first n-type layer, a p-type layer, and a second n-type layer in that order, then forming a trench to expose the p-type layer on the side of the trench, and then performing an annealing treatment to discharge hydrogen from the p-type layer exposed on the side of the trench. [Prior art documents] [Patent Documents]
[0005] [Patent Document 1] Japanese Patent Publication No. 2003-68745 [Overview of the Initiative] [Problems that the invention aims to solve]
[0006] However, in the method described in Patent Document 1, the area of the p-type layer exposed on the side of the trench is small, resulting in low hydrogen emission. Consequently, the activation of Mg becomes insufficient.
[0007] This invention was made in view of the above background, and aims to provide a semiconductor device with a high activation rate of p-type impurities and a method for manufacturing the same. [Means for solving the problem]
[0008] One aspect of the present invention is, A p-type layer formation step involves forming a p-type layer made of a group III nitride semiconductor doped with p-type impurities using a formation method that utilizes materials containing hydrogen as both raw material and carrier gas. An annealing step in which at least a region of the surface of the p-type layer that contributes to the operation of the device is exposed, and an annealing treatment is performed to activate the p-type impurities in the p-type layer, The present invention relates to a method for manufacturing a semiconductor device, comprising: an n-type layer formation step, in which an n-type layer made of an n-type group III nitride semiconductor is formed on the aforementioned p-type layer by a formation method using materials that do not contain hydrogen as raw materials or carrier gas.
[0009] Other aspects of the present invention include: A first n-type layer made of an n-type group III nitride semiconductor, A p-type layer formed on the first n-type layer, which is made of a p-type group III nitride semiconductor, The p-type layer is formed on the p-type layer and comprises a second n-type layer made of an n-type group III nitride semiconductor, The semiconductor device is characterized in that the H concentration of the p-type layer is 10% or less of the p-type impurity concentration. [Effects of the Invention]
[0010] In the above embodiment, the annealing treatment is performed with at least the region of the p-type layer surface that contributes to the device operation exposed, allowing for efficient removal of hydrogen from the p-type layer. Furthermore, since the n-type layer is formed using a formation method that does not contain hydrogen in the raw materials and carrier gas, it is possible to suppress the contamination of the p-type layer with hydrogen and the subsequent deactivation of the p-type impurities. Therefore, even when an n-type layer is formed on top of a p-type layer, the activation rate of the p-type impurities in the p-type layer can be improved.
[0011] According to the above aspect, a semiconductor device with a high activation rate of p-type impurities and a method for manufacturing the same can be provided.
Brief Description of the Drawings
[0012] [Figure 1] It is a cross-sectional view showing the structure of the semiconductor device in the first embodiment, which is a cross-sectional view perpendicular to the main surface of the substrate. [Figure 2] It is a flowchart showing the manufacturing method of the semiconductor device in the first embodiment. [Figure 3] It is a cross-sectional view showing the structure of the semiconductor device in the first embodiment at each stage of the manufacturing process, which is a cross-sectional view perpendicular to the main surface of the substrate. [Figure 4] It is a cross-sectional view showing the structure of the semiconductor device in the first embodiment at each stage of the manufacturing process, which is a cross-sectional view perpendicular to the main surface of the substrate. [Figure 5] It is a cross-sectional view showing the structure of the semiconductor device in the first embodiment at each stage of the manufacturing process, which is a cross-sectional view perpendicular to the main surface of the substrate. [Figure 6] It is a cross-sectional view showing the structure of the semiconductor device in the first embodiment at each stage of the manufacturing process, which is a cross-sectional view perpendicular to the main surface of the substrate. [Figure 7] A graph showing the distribution of impurity concentration in the depth direction.
Embodiments for Carrying Out the Invention
[0013] The method for manufacturing a semiconductor device includes a p-type layer formation step of forming a p-type layer made of a group III nitride semiconductor doped with p-type impurities by a formation method using a material containing hydrogen in the raw material and the carrier gas, an annealing treatment step of performing an annealing treatment in a state where at least a region contributing to device operation on the surface of the p-type layer is exposed to activate the p-type impurities in the p-type layer, and an n-type layer formation step of forming an n-type layer made of an n-type group III nitride semiconductor on the p-type layer by a formation method using a material not containing hydrogen in the raw material and the carrier gas.
[0014] In the above-described method for manufacturing semiconductor devices, the formation method using materials that do not contain hydrogen in the raw materials and carrier gas may be sputtering or MBE.
[0015] In the above-described method for manufacturing a semiconductor device, the semiconductor device is a MOSFET with a trench gate structure having a body electrode on a portion of a p-type layer, and the annealing process may be carried out with at least the region near the trench side and the body electrode formation region of the surface of the p-type layer exposed.
[0016] In the above semiconductor device manufacturing method, the annealing process may be carried out with more than 90% of the surface of the p-type layer exposed. This allows for more efficient removal of hydrogen from the p-type layer.
[0017] In the above semiconductor device manufacturing method, the annealing process may be carried out with the entire surface of the p-type layer exposed. This allows for more efficient removal of hydrogen from the p-type layer.
[0018] In the above-described method for manufacturing semiconductor devices, the annealing treatment may be performed at a heat treatment temperature of 700°C or higher and 900°C or lower, with a heat treatment time of 5 to 60 minutes.
[0019] In the above semiconductor device manufacturing method, the annealing atmosphere may be a mixed gas atmosphere of nitrogen and oxygen. In this case, the ratio of the oxygen flow rate to the nitrogen flow rate may be 1% or more. This can further improve the activation rate of p-type impurities.
[0020] In the above method for manufacturing semiconductor devices, the p-type impurity may be Mg.
[0021] The semiconductor device comprises a first n-type layer made of an n-type group III nitride semiconductor, a p-type layer formed on the first n-type layer and made of a p-type group III nitride semiconductor, and a second n-type layer formed on the p-type layer and made of an n-type group III nitride semiconductor, wherein the H concentration of the p-type layer is 10% or less of the p-type impurity concentration.
[0022] In the above semiconductor device, the p-type impurity concentration of the p-type layer is 1×10 18 / cm 3 or more and 1×10 20 / cm 3 or less may be used.
[0023] (First Embodiment) 1. Structure of Semiconductor Device FIG. 1 is a diagram showing the structure of a semiconductor device according to the first embodiment. The semiconductor device of the first embodiment is a vertical MOSFET having a trench gate structure. As shown in FIG. 1, it includes a substrate 10, a first n-type layer 11, a p-type layer 12, a second n-type layer 13, a gate insulating film 14, a gate electrode 15, a source electrode 16, a drain electrode 17, and a body electrode 18.
[0024] The substrate 10 is made of Si-doped n + -GaN with the c-plane as the main surface. The Si concentration of the substrate 10 is 1×10 18 / cm 3 or more. The material of the substrate 10 may be other than GaN, and any material can be used as long as it is a material capable of growing a group III nitride semiconductor and has conductivity. For example, Si, SiC, ZnO, etc. can be used.
[0025] The first n-type layer 11 is provided on the substrate 10. The first n-type layer 11 is made of Si-doped n - -GaN. The thickness of the first n-type layer 11 is 8 to 15 μm. Also, the Si concentration of the first n-type layer 11 is 1×10 15 to 5×10 16 / cm 3 . For the n-type impurity, O, Ge, etc. may be used instead of or in addition to Si.
[0026] The p-type layer 12 is provided on the first n-type layer 11. The p-type layer 12 is made of Mg-doped p-GaN. The thickness of the p-type layer 12 is 0.1 to 1 μm. Also, the Mg concentration of the p-type layer 12 is 1×10 18 to 8×10 20 / cm 3Therefore, for the p-type impurity, Zn or other materials may be used instead of or in addition to Mg. The H concentration in the p-type layer 12 is 10% or less of the Mg concentration. As a result, the Mg activation rate in the p-type layer 12 is high, and the p-type layer 12 is sufficiently p-type. More preferably, the H concentration in the p-type layer 12 is 5% or less of the Mg concentration, and even more preferably 2% or less.
[0027] Preferably, the Si concentration at the interface between the first n-type layer 11 and the p-type layer 12 is 10 times or less the Si concentration (average in the thickness direction) of the first n-type layer 11. This can suppress the deterioration of semiconductor device characteristics and the reduction of characteristic stability caused by Si at the interface between the first n-type layer 11 and the p-type layer 12. More preferably, the Si concentration at the interface between the first n-type layer 11 and the p-type layer 12 is 5 times or less the Si concentration of the first n-type layer 11.
[0028] The second n-type layer 13 is provided on the p-type layer 12. The second n-type layer 13 is Si-doped n + -It consists of GaN. The thickness of the second n-type layer 13 is 0.1 to 0.5 μm. The Si concentration of the second n-type layer 13 is 1 × 10⁻¹⁶. 18 ~1 × 10 19 / cm 3 That is the case.
[0029] A trench 20 is provided in a portion of the surface of the second n-type layer 13. The trench 20 has a depth that penetrates the second n-type layer 13 and the p-type layer 12 and reaches the first n-type layer 11. The first n-type layer 11 is exposed at the bottom of the trench 20. On the side of the trench 20, the first n-type layer 11, the p-type layer 12, and the second n-type layer 13 are exposed in order from the bottom side.
[0030] A recess 21 is provided in a portion of the second n-type layer 13 that is different from the trench 20 formation region. The recess 21 is a groove that penetrates the second n-type layer 13 and reaches the p-type layer 12.
[0031] The gate insulating film 14 is continuously provided across the bottom, sides, and top surface (the surface of the second n-type layer 13 and the region near the trench 20) of the trench 20. The gate insulating film 14 is made of, for example, SiO2.
[0032] The gate electrode 15 is provided across the bottom, side, and top surfaces of the trench 20 via a gate insulating film 14. The gate electrode 15 is made of, for example, TiN.
[0033] The body electrode 18 is continuously provided across the bottom, side, and top surfaces (the surface of the second n-type layer 13 and the region near the recess 21) of the recess 21. The body electrode 18 is made of, for example, Ni.
[0034] The source electrode 16 is provided on the second n-type layer 13 and the body electrode 18. The source electrode 16 is made of, for example, Pd / Al / Ti.
[0035] The drain electrode 17 is provided on the back surface of the substrate 10. The drain electrode 17 is made of, for example, Pd / Al / Ti.
[0036] 2. Method for manufacturing semiconductor devices Next, the method for manufacturing the semiconductor device in the first embodiment will be described with reference to Figures 2 to 6. Figure 2 is a flowchart showing the manufacturing process of the semiconductor device in the first embodiment. Figures 3 to 6 are cross-sectional views showing the structure of the semiconductor device in the first embodiment at each stage of the manufacturing process, and are cross-sectional views perpendicular to the main surface of the substrate.
[0037] First, a first n-type layer 11 and a p-type layer 12 are formed on the substrate 10 in this order from the substrate 10 side by MOCVD (see step S1 in Figure 2 and Figure 3). TMGa (trimethylgallium) is used as the Ga source gas, and ammonia is used as the N source gas. A mixed gas of hydrogen and nitrogen is used as the carrier gas. Silane is used as the n-type dopant gas, and biscyclopentadienylmagnesium is used as the p-type dopant gas.
[0038] Here, the first n-type layer 11 and the p-type layer 12 are grown in series using the same MOCVD method. The reason for this is as follows: If the first n-type layer 11 and the p-type layer 12 are not grown in series, the first n-type layer 11 may be exposed to the atmosphere. When the first n-type layer 11 is exposed to the atmosphere, a large amount of Si adheres to its surface. This causes a Si layer to form at the interface between the first n-type layer 11 and the p-type layer 12, leading to degradation of the semiconductor device's properties and a decrease in its stability. Therefore, by growing the first n-type layer 11 and the p-type layer 12 in series, the first n-type layer 11 is prevented from being exposed to the atmosphere.
[0039] The reason for forming the first n-type layer 11 and the p-type layer 12 by MOCVD rather than sputtering is that the first n-type layer 11 needs to be made thicker to improve the device's breakdown voltage, and MOCVD is superior to sputtering in terms of growth rate and mass production capabilities. Other formation methods using raw materials and carrier gases containing hydrogen may also be used. For example, the HVPE method.
[0040] Next, an annealing treatment is performed (step S2). This annealing treatment breaks the Mg (magnesium) and H (hydrogen) bonds in the p-type layer 12, and H is discharged from the p-type layer 12. Here, since the annealing treatment is performed before the formation of the second n-type layer 13, the entire surface of the p-type layer 12 is exposed. Therefore, the exposed area of the p-type layer 12 is large, and H can be efficiently discharged from the p-type layer 12.
[0041] The heat treatment temperature for annealing is preferably 700 to 900°C, and the heat treatment time is preferably 5 to 60 minutes. The higher the heat treatment temperature and the longer the heat treatment time, the greater the effect of H emission from the p-type layer 12. On the other hand, if the heat treatment temperature is too high or the heat treatment time is too long, thermal decomposition of GaN occurs, causing deterioration of the crystal quality of the p-type layer 12 and an increase in surface roughness. By setting the heat treatment temperature and heat treatment time for annealing within the above range, the balance between these advantages and disadvantages can be optimized. In other words, the crystallinity of the p-type layer 12 can be maintained while sufficiently improving the Mg activation rate.
[0042] The annealing atmosphere is preferably at atmospheric pressure. Specifically, it is preferably 0.9 to 1.1 atm. Within this range, H can be effectively discharged from the p-type layer 12.
[0043] Furthermore, the annealing atmosphere can be a mixed gas atmosphere of nitrogen and oxygen. Adding oxygen to nitrogen can improve the Mg activation rate. The ratio of oxygen flow rate to nitrogen flow rate is preferably 1% or more, more preferably 2% or more, and even more preferably 5% or more. The reason why adding oxygen to nitrogen improves the Mg activation rate is thought to be that hydrogen and oxygen react readily, so when oxygen is mixed in, it reacts with hydrogen, increasing the effect of hydrogen emission from the p-type layer 12. There is no upper limit to the ratio of oxygen flow rate to nitrogen flow rate, but the effect of improving the Mg activation rate saturates when it exceeds 5%.
[0044] Next, a second n-type layer 13 is formed on the p-type layer 12 by sputtering (step S3, see Figure 4). For example, the second n-type layer 13 is formed by magnetron sputtering with a GaN sintered body as the target. Alternatively, the second n-type layer 13 may be formed by RF sputtering or other methods.
[0045] Since the formation method for the second n-type layer 13 is sputtering, no materials containing H are used in the raw materials or carrier gas. Therefore, H does not enter the p-type layer 12 during the formation of the second n-type layer 13, thereby preventing the Mg in the p-type layer 12 from being deactivated again.
[0046] Furthermore, the second n-type layer 13 may be formed by a method other than sputtering, as long as the source gas and carrier gas do not contain H. For example, the second n-type layer 13 may be formed by molecular beam epitaxy (MBE).
[0047] Next, a predetermined region of the second n-type layer 13 is dry-etched until it reaches the first n-type layer 11 to form a trench 20. Then, a predetermined region of the second n-type layer 13 is dry-etched until it reaches the p-type layer 12 to form a recess 21 (step S4, see Figure 5). Alternatively, the recess 21 may be formed first, followed by the trench 20.
[0048] Here, since the annealing process for p-type formation is performed before the formation of the trench 20, the p-type layer 12 exposed on the side surface of the trench 20 is not roughened by the annealing process. The p-type layer 12 on the side surface of the trench 20 is a channel region, and roughness would cause degradation of the MOSFET characteristics. However, according to the first embodiment, no roughness occurs in the p-type layer 12 on the side surface of the trench 20, and therefore no degradation of the MOSFET characteristics occurs.
[0049] Next, the gate insulating film 14 is formed continuously across the bottom, sides, and top of the trench 20 by the ALD method (step S5, see Figure 6).
[0050] Next, gate electrodes 15 are formed on the bottom, side, and top surfaces of the trench 20 via the gate insulating film 14 by vapor deposition or sputtering. Then, body electrodes 18 are formed continuously on the bottom, side, and top surfaces of the recess 21, and source electrodes 16 are formed on the second n-type layer 13 and the body electrodes 18. Next, drain electrodes 17 are formed on the back surface of the substrate 10. The body electrodes 18, source electrodes 16, and drain electrodes 17 are deposited by vapor deposition or sputtering and patterned by lift-off. The semiconductor device of the first embodiment is manufactured by the above method.
[0051] As described above, according to the semiconductor device manufacturing method of the first embodiment, even in a structure in which a second n-type layer 13 is provided on a p-type layer 12, the activation rate of p-type impurities in the p-type layer 12 can be increased.
[0052] 3. Experimental Results Next, we will explain the experimental results regarding the semiconductor device in the first embodiment. Three types of samples, Example 1, Comparative Examples 1 and 2, were prepared as follows.
[0053] The sample for Example 1 was prepared as follows. First, a first n-type layer 11 made of n-GaN and a p-type layer 12 made of p-GaN were formed on the substrate 10 by MOCVD, in that order from the substrate 10 side. Then, an annealing treatment was performed. Next, a second n-type layer 13 made of n-GaN was formed by sputtering. The sample for Example 1 was prepared in the manner described above.
[0054] The sample for Comparative Example 1 was prepared as follows. First, a first n-type layer made of n-GaN, a p-type layer 12 made of p-GaN, and a second n-type layer 13 made of n-GaN were formed on the substrate 10 in this order from the substrate 10 side by MOCVD. Next, a trench 20 was formed on the surface of the second n-type layer 13. The trench 20 was made to a depth that reached the first n-type layer 11. Next, an annealing treatment was performed. The annealing conditions were the same as in Example 1. The sample for Comparative Example 1 was prepared in the manner described above.
[0055] The sample for Comparative Example 2 was prepared as follows. First, a first n-type layer 11 made of n-GaN and a p-type layer 12 made of p-GaN were formed on the substrate 10 in that order from the substrate 10 side by MOCVD. Next, an annealing treatment was performed. The annealing conditions were the same as in Example 1. Next, a second n-type layer 13 made of n-GaN was formed by MOCVD. The sample for Comparative Example 2 was prepared in the manner described above.
[0056] For each sample in Example 1, Comparative Examples 1 and 2, the Mg concentration and H concentration of the p-type layer 12 were measured. Table 1 summarizes the Mg concentration, H concentration, and N / Mg ratio of the p-type layer 12 for the samples in Example 1, Comparative Examples 1 and 2. The H / Mg ratio is the ratio of the H concentration to the Mg concentration.
[0057] [Table 1]
[0058] As shown in Table 1, in Example 1, the H / Mg ratio was 1.4%, indicating that a large amount of H was discharged from the p-type layer 12. This is thought to be because the annealing treatment was performed after the formation of the p-type layer 12 but before the formation of the second n-type layer 13, resulting in a large exposure of the surface of the p-type layer 12, and because the second n-type layer 13 was formed by sputtering, preventing H from re-entering the p-type layer 12.
[0059] On the other hand, in Comparative Example 1, the H / Mg ratio was 78.4%, indicating that not much H was being discharged from the p-type layer 12. This is thought to be because the area of the p-type layer 12 exposed on the side of the trench 20 was small.
[0060] Furthermore, in Comparative Example 2, the H / Mg ratio was 27.0%, indicating that more H was discharged from the p-type layer 12 than in Comparative Example 1, but less H was discharged than in Example 1. This is thought to be because the second n-type layer 13 was formed by the MOCVD method, causing H to re-enter the p-type layer 12.
[0061] Furthermore, the distribution of impurity concentrations in the depth direction was measured for the sample of Example 1. The measured impurities were Mg, H, and Si. As shown in Figure 7, the Mg and H concentrations in the p-type layer 12 were approximately uniform in the thickness direction, and the H concentration was about two orders of magnitude lower than the Mg concentration. Therefore, it was confirmed that H in the p-type layer 12 was efficiently discharged. In addition, the average Si concentration (average in the thickness direction) of the first n-type layer 11 was approximately 1 × 10⁻⁶. 16 / cm 3 In contrast, the Si concentration near the interface between the first n-type layer 11 and the p-type layer 12 is approximately 2 × 10⁻⁶. 16 / cm 3 Therefore, no increase in Si concentration was observed near the interface between the first n-type layer 11 and the p-type layer 12. In other words, because the first n-type layer 11 and the p-type layer 12 were grown in succession, it was confirmed that the surface of the first n-type layer 11 was not contaminated with Si.
[0062] (Modified form of the first embodiment) The semiconductor device in the first embodiment was a trench-gate MOSFET, but the present invention can be applied to any semiconductor device as long as it has a structure having an n-type layer or an undoped layer on a p-type layer. For example, the present invention can be applied to bipolar transistors, IGBTs, and the like.
[0063] Furthermore, while each semiconductor layer in the semiconductor device of the first embodiment is GaN, the present invention is not limited to GaN and can be applied to any group III nitride semiconductor.
[0064] Furthermore, in the semiconductor device manufacturing method of the first embodiment, the entire surface of the p-type layer 12 is exposed during the annealing process, but areas of the p-type layer 12 surface other than those contributing to the device operation may be covered with an insulating film or the like. Specifically, in the case of the semiconductor device of the first embodiment, the areas contributing to the device operation are the areas near the side surface of the trench 20 and the area below the body electrode 18. For example, the areas where the trench 20 is formed in a later process, and the areas at the outer edge of the device, do not need to have the surface of the p-type layer 12 exposed. Preferably, 90% or more of the surface of the p-type layer 12 is exposed, and most preferably, the entire surface of the p-type layer 12 is exposed. [Explanation of Symbols]
[0065] 10: Circuit board 11: 1st n-type layer 12:p-type layer 13: 2nd n-type layer 14: Gate Insulator 15: Gate Shutdown 16: Source electrode 17: Drain electrode 18: Body electrode 20: Trench 21: Recess
Claims
1. A p-type layer formation step involves forming a p-type layer made of a group III nitride semiconductor doped with p-type impurities using a formation method that utilizes materials containing hydrogen as both raw material and carrier gas. An annealing process is performed in which at least a region of the surface of the p-type layer that contributes to the operation of the element is exposed, thereby activating the p-type impurities in the p-type layer. A method for manufacturing a semiconductor device, comprising: an n-type layer formation step of forming an n-type layer made of an n-type group III nitride semiconductor on the p-type layer by a formation method using materials that do not contain hydrogen as raw materials or carrier gas.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the formation method using materials that do not contain hydrogen in the raw materials and carrier gas is sputtering.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the formation method using materials that do not contain hydrogen in the raw materials and carrier gas is the MBE method.
4. The semiconductor device is a trench gate MOSFET having a body electrode on a portion of the p-type layer, The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the annealing process is carried out with at least the region of the surface of the p-type layer near the trench side and the region where the body electrode is formed exposed.
5. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the annealing process is carried out with 90% or more of the surface of the p-type layer exposed.
6. The method for manufacturing a semiconductor device according to claim 5, wherein the annealing process is performed with the entire surface of the p-type layer exposed.
7. A method for manufacturing a semiconductor element according to any one of claims 1 to 3, wherein the annealing treatment is performed at a heat treatment temperature of 700°C or higher and 900°C or lower, and for a heat treatment time of 5 to 60 minutes.
8. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the annealing treatment is performed using a mixed gas atmosphere of nitrogen and oxygen.
9. A method for manufacturing a semiconductor device according to claim 8, wherein the ratio of oxygen flow rate to nitrogen flow rate is 1% or more.
10. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the p-type impurity is Mg.
11. A first n-type layer made of an n-type group III nitride semiconductor, A p-type layer formed on the first n-type layer, which is made of a p-type group III nitride semiconductor, The p-type layer is formed on the p-type layer and comprises a second n-type layer made of an n-type group III nitride semiconductor, A semiconductor device in which the H concentration of the p-type layer is 10% or less of the p-type impurity concentration.
12. The p-type impurity concentration in the aforementioned p-type layer is 1 × 10⁻⁶ １８ / cm ３ The above 1 x 10 ２０ / cm ３ The semiconductor device according to claim 11, which is as follows: