Semiconductor system and method of testing the same

Abstract

A semiconductor system and a testing method thereof, the semiconductor system comprising an electronic device having a processor and a memory device. The memory device includes an input pad for receiving input signals, an output pad for outputting a first output signal in a first test mode and a second output signal in a second test mode, and a memory interface coupled to the electronic device. The memory interface includes a transceiver and a mode selection circuit. The transceiver communicates with the electronic device. The mode selection circuit selects either a first test mode or a second test mode. The first test mode includes load from the transceiver and the electronic device in the memory interface. The second test mode excludes load from the transceiver and the electronic device in the memory interface.

Description

Technical Field

[0001] This invention relates to the testing of semiconductor systems, and more particularly to a semiconductor system and its testing method that can effectively test the semiconductor system without affecting its normal operation. Background Technology

[0002] Semiconductor systems can have multiple chips interconnected via multiple embedded pins, such as system-on-a-chip (SoC) devices and memory devices. With the diversification of product specifications and varying customer requirements, the transmission and reception between memory devices and SoC devices has become increasingly complex. Monitoring the interface of embedded pins becomes extremely difficult under various conditions, including high-speed operation, high / low voltage operation, different interface power levels, small pin capacitance requirements, a large number of input / output (IOs), and stringent DC or AC parameters. To test interfaces with multiple embedded pins in a semiconductor system, design-for-testing (DfT) circuitry can be directly connected to the memory interface in the memory device. However, DfT circuitry can negatively impact the operation of the semiconductor system, especially during high-speed and / or low-power operation. Specifically, connecting DfT circuitry to the interface of a memory device can introduce additional loads that may affect pin capacitance (Pin-Cap) and the operation of the memory device interface, potentially creating leakage paths between the memory device and the SoC device, and even increasing chip size.

[0003] Alternatively, package ballouts or direct probing methods can be used to test the interfaces of multiple embedded pins in a semiconductor system. However, package ballouts may affect the normal operation of the memory device due to additional load, while direct probing methods may distort the test results. In summary, whether using traditional DfT circuits, package ballouts, or direct probing methods, all can potentially affect chip performance and cost in mass-produced products.

[0004] Therefore, there is an urgent need for a novel semiconductor system testing technology that can effectively test semiconductor systems and their embedded pin interfaces. Summary of the Invention

[0005] In some embodiments disclosed herein, the semiconductor system includes an electronic device and a memory device. The electronic device includes a processor. The memory device includes an input pad for receiving input signals and an output pad for outputting a first output signal in a first test mode and a second output signal in a second test mode. The memory device also includes a memory interface coupled to the electronic device and including a transceiver and mode selection circuitry. The transceiver communicates with the electronic device, and the mode selection circuitry selects either the first test mode or the second test mode. The first test mode includes a load from the transceiver and the electronic device in the memory interface, and the second test mode excludes the load.

[0006] This disclosure describes a testing method for a semiconductor system, wherein the semiconductor system includes a memory device and an electronic device having a processor. The memory device is coupled to the electronic device via a memory interface. The testing method includes the following steps: operating the memory device in a first test mode via a mode selection circuit of the memory interface, causing an input signal to flow through a transceiver of the memory interface and generate a first output signal; operating the memory device in a second test mode via the mode selection circuit, causing the input signal to bypass the transceiver of the memory interface to generate a second output signal; and comparing the first output signal and the second output signal to generate a test result. The first test mode includes a load from the transceiver in the memory interface and the electronic device, while the second test mode excludes the load.

[0007] Based on the above embodiments, this disclosure introduces a testing technique for semiconductor systems, wherein the semiconductor system includes an electronic device with a processor and a memory device connected via multiple embedded pins. The testing technique proposed in this disclosure uses a mode selection circuit and a transceiver built into the memory device for testing. The semiconductor system can be operated sequentially in a first test mode and a second test mode to generate a first output signal and a second output signal. The first output signal generated in the first test mode can be compared with the second output signal generated in the second test mode to generate a test result. In this way, this disclosure can check whether any degradation occurs in the signal as it passes through the transceiver and pin interface between the electronic device and the memory device. Since the transmitter and receiver built into the memory interface of the memory device are already included in the memory device, no additional load caused by DfT circuits, external package leads, or direct point testing methods is introduced when testing the semiconductor system. Therefore, the test results are more accurate, and the power consumption and cost required for testing are reduced. Furthermore, since no additional load is introduced, the semiconductor system and its testing method disclosed in this disclosure do not affect its normal mode operation. The test results derived from this disclosure can also be used to adjust the operation of other circuits in a semiconductor system and / or set the parameters of other circuits, thereby improving the stability of normal mode.

[0008] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0009] Figure 1 A schematic diagram of a semiconductor system according to an embodiment of the present invention is shown;

[0010] Figure 2A The test path of an embodiment of the present invention in the first test mode is shown;

[0011] Figure 2B The test path of an embodiment of the present invention in the second test mode is shown;

[0012] Figure 3 A schematic diagram of a semiconductor system according to another embodiment of the present invention is shown;

[0013] Figure 4A This illustrates a test path in the first test mode according to another embodiment of the present invention;

[0014] Figure 4B This illustrates a test path in a second test mode according to another embodiment of the present invention;

[0015] Figure 5 This is a flowchart illustrating a test method for a semiconductor system based on some embodiments.

[0016] Explanation of icon numbers

[0017] 100, 300: Semiconductor systems;

[0018] 110: System-on-a-Chip (SoC) device;

[0019] 111: Transmitter;

[0020] 113: Receiver;

[0021] 120, 320: Memory devices;

[0022] 121: Memory interface;

[0023] 1211: Transmitter;

[0024] 1213: Receiver;

[0025] 123: Memory test interface;

[0026] 1231: Receiving circuit;

[0027] 1233: Transmission circuit;

[0028] 130: Testing equipment;

[0029] 140: Microbumps;

[0030] 325: Signal generator;

[0031] 327: Signal comparator;

[0032] IN: Input signal;

[0033] N1~N4: Nodes;

[0034] OUT: Output signal;

[0035] OUT1: First output signal;

[0036] OUT2: Second output signal;

[0037] OUT3: Third output signal;

[0038] OUT4: Fourth output signal;

[0039] PAD1: Input pad;

[0040] PAD2: Output pad;

[0041] PATH1~PATH4: Test paths;

[0042] RE_TEST: Test results;

[0043] S501~S504: Square;

[0044] SW1: First switch;

[0045] SW2: Second switch;

[0046] Vtest: Test voltage. Detailed Implementation

[0047] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same component reference numerals are used in the drawings and description to denote the same or similar parts.

[0048] like Figure 1As shown, a semiconductor system 100 according to an embodiment of the present invention includes an electronic device (e.g., a SoC device) 110, a memory device 120, and a test device 130. The SoC device 110, as an example of an electronic device including a processor, may also be referred to as an external device. The test device 130 may be automated test equipment (ATE). Each of the SoC device 110 and the memory device 120 may be packaged as a chip, and the SoC device 110 may be connected to the memory device 120 via micro-bumps (μBumps) 140 or multiple embedded pins. In some embodiments, the memory device 120 may include multiple core dies stacked together using through-silicon via (TSV) technology.

[0049] The SoC device 110 may include a transmitter 111 and a receiver 113, and the SoC device 110 may be connected to the memory device 120 via microbumps 140. The transmitter 111 in the SoC device 110 may transmit multiple signals or data to the memory device 120, and the receiver 113 in the SoC device 110 may receive multiple signals or data from the memory device 120. During test operations of the semiconductor system 100, a test voltage Vtest may be provided to the transmitter 111 and receiver 113 in the SoC device 110. In the normal mode (or user operation mode) of the SoC device 110, a supply voltage that is the same as or different from the test voltage Vtest may be provided to the transmitter 111 and receiver 113 in the SoC device 110. This disclosure does not limit the circuit structure of the transmitter 111 and receiver 113.

[0050] The memory device 120 may include an input pad PAD1, an output pad PAD2, a memory interface 121, and a memory test interface 123. The input pad PAD1 is connected to the test device 130 to receive an input signal IN from the test device 130, and the output pad PAD2 is connected to the test device 130 to output an output signal OUT to the test device 130. The input signal IN and the output signal OUT may be multiple frequency signals.

[0051] The memory interface 121 may include a transceiver and a mode selection circuit. The transceiver may include a transmitter 1211 and a receiver 1213, and the mode selection circuit may include a first switch SW1 and a second switch SW2. The transceiver is used to send or receive data or multiple signals to the SoC device 110 via connection node N3 and microbump 140. For example, transmitter 1211 may transmit data and multiple signals to the SoC device 110 via connection node N3 and microbump 140, and receiver 1213 may receive data and multiple signals from the SoC device 110 via connection node N3 and microbump 140. In the test mode of the memory device 120, a test voltage Vtest may be provided to transmitter 1211 and receiver 1213. In the normal mode of the memory device 120, a supply voltage that is the same as or different from the test voltage Vtest may be provided to transmitter 1211 and receiver 1213 in the memory interface 121.

[0052] The first switch SW1 in the mode selection circuit can be connected between connection node N1 and transmitter 1211 of memory interface 121, and is used to control the electrical connection between connection node N1 and transmitter 1211. The second switch SW2 in the mode selection circuit can be connected between connection node N1 and connection node N2 in memory interface 121, and is used to control the electrical connection between connection node N1 and connection node N2. Connection node N2 is connected to receiver 1213 of memory interface 121.

[0053] The first switch SW1 and the second switch SW2 are used to set the test mode of the semiconductor system 100. For example, when the first switch SW1 is turned on and the second switch SW2 is turned off, the semiconductor system 100 operates in a first test mode. When the first switch SW1 is turned off and the second switch SW2 is turned on, the semiconductor system 100 operates in a second test mode. In some embodiments, the first switch SW1 and the second switch SW2 are controlled by a plurality of control signals (not shown) provided by the memory device 120 or the test device 130.

[0054] The memory test interface 123 includes a receiving circuit 1231 and a transmitting circuit 1233 connected between the memory interface 121 and the test device 130. The receiving circuit 1231 of the memory test interface 123 can receive data or multiple signals from the test device 130 via input pad PAD1, and output data or multiple signals to connection node N1 of the memory interface 121. The transmitting circuit 1233 can receive data or multiple signals from the memory interface 121 via connection node N2, and output data or multiple signals to the test device 130 via output pad PAD2.

[0055] According to some embodiments, Figure 2AThe test path PATH1 of the semiconductor system 100 is shown in the first test mode. The semiconductor system 100 operates in the first test mode when the first switch SW1 is turned on and the second switch SW2 is turned off. Specifically, turning on the first switch SW1 electrically connects the connection node N1 to the transmitter 1211 of the memory interface 121. Turning off the second switch SW2 electrically disconnects the connection node N1 from the connection node N2. In the first test mode, the test path PATH1 is formed, including the input pad PAD1, the receiving circuit 1231, the connection node N1, the first switch SW1, the transmitter 1211, the connection node N3, the receiver 1213, the connection node N2, the transmission circuit 1233, and the output pad PAD2. The test path PATH1 can represent the sum of the loads of the receiving circuit 1231 and the transmission circuit 1233 of the memory test interface 123, the transmitter 1211 and the receiver 1213 in the memory interface 121, and the SoC device 110. When the input signal IN is provided to the input pad PAD1 of the memory device 120 through the test device 130, the input signal IN flows through the test path PATH1 to generate a first output signal OUT1 on the output pad PAD2 of the memory device 120. In this embodiment, the first output signal OUT1 can be provided to the test device 130.

[0056] According to some embodiments, Figure 2B The test path PATH2 of the semiconductor system 100 is shown in the second test mode. The semiconductor system 100 operates in the second test mode when the first switch SW1 is turned off and the second switch SW2 is turned on. Specifically, turning off the first switch SW1 electrically disconnects the connection node N1 from the transmitter 1211 of the memory interface 121. Turning on the second switch SW2 electrically connects the connection node N1 to the connection node N2. In the second test mode, a test path PATH2 is formed, including the input pad PAD1, the receiving circuit 1231, the connection node N1, the connection node N2, the transmission circuit 1233, and the output pad PAD2. The test path PATH2 may represent the load of the receiving circuit 1231 and the transmission circuit 1233 of the memory test interface 123, and excludes the load of the transmitter 1211, the receiver 1213, and the SoC device 110 of the memory interface 121. When the input signal IN is provided to the input pad PAD1 of the memory device 120 through the test device 130, the input signal IN flows through the test path PATH2 to generate a second output signal OUT2 on the output pad PAD2 of the memory device 120. In this embodiment, the second output signal OUT2 can be provided to the test device 130.

[0057] In some embodiments, the semiconductor system 100 may be operated sequentially in a first test mode and a second test mode to sequentially generate a first output signal OUT1 and a second output signal OUT2. For example, the semiconductor system 100 is first operated in the first test mode by turning on the first switch SW1 of the mode selection circuit and turning off the second switch SW2. Then, the semiconductor system 100 is operated in the second test mode by turning off the first switch SW1 of the mode selection circuit and turning on the second switch SW2. In some embodiments, the input signal IN, the first output signal OUT1, and the second output signal OUT2 are multiple frequency signals.

[0058] The testing device 130 can receive and compare a first output signal OUT1 and a second output signal OUT2 to generate a test result RS_TEST. In some embodiments, the testing device 130 can compare the data valid window (DVW) of the first output signal OUT1 and the DVW of the second output signal OUT2 to generate the test result RS_TEST. For example, the testing device 130 can measure and compare multiple DVWs of the first output signal OUT1 and the second output signal OUT2 to generate the test result RS_TEST. The first output signal OUT1 may include the sum of the loads of the SoC device 110, the transmitter 1211 and receiver 1213 of the memory interface 121, and the receiving circuit 1231 and transmission circuit 1233 of the memory test interface 123. In contrast, the second output signal OUT2 excludes the loads of the SoC device 110, the transmitter 1211 and receiver 1213 of the memory interface 121. By comparing the first output signal OUT1 and the second output signal OUT2, the test device 130 can determine whether there is any degradation in the multiple transmitters, multiple receivers, and multiple interfaces between the SoC device 110 and the memory device 120. In this way, the transmitters, receivers, and mode selection circuits built into the memory interface 121 of the memory device 120 can be used to monitor the performance of the semiconductor system 100. In other words, the semiconductor system 100 and its test method disclosed herein eliminate the need for DfT circuitry and improve upon problems caused by methods such as external package lead-out or direct point testing.

[0059] In addition, the test result RS_TEST can also be used to set parameters or operating conditions for other circuits and / or devices in the semiconductor system 100. For example, the test result RS_TEST can be used to adjust the driver strength of the transmitter 1211 and receiver 1213 in the memory device 120. The test result RS_TEST can also be used to adjust the internal fall frequency and rise frequency of the receiver 1213 in the memory device 120.

[0060] like Figure 3As shown, the semiconductor system 300 of this embodiment includes a SoC device 110 and a memory device 320. Figure 1 Unlike the semiconductor system 100 shown, the memory device 320 includes a signal generator 325 and a signal comparator 327, and does not require the installation of such... Figure 1 The memory test interface 123 and test device 130 are shown.

[0061] exist Figure 3 In this configuration, signal generator 325 is connected to input pad PAD1 and configured to generate and provide an input signal IN to input pad PAD1. In other words, the input signal IN is generated by the internal signal generator 325 of the memory device 320, rather than being provided by an external test device. Signal generator 325 may be a frequency generator configured to generate a frequency signal as the input signal IN. Signal comparator 327 is connected to output pad PAD2 to receive multiple output signals OUT. Signal comparator 327 is configured to compare the multiple output signals OUT acquired in different test modes to generate a test result RS_TEST. Signal comparator 327 may output the test result RS_TEST to other circuitry in the semiconductor system 300. For example, signal comparator 327 may provide the test result RS_TEST to a transmitter (e.g., transmitter 1211) of the memory device 320 to adjust the transmitter's operation or parameters.

[0062] Figure 4A The test path PATH3 is shown for the semiconductor system 300 operating in a first test mode. When the first switch SW1 is turned on and the second switch SW2 is turned off, the semiconductor system 300 operates in the first test mode, forming a test path PATH3 that includes input pad PAD1, connection node N1, the first switch SW1, transmitter 1211, connection node N3, receiver 1213, connection node N2, and output pad PAD2. Test path PATH3 can represent the sum of the loads of transmitter 1211 and receiver 1213 of memory interface 121 and SoC device 110. When the input signal IN from signal generator 325 is provided to memory interface 121, the input signal IN flows through test path PATH3 to generate a third output signal OUT3. The third output signal OUT3 is provided to signal comparator 327.

[0063] Figure 4BThe test path PATH4 of the semiconductor system 300 operating in the second test mode is shown. When the first switch SW1 is turned off and the second switch SW2 is turned on, the semiconductor system 300 operates in the second test mode, forming the test path PATH4, which includes input pad PAD1, connection node N1, connection node N2, and output pad PAD2. The test path PATH4 represents the load of the electrical path from input pad PAD1 to output pad PAD2, excluding the loads of the transmitter 1211, receiver 1213 of the memory interface 121, and SoC device 110. When the input signal IN from the signal generator 325 is provided to the input pad PAD1, the input signal IN flows through the test path PATH4 to generate a fourth output signal OUT4. The fourth output signal OUT4 is provided to the signal comparator 327.

[0064] In some embodiments, the semiconductor system 300 can be operated sequentially in a first test mode and a second test mode to sequentially generate a third output signal OUT3 and a fourth output signal OUT4. For example, the semiconductor system 300 is first operated in the first test mode by turning on the first switch SW1 of the mode selection circuit and turning off the second switch SW2. Then, the semiconductor system 300 is operated in the second test mode by turning off the first switch SW1 of the mode selection circuit and turning on the second switch SW2. In some embodiments, the input signal IN, the third output signal OUT3, and the fourth output signal OUT4 are multiple frequency signals.

[0065] Signal comparator 327 can receive and compare the third output signal OUT3 and the fourth output signal OUT4 to generate a test result RS_TEST. In some embodiments, signal comparator 327 can compare the data valid window (DVW) of the third output signal OUT3 and the DVW of the fourth output signal OUT4 to generate the test result RS_TEST. For example, signal comparator 327 can measure and compare multiple DVWs of the third output signal OUT3 and the fourth output signal OUT4 to generate the test result RS_TEST. The third output signal OUT3 may include the sum of the loads of the transmitter 1211 and receiver 1213 of the SoC device 110 and the memory interface 121. In contrast, the second output signal OUT2 excludes the sum of the loads of the transmitter 1211 and receiver 1213 of the SoC device 110 and the memory interface 121. By comparing the third output signal OUT3 and the fourth output signal OUT4, signal comparator 327 can determine whether there is any degradation in the multiple transmitters, multiple receivers, and multiple interfaces between the SoC device 110 and the memory device 320. In this way, the transmitter, receiver, and mode selection circuitry built into the memory interface 121 of the memory device 320 can be used to monitor the performance of the semiconductor system 300. In other words, the semiconductor system 300 and its test method disclosed herein can eliminate the need for DfT circuitry and can improve problems caused by methods such as external package lead-out or direct point testing.

[0066] Figure 5 This is a flowchart illustrating a semiconductor system testing method according to some embodiments. In step S501, an input signal is received through a memory device, wherein the memory device includes a memory interface coupled to an electronic device. In step S502, the memory device is operated in a first test mode by a mode selection circuit of the memory interface, causing the input signal to flow through the transceiver of the memory interface and generate a first output signal. In step S503, the memory device is operated in a second test mode by a mode selection circuit, causing the input signal to bypass the transceiver of the memory interface to generate a second output signal. In step S504, the first output signal and the second output signal are compared to generate a test result. The first test mode includes the load from the transceiver of the memory interface and the electronic device (e.g., a SoC device), while the second test mode excludes this load.

[0067] According to the above embodiments, this disclosure can test a semiconductor system using a transceiver built into the memory device and a mode selection circuit. The testing method includes using the mode selection circuit to operate the semiconductor system in a first test mode and a second test mode at different time points to generate a first output signal and a second output signal, respectively. The first output signal generated in the first test mode can be compared with the second output signal generated in the second test mode to generate a test result. Compared to the prior art which requires additional DfT circuitry for semiconductor system testing, this disclosure uses a transceiver built into the memory interface of the memory device and establishes a bypass path around the transceiver in the second test mode through the mode selection circuit, thus reducing the impact of system load and contributing to miniaturization. Furthermore, according to this disclosure, the power consumption and cost required for testing can be reduced, with almost no impact on the normal mode of the semiconductor system. Moreover, since this disclosure provides more accurate test results, when adjusting the operation of other circuits in the semiconductor system and / or setting the parameters of other circuits based on the test results provided by this disclosure, the performance in normal mode can be improved.

[0068] Thus, this disclosure provides a green technology that can reduce the power consumption of semiconductor systems. Furthermore, according to some embodiments of this disclosure, miniaturization of semiconductor systems is more easily achieved. Therefore, the production cost and energy consumption of manufacturing a single IC can be reduced, and the energy consumption of subsequent packaging production can also be reduced, thereby reducing carbon emissions during the semiconductor system manufacturing process.

[0069] The memory device of the semiconductor system disclosed herein can be DRAM, non-volatile memory, or a combination thereof. Furthermore, this invention is particularly advantageous for 3D IC applications, such as High Bandwidth Memory (HBM) and other types of stacked memory products. By employing a transceiver built into the memory interface for testing, without the additional load caused by DfT circuitry or point testing methods, this invention significantly reduces power consumption and manufacturing costs. This results in a more efficient and concise semiconductor system, which is crucial for meeting the growing demand for high-performance and energy-efficient 3D IC solutions.

[0070] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor system, characterized by, include: Electronic devices, including processors; and Memory device, comprising: Input pad, used to receive input signals; Output pads are used to output a first output signal in a first test mode and a second output signal in a second test mode; and A memory interface coupled to the electronic device, wherein the memory interface includes: A transceiver for communicating with the electronic device; and A mode selection circuit is used to select either a first test mode or a second test mode, wherein the first test mode includes a load from the transceiver and the electronic device in the memory interface, and the second test mode excludes the load.

2. The semiconductor system of claim 1, wherein, Also includes: A testing apparatus, coupled to the memory device and configured to compare the first output signal and the second output signal to generate a test result.

3. The semiconductor system of claim 1, wherein, The mode selection circuit includes: A first switch is connected between the first connection node and the transmitter in the memory interface; and A second switch is connected between the first connection node and the second connection node, wherein the second connection node is connected to the receiver in the memory interface.

4. The semiconductor system of claim 3, wherein, In the first test mode, the first switch is turned on and the second switch is turned off, and in the second test mode, the first switch is turned off and the second switch is turned on.

5. The semiconductor system of claim 3, wherein, Also includes: A memory test interface is connected between the memory interface and the test device, wherein the memory test interface includes: A receiving circuit is connected between the input pad in the memory device and the first connection node; as well as A transmission circuit is connected between the second connection node and the output pad in the memory device.

6. The semiconductor system according to claim 1, characterized in that, The input signal, the first output signal, and the second output signal are multiple frequency signals.

7. The semiconductor system according to claim 2, characterized in that, The testing device is used to compare the data valid window of the first output signal and the data valid window of the second output signal to generate the test result.

8. The semiconductor system according to claim 2, characterized in that, The electronic device is a system-on-a-chip device, and the testing device is an automated testing equipment.

9. The semiconductor system according to claim 1, characterized in that, The memory device further includes: A signal comparator is used to compare the first output signal and the second output signal to generate a test result.

10. The semiconductor system according to claim 9, characterized in that, The memory device further includes: A signal generator is connected to the input pad in the memory device and configured to generate the input signal and provide the input signal to the input pad in the memory device.

11. The semiconductor system according to claim 9, characterized in that, The signal comparator is used to compare the data valid window of the first output signal and the data valid window of the second output signal to generate the test result.

12. The semiconductor system according to claim 9, characterized in that, The input signal, the first output signal, and the second output signal are multiple frequency signals, and the electronic device is a system-on-a-chip device.

13. A testing method for a semiconductor system, characterized in that, The semiconductor system includes a memory device and an electronic device having a processor, the memory device being coupled to the electronic device via a memory interface, and the test method including: The memory device is operated in a first test mode by the mode selection circuit of the memory interface, and the input signal flows through the transceiver of the memory interface to generate a first output signal. The mode selection circuit operates the memory device in a second test mode, causing the input signal to bypass the transceiver of the memory interface to generate a second output signal; and The first output signal and the second output signal are compared to generate a test result. The first test mode includes loads from the transceiver and the electronic device in the memory interface, while the second test mode excludes the loads.

14. The test method according to claim 13, characterized in that, In the first test mode, the first switch in the mode selection circuit is turned on, and the second switch in the mode selection circuit is turned off. In the second test mode, the first switch in the mode selection circuit is turned off, and the second switch in the mode selection circuit is turned on.

15. The test method according to claim 13, characterized in that, Also includes: The input signal is provided by the test device and is provided to the input pad of the memory device.

16. The test method according to claim 13, characterized in that, Also includes: The input signal is generated by the signal generator of the memory device.

17. The test method according to claim 13, characterized in that, The step of comparing the first output signal and the second output signal to generate the test result includes: The test result is generated by comparing the data valid window of the first output signal and the data valid window of the second output signal.

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