Continuous time linear equalizer and electronic device

Abstract

This invention provides a continuous-time linear equalizer and electronic device, belonging to the field of semiconductor device technology. It dynamically adjusts the inductance characteristics of a first and second active inductor circuit by outputting a bias voltage through a bias circuit. Combined with adjustable resistance and capacitance circuits connected between the differential input branches, during differential signal processing, the adjustable resistance and capacitance circuits change the impedance between the branches to set compensation benchmarks for low-frequency and high-frequency gains, respectively. Meanwhile, the bias circuit further reshapes the AC frequency response curve of the output differential voltage by altering the inductive load characteristics of the active inductor circuit. This multi-dimensional impedance and load joint adjustment mechanism enables the system to compensate for device parameter changes caused by process, voltage, and temperature drift in real time, effectively resisting interference from immature processes and ensuring the stability and accuracy of high-frequency gain compensation under different environmental conditions.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and more particularly to a continuous-time linear equalizer and electronic device. Background Technology

[0002] Continuous-Time Linear Equalizers (CTLEs) are widely used in signal transmission systems such as high-speed serial interfaces. During high-speed signal transmission, due to the skin effect and dielectric loss of the transmission line, the attenuation of high-frequency components is often much greater than that of low-frequency components. This frequency-dependent loss causes signal pulses to spread and overlap, resulting in inter-symbol interference (ISI), leading to eye diagram closure at the receiver and a significant increase in the system's bit error rate.

[0003] To address the aforementioned issues, a CTLE circuit is typically introduced at the receiver. A CTLE is essentially an analog high-pass filter (or a filter with peaking characteristics). Its main function is to compensate for high-frequency losses caused by the channel by providing higher gain to the high-frequency components of the signal than to the low-frequency components, thereby flattening the frequency response of the entire transmission link, reducing inter-symbol interference, and reopening the eye diagram of the received signal.

[0004] The CTLE in the relevant technical solution adopts a source degradation structure. Its core adjustment mechanism determines the gain compensation range by setting the values ​​of the source degradation resistor and degradation capacitor. The equalization principle of this structure is to attenuate low-frequency signals while enhancing high-frequency signals. Since its frequency response characteristics are opposite to the channel characteristics, cascading the two can expand the system bandwidth.

[0005] However, the robustness of the aforementioned CTLE structure is poor, and it is highly susceptible to changes in process-voltage-temperature (PVT), which makes it impossible for CTLE to provide stable and compliant high-frequency gain compensation in all scenarios, seriously affecting the stability of high-speed signal transmission. Summary of the Invention

[0006] This invention provides a continuous-time linear equalizer and electronic device to address the shortcomings of existing CTLE structures, which have poor robustness and are highly susceptible to changes in process-voltage-temperature (PVT), making it impossible for CTLEs to provide stable and compliant high-frequency gain compensation in all scenarios. This invention enables CTLEs to provide stable and compliant high-frequency gain compensation in all scenarios, thereby improving the stability of high-speed signal transmission.

[0007] This invention provides a continuous-time linear equalizer, comprising the following modules.

[0008] First active inductor circuit; Second active inductor circuit; A bias circuit is connected to the first active inductor circuit and the second active inductor circuit respectively, and is used to output a bias voltage to adjust the inductance characteristics of the first active inductor circuit and the second active inductor circuit. Adjustable resistance circuit; Adjustable capacitance circuit; The differential input circuit includes a first differential input branch and a second differential input branch. The first differential input branch is connected to a first active inductor circuit, and the second differential input branch is connected to a second active inductor circuit. An adjustable resistance circuit and an adjustable capacitance circuit are respectively connected between the first differential input branch and the second differential input branch. The differential input circuit is used to receive differential signals and output differential voltages corresponding to the differential signals based on the first active inductor circuit, the second active inductor circuit, the adjustable resistance circuit, and the adjustable capacitance circuit.

[0009] According to a continuous-time linear equalizer provided by the present invention, the differential input circuit further includes a current source circuit; The first differential input branch includes: The first switching transistor has a first terminal connected to the first connection terminal of the first active inductor circuit, and a second terminal connected to the current source circuit. The second switch has a first terminal connected to the second connection terminal of the first active inductor circuit, a second terminal connected to the current source circuit, and a control terminal connected to the control terminal of the first switch. The second differential input branch includes: The third switch is connected to the first connection terminal of the second active inductor circuit, and the second terminal of the third switch is connected to the current source circuit. The fourth switch has a first terminal connected to the second connection terminal of the second active inductor circuit, a second terminal connected to the current source circuit, and a control terminal connected to the control terminal of the third switch. The adjustable resistance circuit and the adjustable capacitance circuit are respectively connected between the second terminal of the second switch and the second terminal of the fourth switch.

[0010] According to a continuous-time linear equalizer provided by the present invention, the current source circuit includes: A first current source, the first end of which is connected to the second end of the first switching transistor and the second end of the third switching transistor respectively, and the second end of the first current source is grounded; A second current source, the first end of which is connected to the second end of the second switching transistor, and the second end of which is grounded; A third current source, wherein the first terminal of the third current source is connected to the second terminal of the fourth switching transistor, and the second terminal of the third current source is grounded; The control terminals of the first current source, the second current source, and the third current source are connected together.

[0011] According to a continuous-time linear equalizer provided by the present invention, the first active inductor circuit includes: The first main control switch transistor, the first end of the first main control switch transistor is connected to the first power supply; A first resistor, the first end of which is connected to the second end of the first main control switch and the first end of the first switch, and the second end of the first resistor is connected to the first end of the second switch. A first capacitance adjustment circuit, wherein the control connection terminal of the first capacitance adjustment circuit is connected to the bias circuit, the first output terminal of the first capacitance adjustment circuit is connected to the control terminal of the first main control switch, and the second output terminal of the first capacitance adjustment circuit is connected to the first terminal of the first switch. The first capacitance adjustment circuit adjusts the output voltage of the first output terminal and the second output terminal of the first capacitance adjustment circuit according to the bias voltage output by the bias circuit.

[0012] According to a continuous-time linear equalizer provided by the present invention, the bias voltage includes a first bias sub-voltage and a second bias sub-voltage; The first capacitance adjustment circuit includes: The first slave switch transistor, the first terminal of which is connected to the first power supply; The second slave switch has its first terminal connected to the second terminal of the first slave switch and the control terminal of the first master switch, respectively. The second terminal of the second slave switch is grounded, and the control terminal of the second slave switch is used to receive the second bias sub-voltage. The third slave switch has a first terminal connected to the control terminal of the first slave switch, and a second terminal connected to the first terminal of the first switch. The control terminal of the third slave switch is used to receive the first bias voltage.

[0013] According to a continuous-time linear equalizer provided by the present invention, the second active inductor circuit includes: The second main control switch transistor, the first end of which is connected to the first power supply; The second resistor has its first end connected to the second end of the second main control switch and the first end of the third switch, and its second end is connected to the first end of the fourth switch. The second capacitance adjustment circuit has its control connection terminal connected to the bias circuit, its first output terminal connected to the control terminal of the second main control switch, and its second output terminal connected to the first terminal of the third switch. The second capacitance adjustment circuit adjusts the output voltage of the first output terminal and the second output terminal of the second capacitance adjustment circuit according to the bias voltage output by the bias circuit.

[0014] According to a continuous-time linear equalizer provided by the present invention, the bias voltage includes a first bias sub-voltage and a second bias sub-voltage; The second capacitance adjustment circuit includes: The fourth slave switch transistor, wherein the first terminal of the fourth slave switch transistor is connected to the first power supply; The fifth slave switch has its first terminal connected to the second terminal of the fourth slave switch and the control terminal of the second master switch, respectively. The second terminal of the fifth slave switch is grounded, and the control terminal of the fifth slave switch is used to receive the second bias sub-voltage. The sixth slave switch is connected to the control terminal of the fourth slave switch, and the second terminal of the sixth slave switch is connected to the first terminal of the third switch. The control terminal of the sixth slave switch is used to receive the first bias sub-voltage.

[0015] According to the present invention, a continuous-time linear equalizer is provided, wherein the adjustable resistance circuit includes: Multiple resistors are connected to a branch, the first end of each resistor connected to the branch is connected to the second end of the second switch, and the second end of each resistor connected to the branch is connected to the second end of the fourth switch. Each of the resistor access branches includes a degradation resistor, a first access switch, and a second access switch. The first terminal of the first access switch is connected to the second terminal of the second switch. The first terminal of the degradation resistor is connected to the second terminal of the first access switch. The first terminal of the second access switch is connected to the second terminal of the degradation resistor. The second terminal of the second access switch is connected to the second terminal of the fourth switch. The control terminal of the first access switch is connected to the control terminal of the second access switch. The first access switch and the second access switch are synchronously turned on or off according to the received resistance value control voltage, so as to control the degradation resistor to switch between the second terminal of the second switch and the second terminal of the fourth switch.

[0016] According to a continuous-time linear equalizer provided by the present invention, the adjustable capacitance circuit includes: Multiple capacitors are connected to a branch, the first end of each capacitor connected to the branch is connected to the second end of the second switch, and the second end of each capacitor connected to the branch is connected to the second end of the fourth switch. Each of the capacitor access branches includes a degraded capacitor, a third access switch, and a fourth access switch. The first terminal of the third access switch is connected to the second terminal of the second switch transistor. The first terminal of the degraded capacitor is connected to the second terminal of the third access switch. The first terminal of the fourth access switch is connected to the second terminal of the degraded capacitor. The second terminal of the fourth access switch is connected to the second terminal of the fourth switch transistor. The control terminal of the third access switch is connected to the control terminal of the fourth access switch. The third access switch and the fourth access switch are synchronously turned on or off according to the received capacitance control voltage, so as to control the degraded capacitor to switch between the second terminal of the second switch and the second terminal of the fourth switch.

[0017] According to a continuous-time linear equalizer provided by the present invention, the continuous-time linear equalizer further includes: A negative capacitance load circuit, wherein the first terminal of the negative capacitance load circuit is connected to the first terminal of the second switching transistor, the second terminal of the negative capacitance load circuit is connected to the first terminal of the fourth switching transistor, and the third and fourth terminals of the negative capacitance load circuit are grounded. The negative capacitive load circuit is used to perform phase compensation on the differential voltage output from the first terminal of the second switch and the first terminal of the fourth switch.

[0018] According to a continuous-time linear equalizer provided by the present invention, the negative capacitive load circuit includes: The fifth switching transistor, wherein the first end of the fifth switching transistor is connected to the first end of the second switching transistor; A first bias current source, the first end of the first bias current source is connected to the second end of the fifth switch, and the second end of the first bias current source is grounded; A sixth switching transistor, wherein the first end of the sixth switching transistor is connected to the first end of the fourth switching transistor; The second bias current source has its first terminal connected to the second terminal of the sixth switch transistor, and its second terminal grounded. A first capacitor, wherein a first terminal of the first capacitor is connected to a first terminal of the first bias current source, and a second terminal of the first capacitor is connected to a first terminal of the second bias current source; The first end of the fifth switch is connected to the control end of the sixth switch, and the first end of the sixth switch is connected to the control end of the fifth switch.

[0019] According to a continuous-time linear equalizer provided by the present invention, the bias voltage includes a first bias sub-voltage and a second bias sub-voltage; The bias circuit includes: A first bias sub-circuit, wherein a first terminal of the first bias sub-circuit is connected to a first power supply, is used to receive a first selection signal and output a first bias sub-voltage corresponding to the first selection signal; The third resistor, the first end of which is connected to the second end of the first bias sub-circuit; The second bias sub-circuit has its first terminal connected to the second terminal of the third resistor. It is used to receive the second selection signal and output a second bias sub-voltage corresponding to the second selection signal. The second terminal of the second bias sub-circuit is grounded.

[0020] According to a continuous-time linear equalizer provided by the present invention, the first bias sub-circuit includes: M seventh switching transistors are connected in sequence. The first terminal of the first seventh switching transistor in the M seventh switching transistors is connected to the first power supply. The first terminal of the i-th seventh switching transistor is connected to the second terminal of the (i-1)-th seventh switching transistor. The second terminal of the M-th seventh switching transistor in the M seventh switching transistors is connected to the first terminal of the third resistor. The control terminal of each seventh switching transistor is connected to its second terminal. M first conducting switches, the first terminals of the M first conducting switches are connected one-to-one with the control terminals of the M seventh switching transistors connected in sequence, and the second terminals of the M first conducting switches are connected to output the first bias sub-voltage. Wherein, the first selection signal is used to select one or more of the M first conduction switches to conduct, so as to control the first bias sub-circuit to output the first bias sub-voltage, where M is a positive integer greater than or equal to 2, and i is less than or equal to M; The second bias sub-circuit includes: N sequentially connected eighth switching transistors, the first terminal of the first eighth switching transistor in the N sequentially connected eighth switching transistors is connected to the second terminal of the third resistor, the first terminal of the j-th eighth switching transistor is connected to the second terminal of the (j-1)-th eighth switching transistor, the second terminal of the Nth eighth switching transistor in the N sequentially connected eighth switching transistors is grounded, and the control terminal of each eighth switching transistor is connected to its first terminal. N second conducting switches, the first end of the N second conducting switches is connected one-to-one with the control end of the N sequentially connected eighth switching transistors, and the second end of the N second conducting switches is used to output the second bias sub-voltage. The second selection signal is used to select one or more of the N second conduction switches to conduct, so as to control the second bias sub-circuit to output the second bias sub-voltage. N is a positive integer greater than or equal to 2, and j is less than or equal to N.

[0021] According to a continuous-time linear equalizer provided by the present invention, the bias circuit further includes a fourth resistor and a ninth switch, and the second terminal of the second bias sub-circuit is grounded through the fourth resistor and the ninth switch; The first end of the fourth resistor is connected to the second end of the second bias sub-circuit; The first terminal of the ninth switch is connected to the second terminal of the fourth resistor, the second terminal of the ninth switch is grounded, and the control terminal of the ninth switch is connected to the first terminal of the fourth resistor and the current source circuit respectively.

[0022] The present invention also provides an electronic device, comprising: A continuous-time linear equalizer as described in any of the above examples.

[0023] This invention provides a continuous-time linear equalizer and electronic device. It dynamically adjusts the inductance characteristics of a first and second active inductor circuit by outputting a bias voltage through a bias circuit. Combined with adjustable resistance and capacitance circuits connected between the differential input branches, during differential signal processing, the adjustable resistance and capacitance circuits change the impedance between the branches to set compensation benchmarks for low-frequency and high-frequency gains, respectively. Meanwhile, the bias circuit further reshapes the AC frequency response curve of the output differential voltage by altering the inductive load characteristics of the active inductor circuit. This multi-dimensional impedance and load joint adjustment mechanism enables the system to compensate for changes in device parameters caused by process, voltage, and temperature drift in real time, effectively resisting interference from immature processes and ensuring the stability and accuracy of high-frequency gain compensation under different environmental conditions. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0025] Figure 1 This is one of the topology diagrams of the continuous-time linear equalizer provided by the present invention.

[0026] Figure 2 This is the second topology diagram of the continuous-time linear equalizer provided by the present invention.

[0027] Figure 3 This is the third topology diagram of the continuous-time linear equalizer provided by the present invention.

[0028] Figure label: 10: First active inductor circuit; 101: First capacitance adjustment circuit; 20: Second active inductor circuit; 201: Second capacitance adjustment circuit; 30: Bias circuit; 301: First bias sub-circuit; 302: Second bias sub-circuit; 40: Adjustable resistance circuit; 401: Resistor connection branch; 50: Adjustable capacitance circuit; 501: Capacitor connection branch; 60: First differential input branch; 70: Second differential input branch; 80: Current source circuit; 801: First current source; 802: Second current source; 803: Third current source; 90: Negative capacitance load circuit; Q1: First switching transistor; Q2: Second switching transistor; Q3: Third switching transistor; Q4: Fourth switching transistor; Q5: Fifth switching transistor; Q6: Sixth switching transistor; Q7: Seventh switching transistor; Q8: Eighth switching transistor Transistor; Q9: Ninth switch transistor; ZKQ1: First master control switch transistor; VDD: First power supply; R1: First resistor; CKQ1: First slave control switch transistor; CKQ2: Second slave control switch transistor; CKQ3: Third slave control switch transistor; ZKQ2: Second master control switch transistor; R2: Second resistor; CKQ4: Fourth slave control switch transistor; CKQ5: Fifth slave control switch transistor; CKQ6: Sixth slave control switch transistor; Rs: Degenerate resistor; JK1: First access switch; JK2: Second access switch; Rc: Degenerate capacitor; JK3: Third access switch; JK4: Fourth access switch; PD1: First bias current source; PD2: Second bias current source; C: First capacitor; R3: Third resistor; DK1: First conduction switch; DK2: Second conduction switch; R4: Fourth resistor. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0030] The following is combined Figures 1 to 3 The present invention describes a continuous-time linear equalizer and electronic device.

[0031] This invention provides a continuous-time linear equalizer, comprising the following modules.

[0032] First active inductor circuit 10; Second active inductor circuit 20; The bias circuit 30 is connected to the first active inductor circuit 10 and the second active inductor circuit 20 respectively, and is used to output a bias voltage to adjust the inductance characteristics of the first active inductor circuit 10 and the second active inductor circuit 20. Adjustable resistance circuit 40; Adjustable capacitance circuit 50; The differential input circuit includes a first differential input branch 60 and a second differential input branch 70. The first differential input branch 60 is connected to the first active inductor circuit 10, and the second differential input branch 70 is connected to the second active inductor circuit 20. An adjustable resistance circuit 40 and an adjustable capacitance circuit 50 are respectively connected between the first differential input branch 60 and the second differential input branch 70. The differential input circuit is used to receive differential signals INP and INN, and outputs the differential voltage Vout corresponding to the differential signals based on the first active inductor circuit 10, the second active inductor circuit 20, the adjustable resistance circuit 40, and the adjustable capacitance circuit 50.

[0033] In this embodiment, the frequency response of the entire transmission link is flattened by compensating for the frequency response of the high-speed signal. The continuous-time linear equalizer includes a first active inductor circuit 10, a second active inductor circuit 20, a bias circuit 30, an adjustable resistance circuit 40, an adjustable capacitance circuit 50, and a differential input circuit.

[0034] In the specific circuit connection and signal interaction process, the differential input circuit serves as the signal receiving and preliminary processing unit, internally including a first differential input branch 60 and a second differential input branch 70. The first differential input branch 60 is connected to the first active inductor circuit 10, and the second differential input branch 70 is connected to the second active inductor circuit 20. An adjustable resistance circuit 40 and an adjustable capacitance circuit 50 are respectively connected between the first differential input branch 60 and the second differential input branch 70, forming an impedance network for adjusting the gain. The first active inductor circuit 10 and the second active inductor circuit 20 are connected here as load circuits. Here, the active inductor circuit refers to a circuit module with inductance characteristics equivalently implemented using active devices (such as transistors). Compared to traditional passive spiral inductors, it occupies less chip area and its parameters are adjustable.

[0035] To achieve dynamic adjustment of the characteristics of the aforementioned active inductor circuits, a bias circuit 30 is connected to the first active inductor circuit 10 and the second active inductor circuit 20, respectively. The bias circuit 30 generates and outputs a bias voltage. This bias voltage is input as a control signal to the first active inductor circuit 10 and the second active inductor circuit 20, directly adjusting the internal bias states of both circuits, thereby changing their equivalent inductance characteristics (such as the equivalent inductance value).

[0036] In its actual operation, the differential input circuit receives a differential signal carrying high and low frequency components. This differential signal is converted into a corresponding signal current in the first differential input branch 60 and the second differential input branch 70. The adjustable resistance circuit 40 and the adjustable capacitance circuit 50, connected between the two differential input branches, adjust the AC impedance between the branches by changing their resistance and capacitance values. Specifically, the adjustable resistance circuit 40 mainly adjusts the low-frequency gain of the differential signal, while the adjustable capacitance circuit 50 mainly adjusts the high-frequency gain. Simultaneously, the differential signal current flows through the first active inductor circuit 10 and the second active inductor circuit 20, which act as loads. Because the active inductors present higher impedance to high-frequency signals, they can provide additional gain enhancement (i.e., peaking effect) in the high-frequency band. Ultimately, based on the combined action of the first active inductor circuit 10, the second active inductor circuit 20, the adjustable resistance circuit 40, and the adjustable capacitance circuit 50, the differential input circuit outputs the differential voltage corresponding to the differential signal after frequency equalization.

[0037] The continuous-time linear equalizer provided in this embodiment dynamically adjusts the inductance characteristics of the first active inductor circuit 10 and the second active inductor circuit 20 by outputting a bias voltage through the bias circuit 30. Combined with the adjustable resistance circuit 40 and the adjustable capacitance circuit 50 connected between the differential input branches, during the differential signal processing, the adjustable resistance circuit 40 and the adjustable capacitance circuit 50 change the impedance between the branches to set the compensation benchmarks for low-frequency gain and high-frequency gain respectively. Meanwhile, the bias circuit 30 further reshapes the AC frequency response curve of the output differential voltage by changing the inductive load characteristics of the active inductor circuit. This multi-dimensional impedance and load joint adjustment mechanism enables the system to compensate for changes in device parameters caused by process, voltage and temperature drift in real time, effectively resisting interference caused by immature processes, and ensuring the stability and accuracy of high-frequency gain compensation under different environmental conditions.

[0038] According to the continuous-time linear equalizer provided by the present invention, the differential input circuit further includes a current source circuit 80.

[0039] The current source circuit 80 is used to provide a stable DC bias current for the entire differential input network in order to maintain the operating state of the switching transistors in each branch.

[0040] The first differential input branch 60 includes: The first switch Q1 has its first terminal connected to the first connection terminal of the first active inductor circuit 10, and its second terminal connected to the current source circuit 80. The second switch Q2 has its first terminal connected to the second connection terminal of the first active inductor circuit 10, its second terminal connected to the current source circuit 80, and its control terminal connected to the control terminal of the first switch Q1.

[0041] Specifically, the first differential input branch 60 includes a first switch Q1 and a second switch Q2. Here, the first switch Q1 and the second switch Q2 are typically semiconductor devices with signal amplification and conduction control capabilities, such as field-effect transistors (FETs) or bipolar transistors (BPTs). The first terminal of the first switch Q1 is connected to the first connection terminal of the first active inductor circuit 10, and the second terminal of the first switch Q1 is connected to the current source circuit 80. The first terminal of the second switch Q2 is connected to the second connection terminal of the first active inductor circuit 10, and the second terminal of the second switch Q2 is connected to the current source circuit 80. Furthermore, the control terminal of the second switch Q2 is connected to the control terminal of the first switch Q1. The control terminal typically corresponds to the gate or base of the transistor, used to receive input signals of the same polarity; the first terminal and the second terminal correspond to the drain and source (or collector and emitter) of the transistor, respectively.

[0042] The second differential input branch 70 includes: The third switch Q3 has its first terminal connected to the first connection terminal of the second active inductor circuit 20, and its second terminal connected to the current source circuit 80. The fourth switch Q4 has its first terminal connected to the second connection terminal of the second active inductor circuit 20, its second terminal connected to the current source circuit 80, and its control terminal connected to the control terminal of the third switch Q3. The adjustable resistance circuit 40 and the adjustable capacitance circuit 50 are respectively connected between the second terminal of the second switch Q2 and the second terminal of the fourth switch Q4.

[0043] Specifically, the second differential input branch 70 includes a third switch Q3 and a fourth switch Q4. The first terminal of the third switch Q3 is connected to the first connection terminal of the second active inductor circuit 20, and the second terminal of the third switch Q3 is connected to the current source circuit 80. The first terminal of the fourth switch Q4 is connected to the second connection terminal of the second active inductor circuit 20, and the second terminal of the fourth switch Q4 is connected to the current source circuit 80. Furthermore, the control terminal of the fourth switch Q4 is connected to the control terminal of the third switch Q3. This structure allows the third switch Q3 and the fourth switch Q4 to synchronously receive input signals of the opposite polarity.

[0044] In this connection architecture, the adjustable resistance circuit 40 and the adjustable capacitance circuit 50 are respectively connected between the second terminal of the second switch Q2 and the second terminal of the fourth switch Q4, thereby forming a source degradation network between the sources of the second switch Q2 and the fourth switch Q4.

[0045] In actual signal processing, when the differential input circuit receives a differential signal, this differential signal is applied to the common control terminal of the first switch Q1 and the second switch Q2, and the common control terminal of the third switch Q3 and the fourth switch Q4. The differential voltage signal is converted into the branch current of each switch through these control terminals. Since the adjustable resistance circuit 40 and the adjustable capacitance circuit 50 are only connected between the second terminal of the second switch Q2 and the second terminal of the fourth switch Q4, this means that the AC signal current induced by the differential signal will be modulated by the AC impedance formed by the adjustable resistance circuit 40 and the adjustable capacitance circuit 50 when flowing through the second switch Q2 and the fourth switch Q4, while the first switch Q1 and the third switch Q3 mainly participate in providing the basic DC and part of the AC path.

[0046] Through the connection structure design of the first switch Q1 to the fourth switch Q4 and the limiting access positions of the adjustable resistance circuit 40 and the adjustable capacitance circuit 50, this embodiment cleverly allocates the source-degraded AC adjustment path (the branch where the second switch Q2 and the fourth switch Q4 are located) and part of the main DC path in the physical architecture during the conversion and transmission of differential signals. When a differential signal is input through the control terminal, the adjustable resistance circuit 40 and the adjustable capacitance circuit 50 directly modulate the source AC impedance between the second switch Q2 and the fourth switch Q4, thereby accurately changing the low-frequency and high-frequency gain ratio when the differential signal is converted into a current signal without drastically affecting the overall DC bias current. This structure not only makes the adjustment process of low-frequency gain and high-frequency gain more independent and linear, avoiding serious interference to the DC static operating point when adjusting AC characteristics, but also effectively reduces the additional power consumption caused by impedance adjustment, enabling the continuous-time linear equalizer to achieve smooth and accurate frequency response compensation in a low-power state.

[0047] In some embodiments, the first switch Q1, the second switch Q2, the third switch Q3, and the fourth switch Q4 are NMOS transistors. NMOS stands for N-Metal-Oxide-Semiconductor. The second terminal of each of the first switch Q1, second switch Q2, third switch Q3, and fourth switch Q4 is the source (S), the first terminal of each of the first switch Q1, second switch Q2, third switch Q3, and fourth switch Q4 is the drain (D), and the control terminal of each of the first switch Q1, second switch Q2, third switch Q3, and fourth switch Q4 is the gate (G).

[0048] In some embodiments, NMOS and PMOS are used in parallel to improve robustness.

[0049] According to the present invention, a continuous-time linear equalizer includes a current source circuit 80 comprising: The first current source 801 has its first terminal connected to the second terminal of the first switch Q1 and the second terminal of the third switch Q3, and its second terminal is grounded. The second current source 802 has its first terminal connected to the second terminal of the second switch Q2, and its second terminal is grounded. The third current source 803 has its first terminal connected to the second terminal of the fourth switch Q4, and its second terminal is grounded. The control terminals of the first current source 801, the second current source 802, and the third current source 803 are connected together.

[0050] Specifically, the first terminal of the first current source 801 is connected to the second terminals of both the first switch Q1 and the third switch Q3, with its second terminal grounded. This allows the first switch Q1 and the third switch Q3 to form a non-degrading differential pair sharing a tail current. The first terminal of the second current source 802 is connected only to the second terminal of the second switch Q2, with its second terminal grounded. Similarly, the first terminal of the third current source 803 is connected only to the second terminal of the fourth switch Q4, with its second terminal grounded. This connection method allows the second switch Q2 and the fourth switch Q4 to each have their own independent tail current sinking branch.

[0051] Because the control terminals of the first current source 801, the second current source 802, and the third current source 803 are connected, they can synchronously and proportionally output static DC bias currents based on a unified bias reference. When a differential AC signal is input, the branches containing the first switch Q1 and the third switch Q3, sharing the first current source 801, perform a pure basic differential signal current conversion; while the branches containing the second switch Q2 and the fourth switch Q4, in the process of converting the input signal into current, rely entirely on the adjustable resistance circuit 40 and the adjustable capacitance circuit 50 connected between them for AC signal interaction. The independent second current source 802 and the third current source 803 provide stable DC operating points for these two switches without creating a hard AC short circuit.

[0052] In this embodiment, the current source circuit 80 is subdivided into three independent, sunken, but uniformly controlled current sources. A shared first current source 801 is provided for the first switch Q1 and the third switch Q3, while independent second current sources 802 and third current sources 803 are provided for the second switch Q2 and the fourth switch Q4, respectively. During the extraction and processing of the differential signal current, the uniformly connected control terminal ensures that the DC bias current of all branches can maintain the same direction and proportional change when drifting due to process, voltage, and temperature, thus maintaining extremely high static stability of the entire circuit when processing signals. At the same time, the independently set second current sources 802 and third current sources 803 effectively isolate the DC potential across the source degradation network (adjustable resistance circuit 40 and adjustable capacitance circuit 50). This signal processing method, which combines DC isolation and AC coupling, prevents the source impedance change from causing disturbances to the DC operating point of the main signal amplification path, making the extraction and adjustment process of AC frequency response purer and further improving the robustness and accuracy when compensating for high-frequency signal loss.

[0053] According to a continuous-time linear equalizer provided by the present invention, the first active inductor circuit 10 includes: The first main control switch ZKQ1, the first terminal of the first main control switch ZKQ1 is connected to the first power supply VDD; The first resistor R1 has its first end connected to the second end of the first main control switch ZKQ1 and the first end of the first switch Q1, and its second end is connected to the first end of the second switch Q2. The first capacitance adjustment circuit 101 has a control connection terminal connected to the bias circuit 30, a first output terminal connected to the control terminal of the first main control switch ZKQ1, and a second output terminal connected to the first terminal of the first switch Q1. The first capacitance adjustment circuit 101 adjusts the output voltage of the first output terminal and the second output terminal of the first capacitance adjustment circuit 101 according to the bias voltage output by the bias circuit 30.

[0054] Specifically, the first active inductor circuit 10 utilizes the transconductance of the first master control switch ZKQ1 and the first resistor R1 to create an equivalent inductive impedance at the load end of the circuit. The first capacitance adjustment circuit 101 receives the bias voltage output from the bias circuit 30 in real time and dynamically adjusts the output voltages of the first and second output terminals of the first capacitance adjustment circuit 101 according to the magnitude of the bias voltage. Changes in these two output voltages directly affect the gate bias and source node potential state of the first master control switch ZKQ1.

[0055] By introducing a first capacitance adjustment circuit 101 controlled by a bias voltage into the first active inductor circuit 10, the output voltage change of the first capacitance adjustment circuit 101 can directly change the parasitic capacitance and transconductance parameters equivalent to the first main control switch ZKQ1. The first capacitance adjustment circuit 101, together with the first main control switch ZKQ1 and the first resistor R1, can adaptively change the equivalent inductance and impedance characteristics at the node according to the current process angle or temperature conditions when the differential signal flows through the load. Ultimately, without increasing the additional large current power consumption, the peaking frequency and high-frequency gain of the AC frequency response curve can be accurately reshaped, greatly improving the circuit's robustness against process, voltage, and temperature changes.

[0056] In some embodiments, if the first master control switch ZKQ1 is an NMOS, then the first terminal of the first master control switch ZKQ1 is the drain D, the second terminal of the first master control switch ZKQ1 is the source S, and the control terminal of the first master control switch ZKQ1 is the gate G.

[0057] According to the present invention, a continuous-time linear equalizer includes a bias voltage comprising a first bias sub-voltage VBIAS1 and a second bias sub-voltage VBIAS2. The first capacitance adjustment circuit 101 includes: The first slave switch transistor CKQ1, the first terminal of the first slave switch transistor CKQ1 is connected to the first power supply VDD; The second slave switch CKQ2 has its first terminal connected to the second terminal of the first slave switch CKQ1 and the control terminal of the first master switch ZKQ1, respectively. The second terminal of the second slave switch CKQ2 is grounded, and the control terminal of the second slave switch CKQ2 is used to receive the second bias sub-voltage. The third slave switch CKQ3 has its first terminal connected to the control terminal of the first slave switch CKQ1, and its second terminal connected to the first terminal of the first switch Q1. The control terminal of the third slave switch CKQ3 is used to receive the first bias sub-voltage.

[0058] The first terminal of the first slave-controlled switch CKQ1 is connected to the first power supply VDD, providing an energy source for the first capacitance adjustment circuit 101.

[0059] Specifically, the first bias sub-voltage and the second bias sub-voltage serve as DC control levels, applied to the control terminals of the third slave switch CKQ3 and the second slave switch CKQ2, respectively. Changes in the amplitude of the second bias sub-voltage directly alter the equivalent on-resistance and the magnitude of the extracted current of the second slave switch CKQ2, thereby changing the bias voltage level of the control terminal (gate) of the first master switch ZKQ1. Simultaneously, changes in the amplitude of the first bias sub-voltage alter the operating state of the third slave switch CKQ3, adjusting the level of the control terminal of the first slave switch CKQ1, thus changing the parasitic capacitance at node 101 of the entire first capacitance adjustment circuit and the AC impedance fed back to the first terminal of the first switch Q1.

[0060] In this embodiment, by setting the bias voltage to a first bias sub-voltage and a second bias sub-voltage, and introducing a second slave switch CKQ2 and a third slave switch CKQ3, respectively controlled by these two sub-voltages, into the first capacitance adjustment circuit 101, the first bias sub-voltage and the second bias sub-voltage can collaboratively change the DC level and parasitic parameters of the gate nodes of the first slave switch CKQ1 and the first master switch ZKQ1. This dual-sub-voltage joint control mechanism can continuously and over a wide range adjust the equivalent transconductance and equivalent capacitance within the active inductor network when the high-frequency components of the data signal flow through the first terminal of the first switch Q1, thereby precisely changing the inductance peaking frequency point of the first active inductor circuit 10, and achieving highly robust compensation for AC characteristic deviations under different process, voltage, and temperature drifts.

[0061] In some embodiments, the first slave switch CKQ1 and the third slave switch CKQ3 are PMOS transistors, where PMOS refers to an n-type substrate, p-channel MOS transistor that carries current by the flow of holes, and the second slave switch CKQ2 is an NMOS transistor.

[0062] According to a continuous-time linear equalizer provided by the present invention, the second active inductor circuit 20 includes: The second main control switch ZKQ2, the first terminal of the second main control switch ZKQ2 is connected to the first power supply VDD; The second resistor R2 has its first end connected to the second end of the second main control switch ZKQ2 and the first end of the third switch Q3, and its second end is connected to the first end of the fourth switch Q4. The second capacitance adjustment circuit 201 has its control connection terminal connected to the bias circuit 30, its first output terminal connected to the control terminal of the second main control switch ZKQ2, and its second output terminal connected to the first terminal of the third switch Q3. The second capacitance adjustment circuit 201 adjusts the output voltage of the first output terminal and the second output terminal of the second capacitance adjustment circuit 201 according to the bias voltage output by the bias circuit 30.

[0063] Specifically, the second active inductor circuit 20 utilizes the transconductance of the second master control switch ZKQ2 and the second resistor R2 to create an equivalent inductive impedance at the load end of the circuit. The second capacitance adjustment circuit 201 receives the bias voltage output from the bias circuit 30 in real time and dynamically adjusts the output voltages of its first and second output terminals based on the magnitude of this bias voltage. Changes in these two output voltages directly affect the gate bias and source node potential state of the second master control switch ZKQ2.

[0064] By introducing a second capacitance adjustment circuit 201 controlled by the bias voltage into the second active inductor circuit 20, the output voltage change of the second capacitance adjustment circuit 201 can directly change the parasitic capacitance and transconductance parameters equivalent to the second main control switch ZKQ2. The second capacitance adjustment circuit 201, together with the second main control switch ZKQ2 and the second resistor R2, can adaptively change the equivalent inductance and impedance characteristics at the node according to the current process angle or temperature conditions when the differential signal flows through the load. Ultimately, without increasing additional high current power consumption, the peaking frequency and high-frequency gain of the AC frequency response curve can be accurately reshaped, significantly improving the circuit's robustness against process, voltage, and temperature changes.

[0065] In some embodiments, if the second master control switch ZKQ2 is an NMOS, then the first terminal of the second master control switch ZKQ2 is the drain D, the second terminal of the second master control switch ZKQ2 is the source S, and the control terminal of the second master control switch ZKQ2 is the gate G.

[0066] According to the present invention, a continuous-time linear equalizer includes a bias voltage comprising a first bias sub-voltage VBIAS1 and a second bias sub-voltage VBIAS2. The second capacitance adjustment circuit 201 includes: The fourth slave switch CKQ4, the first terminal of the fourth slave switch CKQ4 is connected to the first power supply VDD; The fifth slave switch CKQ5 has its first terminal connected to the second terminal of the fourth slave switch CKQ4 and the control terminal of the second master switch ZKQ2. The second terminal of the fifth slave switch CKQ5 is grounded. The control terminal of the fifth slave switch CKQ5 is used to receive the second bias sub-voltage. The sixth slave switch CKQ6 has its first terminal connected to the control terminal of the fourth slave switch CKQ4, and its second terminal connected to the first terminal of the third switch Q3. The control terminal of the sixth slave switch CKQ6 is used to receive the first bias sub-voltage.

[0067] Specifically, the first and second bias sub-voltages, as DC control levels, are applied to the control terminals of the fourth slave switch CKQ4 and the fifth slave switch CKQ5, respectively. Changes in the amplitude of the second bias sub-voltage directly alter the equivalent on-resistance and draw current of the fifth slave switch CKQ5, thereby changing the bias voltage level of the gate control terminal of the second master switch ZKQ2. Simultaneously, changes in the amplitude of the first bias sub-voltage change the operating state of the sixth slave switch CKQ6, adjusting the level of the control terminal of the fifth slave switch CKQ5, thus changing the parasitic capacitance at node 201 of the entire second capacitance adjustment circuit and the AC impedance fed back to the first terminal of the third switch Q3.

[0068] In this embodiment, by setting the bias voltage to a first bias sub-voltage and a second bias sub-voltage, and introducing a fifth slave switch CKQ5 and a sixth slave switch CKQ6, respectively controlled by these two sub-voltages, into the second capacitance adjustment circuit 201, the first bias sub-voltage and the second bias sub-voltage can collaboratively change the DC level and parasitic parameters of the gate nodes of the fourth slave switch CKQ4 and the second master switch ZKQ2. This dual-sub-voltage joint control mechanism can continuously and over a wide range adjust the equivalent transconductance and equivalent capacitance within the active inductor network when the high-frequency components of the data signal flow through the first terminal of the third switch Q3, thereby precisely changing the inductance peaking frequency point of the second active inductor circuit 20, achieving highly robust compensation for AC characteristic deviations under different process, voltage, and temperature drifts.

[0069] In some embodiments, the fourth slave switch CKQ4 and the sixth slave switch CKQ6 are PMOS, and the fifth slave switch CKQ5 is NMOS.

[0070] According to the present invention, a continuous-time linear equalizer includes an adjustable resistance circuit 40 comprising: Multiple resistors are connected to branch 401. The first end of each resistor connected to branch 401 is connected to the second end of the second switch Q2, and the second end of each resistor connected to branch 401 is connected to the second end of the fourth switch Q4. Each resistor access branch 401 includes a degradation resistor Rs, a first access switch JK1 and a second access switch JK2. The first terminal of the first access switch JK1 is connected to the second terminal of the second switch Q2. The first terminal of the degradation resistor Rs is connected to the second terminal of the first access switch JK1. The first terminal of the second access switch JK2 is connected to the second terminal of the degradation resistor Rs. The second terminal of the second access switch JK2 is connected to the second terminal of the fourth switch. The control terminal of the first access switch JK1 is connected to the control terminal of the second access switch JK2. The first access switch JK1 and the second access switch JK2 are synchronously turned on or off according to the received resistance value to control the degradation resistor Rs to switch between the second terminal of the second switch Q2 and the second terminal of the fourth switch Q4.

[0071] In this embodiment, the adjustable resistance circuit 40 is specifically manifested as a digitally programmable resistor array in the overall architecture. Its main structure includes multiple parallel resistor access branches 401. In terms of circuit topology, the first end of each resistor access branch 401 is connected to the second end of the second switch Q2 (i.e., the source node of the first differential input branch 60), and the second end of each resistor access branch 401 is connected to the second end of the fourth switch Q4 (i.e., the source node of the second differential input branch 70). This means that all resistor access branches 401 span between the first differential input branch 60 and the second differential input branch 70.

[0072] Specifically, each resistor access branch 401 is composed of a degraded resistor Rs, a first access switch JK1, and a second access switch JK2 connected in series. The specific connection configuration is as follows: the first terminal of the first access switch JK1 is connected to the second terminal of the second switch Q2; the two terminals of the degraded resistor Rs are respectively connected to the second terminals of the first and second access switches JK1 and JK2; and the second terminal of the second access switch JK2 is connected to the second terminal of the fourth switch Q4. Furthermore, to ensure complete symmetry and synchronization of the differential signal branch conduction, the control terminals of the first and second access switches JK1 and JK2 are shorted together in the wiring, forming the control input port of this branch. Here, the degraded resistor Rs refers to the basic impedance component used to introduce AC negative feedback at the source of the differential input circuit to adjust the low-frequency gain, while the resistance control voltage refers to the external digital configuration level received by the aforementioned control input port.

[0073] When the continuous-time linear equalizer needs to adjust the equalization parameters according to the specific loss of the current channel, it sends a configuration command to the adjustable resistance circuit 40 to generate multiple corresponding resistance control voltages. Each resistor access branch 401 receives its corresponding resistance control voltage. The first access switch JK1 and the second access switch JK2 perform synchronous conduction or cutoff actions according to the effective level state of the received resistance control voltage. For example, when a branch receives a conduction enable signal, the first access switch JK1 and the second access switch JK2 at both ends of the branch close simultaneously, so that the degradation resistor Rs sandwiched in the middle is cut in (i.e. physically connected in parallel) between the second terminal of the second switch Q2 and the second terminal of the fourth switch Q4, forming a differential source degradation path; conversely, when a cutoff signal is received, the switches on both sides open synchronously, so that the degradation resistor Rs is completely cut out (i.e., physically isolated from the differential source network). By controlling the combination of multiple resistors with different resistance weights connected to branch 401 for input and output, the total equivalent degraded resistance between the sources of the differential input circuit will change discretely and precisely.

[0074] In some embodiments, the resistance values ​​of the degradation resistor Rs in different resistors connected to branch 401 may be the same or different.

[0075] In some embodiments, when the number of resistors connected to branch 401 is 3, the resistance control voltage is {RSEL}. <0> RSEL <1> RSEL <2>}

[0076] In some embodiments, the degradation resistor Rs can be replaced by a MOSFET.

[0077] In some embodiments, the first access switch JK1 and the second access switch JK2 are NMOS.

[0078] In this embodiment, the adjustable resistance circuit 40 receives discrete resistance control voltages and drives the access switches distributed across the source terminals to synchronously close or open. This symmetrical switching response process dynamically switches different numbers or values ​​of degradation resistors Rs between the source nodes of the differential input circuit. This physical reconstruction process of the impedance network directly changes the AC source degradation feedback depth of the differential input branch. Since the magnitude of the total equivalent degradation resistance determines the attenuation degree of the low-frequency signal, this dynamic switching mechanism of the parallel branch enables the system to independently and precisely adjust the low-frequency gain of the differential signal in multiple levels during data transmission. This mechanism not only effectively improves the adaptability of the continuous-time linear equalizer to the low-frequency loss characteristics of different physical channels, but also, because the switches are located on both sides of the resistors, completely isolates the parasitic interference introduced by the unconnected resistors, thereby ensuring the accuracy and signal integrity of the entire equalization network when adjusting the low-frequency gain.

[0079] According to the present invention, a continuous-time linear equalizer includes an adjustable capacitance circuit 50 comprising: Multiple capacitors are connected to branch 501. The first end of each capacitor connected to branch 501 is connected to the second end of the second switch Q2, and the second end of each capacitor connected to branch 501 is connected to the second end of the fourth switch Q4. Each capacitor access branch 501 includes a degraded capacitor Rc, a third access switch JK3, and a fourth access switch JK4. The first terminal of the third access switch JK3 is connected to the second terminal of the second switch Q2. The first terminal of the degraded capacitor Rc is connected to the second terminal of the third access switch JK3. The first terminal of the fourth access switch JK4 is connected to the second terminal of the degraded capacitor Rc. The second terminal of the fourth access switch JK4 is connected to the second terminal of the fourth switch. The control terminal of the third access switch JK3 is connected to the control terminal of the fourth access switch JK4. Among them, the third access switch JK3 and the fourth access switch JK4 are synchronously turned on or off according to the received capacitance control voltage, so as to control the degradation capacitor Rc to switch in and out between the second terminal of the second switch Q2 and the second terminal of the fourth switch Q4.

[0080] In this embodiment, the adjustable capacitance circuit 50 can be implemented as a capacitor array structure. Specifically, the adjustable capacitance circuit 50 includes multiple parallel capacitor access branches 501. This structure, which spans the second terminals of the second switch Q2 and the fourth switch Q4, provides an AC coupling path for the high-frequency components of the differential signal.

[0081] Specifically, each capacitor access branch 501 includes a degraded capacitor Rc and a third access switch JK3 and a fourth access switch JK4 located on either side of the degraded capacitor Rc. In terms of circuit connections, the first terminal of the third access switch JK3 is connected to the second terminal of the second switch Q2, and the second terminal of the third access switch JK3 is connected to the first terminal of the degraded capacitor Rc; simultaneously, the second terminal of the degraded capacitor Rc is connected to the first terminal of the fourth access switch JK4, and the second terminal of the fourth access switch JK4 is connected to the second terminal of the fourth switch Q4. Furthermore, to ensure the consistency and symmetry of the switching actions, the control terminals of the third access switch JK3 and the fourth access switch JK4 are interconnected to jointly receive the externally input capacitance control voltage. This capacitance control voltage can be a pre-acquired and issued digital configuration signal.

[0082] In practical use, the continuous-time linear equalizer dynamically changes the operating state of each degraded capacitor Rc by applying a corresponding capacitance control voltage to the control terminal of each capacitor access branch 501. The specific execution steps are as follows: When it is determined that a certain amount of high-frequency gain compensation needs to be added based on the current high-frequency loss of the channel, a capacitance control voltage with an effective conduction level is output to the corresponding capacitor access branch 501. Upon receiving this voltage, the third access switch JK3 and the fourth access switch JK4 in this branch synchronously turn on, thereby physically switching the corresponding degraded capacitor Rc between the second terminal of the second switch Q2 and the second terminal of the fourth switch Q4. Conversely, when the received capacitance control voltage is at the off level, the third access switch JK3 and the fourth access switch JK4 synchronously turn off, cutting off the corresponding degraded capacitor Rc from the differential source node. By configuring multiple different capacitance control voltages, the on / off states of multiple capacitor access branches 501 can be flexibly combined to obtain a stepped adjustable total equivalent capacitance value.

[0083] In some embodiments, the capacitance values ​​of the degraded capacitors Rc in different capacitors connected to branch 501 may be the same or different.

[0084] In some embodiments, when the number of capacitors connected to branch 501 is 3, the capacitance control voltage is {CSEL}. <0> CSEL <1> CSEL <2>}

[0085] In some embodiments, the degraded capacitor Rc can be replaced by a MOSFET.

[0086] In some embodiments, the third access switch JK3 and the fourth access switch JK4 are NMOS.

[0087] In this embodiment, an adjustable capacitance circuit 50, consisting of multiple capacitor access branches 501 including degraded capacitors Rc, third access switches JK3, and fourth access switches JK4, is introduced between the connection terminals of the second switch Q2 and the fourth switch Q4. During the differential signal equalization process, the capacitance control voltage synchronously controls the conduction or cutoff of the third access switches JK3 and the fourth access switches JK4, so that degraded capacitors Rc of a specific capacitance value are precisely switched into or out of the source network of the differential input branch. This physical process directly changes the AC bypass impedance at the source node of the differential input transistor. Since the capacitor exhibits low impedance characteristics for high-frequency signals, more degraded capacitors Rc will reduce the source degradation effect of the differential input branch in the high-frequency band, thereby directly improving the signal gain in the high-frequency band. This digital switching-in / switching adjustment method based on the switching array to adjust the degradation capacitor Rc can accurately and independently adjust the compensation amplitude of the continuous-time linear equalizer for high-frequency signal components. In conjunction with the bias circuit 30 and the active inductor circuit, it greatly improves the compensation accuracy and adaptability of the circuit for complex high-frequency attenuation characteristics in different communication environments.

[0088] According to the present invention, a continuous-time linear equalizer further includes: The negative capacitive load circuit 90 has its first terminal connected to the first terminal of the second switch Q2, its second terminal connected to the first terminal of the fourth switch Q4, and its third and fourth terminals grounded. The negative capacitive load circuit 90 is used to perform phase compensation on the differential voltage output from the first terminal of the second switch Q2 and the first terminal of the fourth switch Q4.

[0089] In this embodiment, the negative capacitive load circuit 90 refers to a circuit module whose equivalent impedance exhibits negative capacitance characteristics under AC small-signal model. In terms of circuit topology, the first terminal of the negative capacitive load circuit 90 is connected to the first terminal of the aforementioned second switch Q2, and the second terminal of the negative capacitive load circuit 90 is connected to the first terminal of the aforementioned fourth switch Q4. Simultaneously, the third and fourth terminals of the negative capacitive load circuit 90 are grounded to provide a stable reference potential. Based on the aforementioned differential input branch structure, it can be seen that the first terminals of the second switch Q2 and the fourth switch Q4 are the core nodes for outputting the differential voltage after the differential signal is processed by the input transistors and the load impedance network.

[0090] In actual high-speed signal processing, due to the physical size and wiring layout of transistors, parasitic capacitances inevitably exist at the first terminals of the second switch Q2 and the fourth switch Q4. These parasitic capacitances produce a bypass effect when processing high-frequency signals, leading to high-frequency gain roll-off and thus limiting the overall bandwidth of the continuous-time linear equalizer. In this embodiment, the negative capacitive load circuit 90 is used to perform phase compensation on the differential voltage output from the first terminals of the second switch Q2 and the fourth switch Q4. Specifically, when the differential voltage is generated at the output node, the negative capacitive load circuit 90 senses the change in node voltage and generates a compensation current at its first and second terminals that is opposite in phase to the charging and discharging of conventional parasitic capacitors. This compensation mechanism is equivalent to a negative capacitor connected in parallel at the node in terms of macroscopic electrical characteristics.

[0091] By connecting a negative capacitive load circuit 90 between the first terminal of the second switch Q2 and the first terminal of the fourth switch Q4, the negative capacitive load circuit 90 adaptively performs phase compensation on the differential signal based on the node voltage change during the differential voltage output stage. This phase compensation directly cancels out part of the positive parasitic capacitance on the output node, significantly reducing the total equivalent capacitance of the output node. At the signal frequency domain processing level, the reduction in the node equivalent capacitance directly pushes the dominant pole that determines the bandwidth to a higher frequency range, thereby significantly improving the high-frequency gain performance of the differential signal and expanding the system bandwidth without requiring additional static bias current in each branch. Ultimately, this achieves a synergistic optimization of reduced power consumption and higher bandwidth.

[0092] According to the present invention, a continuous-time linear equalizer includes a negative capacitive load circuit 90 comprising: The first terminal of the fifth switch Q5 is connected to the first terminal of the second switch Q2; The first bias current source PD1 has its first terminal connected to the second terminal of the fifth switch Q5, and its second terminal is grounded. The first terminal of the sixth switch Q6 is connected to the first terminal of the fourth switch Q4. The second bias current source PD2 has its first terminal connected to the second terminal of the sixth switch Q6, and its second terminal is grounded. The first capacitor C has its first terminal connected to the first terminal of the first bias current source PD1, and its second terminal connected to the first terminal of the second bias current source PD2. Among them, the first end of the fifth switch Q5 is connected to the control end of the sixth switch Q6, and the first end of the sixth switch Q6 is connected to the control end of the fifth switch Q5.

[0093] Specifically, the first bias current source PD1 provides a stable bias current to the branch where the fifth switch Q5 is located, and the second bias current source PD2 provides a bias current to the branch where the sixth switch Q6 is located.

[0094] The first terminal of the fifth switch Q5 is connected to the control terminal of the sixth switch Q6, and simultaneously, the first terminal of the sixth switch Q6 is connected to the control terminal of the fifth switch Q5. This connection method creates a cross-coupled structure between the fifth switch Q5 and the sixth switch Q6. This cross-coupled pair of switches, together with the first capacitor C connected across their second terminals, forms an equivalent negative capacitor network.

[0095] When the differential signal causes a voltage change at the first terminals of the second switch Q2 and the fourth switch Q4 (i.e., the differential output node), this voltage change is fed back to the control terminals (gates) of the fifth switch Q5 and the sixth switch Q6 through the cross-coupled circuit. Due to the presence of the first capacitor C and the amplification effect of the cross-coupled transistors, looking into the negative capacitive load circuit 90 from the first terminals of the fifth switch Q5 and the sixth switch Q6, this circuit effectively presents a negative capacitance value under small AC signals. This equivalent negative capacitance is directly connected in parallel across the output nodes of the second switch Q2 and the fourth switch Q4.

[0096] The cross-coupling structure of the fifth switch Q5 and the sixth switch Q6, combined with the first capacitor C, generates an equivalent negative capacitance. This equivalent negative capacitance can physically cancel out or partially neutralize the parasitic capacitance accumulated at the differential output node (i.e., the first terminals of the second switch Q2 and the fourth switch Q4). Because the node parasitic capacitance is reduced, the dominant pole frequency of the circuit can be shifted towards higher frequencies. This mechanism allows the continuous-time linear equalizer to directly improve high-frequency gain performance and expand the overall bandwidth of the system without increasing the main current of the differential input branch (i.e., without increasing additional power consumption). This fundamentally solves the problem that traditional continuous-time linear equalizers often require increased current to increase bandwidth, leading to higher power consumption.

[0097] In some embodiments, the fifth switch Q5 and the sixth switch Q6 are NMOS.

[0098] According to the present invention, a continuous-time linear equalizer includes a bias voltage comprising a first bias sub-voltage and a second bias sub-voltage. The bias circuit 30 includes: The first bias sub-circuit 301 has its first terminal connected to the first power supply VDD, and is used to receive the first selection signal and output the first bias sub-voltage corresponding to the first selection signal. The third resistor R3 has its first end connected to the second end of the first bias sub-circuit 301. The second bias sub-circuit 302 has its first terminal connected to the second terminal of the third resistor R3. It is used to receive the second selection signal and output the second bias sub-voltage corresponding to the second selection signal. The second terminal of the second bias sub-circuit 302 is grounded.

[0099] Specifically, the first terminal of the first bias sub-circuit 301 is connected to the first power supply VDD, which is typically a high-level power supply node inside the device. The first bias sub-circuit 301 serves as a pull-up or high-voltage side adjustment unit for the bias voltage network, receiving a first selection signal and outputting a corresponding first bias sub-voltage based on the control of the first selection signal.

[0100] By changing the logic state or value of the first selection signal, the equivalent impedance or conduction path inside the first bias sub-circuit 301 will change, thereby determining the output level of the first bias sub-voltage.

[0101] The first terminal of the third resistor R3 is connected to the second terminal of the first bias sub-circuit 301, serving as a transition between voltage division and current limiting. The first terminal of the second bias sub-circuit 302 is connected to the second terminal of the third resistor R3, and the second terminal of the second bias sub-circuit 302 is grounded, which represents a connection to a low-level reference node inside the device. The second bias sub-circuit 302 acts as a pull-down or low-voltage side adjustment unit of the bias voltage network, receiving a second selection signal and outputting a corresponding second bias sub-voltage based on the control of the second selection signal.

[0102] When the electronic device receives a control command characterizing the current environment or process state, it sends a first selection signal and a second selection signal to the bias circuit 30, respectively. After receiving their respective selection signals, the first bias sub-circuit 301 and the second bias sub-circuit 302 are equivalent to selecting specific nodes in the bias branch. With the fixed voltage division effect of the third resistor R3, the required first bias sub-voltage and second bias sub-voltage are generated at the output nodes of the first bias sub-circuit 301 and the second bias sub-circuit 302, respectively, and then sent to the subsequent active inductor circuit for inductive characteristic configuration.

[0103] In this embodiment, the bias voltage is subdivided into a first bias sub-voltage and a second bias sub-voltage. A bias network consisting of a first bias sub-circuit 301, a third resistor R3, and a second bias sub-circuit 302 connected in series is introduced into the bias circuit 30. When the first and second selection signals are sent, the first bias sub-circuit 301 and the second bias sub-circuit 302 can change their respective conduction states in the bias branches according to the received signals. This structure, controlled at both ends and isolated by a third resistor R3, allows the bias circuit 30 to accurately convert the externally input digital selection signal into two interconnected and independently fine-tunable analog bias sub-voltages. This ultimately ensures that the subsequent active inductor circuit can obtain a highly matched multi-dimensional bias voltage input, allowing for more precise adjustment of the active inductor's inductance value. This, in turn, ensures that the circuit can output an AC frequency response curve that meets the high-frequency compensation requirements under different process, voltage, and temperature variations, significantly enhancing the robustness of the overall equalizer circuit.

[0104] According to the present invention, a continuous-time linear equalizer includes a first bias sub-circuit 301 comprising: M sequentially connected seventh switching transistors Q7, the first terminal of the first seventh switching transistor Q7 is connected to the first power supply VDD, the first terminal of the i-th seventh switching transistor Q7 is connected to the second terminal of the (i-1)-th seventh switching transistor Q7, the second terminal of the M-th seventh switching transistor Q7 is connected to the first terminal of the third resistor R3, and the control terminal of each seventh switching transistor Q7 is connected to its second terminal; M first conducting switches DK1, the first end of the M first conducting switches DK1 is connected one-to-one with the control end of the M seventh switching transistors Q7 connected in sequence, and the second end of the M first conducting switches DK1 is connected to be used to output the first bias sub-voltage. The first selection signal is used to select one or more of the M first conduction switches DK1 to conduct, so as to control the first bias sub-circuit 301 to output the first bias sub-voltage. M is a positive integer greater than or equal to 2, and i is less than or equal to M. The second bias sub-circuit 302 includes: N sequentially connected eighth switching transistors Q8, the first terminal of the first eighth switching transistor Q8 is connected to the second terminal of the third resistor R3, the first terminal of the j-th eighth switching transistor Q8 is connected to the second terminal of the (j-1)-th eighth switching transistor Q8, the second terminal of the N-th eighth switching transistor Q8 is grounded, and the control terminal of each eighth switching transistor Q8 is connected to its first terminal. N second conducting switches DK2, the first end of the N second conducting switches DK2 is connected one-to-one with the control end of the N sequentially connected eighth switching transistors Q8, and the second end of the N second conducting switches DK2 is used to output the second bias sub-voltage. The second selection signal is used to select one or more of the N second conduction switches DK2 to conduct, so as to control the second bias sub-circuit 302 to output the second bias sub-voltage. N is a positive integer greater than or equal to 2, and j is less than or equal to N.

[0105] Specifically, after M sequentially connected seventh switching transistors Q7 and M first conducting switches DK1 are connected, a diode-like connection structure is formed, thereby creating multiple voltage nodes with different voltage division levels throughout the series branch.

[0106] Where i and j are greater than or equal to 2.

[0107] When a certain first conducting switch DK1 receives the corresponding first selection signal and turns on, it is equivalent to selecting a certain branch node in the series branch of the seventh switch Q7, and the voltage division at that node is used as the first bias sub-voltage for output.

[0108] Corresponding to the architecture of the first bias sub-circuit 301, when the second selection signal controls one or more of the N second conduction switches DK2 to conduct, the voltage of a specific node is extracted from the voltage divider network formed by the eighth switch Q8 and output as the second bias sub-voltage.

[0109] For example, when M is 4, the first selection signal is {PSEL} <0> PSEL <1> PSEL <2> PSEL <3>}

[0110] For example, when N is 4, the second selection signal is {NSEL} <0> NSEL <1> NSEL <2> NSEL <3>}

[0111] In some embodiments, the seventh switch Q7 is a PMOS and the eighth switch Q8 is an NMOS.

[0112] In this embodiment, a series voltage divider network consisting of multiple seventh switches Q7 and eighth switches Q8 connected in sequence is introduced into the bias circuit 30. The bias voltage is extracted through a gating network consisting of a first on switch DK1 and a second on switch DK2. During signal processing and adjustment, the externally input first and second selection signals directly control the closing state of the on switches, enabling the circuit to switch precisely between different power supply voltage divider nodes. This structure, which combines series voltage divider with multiple switch gating, transforms the continuous analog bias voltage adjustment process into a discrete gating control process configurable by digital selection signals. This not only provides a multi-level, high-precision hardware adjustment basis for the generation of the first and second bias sub-voltages, but also allows the output bias voltage to be programmably switched in real time according to actual channel loss and process deviations. This ensures the accuracy of the control voltage supplied to the active inductor circuit, ultimately achieving precise compensation and highly robust control of the AC characteristics of the continuous-time linear equalizer.

[0113] According to the continuous-time linear equalizer provided by the present invention, the bias circuit 30 further includes a fourth resistor R4 and a ninth switch Q9, and the second terminal of the second bias sub-circuit 302 is grounded through the fourth resistor R4 and the ninth switch Q9. The first terminal of the fourth resistor R4 is connected to the second terminal of the second bias sub-circuit 302; The first terminal of the ninth switch Q9 is connected to the second terminal of the fourth resistor R4. The second terminal of the ninth switch Q9 is grounded. The control terminal of the ninth switch Q9 is connected to the first terminal of the fourth resistor R4 and the current source circuit 80, respectively.

[0114] In some embodiments, the ninth switch Q9 is an NMOS.

[0115] In this embodiment, the above connection method establishes a current tracking and mirroring mechanism between the bias circuit 30 and the differential input circuit. Since the control terminal of the ninth switch Q9 is connected to the current source circuit 80, a linkage is formed between the reference branch where the bias circuit 30 is located and the tail current source of the main circuit. The current flowing through the fourth resistor R4 and the ninth switch Q9 is affected by the operating state of the differential input branch, while the voltage drop across the fourth resistor R4 is fed back to the control terminal of the ninth switch Q9, forming a local voltage regulation and adaptive adjustment loop.

[0116] In this embodiment, by introducing a fourth resistor R4 and a ninth switch Q9 between the second bias sub-circuit 302 and ground, and connecting the control terminal of the ninth switch Q9 to the current source circuit 80 of the differential input circuit, a current tracking matching relationship is established between the bias circuit 30 branch and the differential signal processing main branch. This structure allows the bias voltage generated by the bias circuit 30 to sense and follow the fluctuations of the tail current of the main circuit in real time. When the circuit operating point shifts due to changes in process, voltage, and temperature, the ninth switch Q9 and the fourth resistor R4 work together to adaptively adjust the current distribution of the bias branch, thereby synchronously correcting the output bias voltage. This function, combined with the load characteristic adjustment process of the active inductor circuit, achieves precise locking and synchronous following of the bias state at the bottom level, ultimately greatly improving the robustness of the entire continuous-time linear equalizer in immature processes and extreme environments, and ensuring the accuracy and stability of the AC frequency response curve.

[0117] The present invention also provides an electronic device, comprising: Such as a continuous-time linear equalizer as any of the above.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A continuous-time linear equalizer characterized by, include: First active inductor circuit; Second active inductor circuit; A bias circuit is connected to the first active inductor circuit and the second active inductor circuit respectively, and is used to output a bias voltage to adjust the inductance characteristics of the first active inductor circuit and the second active inductor circuit. Adjustable resistance circuit; Adjustable capacitance circuit; The differential input circuit includes a first differential input branch and a second differential input branch. The first differential input branch is connected to a first active inductor circuit, and the second differential input branch is connected to a second active inductor circuit. An adjustable resistance circuit and an adjustable capacitance circuit are respectively connected between the first differential input branch and the second differential input branch. The differential input circuit is used to receive differential signals and output differential voltages corresponding to the differential signals based on the first active inductor circuit, the second active inductor circuit, the adjustable resistance circuit, and the adjustable capacitance circuit.

2. The continuous-time linear equalizer of claim 1, wherein, The differential input circuit also includes a current source circuit; The first differential input branch includes: The first switching transistor has a first terminal connected to the first connection terminal of the first active inductor circuit, and a second terminal connected to the current source circuit. The second switch has a first terminal connected to the second connection terminal of the first active inductor circuit, a second terminal connected to the current source circuit, and a control terminal connected to the control terminal of the first switch. The second differential input branch includes: The third switch is connected to the first connection terminal of the second active inductor circuit, and the second terminal of the third switch is connected to the current source circuit. The fourth switch has a first terminal connected to the second connection terminal of the second active inductor circuit, a second terminal connected to the current source circuit, and a control terminal connected to the control terminal of the third switch. The adjustable resistance circuit and the adjustable capacitance circuit are respectively connected between the second terminal of the second switch and the second terminal of the fourth switch.

3. The continuous-time linear equalizer of claim 2, wherein, The current source circuit includes: A first current source, the first end of which is connected to the second end of the first switching transistor and the second end of the third switching transistor respectively, and the second end of the first current source is grounded; A second current source, the first end of which is connected to the second end of the second switching transistor, and the second end of which is grounded; A third current source, wherein the first terminal of the third current source is connected to the second terminal of the fourth switching transistor, and the second terminal of the third current source is grounded; The control terminals of the first current source, the second current source, and the third current source are connected together.

4. The continuous-time linear equalizer of claim 2, wherein, The first active inductor circuit includes: The first main control switch transistor, the first end of the first main control switch transistor is connected to the first power supply; A first resistor, the first end of which is connected to the second end of the first main control switch and the first end of the first switch, and the second end of the first resistor is connected to the first end of the second switch. A first capacitance adjustment circuit, wherein the control connection terminal of the first capacitance adjustment circuit is connected to the bias circuit, the first output terminal of the first capacitance adjustment circuit is connected to the control terminal of the first main control switch, and the second output terminal of the first capacitance adjustment circuit is connected to the first terminal of the first switch. The first capacitance adjustment circuit adjusts the output voltage of the first output terminal and the second output terminal of the first capacitance adjustment circuit according to the bias voltage output by the bias circuit.

5. The continuous-time linear equalizer of claim 4, wherein, The bias voltage includes a first bias sub-voltage and a second bias sub-voltage; The first capacitance adjustment circuit includes: The first slave switch transistor, the first terminal of which is connected to the first power supply; The second slave switch has its first terminal connected to the second terminal of the first slave switch and the control terminal of the first master switch, respectively. The second terminal of the second slave switch is grounded, and the control terminal of the second slave switch is used to receive the second bias sub-voltage. The third slave switch has a first terminal connected to the control terminal of the first slave switch, and a second terminal connected to the first terminal of the first switch. The control terminal of the third slave switch is used to receive the first bias voltage.

6. The continuous-time linear equalizer according to claim 2, characterized in that, The second active inductor circuit includes: The second main control switch transistor, the first end of which is connected to the first power supply; The second resistor has its first end connected to the second end of the second main control switch and the first end of the third switch, and its second end is connected to the first end of the fourth switch. The second capacitance adjustment circuit has its control connection terminal connected to the bias circuit, its first output terminal connected to the control terminal of the second main control switch, and its second output terminal connected to the first terminal of the third switch. The second capacitance adjustment circuit adjusts the output voltage of the first output terminal and the second output terminal of the second capacitance adjustment circuit according to the bias voltage output by the bias circuit.

7. The continuous-time linear equalizer according to claim 6, characterized in that, The bias voltage includes a first bias sub-voltage and a second bias sub-voltage; The second capacitance adjustment circuit includes: The fourth slave switch transistor, wherein the first terminal of the fourth slave switch transistor is connected to the first power supply; The fifth slave switch has its first terminal connected to the second terminal of the fourth slave switch and the control terminal of the second master switch, respectively. The second terminal of the fifth slave switch is grounded, and the control terminal of the fifth slave switch is used to receive the second bias sub-voltage. The sixth slave switch is connected to the control terminal of the fourth slave switch, and the second terminal of the sixth slave switch is connected to the first terminal of the third switch. The control terminal of the sixth slave switch is used to receive the first bias sub-voltage.

8. The continuous-time linear equalizer according to claim 2, characterized in that, The adjustable resistance circuit includes: Multiple resistors are connected to a branch, the first end of each resistor connected to the branch is connected to the second end of the second switch, and the second end of each resistor connected to the branch is connected to the second end of the fourth switch. Each of the resistor access branches includes a degradation resistor, a first access switch, and a second access switch. The first terminal of the first access switch is connected to the second terminal of the second switch. The first terminal of the degradation resistor is connected to the second terminal of the first access switch. The first terminal of the second access switch is connected to the second terminal of the degradation resistor. The second terminal of the second access switch is connected to the second terminal of the fourth switch. The control terminal of the first access switch is connected to the control terminal of the second access switch. The first access switch and the second access switch are synchronously turned on or off according to the received resistance value control voltage, so as to control the degradation resistor to switch between the second terminal of the second switch and the second terminal of the fourth switch.

9. The continuous-time linear equalizer according to claim 2, characterized in that, The adjustable capacitance circuit includes: Multiple capacitors are connected to a branch, the first end of each capacitor connected to the branch is connected to the second end of the second switch, and the second end of each capacitor connected to the branch is connected to the second end of the fourth switch. Each of the capacitor access branches includes a degraded capacitor, a third access switch, and a fourth access switch. The first terminal of the third access switch is connected to the second terminal of the second switch transistor. The first terminal of the degraded capacitor is connected to the second terminal of the third access switch. The first terminal of the fourth access switch is connected to the second terminal of the degraded capacitor. The second terminal of the fourth access switch is connected to the second terminal of the fourth switch transistor. The control terminal of the third access switch is connected to the control terminal of the fourth access switch. The third access switch and the fourth access switch are synchronously turned on or off according to the received capacitance control voltage, so as to control the degraded capacitor to switch between the second terminal of the second switch and the second terminal of the fourth switch.

10. The continuous-time linear equalizer according to claim 2, characterized in that, The continuous-time linear equalizer also includes: A negative capacitance load circuit, wherein the first terminal of the negative capacitance load circuit is connected to the first terminal of the second switching transistor, the second terminal of the negative capacitance load circuit is connected to the first terminal of the fourth switching transistor, and the third and fourth terminals of the negative capacitance load circuit are grounded. The negative capacitive load circuit is used to perform phase compensation on the differential voltage output from the first terminal of the second switch and the first terminal of the fourth switch.

11. The continuous-time linear equalizer according to claim 10, characterized in that, The negative capacitance load circuit includes: The fifth switching transistor, wherein the first end of the fifth switching transistor is connected to the first end of the second switching transistor; A first bias current source, the first end of the first bias current source is connected to the second end of the fifth switch, and the second end of the first bias current source is grounded; A sixth switching transistor, wherein the first end of the sixth switching transistor is connected to the first end of the fourth switching transistor; The second bias current source has its first terminal connected to the second terminal of the sixth switch transistor, and its second terminal grounded. A first capacitor, wherein a first terminal of the first capacitor is connected to a first terminal of the first bias current source, and a second terminal of the first capacitor is connected to a first terminal of the second bias current source; The first end of the fifth switch is connected to the control end of the sixth switch, and the first end of the sixth switch is connected to the control end of the fifth switch.

12. The continuous-time linear equalizer according to any one of claims 1 to 11, characterized in that, The bias voltage includes a first bias sub-voltage and a second bias sub-voltage; The bias circuit includes: A first bias sub-circuit, wherein a first terminal of the first bias sub-circuit is connected to a first power supply, is used to receive a first selection signal and output a first bias sub-voltage corresponding to the first selection signal; The third resistor, the first end of which is connected to the second end of the first bias sub-circuit; The second bias sub-circuit has its first terminal connected to the second terminal of the third resistor. It is used to receive the second selection signal and output a second bias sub-voltage corresponding to the second selection signal. The second terminal of the second bias sub-circuit is grounded.

13. The continuous-time linear equalizer according to claim 12, characterized in that, The first bias sub-circuit includes: M seventh switching transistors are connected in sequence. The first terminal of the first seventh switching transistor in the M seventh switching transistors is connected to the first power supply. The first terminal of the i-th seventh switching transistor is connected to the second terminal of the (i-1)-th seventh switching transistor. The second terminal of the M-th seventh switching transistor in the M seventh switching transistors is connected to the first terminal of the third resistor. The control terminal of each seventh switching transistor is connected to its second terminal. M first conducting switches, the first terminals of the M first conducting switches are connected one-to-one with the control terminals of the M seventh switching transistors connected in sequence, and the second terminals of the M first conducting switches are connected to output the first bias sub-voltage. Wherein, the first selection signal is used to select one or more of the M first conduction switches to conduct, so as to control the first bias sub-circuit to output the first bias sub-voltage, where M is a positive integer greater than or equal to 2, and i is less than or equal to M; The second bias sub-circuit includes: N sequentially connected eighth switching transistors, the first terminal of the first eighth switching transistor in the N sequentially connected eighth switching transistors is connected to the second terminal of the third resistor, the first terminal of the j-th eighth switching transistor is connected to the second terminal of the (j-1)-th eighth switching transistor, the second terminal of the Nth eighth switching transistor in the N sequentially connected eighth switching transistors is grounded, and the control terminal of each eighth switching transistor is connected to its first terminal. N second conducting switches, the first end of the N second conducting switches is connected one-to-one with the control end of the N sequentially connected eighth switching transistors, and the second end of the N second conducting switches is used to output the second bias sub-voltage. The second selection signal is used to select one or more of the N second conduction switches to conduct, so as to control the second bias sub-circuit to output the second bias sub-voltage. N is a positive integer greater than or equal to 2, and j is less than or equal to N.

14. The continuous-time linear equalizer according to claim 12, characterized in that, The bias circuit further includes a fourth resistor and a ninth switch, and the second terminal of the second bias sub-circuit is grounded through the fourth resistor and the ninth switch; The first end of the fourth resistor is connected to the second end of the second bias sub-circuit; The first terminal of the ninth switch is connected to the second terminal of the fourth resistor, the second terminal of the ninth switch is grounded, and the control terminal of the ninth switch is connected to the first terminal of the fourth resistor and the current source circuit respectively.

15. An electronic device, characterized in that, include: The continuous-time linear equalizer as described in any one of claims 1 to 14.

Images