An edge-computing-based smart park super-converged integrated machine system

Abstract

This application provides a smart park hyperconverged integrated machine system based on edge computing. This integrated machine integrates a multi-mode heterogeneous communication interface unit, a protocol adaptive conversion module, an edge computing unit, and an instruction control unit. The protocol adaptive conversion module uses an FPGA and a protocol feature library to identify data frames of different communication protocols in real time at the data link layer, convert them into a unified data format, and then deliver them to shared memory via DMA zero-copy. The edge computing unit adopts a heterogeneous architecture of ARM and NPU, performing spatiotemporal alignment and multi-source data fusion analysis based on graph neural networks on the unified data, outputting a state vector. The instruction control unit is independent of the edge computing unit, generating control instructions based on the state vector and independently generating key control instructions in response to hard-wired signals from the IO input interface. This invention eliminates the problems of distributed device deployment and protocol incompatibility, reduces bandwidth consumption and construction costs, and improves system response speed and reliability.

Description

Technical Field

[0001] This invention relates to the fields of smart park and Internet of Things (IoT) technology, and more specifically, to a smart park hyper-converged integrated machine system based on edge computing. Background Technology

[0002] Currently, smart park management systems generally adopt a "distributed hardware + centralized platform" architecture. Specifically, security cameras, energy consumption sensors, access controllers, lighting controls, and other equipment are provided by different manufacturers and deployed independently. These devices lack direct data interaction channels, creating information silos. When conducting emergency response or routine management, administrators need to switch between multiple different system platforms, making cross-system coordinated control impossible. This results in low emergency response efficiency and high management complexity.

[0003] Furthermore, due to the large number of hardware equipment manufacturers and the lack of standardized communication protocols (such as Modbus, BACnet, ONVIF, etc.), existing systems typically require the deployment of numerous additional protocol conversion gateways to complete data interoperability. This not only increases equipment procurement costs and occupies data center space, but also causes data transmission delays due to multi-level gateway forwarding, affecting the issuance and execution speed of control commands.

[0004] On the other hand, the data processing of existing systems is highly dependent on cloud servers. A large amount of raw data needs to be uploaded to the cloud for processing and analysis, consuming a significant amount of network bandwidth. When network failures or fluctuations occur, local devices lack autonomous data processing and decision-making capabilities, which can easily lead to the paralysis of the entire control system, resulting in insufficient system stability and reliability.

[0005] On the other hand, the data processing of existing systems is highly dependent on cloud servers. A large amount of raw data needs to be uploaded to the cloud for processing and analysis, consuming a significant amount of network bandwidth. When network failures or fluctuations occur, local devices lack autonomous data processing and decision-making capabilities, which can easily lead to the paralysis of the entire control system, resulting in insufficient system stability and reliability.

[0006] Therefore, the existing technologies have many problems that urgently need to be solved, such as the information silos caused by the decentralized deployment of equipment, the increased cost and latency due to the need for additional gateways due to inconsistent protocols, and the vulnerability of data processing to network failures due to reliance on the cloud. Summary of the Invention

[0007] To address this, this application provides a smart park hyper-converged integrated machine system based on edge computing, which helps to solve the problems of existing smart park management and control systems, such as information silos caused by dispersed hardware deployment, increased costs and latency due to inconsistent protocols requiring additional gateways, and data processing relying on the cloud which is prone to paralysis due to network failures, resulting in high construction costs, slow response speeds and poor stability.

[0008] To achieve the above objectives, this application adopts the following technical solution:

[0009] This application provides a smart campus hyperconverged integrated machine system based on edge computing, including: A multimode heterogeneous communication interface unit includes a wired access part and a wireless access part. The multimode heterogeneous communication interface unit is configured to access sensing devices and control devices and output data frames; wherein, the data frames carry the output data of the sensing devices and control devices. The protocol adaptive conversion module includes: an FPGA chip and a preset protocol feature library. The input end of the protocol adaptive conversion module is connected to the output end of the multi-mode heterogeneous communication interface unit, and is configured to identify the communication protocol of the data frame in real time at the data link layer, convert it into a predetermined unified data format, and deliver it to the shared memory through a DMA channel with zero copy. The edge computing unit adopts a heterogeneous architecture of ARM processor and NPU. The input end of the edge computing unit is connected to the shared memory and is configured to read data in a predetermined unified data format from the shared memory, perform spatiotemporal alignment and multi-source data fusion analysis based on graph neural network, and output the fused state vector; wherein, the fused state vector represents the comprehensive status of each area and each device in the park. The instruction control unit, independent of the edge computing unit, has its first input terminal connected to the output terminal of the edge computing unit to receive the state vector, its state input terminal for connecting to an external I / O input interface, and its control output terminal for connecting to an external execution device. The instruction control unit is configured to generate control instructions based on the state vector, and to independently generate key control instructions based on the hard-wired signals of the IO input interface. This application employs the above technical solution and possesses at least the following beneficial effects: 1. Reduce construction costs and complexity By integrating a multi-mode heterogeneous communication interface unit, a protocol adaptive conversion module, an edge computing unit, and an instruction control unit into a single industrial-grade fanless chassis, this invention replaces multiple devices such as protocol conversion gateways, edge servers, PLC controllers, and network switches that are distributed in traditional solutions with a single hardware device. This integrated design significantly reduces the number of hardware devices, simplifies cabling, lowers equipment procurement costs and server room space requirements, while also making subsequent maintenance easier and resolving the issue of protocol inconsistencies.

[0010] 2. Improve command response speed This invention employs FPGA hardware to implement protocol identification and conversion, reducing processing latency from milliseconds to microseconds—a three-order-of-magnitude improvement—from milliseconds in traditional software gateways. A two-stage parallel matching structure using Bloom filters and hash indexes, combined with multiple parallel processing channels, allows data from each interface to be processed independently and simultaneously. The converted data is delivered to shared memory via a DMA channel with zero-copy delivery, without consuming CPU resources, effectively separating the data plane from the control plane. Critical events are directly triggered by hardware interrupts to respond to associated devices, achieving microsecond-level response times and significantly improving instruction execution speed.

[0011] 3. Enhance system stability and reliability The instruction control unit employs a dual-path design: the regular path performs fine-grained control based on the state vector output by the edge computing unit; the emergency path, via a hardware interrupt link, directly responds to hard-wired signals and independently executes critical control operations in the event of an edge computing unit malfunction or network interruption. A hardware watchdog automatically performs a hardware reset when the MCU crashes, enabling the system to self-heal. This design ensures that critical safety functions can still be executed normally under extreme conditions (such as main system crashes or network failures), providing the system with network outage operation capability and high availability.

[0012] 4. Saves cloud bandwidth resources The edge computing unit uses a data distillation mechanism to upload only the fused summary information and feature samples to the cloud, while the original video stream and sensor time-series data are stored locally in a loop. This reduces the daily data upload volume from approximately 50GB in the original solution to less than 200MB, and bandwidth usage is reduced by over 99%. Simultaneously, the local rule engine and lightweight decision model can still operate completely during network outages, ensuring system availability under network interruption conditions.

[0013] 5. Break down information silos and enhance the level of intelligence. Through unified hardware-level access and adaptive protocol conversion, this invention achieves seamless access for devices from different manufacturers and using different protocols. A multi-source data fusion method based on graph neural networks constructs heterogeneous temporal graph neural networks for each device within the park. Node types include sensing nodes, identity nodes, spatial nodes, and execution nodes, and edges include physical spatial edges and logically related edges. Message passing and state update mechanisms enable the state of each node to incorporate neighbor information, upgrading the traditional rule-based "If-Then" rigid linkage to a context-state-based "soft linkage" decision-making. Experimental data shows that in scenarios such as personnel tailing, cross-camera tracking, and energy consumption anomaly tracing, the recognition accuracy is improved by more than 40% compared to single-sensor logic, and the false alarm rate is reduced by 60%.

[0014] 6. Possesses protocol self-learning and online expansion capabilities. This invention achieves online adaptive recognition of unknown proprietary protocols through a closed-loop mechanism of "local feature extraction - cloud-based deep inference - hardware feature library hot update". The cloud employs a hybrid model of one-dimensional convolutional neural networks and gated recurrent units to perform deep protocol reverse analysis on data packets, automatically generating parsing templates. The FPGA uses a dual-buffer mechanism to load new feature libraries during frame idle intervals and atomically switch at frame boundaries, achieving online hot updates of the hardware feature library. This feature enables the all-in-one machine to have excellent protocol scalability in complex industrial environments, avoiding the drawbacks of traditional gateways requiring hardware replacement for protocol upgrades.

[0015] In summary, this invention effectively solves the problems of high cost, low efficiency, and poor stability caused by the dispersed deployment of equipment, protocol incompatibility, and reliance on cloud processing in existing technologies through technological innovations such as hardware integration, FPGA hardware acceleration, edge intelligence fusion, and dual-path reliable control. It has significant technological progress and application value in the field of smart park construction.

[0016] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram illustrating the composition of a smart park hyperconverged integrated machine system based on edge computing, according to an exemplary embodiment. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be described in detail below. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other implementation methods obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] Please see Figure 1 , Figure 1 This is a schematic diagram illustrating the composition of a smart park hyperconverged integrated machine system based on edge computing, according to an exemplary embodiment. The system includes: The multi-mode heterogeneous communication interface unit 10 includes a wired access part and a wireless access part, configured to access sensing devices and control devices, and output data frames; The protocol adaptive conversion module 20 is composed of an FPGA chip and a preset protocol feature library. Its input end is connected to the output end of the multi-mode heterogeneous communication interface unit 10. It is configured to identify the communication protocol of the data frame in real time at the data link layer, convert it into a predetermined unified data format, and deliver it to the shared memory through a DMA channel with zero copy. Edge computing unit 30 adopts a heterogeneous architecture of ARM processor and NPU. Its input is connected to the shared memory and configured to read data in the predetermined unified data format from the shared memory, perform spatiotemporal alignment and multi-source data fusion analysis based on graph neural network, and output the fused state vector. The instruction control unit 40 is independent of the edge computing unit 30. Its first input terminal is connected to the output terminal of the edge computing unit 30 to receive the state vector. Its state input terminal is used to connect to an external IO input interface, and its control output terminal is used to connect to an external execution device. The instruction control unit 40 is configured to generate control instructions based on the state vector, and to independently generate key control instructions based on the hard-wired signals of the IO input interface.

[0021] Example 1 This embodiment provides a smart park hyperconverged integrated machine system based on edge computing. The system integrates a multi-mode heterogeneous communication interface unit 10, a protocol adaptive conversion module 20, an edge computing unit 30, and an instruction control unit 40 into the same industrial-grade fanless chassis, forming a single hardware device.

[0022] In practical deployment, this integrated system can be installed in the park's low-voltage equipment room or low-voltage well. The multi-mode heterogeneous communication interface unit 10 connects to various sensing and control devices within the park via wired and wireless means, including security cameras, energy consumption sensors, access controllers, lighting circuits, smoke detectors, etc. The multi-mode heterogeneous communication interface unit 10 outputs the data frames from these devices to the protocol adaptive conversion module 20.

[0023] The protocol adaptive conversion module 20 consists of an FPGA chip and a preset protocol feature library, and its input is connected to the output of the multi-mode heterogeneous communication interface unit 10. When a data frame is received, the FPGA identifies the communication protocol type of the data frame in real time at the data link layer, converts it into an internally predetermined unified data format, and delivers it to the shared memory in a zero-copy manner through the DMA channel.

[0024] The edge computing unit 30 adopts a heterogeneous architecture of ARM processor and NPU (Neural Processing Unit). Its input is connected to shared memory, reading data in a unified format from the shared memory. The edge computing unit 30 performs spatiotemporal alignment of the data and performs multi-source data fusion analysis based on graph neural networks, finally outputting a fused state vector. This state vector reflects the comprehensive status of various areas and devices within the park, such as "suspected personnel are following near Gate 3 in Area A" or "abnormal increase in energy consumption in Area B".

[0025] It should be noted that the heterogeneous architecture of ARM processor and NPU can leverage the respective strengths of ARM in complex logic control and NPU in high-parallel matrix operations: NPU hardware-accelerated graph neural network multi-source data fusion and video stream analysis reduce end-to-end processing latency to the millisecond level, while freeing up ARM core resources to ensure the stable operation of critical tasks such as protocol management, data distillation and interrupt response. This enables real-time intelligent decision-making at the edge in low-power, fanless industrial environments, significantly reducing reliance on cloud computing power and network bandwidth usage, and ensuring that the system still has complete autonomous analysis and control capabilities even when the network is down.

[0026] The instruction control unit 40 is independent of the edge computing unit 30. Its first input terminal is connected to the output terminal of the edge computing unit 30 to receive the state vector. Its state input terminal is connected to an external I / O input interface (such as the hardwired output of a smoke detector), and its control output terminal is connected to an external actuator (such as a door lock, alarm light, air conditioner, etc.). The instruction control unit 40 is configured with two parallel control paths: on the one hand, it generates regular control commands based on the state vector output by the edge computing unit 30; on the other hand, it independently generates critical control commands based on the hardwired signals of the I / O input interface, ensuring that critical safety functions can still be executed normally when the edge computing unit 30 malfunctions or the network is interrupted.

[0027] Furthermore, by integrating the four functional modules into a single chassis, hardware replacement of traditionally distributed protocol conversion gateways, edge servers, PLC controllers, and other equipment is achieved, significantly reducing the number of devices and cabling work, lowering procurement costs and data center space requirements. Simultaneously, the dual-path design of the instruction control unit 40 ensures that critical security functions can still be executed independently in the event of an malfunction in the edge computing unit 30 or network interruption, improving system reliability and emergency response capabilities.

[0028] Example 2 This embodiment provides a detailed description of the multimode heterogeneous communication interface unit 10. Specifically, the multimode heterogeneous communication interface unit 10 includes a wired access section and a wireless access section. The wired access section includes multiple industrial serial interfaces (such as RS485 / RS232) and multiple Ethernet interfaces, of which at least some Ethernet interfaces support PoE power supply. In actual deployment, four RS485 serial interfaces are used to connect traditional industrial equipment such as electricity meters, water meters, and access control controllers; eight RJ45 Ethernet interfaces are used to connect devices such as network cameras, IP access control systems, and wireless APs, while simultaneously powering these devices via PoE, simplifying the cabling process.

[0029] The wireless access component includes at least a Wi-Fi 6 module, a Zigbee 3.0 coordinator module, and a LoRa gateway module for connecting wireless terminals and low-power sensors. For example, the Wi-Fi 6 module supports high-density mobile terminal access, the Zigbee module is used for self-organizing network access of temperature and humidity sensors, smoke sensors, etc., and the LoRa module is used to connect long-distance outdoor water meters, gas meters, and other devices.

[0030] All wired interfaces are connected to an internal high-speed data bus (such as the PCIe bus), while the wireless module is connected to the main control system via a peripheral bus (such as USB or SDIO).

[0031] The system also includes a multi-protocol concurrent driver manager, which runs on the ARM core's real-time operating system layer. This manager includes an interface abstraction layer, a clock synchronization unit, and a timestamp engine. The interface abstraction layer is implemented as a set of device drivers within the real-time operating system. Each physical interface corresponds to an independent driver instance, and each driver instance provides a unified registration interface and data transmission / reception callback functions, encapsulating the underlying hardware differences within the driver. The clock synchronization unit is implemented as a hardware timer module within the FPGA. This timer is driven by the FPGA's system clock, providing a 64-bit counter with a counting accuracy of 1 nanosecond. It is mapped to the ARM's memory address space via the PCIe bus for the ARM core to read. Simultaneously, this hardware timer broadcasts a global clock to each parallel processing channel within the FPGA. The timestamp engine is implemented as a set of hardware logic within the FPGA, configured at the entry point of each parallel processing channel. When a data packet is received from any interface, the corresponding parallel processing channel immediately captures the current global hardware clock value before the data packet enters the frame boundary detection unit and appends this value as a hardware timestamp to the header of the data packet. When reading data packets, the driver instance in the interface abstraction layer simultaneously obtains the data packet content and its accompanying hardware timestamp from the FPGA's circular buffer, encapsulates both into a unified format, and delivers them to the upper layer.

[0032] With the above structure, data packets from different physical interfaces are assigned nanosecond-level timestamps under the same time base when they enter the system, laying a high-precision time synchronization foundation for subsequent multi-source data fusion processing.

[0033] Example 3 The protocol adaptive conversion module 20 includes an FPGA chip and a protocol feature library storage unit. The FPGA chip internally includes a first processing unit, multiple parallel processing channels, a frame boundary detection unit, a protocol parsing and conversion unit, and a DMA controller.

[0034] The protocol feature library storage unit is configured in the FPGA's BlockRAM and is used to store the protocol features of various industrial IoT protocols and their corresponding parsing templates. The protocol feature library pre-configures features for at least the following protocols: industrial control protocols such as Modbus RTU, Modbus TCP, BACnet MSTP, BACnet IP, PROFINET, and EtherCAT; video and security protocols such as ONVIF, RTSP, and GB / T28181; and IoT communication protocols such as MQTT, CoAP, and LwM2M. The feature vector for each protocol includes a frame header identifier, a frame trailer or checksum feature, the position of the length field, and a protocol type identifier. The parsing template corresponding to each protocol feature includes a field mapping table and a checksum algorithm identifier. The field mapping table maps specific offsets in the protocol data frame to corresponding fields in the internal unified data model, and the checksum algorithm identifier indicates which hardware checksum unit the FPGA uses to perform integrity checks on the data frame.

[0035] The first processing unit is configured in the FPGA's BlockRAM and consists of a hash index module and a Bloom filter module connected in series to form a two-stage parallel matching structure. The output of the Bloom filter module is connected to the input of the hash index module. The matching process is as follows: First, the Bloom filter module uses multiple independent hash functions to perform parallel hash calculations on the header features of the data frame, mapping the calculation results to its bit array to quickly eliminate protocol types that cannot be matched, outputting a candidate protocol set. Then, the hash index module performs precise comparisons on the complete feature vectors of the data frames within this candidate protocol set to locate the specific protocol type. The output of the Bloom filter module is connected to the input of the hash index module, forming a two-stage parallel matching structure. The fast filtering capability of the Bloom filter reduces the number of comparisons performed by the hash index module, thereby achieving high-throughput real-time protocol identification within the limited logic resources of the FPGA. In actual operation, multiple parallel processing channels correspond to different physical interfaces, and the input of each channel is connected to the multi-mode heterogeneous communication interface unit 10, independently receiving data frames from the corresponding interface. Taking the Modbus RTU protocol as an example, when the RS485 interface receives a data frame, the corresponding parallel processing channel sends the frame to the frame boundary detection unit. The frame boundary detection unit defines the frame boundary by detecting the idle time between frames.

[0036] Specifically, multiple parallel processing channels are implemented by instantiating independent processing modules for each physical interface type using a hardware description language within the FPGA. Each processing module contains dedicated frame boundary detection logic, protocol matching logic, and format conversion logic. The modules are isolated from each other and run in parallel, together forming the multiple parallel processing channels.

[0037] After frame boundaries are defined, the first input of the protocol parsing and conversion unit receives the data frame, and its second input is connected to the output of the protocol feature library storage unit. The matching process is as follows: First, the Bloom filter module performs parallel hash calculations on the frame header features of the data frame and the frame header features of all protocols in the protocol feature library to quickly eliminate protocol types that cannot be matched; then, the hash index module performs a precise comparison of the complete features of the data frame in the candidate protocol set initially matched by the Bloom filter to accurately locate the protocol type.

[0038] Upon successful matching, the protocol parsing and conversion unit extracts the payload from the data frame based on the parsing template corresponding to the matched protocol characteristics and fills it into a predetermined unified data format. This unified data format includes fields such as device identifier, hardware timestamp, data type, value, and quality stamp. The converted data is directly written to the ARM shared memory via the DMA controller, achieving zero-copy forwarding. The entire process is completed by FPGA hardware, without consuming ARM core CPU resources, and the conversion latency is controlled at the microsecond level, which is three orders of magnitude faster than traditional software gateways.

[0039] Example 4 When a new private protocol device is added to the park, the protocol adaptive conversion module 20 cannot recognize the data frames of that device. At this time, the protocol self-learning unit starts the self-learning process.

[0040] The input of the matching result monitoring module is connected to the Bloom filter module in the first processing unit to monitor the matching results of the Bloom filter in real time. When the Bloom filter determines that multiple data frames (e.g., three consecutive frames) cannot match the existing feature library, the matching result monitoring module outputs a continuous matching failure signal to the trigger module. In response to this signal, the trigger module generates an unknown protocol capture event.

[0041] The input of the feature pre-extraction engine is connected to the output of multiple parallel processing channels, and its enable is connected to the output of the trigger module. When an unknown protocol capture event is received, the feature pre-extraction engine extracts the statistical features (such as frame length distribution and byte entropy), structural features (such as fixed frame header and check bit type), and temporal features (such as inter-frame arrival interval) of the data frame, and encapsulates the extracted features with the first byte of the data frame into an unknown protocol data packet.

[0042] The input of the upload interface connects to the output of the feature pre-extraction engine, and its output connects to the cloud via a separate secure channel (such as a TLS 1.3 encrypted channel). The upload interface uploads unknown protocol data packets to the cloud protocol analysis service.

[0043] A hybrid model combining a one-dimensional convolutional neural network and a gated recurrent unit (ROU) is deployed in the cloud for deep reverse engineering of unknown protocol data packets. The model's input includes the original data frame byte sequence (first 256 bytes) uploaded from the FPGA and pre-extracted shallow feature vectors. The model structure is as follows: a three-layer one-dimensional convolutional neural network with kernel sizes of 3, 5, and 7, each layer containing 64 filters to extract correlation features of local bytes in the data frame; a two-layer gated recurrent unit with a hidden layer dimension of 128 to capture long-range dependencies in the byte sequence; a feature fusion layer concatenating the shallow feature vectors with the output of the gated recurrent unit to form a comprehensive feature vector; and an output layer that outputs the protocol type probability distribution through a fully connected layer and Softmax, while simultaneously using an attention mechanism to locate the start and end positions of key fields in the data frame.

[0044] The model is trained using supervised learning, with training data derived from publicly available industrial protocol datasets (such as standard communication samples from Modbus, BACnet, and ONVIF) and user-uploaded private protocol samples, enabling the model to master general protocol reverse engineering capabilities. When receiving unknown protocol data packets from an FPGA, the model outputs the most likely protocol type and, through an attention mechanism, outputs the position index of key fields (such as frame header, length field, data field, and checksum field) within the data frame.

[0045] Based on the protocol type and key field locations output by the model, the cloud automatically generates a parsing template using a rule engine. The parsing template contains three parts: a feature matching vector, which is a feature fingerprint extracted from the original data frame for fast matching using a Bloom filter; a field mapping table, which maps specific offsets in the protocol data frame to fields in the unified data model within this invention (such as device identifier, data type, value, etc.); and a verification algorithm identifier, indicating the type of verification algorithm used by the protocol (such as CRC-16, CRC-32, LRC, or no verification), used for selecting the FPGA hardware verification unit.

[0046] The input of the receiving interface is connected to the cloud, and its output is connected to the protocol feature library storage unit. The receiving interface receives the parsing template returned by the cloud and loads the parsing template into the protocol feature library storage unit.

[0047] To achieve uninterrupted online updates, the FPGA employs a dual-buffer mechanism: the protocol feature library storage unit is physically divided into two independent storage areas, denoted as Buffer A and Buffer B. The currently used protocol feature library (e.g., Buffer A) is used for normal protocol identification and conversion services. When a new parsing template is received, the receiving interface loads the template into the backup buffer (Buffer B) and performs an integrity check. After the check passes, the FPGA, upon detecting the end of the current frame boundary (i.e., the frame idle gap where the current data frame has been processed and the next frame has not yet started), switches the pointers of the primary and backup buffers through an atomic operation, making Buffer B the new working area and Buffer A the backup area. The entire process is completed within microseconds, without interrupting any ongoing protocol conversion services.

[0048] After this, the data frames of the proprietary protocol device can be correctly identified and converted. For protocols with low identification confidence, the system supports manual verification or re-analysis after supplementing samples, gradually improving the protocol feature library.

[0049] This embodiment achieves online adaptive identification and automatic template generation for unknown private protocols through a closed-loop mechanism of "local feature extraction - cloud deep inference - hardware feature library hot update". It can dynamically expand protocol support capabilities without manual protocol analysis or downtime upgrades, significantly improving the protocol compatibility and scalability of the system.

[0050] Example 5 The edge computing unit 30 adopts a heterogeneous architecture of ARM processor and NPU (Neural Processing Unit), and includes a spatiotemporal alignment unit, a video analysis unit, a graph structure construction unit, a graph neural network processing unit, a decision execution unit, a data distillation unit, and an interrupt response module.

[0051] The spatiotemporal alignment unit's input is connected to shared memory to read data in a predefined uniform data format. For each data packet, the spatiotemporal alignment unit adds a hardware timestamp with a precision of 1 millisecond and establishes a spatiotemporal index based on the device coordinates of the data source (entered during device configuration), outputting uniform data with the spatiotemporal index.

[0052] The input of the video analytics unit is connected to the output of the spatiotemporal alignment unit. For video stream data, the video analytics unit performs frame-by-frame analysis via the NPU to extract structured information, such as person IDs, motion trajectories, and behavioral actions. The video analytics unit aligns this structured information with sensing device data (such as access control card swipe records and infrared sensor trigger signals) under the same spatiotemporal index within the same time window (e.g., 500 milliseconds), and outputs the aligned multi-source data.

[0053] The input of the graph structure construction unit is connected to the output of the video analysis unit, and a heterogeneous temporal graph neural network is constructed based on aligned multi-source data. In this graph neural network, node types include perception nodes (such as smoke detectors, temperature and humidity sensors), identity nodes (such as access control card swipe records, facial IDs), spatial nodes (such as rooms, corridors, and floors), and execution nodes (such as air conditioners, lighting, and broadcasting). Edges include physical spatial edges and logical association edges: physical spatial edges are constructed according to the spatial hierarchy of the devices, with each device node within the same space connected to the next, and the edge weight inversely proportional to the physical distance between the devices; logical association edges are constructed based on business rules or the temporal correlation of events between two devices statistically analyzed through FPGA.

[0054] The input of the graph neural network processing unit is connected to the output of the graph structure building unit, and is used to run heterogeneous temporal graph neural networks. This processing unit includes a node state storage module, a message passing module, a node state update module, and a state write-back module.

[0055] The node state storage module stores the current state vector of each node. The message passing module runs on the ARM core. Its first input is connected to the output of the graph structure building unit, and its second input is connected to the output of the node state storage module. Based on the edges in the graph structure, it collects the state vectors from the neighboring nodes of each node and aggregates them to generate the neighbor message vectors of each node.

[0056] The node state update module runs on the NPU. Its first input is connected to the output of the node state storage module, and its second input is connected to the output of the message passing module. It fuses the current state vector of each node with the corresponding neighbor message vector, and generates a new state vector after processing by a time-series state update model (such as a gated loop unit).

[0057] The input of the state write-back module is connected to the output of the node state update module, and its output is connected to the input of the node state storage module, writing the new state vector back to the node state storage module.

[0058] The node state storage module, message passing module, node state update module, and state write-back module form an iterative update loop. Each time the message passing module and node state update module complete a neighbor message aggregation and state update, the state vector in the node state storage module is updated once. After a preset number of iterations (e.g., K=3 layers), the state vector of each node has incorporated the information of its K-hop neighbors, and the state vector stored in the node state storage module is output as the fused state vector.

[0059] The input of the decision execution unit is connected to the output of the graph neural network processing unit. It receives the fused state vector, inputs it into the local rule engine (based on the Rete algorithm) and the lightweight decision model (such as XGBoost), generates control commands, and outputs the control commands and the fused state vector.

[0060] The first input of the data distillation unit is connected to the output of the graph neural network processing unit, and its second input is connected to the output of the decision execution unit, receiving the fused state vector and control commands. The data distillation unit uploads the summary information from the fused state vector (such as "a person tailgating incident occurred at Gate 3 in Area A") and feature samples from the control commands to the cloud for remote monitoring and model training; the original video stream and sensor time-series data are stored locally in a cyclical overlay manner, with a retention period of 30 days. Through this data distillation mechanism, the daily data upload volume is reduced from approximately 50GB in the original scheme to less than 200MB, reducing bandwidth usage by more than 99%, and the local decision engine can still operate completely when the network is interrupted.

[0061] The input of the interrupt response module is connected to the output of the decision execution unit, and its output is connected to the execution device. The interrupt response module is used to handle critical events (such as fire alarms and security intrusions). When the control commands output by the decision execution unit involve critical events, the interrupt response module directly triggers the real-time response of the associated device through the hardware interrupt path, and uses the fusion results of the graph neural network processing unit for subsequent confidence correction and multi-round linkage decision-making to ensure millisecond-level response in critical scenarios.

[0062] This embodiment achieves deep correlation analysis of multi-source data and local intelligent decision-making through the collaborative work of spatiotemporal alignment, graph neural network fusion, decision execution, data distillation, and interruption response. It reduces bandwidth consumption while ensuring system availability under network outage conditions, and significantly improves the intelligence level of park management and emergency response capabilities.

[0063] The graph structure building unit includes a spatial edge building module, a logical edge building module, and a relational graph convolution processing module.

[0064] The input of the spatial edge construction module is connected to the output of the video analytics unit. The spatial edge construction module constructs physical spatial edges based on the spatial hierarchy of the devices. For example, edge connections are established between smoke sensors, temperature and humidity sensors, and lighting controllers in the same room. The edge weight is inversely proportional to the physical distance between the devices; the closer the nodes are, the higher their weight.

[0065] The input of the logic edge construction module is connected to the output of the video analysis unit and to the event statistics output of the FPGA. The logic edge construction module constructs logical association edges based on business rules (such as "lighting circuits are controlled by energy consumption collection points in this area") or through the temporal correlation of events between two devices statistically analyzed by the FPGA (such as the high temporal correlation between access control card swiping events and nearby camera capture events).

[0066] The inputs of the graph convolution processing module are connected to the outputs of the spatial edge construction module and the logical edge construction module, respectively. The graph convolution processing module employs a variant of the graph convolutional network, setting independent weight transformation matrices for different types of edges (physical spatial edges, logically related edges) to generate graph structure data and output it to the graph neural network processing unit. This design enables the graph neural network to learn the different effects of different types of edges on node state fusion, improving fusion accuracy.

[0067] Example 7 The interrupt response module includes an event type register, an event monitoring unit, and a hardware interrupt controller.

[0068] The event type register stores preset real-time response event types, such as "fire alarm," "illegal intrusion," and "emergency button pressed." The first input of the event monitoring unit is connected to the output of the decision execution unit, and its second input is connected to the event type register. The event monitoring unit monitors the control commands output by the decision execution unit in real time and compares the event type of the control commands with the real-time response event types stored in the event type register. When a match is found, the event monitoring unit generates an interrupt trigger signal.

[0069] The input of the hardware interrupt controller is connected to the output of the event monitoring unit, and its output is connected to the execution device. Responding to an interrupt trigger signal, the hardware interrupt controller bypasses the operating system and directly drives the associated execution device. For example, when a "fire alarm" event is detected, the hardware interrupt controller directly drives the access control controller to unlock all access points, activates the broadcast system to play evacuation instructions, and forces the elevator to land. The entire process does not rely on the operating system's scheduling, ensuring that critical linkages continue to execute reliably even when the edge computing unit's 30 CPUs are fully loaded or the system crashes.

[0070] Example 8 The instruction control unit 40 includes an MCU, a finite state machine storage unit, a rule matching engine, an instruction generation unit, and a hardware interrupt link.

[0071] The first input terminal of the MCU is connected to the output terminal of the decision execution unit in the edge computing unit 30 to receive the state vector; its control output terminal is connected to the relay output interface and the infrared transmission interface to drive the execution device; its state input terminal is connected to the IO input interface to receive hard-wired signals.

[0072] The finite state machine storage unit is configured inside the MCU to store preset linkage rules compiled into a finite state machine. For example, the fire linkage rule is compiled as follows: when the IO input interface receives a smoke alarm signal, the following actions are executed in sequence: unlocking the access control, broadcasting evacuation, emergency elevator descent, and cutting off non-fire-fighting power.

[0073] The first input of the rule matching engine is connected to the first input of the MCU, and its second input is connected to the output of the finite state machine storage unit. The rule matching engine matches the received state vector with preset linkage rules to generate a matching result. The input of the instruction generation unit is connected to the output of the rule matching engine, and its output is connected to the control output of the MCU. Based on the matching result, it generates control instructions and drives the execution device through the control output.

[0074] The first input of the hardware interrupt link is connected to the I / O input interface, and its output is connected to the interrupt pin of the MCU. When a hardwired signal (such as the 24V level signal of a smoke detector) is connected to the I / O input interface, the hardware interrupt link simultaneously routes this signal to the interrupt pin of the MCU. When the MCU detects that the interrupt pin has been triggered, it suspends the currently executing rule matching and instruction generation process and executes the hardware interrupt service routine. In this interrupt service routine, the MCU directly reads the key linkage rule corresponding to the hardwired signal from the finite state machine memory unit and drives the execution device.

[0075] Through this dual-path design, the instruction control unit 40 can perform refined control based on the intelligent state vector output by the edge computing unit 30, and in emergency situations, it can bypass all software processing through hard-wired signals and directly execute critical control, thus achieving a balance between intelligence and high reliability.

[0076] Example 9 To further improve the reliability of the instruction control unit 40, this embodiment describes the specific implementation of the hardware watchdog.

[0077] The hardware watchdog is an independent hardware timer. Its monitoring pin is connected to the heartbeat output of the MCU, and its reset pin is connected to the MCU's reset pin. During normal system operation, the MCU outputs a pulse signal from the heartbeat output at a preset period (e.g., every 50 milliseconds), which is the "feeding the watchdog" operation, continuously clearing the internal timer of the hardware watchdog and keeping it in an untriggered state. The hardware watchdog has a preset timeout period (e.g., 200 milliseconds). If no heartbeat signal is received from the MCU within this time, the MCU is considered to be malfunctioning.

[0078] When the MCU fails to output a heartbeat signal due to software crashes, program malfunctions, or external electromagnetic interference, the hardware watchdog timer resets to zero, triggering a reset operation. The hardware watchdog outputs a reset pulse to the MCU via the reset pin, forcing the MCU to perform a hardware reset. After the MCU resets, it reinitializes all registers, peripheral interfaces, and internal states, and begins executing the program from the preset start address, automatically restoring the system to normal operation.

[0079] The hardware watchdog and hardware interrupt link complement each other: the hardware interrupt link ensures that external hardwired signals (such as smoke alarms) can still be responded to immediately when the MCU is busy or partially abnormal; the hardware watchdog ensures that the MCU can automatically reset and recover in the event of a complete system crash. The two work together to ensure that the instruction control unit 40 can maintain reliable operation under various abnormal conditions.

[0080] Through the above design, the instruction control unit 40 has self-recovery capability. Even in the event of extreme abnormalities (such as MCU crash), the system can automatically recover without manual intervention, which significantly improves the overall reliability of the smart park management and control system.

[0081] The following describes the operation process of the present invention in a specific scenario.

[0082] Scenario 1: Person Tail-Following Detection and Response On a weekday after get off work, a tailgating incident occurred at Gate 3 of Area A in the smart park. The access control system reported card swipe records, infrared sensors in the corridor detected two people passing through, and cameras in the corresponding area captured video streams.

[0083] The wired access portion of the multi-mode heterogeneous communication interface unit 10 receives Modbus RTU data frames from the access controller via an RS485 interface and receives ONVIF video streams from the camera via an Ethernet interface; the wireless access portion receives data frames from the infrared sensor via a Zigbee coordinator. Data frames from each interface enter their corresponding parallel processing channels. The FPGA of the protocol adaptive conversion module 20 performs hardware-level identification and conversion of the Modbus RTU and ONVIF protocols: a two-level matching structure using a Bloom filter and hash index completes protocol type positioning within microseconds. The protocol parsing and conversion unit extracts the payload according to the parsing template, fills it into a predetermined unified data format, and writes it to the ARM shared memory via zero-copy using a DMA controller. All three data streams are stamped with nanosecond-level hardware timestamps.

[0084] The spatiotemporal alignment unit of the edge computing unit 30 reads three data streams from shared memory and establishes a spatiotemporal index based on hardware timestamps and device coordinates. The video analytics unit performs frame-by-frame analysis of the video stream through the NPU, extracting personnel IDs, motion trajectories, and behavioral features, and aligns them with access control card swipe records and infrared sensor signals within the same 500-millisecond time window.

[0085] The spatial edge construction module of the graph structure construction unit constructs physical spatial edges based on the spatial hierarchy to which the devices belong: access control nodes, infrared nodes, and camera nodes are treated as devices in the same spatial region, and edges are established between each pair of them, with the edge weight inversely proportional to the physical distance between the devices. The logical edge construction module constructs logical association edges based on business rules: access control card swipe events and camera capture events are highly correlated in time, and strong association edges are established between them.

[0086] The graph neural network processing unit runs a heterogeneous temporal graph neural network. The node state storage module initializes the state vectors of each node: the access control node's state vector includes card swipe time and card number information; the infrared node's state vector includes trigger time and trigger count; and the camera node's state vector includes personnel detection results and trajectory information. The message passing module, running on the ARM core, collects state vectors from each node's neighbor nodes based on the edges in the graph structure, aggregating them to generate neighbor message vectors for each node. The node state update module, running on the NPU, fuses each node's current state vector with its corresponding neighbor message vector. After processing by the gating loop unit, a new state vector is generated and written back to the node state storage module by the state write-back module. After three iterations, the camera node's state vector has fused access control card swipe information and infrared sensor information, comprehensively judging it as a "tailgating event" with a confidence level of 87%. The fused state vector is output to the decision execution unit.

[0087] The decision execution unit receives the fused state vector and inputs it into the local rule engine. The rule engine performs pattern matching based on the Rete algorithm and finds that the state vector satisfies the preset rule "trigger capture and alarm when the confidence of the trailing event is greater than 80%". The instruction generation unit generates control instructions: the camera captures the current image, the audible and visual alarm is activated, and the security terminal pushes an alarm.

[0088] The data distillation unit receives the fused state vector and control commands, and uploads the summary information "A person tailgating event occurred at Gate 3 in Area A, with a confidence level of 87%" and feature samples from the control commands to the cloud; the original video stream and sensor data are stored locally in a loop, with a retention period of 30 days.

[0089] The event type register of the interrupt response module is pre-set with "tailing event" as a real-time response event. When the event monitoring unit detects that the control command output by the decision execution unit matches this event type, it generates an interrupt trigger signal. The hardware interrupt controller responds to this signal, bypassing the operating system to directly drive the security terminal alarm, ensuring that security personnel can respond immediately. The entire interrupt response process is completed within microseconds.

[0090] Scenario 2: Operation without network access and self-healing When the network connection between the smart park and the cloud is interrupted, the all-in-one machine automatically switches to offline independent operation mode.

[0091] The data distillation unit detects a network connection interruption and temporarily stores the summary information and feature samples to be uploaded in a local cache. The cache uses a circular queue structure with a capacity of 7 days' worth of data. All local linkage rules continue to be executed normally by the edge computing unit 30: automatically adjusting the air conditioning temperature based on personnel density, automatically turning off the lights after get off work, and optimizing equipment operation strategies based on energy consumption data, etc. The graph neural network processing unit continues to run, the decision execution unit continuously outputs control commands, and the command control unit 40 performs fine-grained control based on the state vector. The entire system function is completely unaffected by the network interruption.

[0092] When network connectivity is restored, the data distillation unit automatically synchronizes key logs and statistical data from the outage period in chronological order to the cloud, and clears the synchronized cache. The cloud then updates its database upon receiving the data, ensuring data integrity. The synchronization process employs a breakpoint resumption mechanism to ensure the reliability of large-volume data transmissions.

[0093] When the ARM main system crashes due to a software fault, the edge computing unit 30 stops working and cannot output state vectors. However, the instruction control unit 40 operates independently of the edge computing unit 30, and its hardware interrupt link remains active. At this time, if the smoke detector outputs a 24V level signal (fire alarm signal), this hardwired signal is connected to the first input terminal of the hardware interrupt link via the IO input interface. The hardware interrupt link simultaneously routes this signal to the interrupt pin of the MCU. The MCU detects that the interrupt pin has been triggered, immediately suspends any currently executing operations, and instead executes the hardware interrupt service routine. In this interrupt service routine, the MCU bypasses the rule matching engine and instruction generation unit, and directly reads the key linkage rule corresponding to the hardwired signal from the finite state machine storage unit. This fire linkage rule is compiled into a finite state machine, with the preset action sequence as follows: sequentially execute access control unlocking, broadcast evacuation, elevator forced descent, and cut off non-fire power. The MCU connects to the relay output interface through the control output terminal and drives the execution devices item by item: first, it drives the access control controller to unlock all access control devices, then starts the broadcast system to play evacuation instructions, then controls the elevator to be forced to the first floor and locked, and finally cuts off non-fire power. The entire process is completed independently by the MCU, without relying on the ARM system, ensuring the safe evacuation of personnel.

[0094] This embodiment demonstrates the collaborative operation of multi-source data fusion, graph neural network intelligent decision-making, data distillation, and interruption response through a scenario of personnel tailing detection and response; it also demonstrates the system's offline operation capability, data synchronization mechanism, and hardware-level emergency response capability in the event of a main system crash through a scenario of network outage operation and fault self-healing, fully verifying the significant progress of this invention in improving the level of intelligent management and control of the park and the reliability of the system.

[0095] Furthermore, in the actual operation of this invention deployed in a smart park, a localized closed loop is achieved for the temporary access rights management of access control, gates, and elevators for users outside the park, as well as property services. When a visitor initiates a "self-reservation" (effective upon expiration) or "visitee reservation" via a mobile terminal, the decision execution unit of the edge computing unit 30 generates a temporary state vector based on the reservation time window and visitor identity information. This vector includes fields such as the reservation start and end times, the visited company, and a list of authorized devices (such as elevator control for a specified floor). After receiving the state vector, the instruction control unit 40 compiles it into an encrypted QR code access code through the instruction generation unit and links the QR code printer through the relay output interface or directly pushes it to the visitor's mobile terminal. After the visitor arrives at the park, the barcode scanner connected to the multi-mode heterogeneous communication interface unit 10 identifies the QR code, and the protocol adaptive conversion module 20 completes data parsing at a microsecond speed and delivers it to the shared memory. The spatiotemporal alignment unit of edge computing unit 30 compares the current time with the reservation time window. If it is in the "effective" state, the graph neural network processing unit updates the visitor node status, and the decision execution unit outputs a release command. If it is in the "under review" or "not effective" state, it refuses access and records the abnormal attempt. For "first-time visitors," the system automatically assigns parking information (such as guidance on remaining parking spaces) and target floor permissions. For "repeat visitors," the one-click reservation mechanism triggers the decision execution unit to load the visitor's historical reservation information (including frequently visited companies, frequently used license plates, etc.) from the cache of the local data distillation unit, without the need for repeated entry. All access records (including time, device, and verification results) are written to the local logs of access control, gate, and elevator control in real time, and the data distillation unit uploads summary information (such as "Visitor Zhang XX entered the elevator in Building A at 14:30") to the "Visitor Record List" of the cloud management platform for the park property management to query. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. An edge-computing-based smart park super-converged appliance system, characterized in that, include: A multimode heterogeneous communication interface unit includes a wired access part and a wireless access part. The multimode heterogeneous communication interface unit is configured to access sensing devices and control devices and output data frames; wherein, the data frames carry the output data of the sensing devices and control devices. The protocol adaptive conversion module includes: an FPGA chip and a preset protocol feature library. The input end of the protocol adaptive conversion module is connected to the output end of the multi-mode heterogeneous communication interface unit, and is configured to identify the communication protocol of the data frame in real time at the data link layer, convert it into a predetermined unified data format, and deliver it to the shared memory through a DMA channel with zero copy. The edge computing unit adopts a heterogeneous architecture of ARM processor and NPU. The input end of the edge computing unit is connected to the shared memory and is configured to read data in a predetermined unified data format from the shared memory, perform spatiotemporal alignment and multi-source data fusion analysis based on graph neural network, and output the fused state vector; wherein, the fused state vector represents the comprehensive status of each area and each device in the park. The instruction control unit, independent of the edge computing unit, has its first input terminal connected to the output terminal of the edge computing unit to receive the state vector, its state input terminal for connecting to an external I / O input interface, and its control output terminal for connecting to an external execution device. The instruction control unit is configured to generate control instructions based on the state vector, and to independently generate key control instructions based on the hard-wired signals of the IO input interface.

2. The system of claim 1, wherein, The multi-mode heterogeneous communication interface unit includes: The wired access portion includes: multiple industrial serial interfaces configured to connect to industrial serial port devices; and multiple Ethernet interfaces, with at least some of the interfaces supporting PoE power supply, configured to connect to network devices and supply power to the network devices; The wireless access section includes: various wireless communication modules configured to access wireless terminals and low-power sensors; The wired access section is mounted on an internal high-speed data bus, while the wireless access section is connected to the main control system via a peripheral bus.

3. The system according to claim 2, characterized in that, It also includes a multi-protocol concurrency driver manager, which runs on the ARM core's real-time operating system layer. The multi-protocol concurrency driver manager includes: The interface abstraction layer provides a unified data transceiver interface for each physical interface in the multi-mode heterogeneous communication interface unit; The clock synchronization unit is connected to the FPGA and is used to obtain the global hardware clock provided by the FPGA. The timestamp engine, connected to the clock synchronization unit and the interface abstraction layer, is used to uniformly timestamp data packets of all interfaces, so that data from different physical media can be processed collaboratively under a unified time base.

4. The system according to claim 1, characterized in that, The protocol adaptive conversion module includes an FPGA chip and a protocol feature library storage unit. The FPGA chip includes: The first processing unit, configured in the Block RAM of the FPGA, includes a hash index module and a Bloom filter module; The Bloom filter module is used to perform parallel hash calculations on the header features of the input data frame to quickly eliminate mismatched protocol types, and its output is connected to the input of the hash index module. The hash index module is used to perform a precise comparison in the candidate protocol set initially matched by the Bloom filter module, and output the identifier of the successfully matched protocol. The protocol feature library storage unit is also used to store parsing templates corresponding to each protocol feature; Multiple parallel processing channels, each corresponding to a different physical interface, are connected to the multi-mode heterogeneous communication interface unit for independently receiving data frames from the corresponding interface. The frame boundary detection unit has its input terminals connected to the output terminals of the multiple parallel processing channels, and is used to define the frame boundary by detecting the fixed frame header through a hardware state machine or by using a timer to detect the inter-frame idle time. The protocol parsing and conversion unit has its first input connected to the output of the frame boundary detection unit and its second input connected to the output of the protocol feature library storage unit. It is used to extract the payload according to the parsing template corresponding to the successfully matched protocol feature and fill it into a predetermined unified data format. The predetermined unified data format includes device identifier, hardware timestamp, data type, value, and quality stamp fields. The DMA controller has its input connected to the output of the protocol parsing and conversion unit, and its output is used to connect to the ARM shared memory to directly write the converted data into the ARM shared memory via the DMA channel.

5. The system according to claim 4, characterized in that, The protocol adaptive conversion module further includes a protocol self-learning unit, which includes: The matching result monitoring module has its input connected to the Bloom filter module in the first processing unit, and is used to monitor the matching results of the Bloom filter module. A trigger module, whose input is connected to the output of the matching result monitoring module, is used to generate an unknown protocol capture event when the matching result monitoring module outputs a signal of continuous matching failure. The feature pre-extraction engine has its input connected to the output of the multiple parallel processing channels and its enable connected to the output of the trigger module. In response to the unknown protocol capture event, it extracts the statistical features, structural features and temporal features of the data frame and encapsulates the extracted features and the first byte of the data frame into an unknown protocol data packet. The upload interface has its input end connected to the output end of the feature pre-extraction engine, and its output end is used to connect to the cloud through an independent secure channel to upload the unknown protocol data packet to the cloud. The receiving interface has an input end for connecting to the cloud and an output end for connecting to the protocol feature library storage unit. It is used to receive the parsing template returned by the cloud and load the parsing template into the protocol feature library storage unit to update the protocol feature library. The protocol feature library storage unit adopts a dual-buffer mechanism inside the FPGA, that is, it is divided into two independent storage areas. The receiving interface loads the new parsing template into the non-currently used backup buffer and switches the main and backup buffer pointers through atomic operations during the frame idle interval, so as to realize the online hot update of the protocol feature library.

6. The system according to claim 1, characterized in that, The edge computing unit adopts a heterogeneous architecture of ARM processor and NPU, including: The spatiotemporal alignment unit, whose input is connected to the shared memory, is used to read data in the predetermined unified data format, stamp each data packet with a hardware timestamp, establish a spatiotemporal index based on the device coordinates of the data source, and output unified data with the spatiotemporal index. The video analysis unit, whose input is connected to the output of the spatiotemporal alignment unit, is used to perform frame-by-frame analysis of video stream data through the NPU, extract structured information, and align it with the data of sensing devices under the same spatiotemporal index within the same time window, and output the aligned multi-source data; wherein, the video stream data refers to a continuous sequence of image frames that are acquired and output in real time by video acquisition devices deployed in the park. The graph structure construction unit has its input end connected to the output end of the video analysis unit. It is used to construct a heterogeneous temporal graph neural network based on the aligned multi-source data. The node types include perception nodes, identity nodes, spatial nodes and execution nodes, and the edges include physical space edges and logical association edges. The output is graph structure data. A graph neural network processing unit, whose input is connected to the output of the graph structure construction unit, is used to run the heterogeneous temporal graph neural network. The graph neural network processing unit includes: The node state storage module is used to store the current state vector of each node; The message passing module, running on the ARM core, has its first input connected to the output of the graph structure building unit and its second input connected to the output of the node state storage module. It is used to collect state vectors from the neighboring nodes of each node according to the edges in the graph structure and aggregate them to generate neighbor message vectors for each node. The node state update module runs on the NPU. Its first input is connected to the output of the node state storage module, and its second input is connected to the output of the message passing module. It is used to fuse the current state vector of each node with the corresponding neighbor message vector, and generate a new state vector after processing by the time-series state update model. The state write-back module has its input connected to the output of the node state update module and its output connected to the input of the node state storage module, and is used to write the new state vector back to the node state storage module. The node state storage module, message transmission module, node state update module, and state write-back module form an iterative update loop. Each time the message transmission module and the node state update module complete a neighbor message aggregation and state update, the state vector in the node state storage module is updated once. After a preset number of iterations, the state vector stored in the node state storage module is output as the fused state vector. The decision execution unit has its input end connected to the output end of the graph neural network processing unit. It is used to receive the fused state vector, input the fused state vector into the local rule engine and the lightweight decision model, generate control commands, and output the control commands and the fused state vector. The data distillation unit has its first input terminal connected to the output terminal of the graph neural network processing unit and its second input terminal connected to the output terminal of the decision execution unit. It is used to receive the fused state vector and the control command, upload the summary information in the fused state vector and the feature samples in the control command to the cloud, and store the original data locally in a loop. It also includes an interrupt response module, whose input is connected to the output of the decision execution unit and whose output is connected to the execution device. For critical events, it directly triggers the real-time response of the associated device through the hardware interrupt path and uses the fusion result of the graph neural network processing unit for subsequent confidence correction and multi-round linkage decision-making.

7. The system according to claim 6, characterized in that, The graph structure building unit includes: The spatial edge construction module, whose input end is connected to the output end of the video analysis unit, is used to construct physical spatial edges according to the spatial hierarchy to which the device belongs. Device nodes in the same space are connected to each other, and the edge weight is inversely proportional to the physical distance between devices. The logical edge construction module has its input end connected to the output end of the video analysis unit and to the event statistics output end of the FPGA. It is used to construct logical association edges based on business rules or by statistically analyzing the temporal correlation of events between two devices through the FPGA. The relational graph convolution processing module has its input terminals connected to the output terminals of the spatial edge construction module and the logical edge construction module, respectively. It is used to adopt a variant of the relational graph convolutional network, set independent weight transformation matrices for different types of edges, generate graph structure data, and output it to the graph neural network processing unit.

8. The system according to claim 6, characterized in that, The edge computing unit further includes an interrupt response module, which includes: The event type register is used to store preset real-time response event types; An event monitoring unit has its first input terminal connected to the output terminal of the decision execution unit and its second input terminal connected to the event type register. It is used to monitor the control commands output by the decision execution unit, compare the event type of the control commands with the real-time response event types stored in the event type register, and generate an interrupt trigger signal when a match is found. A hardware interrupt controller, whose input is connected to the output of the event monitoring unit, and whose output is connected to the execution device, is used to respond to the interrupt trigger signal and bypass the operating system to directly drive the associated execution device.

9. The system according to claim 1, characterized in that, The instruction control unit includes: The MCU has its first input terminal connected to the output terminal of the decision execution unit in the edge computing unit to receive the state vector; its control output terminal is connected to the relay output interface and the infrared transmission interface; and its state input terminal is connected to the IO input interface. A finite state machine storage unit, configured inside the MCU, is used to store preset linkage rules compiled into a finite state machine; The rule matching engine has its first input terminal connected to the first input terminal of the MCU and its second input terminal connected to the output terminal of the finite state machine storage unit. It is used to match the received state vector with the preset linkage rule to generate a matching result. The instruction generation unit has its input end connected to the output end of the rule matching engine and its output end connected to the control output end of the MCU. It is used to generate control instructions based on the matching results and drive the execution device through the control output end. The hardware interrupt link has its first input terminal connected to the IO input interface and its output terminal connected to the interrupt pin of the MCU. It is used to route the signal to the interrupt pin of the MCU when a hard-wired signal is connected to the IO input interface. The MCU is further configured to bypass the rule matching engine and instruction generation unit when the interrupt pin is detected to be triggered, directly read the key linkage rule corresponding to the hard-wired signal from the finite state machine storage unit, and drive the execution device.

10. The system according to claim 9, characterized in that, The command control unit further includes: The hardware watchdog has its monitoring terminal connected to the heartbeat output terminal of the MCU and its reset terminal connected to the reset pin of the MCU. The hardware watchdog is configured to monitor the heartbeat signal of the MCU. When the heartbeat signal is abnormal, the MCU is hardware reset through the reset terminal.

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