An edge medical emergency signal encryption processing method based on a racing dormancy strategy

Abstract

This invention discloses an edge medical emergency signal encryption processing method based on a race-sleep strategy, relating to information security technology and embedded hardware acceleration technology. The method includes the following steps: S1, real-time monitoring of the number K of physiological data blocks to be encrypted in the data input buffer; S2, comparing the number K of data blocks with a preset minimum start threshold, and generating a global wake-up pulse when K ≥ 0; S3, responding to the global wake-up pulse, causing the fully expanded pipeline layer to transition from a sleep state to a full-speed running state, and sequentially injecting K data blocks into the fully expanded pipeline layer for encryption processing. This invention originates from the fully expanded architecture, which eliminates iterative feedback loops and, in conjunction with a deep pipeline, cuts off critical paths. By spatially instantiating R round function units, it achieves the output of a complete ciphertext block per clock cycle, improving throughput while reducing power consumption.

Description

Technical Field

[0001] This invention relates to the fields of information security technology and embedded hardware acceleration technology, and in particular to an edge medical burst signal encryption processing method based on a racing sleep strategy. Background Technology

[0002] With the widespread adoption of IoT technology in smart healthcare, edge applications such as stroke monitoring face stringent requirements for real-time encryption of sudden physiological data. These applications typically involve the acquisition of high-frequency physiological data, such as multi-channel continuous speech and high-density electrophysiological signals (e.g., EEG, EMG). This data is highly sensitive to user privacy and must be encrypted in real-time at the edge acquisition terminal to prevent data leakage or tampering during wireless transmission. Since edge medical devices (such as wearable monitors and implantable sensors) are usually powered by miniature batteries, power consumption is extremely limited. To extend battery life, these devices commonly employ "duty-cycle control" or "race-to-sleep" strategies. The core of this strategy is that the encryption module completes the instantaneous processing of backlogged data with extremely high throughput within a very short wake-up time (Burst Processing), and then quickly enters a deep sleep state, thereby minimizing the dynamic power consumption of the system in the active state.

[0003] The existing lightweight block cipher algorithms in hardware implementation mainly suffer from the following technical shortcomings: 1. Resulting Throughput Bottleneck: Existing hardware encryption accelerators mostly employ iterative or bit-serial architectures. These designs trade off a very small chip area by time-multiplexing a single round function hardware logic. However, processing a single data block requires tens or even hundreds of clock cycles, typically limiting its throughput to the Mbps level. In scenarios involving multi-channel high-frequency physiological signals (convergence rates easily exceeding 10Mbps) and strictly limited duty cycles (e.g., D≤1%), according to the physical boundary formula... The system requires instantaneous peak throughput to reach the Gbps level, which traditional iterative architectures obviously cannot meet.

[0004] 2. Insufficient energy utilization: Existing low-speed encryption modules have weak processing power, resulting in excessively long active times. Under the "race-to-sleep" model, a longer wake-up time means that the device cannot enter sleep mode in time, leading to an increase in both static and dynamic power consumption, which severely weakens the battery life of edge devices.

[0005] 3. Lack of adaptability to bursty data: Medical sensor data often exhibits the characteristics of periodic discrete arrival and batch burst processing. Although the existing partial unrolling architecture improves speed to some extent, there are still periodic waits caused by feedback loops, which cannot achieve the ultimate pipeline operation without unidirectional feedback. As a result, when processing large-scale backlogged sensor data packets (such as 100KB and above), the proportion of the initial fill delay (Tfill) in the total processing cycle cannot be effectively reduced, and the effective throughput is far lower than the physical peak.

[0006] Therefore, designing a fully parameterized, configurable encryption acceleration architecture that can break through the Gbps throughput bottleneck and perfectly adapt to the "race-to-sleep" strategy on resource-constrained edge FPGA or chip platforms is a key technical problem that urgently needs to be solved in the field of medical IoT security. Summary of the Invention

[0007] The purpose of this invention is to provide a fully deployable pipeline and a fully parameter-configurable Simon hardware acceleration system for edge medical monitoring. This system addresses the problems of existing Simon hardware encryption architectures, which suffer from limited throughput due to iterative or bit-serial designs, inability to meet the demands of Gbps-level instantaneous burst data processing, lack of flexibility in adapting to different security levels, and high hardware redundancy overhead. The proposed method is an edge medical burst signal encryption processing method based on a race-and-sleep strategy.

[0008] A method for encrypted processing of edge medical burst signals based on a race-to-sleep strategy includes the following steps: S1, the number K of physiological data blocks to be encrypted in the real-time monitoring data input buffer; S2. Calculate the number of data blocks K and the preset minimum start threshold. Compare, when K≥ At that time, a global wake-up pulse is generated; S3. In response to the global wake-up pulse, the fully expanded pipeline layer transitions from the dormant state to the full-speed running state, and K data blocks are injected into the fully expanded pipeline layer in sequence for encryption processing. The fully deployed assembly line layer consists of The pipeline layer consists of cascaded round function units and pipeline registers deployed therebetween. When processing a burst data packet containing K data blocks, the pipeline layer operates in three physical phases: cascaded filling and latency phase, full-load steady-state processing phase, and count-driven precise emptying and shutdown phase.

[0009] Preferably, in step S2, the minimum start threshold The calculation method is as follows: Cost assessment: Identify the fixed time overhead present in the initial filling phase of the pipeline:

[0010] in, The time cost is one clock cycle. Performance constraint: Set the ratio of the system's target effective throughput to its peak throughput as [value missing]. ,in ; Threshold derivation: Based on the effective throughput model:

[0011] in, The total number of rounds configured for the current algorithm; The minimum data block length that satisfies the performance objective is derived by working backwards: .

[0012] Preferably, the calculation model for the target effective throughput and peak throughput is as follows: Peak throughput model:

[0013] Effective throughput calculation model:

[0014] The system's real-time evaluation function is: .

[0015] Preferably, in step S3, the cascaded filling and latency stage includes: In the beginning To the Within one clock cycle, raw physiological data blocks Driven by the enable signal, the cascaded links are injected sequentially from the first-stage round function unit; Each pipeline register captures the intermediate value generated by the previous stage on the rising edge of the clock, and in the... One cycle ( ), data grouping Reaching the Level physical unit, and at this time the subsequent The physical unit is still in a logical idle or preset state.

[0016] Preferably, in step S3, the full-load steady-state processing stage includes: From the From the 1st clock cycle until the 1st clock cycle Once all data blocks are fully injected into the fully expanded pipeline layer, the system enters a high-saturation steady-state operation period; Cascaded links Each round function unit, within the same clock cycle, simultaneously processes data from different encryption rounds. The data is processed in parallel by groups of data that do not interfere with each other.

[0017] Preferably, in step S3, the precise emptying and shutdown stage driven by counting includes: When the input enable signal is pulled low, the first step is determined. After a data block has entered the first-level unit, the system logic controller starts a module. The emptying counter; The following Within one clock cycle, the amount remaining in the pipeline When no new data is input, the group continues to shift to the subsequent physical link driven by the clock pulse; When the empty counter reaches zero, and the last group... The ciphertext from the first The moment the stage unit is removed, the system logic immediately triggers a timing termination pulse, forcibly cutting off the global clock supply to the fully expanded pipeline layer.

[0018] An edge medical burst signal encryption processing system based on a race-and-sleep strategy, the system employs a physically fully deployed and deeply pipelined coupled architecture, the fully deployed architecture consisting of... It consists of a cascaded round function unit and a dynamic water level line adaptive trigger control unit; The dynamic water level adaptive trigger control unit is deployed between the data input buffer and the fully expanded pipeline layer, and is used to dynamically determine the wake-up time of the hardware core according to the physical characteristics configured by the current algorithm.

[0019] Preferably, the internal structure and physical interconnection characteristics of each single-stage round function unit are as follows: The zero-overhead shift layer implements cyclic left shift operations through physical hardwires, and the shift logic does not go through a logic lookup table, but directly achieves spatial offset of signal bits through metal wiring. The nonlinear term parallel mapping unit consists of N parallel two-input AND gates; The timing barrier registers are a set of N-bit wide pipeline registers deployed at the output of each round function unit to cut off the critical path of combinational logic.

[0020] Preferably, the dynamic water level adaptive trigger control unit specifically includes: The backlog counter, connected to the write enable pin of the data input buffer, is used to count in real time the number of raw physiological data blocks that have been temporarily stored in the buffer and are yet to be encrypted. ; An energy efficiency threshold register is used to store a preset minimum startup threshold. ; The trigger comparison logic circuit has its inputs connected to the backlog counter and the energy efficiency threshold register, respectively, to determine whether K has been reached. ; An adaptive clock gating controller is connected to the clock enable terminal of the fully deployed pipeline layer to control the clock enable of the fully deployed pipeline layer.

[0021] Compared with existing technologies, the advantages of this invention are: 1. This invention originates from a fully deployed architecture that eliminates iterative feedback loops and, in conjunction with deep pipelines, cuts off critical paths; the throughput of traditional iterative architectures is limited by... (R is the number of rounds), and this invention realizes the output of a complete ciphertext block in each clock cycle by instantiating R round function units in space, thereby improving throughput while reducing power consumption.

[0022] 2. All configuration logic in this invention is parsed and transformed into specific physical networks during the compilation stage. The final generated hardware netlist does not contain any redundant logic gates for compatibility with multiple modes, achieving an absolutely simplified form for configuration of specific security levels. This not only saves about 10%-20% of redundant lookup table resources, but also eliminates the timing delay and static leakage power consumption introduced by redundant logic from the root.

[0023] 3. This invention addresses the characteristics of medical sensor data arriving periodically and in bursts, by monitoring the buffer status in real time to determine the start and stop of the hardware core, ensuring that the encryption of each bit of data is in the highest energy efficiency range. Attached Figure Description

[0024] Figure 1 This is a detailed architecture of the fully expanded Simon round function of this invention.

[0025] Figure 2 This is a spatiotemporal diagram of the fully deployed pipeline architecture of the present invention.

[0026] Figure 3 This is a comparison diagram of the fully deployed architecture of this invention and the traditional iterative architecture.

[0027] Figure 4 This is a graph showing the hardware processing matching rate and cumulative test scale of the present invention under different burst sequence lengths. Detailed Implementation

[0028] To facilitate understanding of this application and to make the above-mentioned objectives, features and advantages of this application more apparent, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0029] Reference Figure 1 As shown, an edge medical burst signal encryption processing method based on a racing sleep strategy includes the following steps: S1, the number K of physiological data blocks to be encrypted in the real-time monitoring data input buffer; S2. Calculate the number of data blocks K and the preset minimum start threshold. Compare, when K≥ At that time, a global wake-up pulse is generated; S3. In response to the global wake-up pulse, the fully expanded pipeline layer transitions from the dormant state to the full-speed running state, and K data blocks are injected into the fully expanded pipeline layer in sequence for encryption processing. Fully unfolded architecture by It consists of cascaded round function units, see appendix. Figure 1 The internal structure and physical interconnection characteristics of a single-level round function unit are as follows: Zero-Overhead Shift Layer: Circular left shift operations within a cell ( 1, 8, 2) It is implemented as a physical hard-wiring between channels. The shift logic does not go through a logic lookup table (LUT) and directly realizes the spatial offset of signal bits through metal wiring, eliminating the logic delay and resource consumption of shift instructions in traditional designs.

[0030] Parallel mapping of nonlinear terms: Nonlinear terms in round functions Mapped to A parallel two-input AND gate.

[0031] Timing barrier settings: At the output of each round function unit (i.e., combinational logic) After that, a group was deployed. Pipeline registers (composed of arrays of D flip-flops) are bit-wide. These registers are used to cut off long combinational logic on the critical path, allowing the system to operate at a certain frequency. It is limited only by the propagation delay of a single-level round function, which is the sum of the logic delays of a single-level AND gate and a three-level XOR gate.

[0032] To address the periodic, discrete, and sudden arrival characteristics of peripheral physiological signals (such as EEG and ECG), a dynamic performance balance controller was integrated. This controller not only adheres to a physical performance model but also determines the start and stop of the hardware cores by monitoring the buffer state in real time, ensuring that every bit of data encryption operates within the highest energy efficiency range. (1) Physical model constraints for performance evaluation The system's internal logic maintains two sets of throughput evaluation metrics in real time to guide energy efficiency decisions.

[0033] Peak throughput model: Defines the instantaneous physical limit of the system.

[0034] This metric represents the pipeline's processing capacity under full load and steady state, and is determined by the parallelism of the fully deployed architecture.

[0035] Effective throughput ( Computational model: Considering pipeline setup overhead, for pipelines containing... The actual processing efficiency of burst packets of data blocks is limited by the initial pipeline fill delay. Its mathematical expression is:

[0036] After logical simplification, the system's real-time evaluation function is:

[0037] in, The total number of rounds configured for the current algorithm. This model reveals the relationship between effective throughput and packet length. The positive correlation.

[0038] (2) Adaptive triggering mechanism based on energy efficiency threshold The system integrates a dynamic water level adaptive trigger control unit, characterized in that the trigger control unit is deployed between the data input buffer (FIFO) and the fully expanded pipeline core, and is used to dynamically determine the wake-up time of the hardware core according to the physical characteristics of the current algorithm configuration.

[0039] The dynamic water level adaptive trigger control unit specifically includes: 1. BurstCounter: Connected to the write enable pin of the data input buffer, it is used to count in real time the number of raw physiological data blocks that have been temporarily stored in the buffer and are yet to be encrypted. .

[0040] 2. Energy Efficiency Threshold Register: Used to store the preset minimum start-up threshold. . It is not a fixed value, but is determined by the compile-time parameter derivation unit based on the total number of rounds in the current algorithm. Compared with preset energy efficiency targets (For example (Dynamically generated reference value)

[0041] 3. Trigger Comparator: Its inputs are connected to a counter and a register, respectively.

[0042] 4. Adaptive Clock Gating Controller: Connects to the clock enable pin (ClockEnable) of the fully deployed pipeline core.

[0043] Based on the physical characteristics of the fully deployed pipeline, the system determines the water level line through the following logic.

[0044] Cost assessment: Identify the fixed time overhead present in the initial filling phase of the pipeline:

[0045] in, The time cost is one clock cycle.

[0046] Performance constraint: Set the ratio of the system's target effective throughput to its peak throughput as [value missing]. (in ).

[0047] Threshold derivation: Based on the effective throughput model By working backwards, we can derive the minimum data block length that satisfies the performance objective:

[0048] The system uses pre-defined hardware logic to complete the compilation process for different configurations such as Simon64 / 128 and 128 / 256 during the compilation phase. Pre-calculate and then solidify or write the result into the energy efficiency threshold register.

[0049] The fully deployed pipeline layer serves as the core of the system's encrypted execution. The pipeline layer consists of... It consists of cascaded round function units and pipelined registers deployed between them. (See attached document.) Figure 2 (Spatiotemporal diagram), the pipeline layer processes a... When a burst of data packets occurs, its operating mechanism is strictly divided into the following three physical stages: (1) Cascaded filling and latent phase (Fill Phase) Operation sequence: In the initial... To the Within one clock cycle, raw physiological data blocks Driven by the enable signal, the cascaded links are injected sequentially from the first-level round function unit.

[0050] Hardware state evolution: Each pipeline register captures the intermediate value generated by the previous stage on the rising edge of the clock. Its characteristic is that, in the... One cycle ( ), data grouping Reaching the Level physical unit, and at this time the subsequent The physical unit is still in a logical idle or preset state.

[0051] Output characteristics: This stage is defined as the system's hardware latency period. Due to the initial grouping... Not yet penetrated completely In the first-level logic link, the output terminal (Text_out) does not generate valid ciphertext, and the system output valid signal (vld_out) remains at a low level, thereby avoiding the power consumption waste caused by nondeterministic logic flipping in the initial stage.

[0052] (2) Steady-state processing phase under full load Operation sequence: From the first From the 1st clock cycle until the 1st clock cycle Once all data blocks are fully injected into the pipeline, the system enters a high-saturation steady-state operation period.

[0053] Spatial-temporal parallel mechanism: Its key feature is that the fully deployed pipeline reaches full load saturation in physical space. At this point, the cascaded links... Each round function unit, within the same clock cycle, simultaneously processes data from different encryption rounds (Round 1 to Round R). The data is processed in parallel by groups of data that do not interfere with each other.

[0054] Performance characteristics: At this stage, the pipeline exhibits an ideal "one-in, one-out" throughput pattern, meaning that a complete 2N-bit ciphertext block (1 block / cycle) is shifted out from the output in each clock cycle. At this point, the effective utilization rate of hardware resources remains constant. The system's instantaneous throughput reached its theoretical physical peak. , corresponding to the appendix Figure 2 The green area in the middle shows the parallel operation status.

[0055] (3) Count-driven precise drain and shut-off phase (DrainPhase) Triggering mechanism: When the input enable signal (vld_in) is pulled low, the triggering mechanism is determined. After a data block (end group) has entered the first-level unit, the system logic controller initiates a module... The emptying counter.

[0056] Residual data extraction: in the subsequent Within one clock cycle, the amount remaining in the pipeline When no new data is input, the group continues to shift to the subsequent physical link driven by clock pulses.

[0057] Precise shutdown logic: See attached document Figure 2 The blue area represents the time when the empty counter reaches zero and the last group... The ciphertext from the first The moment the stage unit is removed, the system logic immediately triggers a timing termination pulse. This pulse drives the aforementioned adaptive clock gating controller to forcibly cut off the global clock supply to the fully deployed pipeline core. Its key feature is that the shutdown operation occurs precisely within nanoseconds (ns) of the last valid data block being removed, achieving an energy-efficient shutdown with "zero redundancy flip-over" and completely suppressing static and dynamic power consumption after emptying.

[0058] "Racing Sleep" Energy Efficiency Management Logic The system relies on a high-throughput physical architecture with a fully deployable pipeline and supports a race-to-sleep energy efficiency management strategy optimized for the 1.0W power supply and heat dissipation limits of edge medical monitoring terminals. This strategy includes the following three dimensions: (1) Instantaneous wake-up control mechanism based on water level monitoring The system internally incorporates an independent low-power monitoring domain, which monitors the water level status of the front-end FIFO buffer in real time through a data backlog counter. This counter tracks the number of backlogged physiological data blocks. Reaching the preset adaptive wake-up threshold At that moment, the logic controller instantly generates a global wake-up pulse. This pulse drives the adaptive clock gating controller to resume from the shutdown state, enabling the fully deployed pipeline core to transition from a dormant state to a full-speed running state within nanoseconds. This threshold-based triggering mechanism ensures that the encryption core is activated only in the "high watermark" range where high-efficiency processing conditions are available, avoiding pipeline fill overhead caused by frequent wake-ups of scattered small data packets.

[0059] (2) High-throughput gain active window rapid compression strategy The system leverages the Gbps-level instantaneous peak throughput provided by its fully deployed architecture to rapidly compress the processing time (ActiveTime) of encryption tasks. Based on the "power consumption-time balance principle," the system increases throughput to more than 50 times that of traditional iterative architectures, proportionally compressing the active window time required to process the same scale of bursty physiological data packets to microseconds. This strategy forces the effective duty cycle of the system to be suppressed to less than 1% throughout its life cycle. By drastically shortening the duration of high dynamic power consumption, it achieves a significant reduction in total energy consumption (pJ / bit), thereby meeting the long-term battery life requirements of edge devices with limited battery capacity.

[0060] (3) Clock gating fine-grained shutdown logic based on emptying perception At the instant the pipeline drain phase ends, the system control logic precisely triggers the gating instruction at the root of the clock tree based on the zeroing signal of the drain counter. This logic completely cuts off the global clock supply to the fully deployed pipeline core within nanoseconds of the last valid ciphertext block being removed from the physical link. The shutdown operation not only eliminates dynamic power consumption by stopping logic flip-flops but also significantly suppresses the accumulation of static leakage current in transistors at high temperatures through a level-locking mechanism. This closed-loop control, where "data ends, clock stops," ensures that although the system's instantaneous power consumption is high, its long-term average energy consumption and heat generation are strictly controlled within the safe physical boundary of 1.0W.

[0061] To verify the energy efficiency advantages of the fully deployed pipeline architecture of this invention, physical synthesis and evaluation in out-of-context (OOC) mode were performed on an edge low-power FPGA platform (such as Xilinx Artix-7xc7a35tcsg324-1). Gradient clock constraints were set in the experiment to explore the physical boundaries, and power consumption and timing reports were extracted, as shown in Table 1. Table 1 Energy efficiency data at multiple operating frequencies

[0062] Experimental results show that, at a target deployment clock cycle of 5.15ns (i.e., 194.17MHz), the peak throughput of this invention reached 12.43Gbps, with total power consumption controlled at 0.959W, strictly adhering to the 1.0W physical power supply limit for edge devices. At the target deployment frequency of 194.17MHz, the energy consumption per bit of this system is only 77.15pJ / bit. Taking the processing of 1Gb of backlogged sensor data accumulated during a single wake-up as an example, the system only needs approximately 80.45ms to complete the processing and enter deep sleep mode, significantly reducing the average overall power consumption of edge nodes and achieving long-term stable operation within the 1.0W power supply limit.

[0063] In contrast, existing lightweight cryptographic hardware mostly adopts a traditional iterative architecture, such as... Figure 3 As shown on the right, its throughput is limited by the feedback loop and is typically only in the Mbps range. Even with a partially expanded architecture, its throughput is only around 5Gbps. (See Table 2.) Table 2 Comparison of the architecture of this invention with architectures of recent years

[0064] Note: Sheikhpour's data is based on the high-end FPGA model Virtex-7, which performs far better than Artix-7.

[0065] As shown in Table 2, the throughput of the present invention is nearly 50 times higher than that of the traditional standard iterative architecture (Ghayoula) and 2.48 times higher than that of the partially expanded architecture (Wijesinghe) on the same platform. Although the instantaneous dynamic power consumption of the present invention is slightly higher, the time required to process a unit bit of data is reduced by two orders of magnitude, thereby greatly compressing the wake-up time of the encryption module.

[0066] To verify the functional equivalence of the fully deployed pipeline architecture of this invention and its physical reliability under race-and-sleep scheduling, black-box testing was conducted on the system under full configuration parameters. The experiment used the official standard test vectors of the Simon algorithm released by the National Security Agency (NSA) as a benchmark to compare exhaustive and random burst modes on the hardware instance of this system.

[0067] Firstly, regarding static functional verification, the system extracted configurations for all 10 standard algorithms, covering Simon32 / 64, Simon48 / 72, Simon64 / 128, and even Simon128 / 256 for ultra-wide bit data operations, and input the plaintext and key provided by the official documentation into the hardware module. As shown in Table 3: Table 3. Validation Results of Architecture Operation Correctness

[0068] Experimental results show that, under the operation of the zero-overhead shift layer and nonlinear parallel mapping unit, the output ciphertext data is completely consistent with the expected ciphertext of the official mathematical model at the bit level, with a test vector pass rate of 100%. This proves that the physically fully unfolded architecture and its deep pipelined cutting did not introduce any algorithmic logic deviations. This rigorous verification system ensures the absolute reliability of medical privacy data encryption and provides an important architectural reference for the design of secure chips for high-performance medical IoT terminals.

[0069] Secondly, considering the sudden characteristics of physiological signals and the "race-to-sleep" working mode in edge healthcare scenarios, the system underwent further dynamic stability testing. The tests constructed multiple sets of parameters ranging from... to The system uses a pseudo-random test sequence of data blocks and simulates irregular discrete arrival time intervals. During the frequent state transitions across three physical stages—triggering a global wake-up pulse, pipeline full-load steady-state processing, and count-driven draining and shutdown—the hardware system continuously processed over 1 billion (10^10) data blocks. 9 Encryption tasks at the bit level. For example... Figure 4As shown, the comparison results indicate that even under extreme burst conditions of high-frequency start and stop of the clock enable signal, its bit-level matching rate remains at 100%, and no metastable bit errors or data packet loss occur due to timing gating.

[0070] In summary, the rigorous test data demonstrates that the encryption processing method of this invention, while achieving breakthroughs in Gbps-level throughput and microwatt-level average power consumption, ensures the absolute correctness and reliability of medical privacy data encryption, providing solid theoretical and experimental support for the secure underlying chip design of high-performance medical IoT terminals.

[0071] As is known from common technical knowledge, this invention can be implemented through other embodiments that do not depart from its spirit or essential characteristics. Therefore, the disclosed embodiments described above are merely illustrative in all respects and are not the only ones. All modifications within the scope of this invention or its equivalents are included in this invention.

Claims

1. A method for encrypted processing of edge medical burst signals based on a race-and-sleep strategy, characterized in that: Includes the following steps: S1, the number K of physiological data blocks to be encrypted in the real-time monitoring data input buffer; S2. Calculate the number of data blocks K and the preset minimum start threshold. Compare, when K≥ At that time, a global wake-up pulse is generated; S3. In response to the global wake-up pulse, the fully expanded pipeline layer transitions from the dormant state to the full-speed running state, and K data blocks are injected into the fully expanded pipeline layer in sequence for encryption processing. The fully deployed assembly line layer consists of The pipeline layer consists of cascaded round function units and pipeline registers deployed therebetween. When processing a burst data packet containing K data blocks, the pipeline layer operates in three physical phases: cascaded filling and latency phase, full-load steady-state processing phase, and count-driven precise emptying and shutdown phase.

2. The edge medical burst signal encryption processing method based on a racing sleep strategy according to claim 1, characterized in that: In step S2, the minimum start threshold The calculation method is as follows: Cost assessment: Identify the fixed time overhead present in the initial filling phase of the pipeline: in, The time cost is one clock cycle. Performance constraint: Set the ratio of the system's target effective throughput to its peak throughput as [value missing]. ,in ; Threshold derivation: Based on the effective throughput model: in, The total number of rounds configured for the current algorithm; The minimum data block length that satisfies the performance objective is derived by working backwards: 。 3. The edge medical burst signal encryption processing method based on a racing sleep strategy according to claim 2, characterized in that: The calculation models for the target effective throughput and peak throughput are as follows: Peak throughput model: Effective throughput calculation model: The system's real-time evaluation function is: 。 4. The edge medical burst signal encryption processing method based on a racing sleep strategy according to claim 1, characterized in that: In step S3, the cascade filling and latency stages include: In the beginning To the Within one clock cycle, raw physiological data blocks Driven by the enable signal, the cascaded links are injected sequentially from the first-stage round function unit; Each pipeline register captures the intermediate value generated by the previous stage on the rising edge of the clock, and in the... One cycle ( ), data grouping Reaching the Level physical unit, and at this time the subsequent The physical unit is still in a logical idle or preset state.

5. The edge medical burst signal encryption processing method based on a racing sleep strategy according to claim 1, characterized in that: In step S3, the full-load steady-state processing stage includes: From the From the 1st clock cycle until the 1st clock cycle Once all data blocks are fully injected into the fully expanded pipeline layer, the system enters a high-saturation steady-state operation period; Cascaded links Each round function unit, within the same clock cycle, simultaneously processes data from different encryption rounds. The data is processed in parallel by groups of data that do not interfere with each other.

6. The edge medical burst signal encryption processing method based on a racing sleep strategy according to claim 1, characterized in that: In step S3, the precise emptying and shutdown phase driven by counting includes: When the input enable signal is pulled low, the first step is determined. After a data block has entered the first-level unit, the system logic controller starts a module. The emptying counter; The following Within one clock cycle, the amount remaining in the pipeline When no new data is input, the group continues to shift to the subsequent physical link driven by the clock pulse; When the empty counter reaches zero, and the last group... The ciphertext from the first The moment the stage unit is removed, the system logic immediately triggers a timing termination pulse, forcibly cutting off the global clock supply to the fully expanded pipeline layer.

7. An edge medical emergency signal encryption processing system based on a race-and-sleep strategy, characterized in that: The system employs a physically fully deployed and deeply pipelined coupled architecture. The fully deployed architecture consists of... It consists of a cascaded round function unit and a dynamic water level line adaptive trigger control unit; The dynamic water level adaptive trigger control unit is deployed between the data input buffer and the fully expanded pipeline layer, and is used to dynamically determine the wake-up time of the hardware core according to the physical characteristics configured by the current algorithm.

8. The edge medical burst signal encryption processing system based on a racing sleep strategy according to claim 7, characterized in that: The internal structure and physical interconnection characteristics of each single-level round function unit are as follows: The zero-overhead shift layer implements cyclic left shift operations through physical hardwires, and the shift logic does not go through a logic lookup table, but directly achieves spatial offset of signal bits through metal wiring. The nonlinear term parallel mapping unit consists of N parallel two-input AND gates; The timing barrier registers are a set of N-bit wide pipeline registers deployed at the output of each round function unit to cut off the critical path of combinational logic.

9. The edge medical burst signal encryption processing system based on a racing sleep strategy according to claim 7, characterized in that: The dynamic water level adaptive triggering control unit specifically includes: The backlog counter, connected to the write enable pin of the data input buffer, is used to count in real time the number of raw physiological data blocks that have been temporarily stored in the buffer and are yet to be encrypted. ; An energy efficiency threshold register is used to store a preset minimum startup threshold. ; The trigger comparison logic circuit has its inputs connected to the backlog counter and the energy efficiency threshold register, respectively, to determine whether K has been reached. ; An adaptive clock gating controller is connected to the clock enable terminal of the fully deployed pipeline layer to control the clock enable of the fully deployed pipeline layer.

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