A self-recovery si / 4h-sic heterojunction tunneling field effect transistor and a preparation method thereof

Abstract

A self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor and its fabrication method, namely, using hot-wall chemical vapor deposition technology, in n + n-type 4H-SiC substrates are grown sequentially ‑ Type 4H-SiC drift region, p + A p-type 4H-SiC shielding layer and an n-type 4H-SiC carrier extension layer 1 are constructed; an n-type Si carrier extension layer 2 is grown using low-pressure chemical vapor deposition to construct a Si / 4H-SiC heterojunction; and a p-type Si bulk region and an n-type Si carrier extension layer 2 are formed using ion implantation. + Type Si source layer and n ‑ The device employs a Si channel layer; edge trenches are etched, and then a planar main gate and two auxiliary gates are fabricated using low-pressure chemical vapor deposition (LPCVD); electrodes are then deposited. In this invention, an accumulation layer channel is formed at the bottom of the main gate oxide layer, and an inversion layer channel is formed inside the auxiliary gate oxide layer, allowing electrons to transport in parallel. The auxiliary gate voltage regulates the Si / 4H-SiC heterojunction barrier to achieve tunneling, reducing specific on-resistance. During reverse recovery, this heterojunction isolates the transport paths of tail-state electrons and holes in the drift region, preventing recombination, reducing reverse recovery loss, and improving static and dynamic performance.

Description

Technical Field

[0001] This invention relates to a self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor and its fabrication method, belonging to the field of semiconductor power device technology. Background Technology

[0002] In silicon carbide (4H-SiC) inversion layer channel and accumulation layer channel metal-oxide-semiconductor field-effect transistors (MOSFETs), the gate voltage of the inversion layer channel MOSFET ( V GS By exciting an electric field, minority carriers—electrons—are attracted on the p-body side of the gate oxide layer (SiO2, etc.) / p-SiC heterojunction to form a conductive channel; accumulation layer channel MOSFET V GS By exciting the electric field in the gate oxide layer (SiO2, etc.) / n-SiC heterostructure, n - -SiC attracts majority carriers—electrons—to form a conductive channel. The research results in the paper "Accumulation channel vs. inversion channel 1.2 kVrated 4H-SiC buffered-gate (BG) MOSFETs: Analysis and experimental results (DOI: 10.1109 / ispsd.2018.8393680)" show that the field-effect mobility of the 4H-SiC accumulation layer channel can reach 2 to 3 times that of the inversion layer channel. This is because the carrier movement in the accumulation layer channel is less affected by the scattering of the SiO2 / 4H-SiC interface states on the gate side, thus reducing the channel resistance and even the overall specific on-resistance of the device. R on,sp ), but its gate threshold voltage ( V th The low efficiency poses a risk of false turn-on during high-speed switching. The paper "A heterojunction-based SiCpower double trench MOSFET with improved switching performance and reverse recovery (DOI: 10.1016 / j.spmi.2020.106466)" demonstrates a double trench MOSFET with improved switching performance and reverse recovery. + / p - p-type polysilicon gate, intermediate trench source and its bottom corner shielding layer - -Si(source) / n -The -4H-SiC (drift region) heterojunction field-effect transistor uses a double-sided gate oxide layer / p-4H-SiC heterojunction to form an inversion layer channel. Its double-sided trench n + / p - The polysilicon gate heterojunction introduces gate capacitance, which is related to the oxide layer capacitance. C ox ), drift region depletion capacitance ( C dep ) Series connection, reduce the total C gd Reduce dynamic quality factor FOM HF =( R on,sp • C gd and dynamic losses; bottom p of the intermediate slot source electrode - -Si / n - -4H-SiC heterojunction improves reverse recovery characteristics. The paper "A Si / SiC heterojunction double-trench MOSFET with improved conduction characteristics (DOI: 10.3390 / mi16121335)" proposes a 4H-SiC / Si heterojunction tunneling field-effect transistor with an embedded double-trench source and a bottom grounded shield layer. It utilizes the gate voltage to form an inversion layer channel in the high-k gate dielectric layer / p-Si heterojunction, and further utilizes... V GS By adjusting the barrier height and width of the gate-side p-Si / n-4H-SiC heterojunction, electrons from the source can tunnel through the inversion layer channel, then enter the n-4H-SiC carrier extension layer (CSL). R on,sp and forward conduction voltage ( V on The degradation effect is significantly reduced, and the bipolar degradation effect is eliminated. The paper "Anovel 4H-SiC accumulation mode MOSFET with ultra-low specific on-resistance and improved reverse recovery capability (DOI: 10.1049 / pel2.12556)" presents a 4H-SiC multi-trench gate accumulation layer channel MOSFET, utilizing p... + n-type poly-Si gate-assisted depletion of the gate oxide layer outside - Enhancement-mode devices are achieved using a channel layer with optimized gate spacing and... Ron,sp The relationship; embedding a Schottky barrier diode (SBD) at the bottom of the gate edge to improve reverse recovery performance and p + A shielding layer is used to boost voltage. The authorized invention patent, "A Two-Dimensional Heterojunction Tunneling Field-Effect Transistor Immunosensor and its Fabrication Method," (patent number ZL202010858426.6), describes a two-dimensional heterojunction tunneling field-effect transistor. By applying a gate voltage through a buried gate in the substrate, the energy bands of the two-dimensional heterojunction are controlled to be arranged in a staggered or gapped configuration. In the staggered configuration, the conduction band of one two-dimensional material is located above the conduction and valence bands of another two-dimensional material, with no tunneling window, preventing tunneling and resulting in extremely low current, thus achieving turn-off. In the gapped configuration, the conduction band of one two-dimensional material is located below the valence band of another two-dimensional material, with a tunneling window, enabling tunneling and resulting in a large conduction current. The two two-dimensional materials here are only nanometer-thick, making fabrication difficult.

[0003] Existing technology has confirmed that Si / 4H-SiC heterojunction tunneling can effectively reduce the voltage drop of field-effect transistors. R on, sp Furthermore, it improves reverse recovery. However, a substantial integration of a high carrier mobility accumulation layer channel and a high threshold stability inversion layer channel, along with a simultaneously nested Si / 4H-SiC heterojunction tunneling self-recovery mechanism, has not yet been achieved. This structural simplicity and functional separation in the design prevents existing devices from overcoming the physical constraints between forward transport impedance and dynamic reverse recovery loss through structural complementarity in complex power conversion systems. Therefore, it is urgent to break through existing technologies and overcome the current limitations of silicon carbide MOSFETs in simultaneously achieving extremely low forward transport impedance and dynamic reverse recovery loss. R on,sp The dilemma of excellent reverse recovery characteristics. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings and deficiencies of the existing technology and to provide a self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor and its fabrication method, so as to solve the problem that existing devices are difficult to achieve both extremely low specific on-resistance, excellent reverse recovery characteristics and flexible switching of multiple operating modes.

[0005] This application provides a method for fabricating a self-restoring Si / 4H-SiC heterojunction tunneling field-effect transistor, comprising the following steps: S1. Using hot-wall chemical vapor deposition (HWCVD) technology, in n + Type 4H-SiC substrate (n + -SUB) grows n - Type 4H-SiC drift region (n - -DR); using masking and ion implantation methods, in n - -Aluminum (Al) ions are injected into both sides of the DR to form p+ Type 4H-SiC shielding layer (p + -SL); then in n - -DR and p + - Nitrogen (N)-doped n-type 4H-SiC carrier extension layer 1 (n-CSL1) is grown on SL using hot-wall chemical vapor deposition (HWCVD); high-temperature vacuum annealing is used to activate impurities and reduce defects; S2. Using low-pressure chemical vapor deposition (LPCVD) technology, an n-type Si carrier extension layer 2 (n-CSL2) is grown on an n-type 4H-SiC carrier extension layer 1 (n-CSL1) to construct a Si / 4H-SiC heterojunction. S3. Using a masking and ion implantation method, boron (B) ions are implanted on both sides of the n-type Si carrier extension layer 2 (n-CSL2) to form a p-type Si body region; then phosphorus (P) ions are implanted on the p-type Si body region to form an n + Type Si source layer (n + -S) and n - Type Si channel layer (n - -CH); then vacuum annealing is performed to activate impurities and reduce defects; S4. Using mask and inductively coupled plasma (ICP) etching technology, side trenches are formed on both sides of the upper end of the multilayer structure. The top of the multilayer structure and the surface of the side trenches are thermally oxidized to form an oxide layer (SiO2). Then, low-pressure chemical vapor deposition (LPCVD) technology is used to etch the n-type Si carrier extension layer 2 (n-CSL2) and n... - Type Si channel layer (n - n grows on the top oxide layer of -CH) + Type-1 polycrystalline Si main gate; n-type growth on the side slot oxide layer + Polycrystalline Si auxiliary gate; thinning of n-type silicon using chemical mechanical polishing (CMP) method. + Type 4H-SiC substrate (n + -SUB) to target thickness; S5. Using mask and inductively coupled plasma (ICP) etching technology, etch n + Type Si source layer (n + -S) and p-type Si body oxide (SiO2) layers; electron beam evaporation is used to evaporate the oxide layer in the n-type Si body region. + The top of the polycrystalline Si main gate and auxiliary gate, n + Type Si source layer (n + -S) and the top of the p-type Si body region (p-body), 4H-SiC substrate (n +Alloy thin films are deposited on the bottom of the SUB to form ohmic contacts for the main gate (PG), auxiliary gate (AG), source (S), and drain (D); thus creating a self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor.

[0006] Furthermore, when the self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor is turned on, the planar main gate oxide layer and the bottom n-type Si channel layer (n-CH) form a SiO2 / n-Si heterojunction accumulation layer channel at the bottom of the main gate; the side auxiliary gate oxide layer and the inner p-type Si body region (p-body) form a SiO2 / p-Si heterojunction inversion layer channel inside the auxiliary gate. The accumulation layer channel and the inversion layer channel transport charge carriers—electrons—in parallel to reduce the channel resistance and the specific on-resistance of the device. R on, sp ).

[0007] Furthermore, in the self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor, the side gate voltage applied by the auxiliary gate (AG) is... V GS It is used to control the height and width of the heterojunction barrier formed by the n-type Si carrier extension layer 2 (n-CSL2) and the n-type 4H-SiC carrier extension layer 1 (n-CSL1) below the p-type Si body region (p-body), as well as the probability of electrons tunneling through this heterojunction, thereby controlling the switching of the device.

[0008] Furthermore, when the self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor is turned on in reverse, the n + Type 4H-SiC substrate (n + -SUB), n - Type 4H-SiC drift region (n - -DR), n-type 4H-SiC carrier extension layer 1 (n-CSL1), n-type Si carrier extension layer 2 (n-CSL2), n - Type Si channel layer (n - -CH) and n + Type Si source layer (n + Tail-state electrons in the -S) are driven from the source (S) by a reverse electric field; while the n-type 4H-SiC carrier extension layer 1 (n-CSL1), n - Type 4H-SiC drift region (n - -DR), n + Type 4H-SiC substrate (n + Minority carriers—holes—are extracted from the drain (D) of the n-type Si carrier extension layer 2 (n-CSL2). - Type Si channel layer (n- -CH) and n + Type Si source layer (n + Minority carriers—holes—in the Si / 4H-SiC heterostructure are blocked by the Si / 4H-SiC heterostructure barrier; p-type Si body region (p-body), p + Type 4H-SiC shielding layer (p + The majority carriers—holes—in the p-body / n-CSL2 Si homojunction are respectively disposed of by the p-body / n-CSL2 Si homojunction and p + -SL / n - The -DR 4H-SiC homojunction barrier prevents electrons and holes from recombining, thus improving the reverse recovery characteristics of the device and reducing reverse recovery loss.

[0009] Furthermore, the p + Type 4H-SiC shielding layer (p + -SL) is used to shield the field strength peak at the corner of the auxiliary gate oxide layer to improve the device withstand voltage and control the current distribution.

[0010] Furthermore, in the self-restoring Si / 4H-SiC heterojunction tunneling field-effect transistor, the n + The thickness of the 4H-SiC substrate is 2.0 × 10⁻⁶. -4 cm, width 4.6×10 -4 cm, with a doping concentration of 1.0 × 10⁻⁶. 20 cm -3 The n - The thickness of the 4H-SiC drift region is 15.0 × 10⁻⁶. -4 cm, width 4.6×10 - 4 cm, with a doping concentration of 6.0 × 10⁻⁶. 15 cm -3 The p + The thickness of the 4H-SiC shielding layer is 1.0 × 10⁻⁶. -4 cm, width 1.1×10 -4 cm, with a doping concentration of 8.0 × 10⁻⁶. 17 cm -3 The thickness of the n-type 4H-SiC carrier extension layer 1 (n-CSL1) is 0.7 × 10⁻⁶. -4 cm, width 3.6×10 -4 cm, with a doping concentration of 5.0 × 10⁻⁶. 15~17 cm -3 The thickness of the n-Si carrier extension layer 2 (n-CSL2) is 1.7 × 10⁻⁶. -4 cm, width 3.6×10-4 cm, with a doping concentration of 1.0 × 10⁻⁶. 15~17 cm -3 The thickness of the p-Si bulk region is 1.0 × 10⁻⁶. -4 cm, width is (1.2~1.6)×10 -4 cm, with a doping concentration of 1×10 17 cm -3 The thickness of the parasitic JFET channel is 1.2 × 10⁻⁶. -4 cm, width is (0.4~1.2)×10 -4 cm, with a doping concentration of 5.0 × 10⁻⁶. 16 cm -3 The n - The thickness of the Si channel layer is 2.0 × 10⁻⁶. -5 cm, width 0.6×10 -4 cm, with a doping concentration of 1.0 × 10⁻⁶. 16 cm -3 The n + The thickness of the Si source layer is 2.0 × 10⁻⁶. -5 cm, width is (0.2~0.4)×10 -4 cm, with a doping concentration of 1.0 × 10⁻⁶. 20 cm -3 The n + The thickness of the polycrystalline Si gate is 5.0 × 10⁻⁶. -5 cm, width 2.0 × 10 -4 cm, doping concentration is 1.0×10 20 cm -3 The n + The thickness of the auxiliary gate in polycrystalline Si is 2.4~3.2×10⁻⁶. -4 cm, width 5.0 × 10 -5 cm, doping concentration is 1.0×10 20 cm -3 The thickness of the gate oxide layer is 5.0 × 10⁻⁶. -6 cm.

[0011] The present invention also provides a self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor, characterized in that it is manufactured using the preparation method of the self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor described in any one of the above-mentioned methods.

[0012] This invention discloses a self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor and its fabrication method. The core of this invention lies in the heterojunction integration of Si and 4H-SiC materials, constructing multiple carrier transport paths that can be controlled collaboratively by two gates. Compared to existing technologies, this invention has significant advantages: During the turn-on phase, the device achieves parallel carrier transport through the accumulation layer channel under the planar main gate and the inversion layer channel within the side gate. This structure overcomes the low mobility defect of a single 4H-SiC inversion channel. Combined with the tunneling effect of the Si / 4H-SiC heterojunction, it promotes efficient electron transport through the Si / 4H-SiC heterojunction interface into the drift region, greatly reducing the specific on-resistance of the device. Regarding reverse characteristics, due to the self-recovery mechanism, at the turn-off instant, tail-state electrons and minority carriers—holes—are extracted from the n-type doped region through different paths; simultaneously, the p-type Si body region (p-body) and p-type... + Type 4H-SiC shielding layer (p + The majority carriers—holes—in the p-body / n-CSL2 Si homojunction are respectively disposed of by the p-body / n-CSL2 Si homojunction and p + -SL / n - The -DR 4H-SiC homojunction barrier prevents electron and hole recombination, thus improving the reverse recovery characteristics of the device and reducing reverse recovery loss by more than 50%. Furthermore, the embedded p... + The 4H-SiC shielding layer avoids the pre-breakdown problem of the deep edge trench oxide layer and significantly improves the withstand voltage of the device. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings required in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, obtaining other drawings based on these drawings without creative effort still falls within the scope of the present invention.

[0014] Appendix Figure 1 This is a flowchart of the present invention; Appendix Figure 2 This is a schematic diagram of the preparation process of the present invention; Appendix Figure 3 This is a two-dimensional schematic diagram of the cell of the device of the present invention; Appendix Figure 4 (a), (b), (c), and (d) represent n in the device of this invention, respectively. + -S / n - -CH / n-CSL2 Si homojunction, n +-S / p-body / n-CSL2 Si homojunction, n-CSL2 / n-CSL1 (i.e., Si / 4H-SiC) heterojunction, n-CSL1 / n - -DR / n + -SUB 4H-SiC homojunctions are respectively in V GS =0.00 V and V DS =5.00 V、 V GS =15.00 V and V DS Simulated energy band diagram at 5.00 V (black curve, blue curve); Appendix Figure 5 (a), (b), (c), and (d) represent n in the device of this invention, respectively. + -S / n - -CH / n-CSL2 Si homojunction, n-Si(n-CSL2) / n-4H-SiC(n-CSL1) / n - -4H-SiC(n - -DR) / n + -4H-SiC(n + -SUB) heterojunction, p-body / n-CSL2 Si homojunction, p + -SL / n - -DR 4H-SiC homojunction in V GS = 0.00 V and V DS Simulated band structure of -1.00 V; Appendix Figure 6 (a), (b), (c), and (d) represent the transfer characteristics of the device of the present invention, respectively. J DS - V GS The relationship curve for the doping concentration of the n-Si carrier extension layer (n-CSL2) N CSL2 The doping concentration of the n-4H-SiC carrier extension layer (n-CSL1) N CSL1 ), width of parasitic JFET ( W J ), n + Thickness of polycrystalline Si side gate ( L Gate The dependence of the reference device on the data is used for comparison. Appendix Figure 7(a) Doping concentration of the n-Si carrier extension layer (n-CSL2) N CSL2 (b) Doping concentration of the n-4H-SiC carrier extension layer (n-CSL1) N CSL1 (c) Width of the parasitic JFET W J ), (d) n + Thickness of polycrystalline Si side gate ( L Gate The output characteristics of the device of this invention ( J DS - V DS The influence of the relationship, where data from the reference device is used for comparison; Appendix Figure 8 (a), (b), (c), and (d) represent the doping concentration of the n-Si carrier extension layer (n-CSL2) as a function of the blocking and breakdown characteristics of the device of the present invention. N CSL2 The doping concentration of the n-4H-SiC carrier extension layer (n-CSL1) N CSL1 ), width of parasitic JFET ( W J ), n + Thickness of polycrystalline Si side gate ( L Gate The dependence of the reference device on the data is used for comparison. Appendix Figure 9 (a) Doping concentration of the n-Si carrier extension layer (n-CSL2) N CSL2 (b) Doping concentration of the n-4H-SiC carrier extension layer (n-CSL1) N CSL1 (c) Width of the parasitic JFET W J ), (d) n + Thickness of polycrystalline Si side gate ( L Gate The impact of this on the reverse turn-on characteristics of the device is shown in the data of the reference device for comparison. Appendix Figure 10 (a), (b), (c), and (d) represent the reverse recovery characteristics of the device of the present invention with respect to the doping concentration of the n-Si carrier extension layer (n-CSL2), respectively. N CSL2 The doping concentration of the n-4H-SiC carrier extension layer (n-CSL1) NCSL1 ), width of parasitic JFET ( W J ), n + Thickness of polycrystalline Si side gate ( L Gate The dependence of the reference device on the data is used for comparison. Appendix Figure 11 (a) Doping concentration of the n-Si carrier extension layer (n-CSL2) N CSL2 (b) Doping concentration of the n-4H-SiC carrier extension layer (n-CSL1) N CSL1 (c) Width of the parasitic JFET W J ), (d) n + Thickness of polycrystalline Si side gate ( L Gate The impact of the device's turn-off and turn-on processes on the present invention is described, with data from a reference device used for comparison. Detailed Implementation

[0015] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0016] It should be noted that all uses of "first" and "second" in the embodiments of the present invention are for the purpose of distinguishing two entities with the same name but different names or different parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be construed as limiting the embodiments of the present invention. Subsequent embodiments will not explain this in detail.

[0017] The directional and positional terms used in this invention, such as "up," "down," "front," "back," "left," "right," "inner," "outer," "top," "bottom," and "side," are merely for reference to the accompanying drawings. Therefore, the directional and positional terms used are for illustrating and understanding this invention, and not for limiting the scope of protection of this invention.

[0018] The self-recovery described in this invention refers to the device automatically entering a unipolar conduction mode during reverse recovery. The Si / 4H-SiC heterojunction barrier blocks hole transport and avoids electron-hole recombination. After being turned off, there is no performance degradation and the device quickly recovers its conduction capability.

[0019] As attached Figure 1 As shown in the embodiment of the present invention, a method for fabricating a self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor is provided, comprising the following steps: S1. Using hot-wall chemical vapor deposition (HWCVD) technology, in n+ Type 4H-SiC substrate (n + -SUB) grows n - Type 4H-SiC drift region (n - -DR); using masking and ion implantation methods, in n - -Aluminum (Al) ions are injected into both sides of the DR to form p + Type 4H-SiC shielding layer (p + -SL); then in n - -DR and p + - Nitrogen (N)-doped n-type 4H-SiC carrier extension layer 1 (n-CSL1) is grown on SL using hot-wall chemical vapor deposition (HWCVD); high-temperature vacuum annealing is used to activate impurities and reduce defects; S2. Using low-pressure chemical vapor deposition (LPCVD) technology, an n-type Si carrier extension layer 2 (n-CSL2) is grown on an n-type 4H-SiC carrier extension layer 1 (n-CSL1) to construct a Si / 4H-SiC heterojunction. S3. Using a masking and ion implantation method, boron (B) ions are implanted on both sides of the n-type Si carrier extension layer 2 (n-CSL2) to form a p-type Si body region; then phosphorus (P) ions are implanted on the p-type Si body region to form an n + Type Si source layer (n + -S) and n - Type Si channel layer (n - -CH); then vacuum annealing is performed to activate impurities and reduce defects; S4. Using mask and inductively coupled plasma (ICP) etching technology, side trenches are formed on both sides of the upper end of the multilayer structure. The top of the multilayer structure and the surface of the side trenches are thermally oxidized to form an oxide layer (SiO2). Then, low-pressure chemical vapor deposition (LPCVD) technology is used to etch the n-type Si carrier extension layer 2 (n-CSL2) and n... - Type Si channel layer (n - n grows on the top oxide layer of -CH) + Type-1 polycrystalline Si main gate; n-type growth on the side slot oxide layer + Polycrystalline Si auxiliary gate; thinning of n-type silicon using chemical mechanical polishing (CMP) method. + Type 4H-SiC substrate (n + -SUB) to target thickness; S5. Using mask and inductively coupled plasma (ICP) etching technology, etch n + Type Si source layer (n + -S) and p-type Si body oxide (SiO2) layers; electron beam evaporation is used to evaporate the oxide layer in the n-type Si body region.+ The top of the polycrystalline Si main gate and auxiliary gate, n + Type Si source layer (n + -S) and the top of the p-type Si body region (p-body), 4H-SiC substrate (n + Alloy thin films are deposited on the bottom of the SUB to form ohmic contacts for the main gate (PG), auxiliary gate (AG), source (S), and drain (D); thus creating a self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor.

[0020] The beneficial effect of this process path is that it significantly improves the long-term reliability and upper limit of the breakdown voltage of the device. Gate oxide breakdown is the leading cause of power FET failure, especially the electric field crowding effect at the corner of the edge slot. By setting p + The shielding layer reduces the maximum electric field strength in this region by more than 40%, effectively alleviating gate oxide stress. Simultaneously, this layer also regulates the conduction current path, resulting in a more uniform current distribution and preventing localized overheating. This design allows the device to withstand high-voltage surges with ease, enhancing its robustness in industrial applications. As an alternative embodiment, those skilled in the art can also design the shielding layer as a floating structure or a source-terminal structure to optimize the junction capacitance according to specific dynamic response requirements.

[0021] The specific process is as follows: In step S1, hot-wall chemical vapor deposition (HWCVD) technology is used to deposit vapor on n... + Type 4H-SiC substrate (n + Nitrogen (N)-doped n-type nitrogen-doped ... - Type 4H-SiC drift region (n - -DR); then using masking and ion implantation methods, in n - -Aluminum (Al) is injected into both sides of DR to form p + Type 4H-SiC shielding layer (p + -SL); then use HWCVD technology, in n - -DR and p + Nitrogen (N)-doped n-type 4H-SiC carrier extension layer 1 (n-CSL1) is grown on the -SL; high-temperature vacuum annealing is used to activate impurities and reduce defects.

[0022] After completing step S1, the result is as follows: Figure 2 The structure shown in (a) has parameters such as the thickness, width and doping concentration of each layer listed in Appendix 1.

[0023] In step S2, low-pressure chemical vapor deposition (LPCVD) is used to grow an n-type Si carrier extension layer 2 (n-CSL2) on an n-type 4H-SiC carrier extension layer 1 (n-CSL1) to construct a Si / 4H-SiC heterojunction.

[0024] After completing step S2, the result is as follows: Figure 2 The structure shown in (b) is prepared with parameters such as the thickness, width and doping concentration of each layer listed in Appendix 1.

[0025] In step S3, boron (B) ions are implanted on both sides of the n-type Si carrier extension layer 2 (n-CSL2) using a masking and ion implantation method to form a p-type Si body region; then phosphorus (P) ions are implanted on the p-type Si body region to form an n + Type Si source layer (n + -S) and n - Type Si channel layer (n - -CH); then vacuum annealing is performed to activate impurities and reduce defects.

[0026] In step S4, firstly, mask and inductively coupled plasma (ICP) etching technology is used to etch the upper two sides of the above multilayer structure to form side grooves; Secondly, thermally oxidized n-type Si carrier extension layer 2 (n-CSL2) and n - Type Si channel layer (n - An oxide layer (SiO2) is formed on the top and side groove surfaces of the -CH). Then, using low-pressure chemical vapor deposition (LPCVD), on the n-type Si carrier extension layer 2 (n-CSL2) and n - Type Si channel layer (n - n grows on the top oxide layer of -CH) + Type-1 polycrystalline Si main gate; n-type growth on the side slot oxide layer + Type-type polycrystalline Si auxiliary gate; Finally, chemical mechanical polishing (CMP) was used to thin n. + Type 4H-SiC substrate (n + -SUB).

[0027] After completing steps S3 and S4, the following results are obtained: Figure 2 The structure shown in (c) is prepared with parameters such as the thickness, width and doping concentration of each layer listed in Table 1.

[0028] In step S5, n is etched using mask and inductively coupled plasma (ICP) etching technology. + Type Si source layer (n + -S) and p-type Si body oxide (SiO2) layers; electron beam evaporation is used to evaporate the oxide layer in the n-type Si body region. + The top of the polycrystalline Si main gate and auxiliary gate, n + Type Si source layer (n +-S) and the top of the p-type Si body region (p-body), 4H-SiC substrate (n + The bottom of the SUB is deposited with alloy thin films to form ohmic contacts for the main gate (PG), auxiliary gate (AG), source (S), and drain (D).

[0029] After completing step S5, the result is as follows: Figure 2 The structure shown in (d) is prepared with parameters such as the thickness, width and doping concentration of each layer listed in Table 1.

[0030] By completing all the above steps, in this embodiment of the invention, a self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor comprising an accumulation layer channel and an inversion layer channel is obtained.

[0031] Appendix Table 1 Cell structure parameters of the device of the present invention Among them 2× W body + W J = 3.60×10 -4 cm, 2× W SiS + W PSiS + W Ch = W body , L AG The parameter change is in p + -Depth changes in SL.

[0032] Figure 3 This is a cross-sectional schematic diagram of the cell of the self-recovering 4H-SiC / Si heterojunction tunneling field-effect transistor (IC-HJ-TFET) prepared according to the present invention. In this invention, the planar main gate oxide layer and the bottom n-Si layer form a SiO2 / n-Si heterojunction accumulation layer channel at the bottom of the main gate; the side auxiliary gate oxide layer and the inner p-Si body region form a SiO2 / p-Si heterojunction inversion layer channel inside the auxiliary gate. Both layers transport carriers in parallel, which can reduce the channel resistance and even the overall resistance. R on,sp ; Utilizing higher side gate voltage ( V GS By controlling the barrier width and electron tunneling probability of the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction beneath the p-Si bulk region, the switching of the device can be controlled, thereby achieving lower [potential]. R on, sp higher V thDuring reverse freewheeling, n-4H-SiC carrier extension layer 1 (n-CSL1), n-Si carrier extension layer 2 (n-CSL2), n - -4H-SiC drift region (n - In the reverse recovery (DR) state, tail-state electrons are extracted from the source; minority carriers—holes—are extracted from the drain, preventing electron-hole recombination, shortening the reverse recovery time, and reducing reverse recovery losses.

[0033] If the voltage between the main gate (PG), auxiliary gate (AG), and source (S) is... V GS ) is 0, n at the bottom of the main gate oxide layer - -Si is depleted by the bottom p-Si (p-body), while p-Si is depleted by the top n + -Si source layer (n + -S) depletion. Therefore, the SiO2 / n at the bottom of the main gate (PG) is depleted. - -Si heterojunction interface has no n - The majority carriers—electrons—in p-Si accumulate; the SiO2 / p-Si heterojunction interface inside the auxiliary gate (AG) also lacks the minority carriers—electrons—of p-Si, thus failing to form a conductive channel; even with a forward drain-source voltage applied ( V DS When no charge carriers pass through the device, the device is cut off and withstands voltage. V DS .when V GS ≥ Forward gate threshold voltage ( V th ), V GS The excitation electric field attracts SiO2 / n at the bottom of the main gate. - -Si heterojunction n - The majority carriers of Si—electrons—accumulate in this junction, forming an accumulation layer channel; simultaneously, they attract the minority carriers of p-Si from the SiO2 / p-Si heterojunction inside the auxiliary gate (AG), forming an inversion layer channel. Additionally... V GS The excitation electric field attracts electrons from the n-Si(CSL2) and n-4H-SiC(CSL1) atoms inside the auxiliary gate (AG) to accumulate near the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction inside the gate. This reduces the barrier height and width of the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction near the inside of the auxiliary gate (AG). If a forward electric field is applied... V DS The probability of electrons tunneling through this heterojunction increases dramatically. Therefore, inV GS and V DS Under the combined control of the source (S), electrons can start from the source layer (n) and pass through the source layer (n). + -Si), accumulation layer channel (SiO2 / n) - The inversion layer channel (SiO2 / p-Si heterojunction) and the inversion layer channel (SiO2 / p-Si heterojunction) enter the n-Si carrier extension layer 2 (CSL2), tunnel through the n-Si (CSL2) / n-4H-SiC (CSL1) heterojunction and enter the carrier extension layer 1 (CSL1), and then pass through the n-Si carrier extension layer 2 (CSL2). - -4H-SiC drift region (n - -DR), n + -4H-SiC substrate (n + When the -SUB) voltage reaches the drain, the device is turned on, and the voltage drop is very low.

[0034] The device of this invention simultaneously possesses parallel SiO2 / Si heterojunction accumulation layer height and inversion layer channels for parallel electron transport, resulting in a carrier injection efficiency significantly higher than that of a single channel. Furthermore, the channel mobility is significantly higher than the corresponding value for a SiO2 / 4H-SiC channel because the SiO2 / Si interface state density is lower than that of SiO2 / SiC, leading to lower resistance and even lower overall specific on-resistance. R on, sp () significantly reduced. In addition, V GS By controlling the barrier height and width, as well as the electron tunneling probability, of the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction, the controllability and reliability of the device are enhanced. The p⁺-4H-SiC shielding layer (p + -SL) can shield the field strength peak at the corner of the auxiliary gate oxide layer, improving the device's breakdown voltage while controlling the current distribution. Utilizing n - -4H-SiC serves as the drift region (n - -DR) leverages its high critical breakdown field strength to improve device withstand voltage and reduce device size.

[0035] A reference device, IC-HJ-CHT-TFET (Counterpart 1), was set up using n-4H-SiC material instead of n-Si (CSL2) to compare and investigate the impact of CSL2 material type on device performance. A reference device, HJ-CHT-TFET (Counterpart 2), was set up without an auxiliary gate and using an inversion layer channel to compare and analyze the impact of the auxiliary gate and accumulation layer channel on device performance. A device using p... +The IC-HJ-PG-TFET (Counterpart3) is used as a reference device with a polycrystalline Si main gate and auxiliary gate to investigate the effect of gate doping type on device performance.

[0036] The working principle of the device provided in the embodiments of the present invention is as follows: Figures 4 to 5 As shown, the specific explanation is as follows.

[0037] (1) Forward cutoff and conduction In the appendix Figure 4 In V GS = 0.00V& V DS At 5.00V, n in the device of this invention + -Si source layer (n + Electrons from the -S group cannot enter the bottom of the main gate (PG) oxide layer. - -Si layer(n - -CH), and cannot enter the p-Si body region inside the auxiliary gate (AG), because n + -Si / n - -Si、n + -Si / p-Si homojunctions have an electronic potential barrier, as shown in the attached figure. Figure 4 The black curves in (a) and (b) indicate the SiO2 / n ratio at this point. - -Si and SiO2 / p-Si heterojunctions do not have electrons because n - -Si and p-body mutually deplete each other. Simultaneously, electrons cannot pass through the n-Si(CSL2) / n-4H-SiC (CSL1) heterojunction and the n-CSL1 / n... - -DR 4H-SiC homojunction, as shown in the attached diagram. Figure 4 The black curves in (c) and (d) are shown.

[0038] like V GS = 15.00 V& V DS = 5.00V, n + -Si / n - -Si、n + The electron barrier of the -Si / p-Si homojunction disappears, as shown in the attached figure. Figure 4 The blue curves in (a) and (b) are shown. Furthermore, V GSThe excited electric field induces a high concentration of electrons on both sides of the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction near the auxiliary gate (AG), resulting in a very low and thin electron barrier and an extremely thin depletion region. This is based on the heterojunction tunneling probability... P T The expression, in D T The barrier width of the heterojunction is expressed in meters (m). ψ is the effective mass of the particle, expressed in kg. b Here, is the barrier height in J; h is Planck's constant. Calculations show that at this point... P T It equals 40.1%.

[0039] Additionally, n-CSL1 / n - -DR、n - -DR / n + The electron barrier of the -SUB 4H-SiC homojunction disappears, as shown in the attached figures. Figure 4 The blue curves in (c) and (d) represent the SiO2 / n ratio at this point. - Electrons appear in the -Si and SiO2 / p-Si heterojunctions, forming the accumulation layer channel and inversion layer channel, respectively. Electrons can originate from the source (S), pass through the n... + -Si(n + -S), n - -Si(n - -CH) and p-Si(p-body), n-Si(CSL2), tunneling through the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction barrier, and then through n-4H-SiC(CSL1), n - -4H-SiC(n - -DR), n + -4H-SiC(n + -SUB) reaches the drain (D). Holes traveling in the opposite direction along this path also have no hole barrier, but CSL2, CSL1, and n - -DR、n + -SUB is all n-type doped, and holes are minority carriers with a very small number of them.

[0040] (2) Reverse opening As attached Figure 5 As shown, the device of the present invention is in V GS = 0.00 V&V DS At a voltage of -1.00 V, electrons can flow from the drain (D) through the substrate (n). + -SUB), Drift Zone (n - -DR), carrier extension layers (n-CSL1, n-CSL2), and then through the channel (n - -CH) reaches the source layer (n + -S) up to the source (S), as shown in the appendix Figure 5 As shown in (a) and (b), in this case, the n-Si(n-CSL2) / n-4H-SiC(n-CSL1) heterojunction does not have an electron barrier, but a hole barrier blocks the reverse conduction of holes, as shown in the attached diagram. Figure 5 As shown in (b). Figure 5 As shown in (c) and (d), electrons and holes cannot pass through the p-body / n-CSL2 Si homojunction, p + -SL / n - -DR 4H-SiC homojunction. Therefore, when the device is reversed, only as shown in the attached diagram... Figure 5 The electron transport paths shown in (a) and (b) belong to the unipolar (electron) conduction mode. Therefore, when the device is reversed, the recombination process of minority carriers—holes—with residual electrons in the drift region is avoided, thereby significantly reducing the reverse recovery charge. Q rr Peak current density () J rrm ), shortening the reverse recovery time ( t rr ).

[0041] The main static characteristics of the device of the present invention are further analyzed below, such as Figures 6 to 9 As shown, the specific explanation is as follows.

[0042] (1) Transfer characteristics The transfer characteristics (drain current density) of the device of this invention J DS - Gate-source voltage ( V GS The relationship curve for the doping concentration of the n-Si carrier extension layer (CSL2) is shown in the curve. N CSL2 The doping concentration of the n-4H-SiC carrier extension layer (CSL1) N CSL1 ), width of parasitic JFET ( W J ), n + Thickness of polycrystalline Si side gate ( L Gate The dependency of ) is as follows: Figure 6As shown. From the appendix Figure 6 (a) It is evident that the device transfer characteristics are almost unaffected by N CSL2 The influence of this. This indicates that in this device N CSL2 The tolerance is relatively large. (See attached image) Figure 6 As shown in (b), with N CSL1 From 5.00×10 15 cm -3 Increased to 5.00×10 17 cm -3 The gate threshold voltage of the device of the present invention ( V th The voltage dropped from 7.22V to 5.66V, but the drain current density ( J DS A significant improvement. Because of the increase... N CSL1 This leads to a decrease and thinning of the electron barrier in the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction, significantly increasing the probability of electron tunneling through this heterojunction. V GS The conditions for device conduction can be met at this point, that is... V th along with N CSL1 The increase leads to a decrease; or, in the same... V GS Time saturation J DS along with N CSL1 Increased accordingly. (Attached) Figure 6 (c) and (d) reflect that the device transfer characteristics are almost unaffected by the transfer characteristics. W J and L Gate The effect of these two parameters is because changes in the SiO2 / n ratio of the main gate oxide layer... - The formation of the SiO2 / p-Si heterojunction inversion layer channel and the auxiliary gate oxide layer channel in the SiO2 / p-Si heterojunction, and the lack of tunneling function in the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction, also reflect the fact that in this device... W J and L Gate The tolerance is relatively large.

[0043] As attached Figure 6 As shown, the device of the present invention V th With reference device (counterpart) 1 V thThe results are largely the same because the reference device's channel was already formed before the tunneling probability increased significantly, so the presence or absence of an n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction does not change the overall situation. V th Reference device 2 V th It is slightly larger because it contains only the inversion layer channel. (Refer to device 3.) V th Up to 10.01 V, this is due to the p-value. + Polycrystalline Si gate-assisted depletion accumulation layer channel, inversion layer channel V GS The device can only conduct at higher temperatures. V th Higher. The n of this device + The polycrystalline Si gate will not deplete the accumulation layer channel or the inversion layer channel. V th Lower. Furthermore, as shown in the attached document... Figure 6 As shown, V DS At >15V, the device of the present invention and reference device 3 J DS Significantly larger than reference devices 1 and 2 J DS This reflects the advantage of tunneling in the n-Si(CSL2) / n-4H-SiC (CSL1) heterojunction in improving the current transport capability of the device, while the latter two CSL2 / CSL1 4H-SiC homojunctions do not tunnel.

[0044] (2) Output characteristics Appendix Figure 7 The doping concentration of the n-Si carrier extension layer (CSL2) is shown. N CSL2 The doping concentration of the n-4H-SiC carrier extension layer (CSL1) N CSL1 ), width of parasitic JFET ( W J ), n + Thickness of polycrystalline Si side gate ( L Gate Changes in ) affect the device's output characteristics (drain current density). J DS - Drain-source voltage ( V DS The influence of the relationship curve. From the appendix Figure 7 (a) It is evident that, J DS and R on, sp Not followingN CSL2 The change is due to the increase in the band gap, because the barrier of the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction is mainly located on the wide band gap n-4H-SiC(CSL1) side, while the change in the narrow band gap n-Si(CSL2) side... N CSL2 The height and width of the barrier to this heterojunction have negligible impact, meaning their influence on the tunneling probability of the heterojunction is insignificant. J DS and ratio of on-resistance ( R on, sp ) does not follow N CSL2 And change. (See attached) Figure 7 As shown in (b) J DS along with N CSL1 Increased with the increase R on, sp Significantly reduced. This is because of the increase N CSL1 This results in a decrease in the height and width of the barrier and the width of the depletion region in the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction, significantly increasing the probability of electron tunneling through the junction. (From the attached...) Figure 7 (c) It is evident that the change W JFET Almost no impact J DS and R on, sp This means that the tolerance for the parasitic JFET channel width is relatively large. (From the attached...) Figure 7 (d) It can be seen that, R on, sp along with L Gate The increase slightly decreased due to the auxiliary gate. V GS This is equivalent to passing through this gate to p + -SL and n - Applying a forward voltage to the pn junction formed by -DR causes the depletion region of this junction to shrink back, and the two p + The carrier channels between -SL widen, but this effect is minimal due to the isolation provided by the auxiliary gate oxide layer.

[0045] From the appendix Figure 7 As can be seen, the present invention device and reference device 3 R on, sp All are lower than reference devices 1 and 2 R on, sp This reflects that tunneling in the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction improves carrier injection and reduces... Ron, sp The CSL2 / CSL1 4H-SiC homojunctions of the latter two do not tunnel. Refer to p in device 3. + The polycrystalline Si gate-assisted depletion n-CH channel, while the n-CH channel of this device... + The polycrystalline Si gate does not deplete the n-CH channel, and all other aspects are consistent between the two. Therefore, the channel resistance of reference device 3 is even lower. R on, sp It is greater than the corresponding value of this device.

[0046] (3) Positive blocking and breakdown characteristics Appendix Figure 8 This reflects the positive blocking and breakdown characteristics of the device of the present invention in response to the doping concentration of the n-Si carrier extension layer (CSL2). N CSL2 The doping concentration of the n-4H-SiC carrier extension layer (CSL1) N CSL1 ), width of parasitic JFET ( W J ), n + Thickness of polycrystalline Si side gate ( L Gate Dependence on ( ). See attached Figure 8 As shown in (a), the forward blocking and breakdown characteristics of the device do not change with... N CSL2 The voltage barrier changes accordingly. This is because CSL2 is not the primary breakdown layer, while the barrier of the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction is mainly distributed on the CSL1 side, as shown in the attached figure. Figure 4 As shown in (c). Therefore, change N CSL2 It will not affect the breakdown voltage of the device. V B ). As attached Figure 8 As shown in (b), the device of the present invention V B along with N CSL1 The increase and decrease are due to the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction and the n-4H-SiC(CSL1) / p + -4H-SiC(p + -SL) The depletion region of the homojunction follows N CSL1 As the voltage increases, the device gradually shrinks, and its withstand voltage decreases. V B As the current decreases, the leakage current increases. When... N CSL1 From 5.00×10 15Increased to 1.00×10 17 cm -3 Even after deducting a 20% design margin, the device still meets the 1700.00 V withstand voltage requirement, demonstrating the high performance of this device. N CSL1 The difference is quite large. (See attached image) Figure 8 As shown in (c) and (d), the forward blocking and breakdown characteristics of the device do not change with... W JFET , L Gate The changes reflect the variations in this device. W JFET , L Gate The tolerance is relatively large.

[0047] (4) Reverse opening characteristic Appendix Figure 9 This shows the doping concentration of the n-Si carrier extension layer (CSL2). N CSL2 The doping concentration of the n-4H-SiC carrier extension layer (CSL1) N CSL1 ), width of parasitic JFET ( W J ), n + Thickness of polycrystalline Si side gate ( L Gate The effect of changes on the reverse turn-on characteristics of the device of the present invention. (From the appendix...) Figure 9 As can be seen from (a) and (b), the absolute value of the reverse turn-on voltage along with N CSL2 , N CSL1 The increase leads to a decrease, because the increase... N CSL2 , N CSL1 This will reduce the width of the depletion region in the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction, facilitating the smooth passage of electrons through this heterojunction, meaning the device can operate at lower... Reverse opening. (See attached image) Figure 9 As shown in (c) and (d), W J and L Gate The changes will not change This is because of change W J and L Gate Reverse device J DS The effect is weak, reflecting the fact that in this deviceW JFET , L Gate The tolerance is relatively large.

[0048] As attached Figure 9 As shown, the device of the present invention Minimum. Refer to device Counterpart1. The larger the value, the more likely n is to be. - -Si(n - The concentrations on both sides of the -CH) / n-4H-SiC(n-CSL2) heterojunction are low, resulting in a high heterojunction barrier and requiring high concentrations of ions. Overcoming the potential barrier is necessary for reverse conduction. Refer to device Counterpart2. The highest value is due to the increase in the barrier peak of the p-Si(p-CH) / n-4H-SiC(n-CSL2) heterojunction caused by the inversion layer channel p-Si, while the other three do not exhibit this phenomenon.

[0049] The following further analyzes the dynamic characteristic simulation of the device of the present invention, such as... Figures 10 to 11 As shown, the specific explanation is as follows.

[0050] (1) Reverse recovery characteristics Appendix Figure 10 The reverse recovery characteristics of the device of the present invention are shown to be affected by the doping concentration of the n-Si carrier extension layer (CSL2). N CSL2 The doping concentration of the n-4H-SiC carrier extension layer (CSL1) N CSL1 ), width of parasitic JFET ( W J ), n + Thickness of polycrystalline Si side gate ( L Gate The diagram shows the dependence on [something], with the reverse recovery analog circuit in the lower right corner. (See attached diagram.) Figure 9 As shown in (a) and (c), the inverse recovery curve hardly follows... N CSL2 , W J And change, reverse recovery time ( T rr The values ​​are essentially constant. This is because the reverse recovery process involves the extraction of residual electrons and minority carriers—holes—from the source and drain, respectively, while the n-Si(n-CSL2) / n-4H-SiC(n-CSL1) heterojunction hinders the outflow of minority carriers—holes—from n-CSL2, and p-Si(p-body), p + -4H-SiC(p +Holes in -SL) are also blocked, as shown in the attached image. Figure 5 As shown in (b), (c), and (d). N CSL2 and W J The changes are insufficient to significantly alter the distribution and reverse extraction of residual electrons and minority carriers—holes—within the drift region. (See attached...) Figure 10 As shown in (b), with N CSL1 Increase in concentration N CSL1 This leads to a decrease in the height and width of the barrier and the width of the depletion region in the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction, resulting in the extraction of more tail-state electrons. T rr Extended. See attached. Figure 10 As shown in (d), T rr Not following L Gate The increase changes, while the peak reverse recovery current density ( J rrm ) L Gate It increases with the increase of the auxiliary gate. V GS This is equivalent to passing through this gate to p + -SL and Applying a forward voltage to the formed pn junction causes the depletion region of the junction to shrink back, while the residual electrons and minority carriers—holes—increase in the drift region.

[0051] As attached Figure 10 As shown, the device of the present invention and the reference device (counterpart) 3 T rr The two devices are identical because, apart from the gate, their structures are the same, and the gate does not affect the reverse recovery process. Refer to devices 1 and 2. T rr The difference is the same but smaller because their n-CSL2 is replaced by n-4H-SiC with a lower concentration of n-Si, resulting in fewer residual electrons in the device.

[0052] (2) Switching characteristics Appendix Figure 11 This reflects the doping concentration of the n-Si carrier extension layer (CSL2). N CSL2 The doping concentration of the n-4H-SiC carrier extension layer (CSL1) N CSL1 ), width of parasitic JFET ( WJ ), n + Thickness of polycrystalline Si side gate ( L Gate The effect of changes on the switching characteristics of the device is illustrated in the inset, which shows a simulation circuit of a double-pulse switching characteristic. (See attached diagram.) Figure 11 As shown in the (a-1) and (a-2) series, with N CSL2 The increase in [the amount of something] reduces the device's on-time. t on ) and shutdown time ( t off There was no change. This is because the device is under stress. V DS At that time, increase N CSL2 This causes the depletion region to primarily extend into the less doped and thicker drift region, with almost no change to the gate-drain capacitance that determines the switching delay. C GD .and N CSL2 Changes V th Almost no effect, as shown in the attached document. Figure 5 As shown in (a). Therefore, the device did not exhibit obvious premature turn-on or delayed turn-off. From the attached... Figure 11 As can be seen in the (b-1) and (b-2) series, with N CSL1 The increase, t off , t on Shorten. Because of the increase. N CSL1 This narrows the depletion region of the n-Si(CSL2) / n-4H-SiC(CSL1) heterojunction, enhances electron tunneling in the heterojunction, and accelerates the charging and discharging process. (See attached image) Figure 11 As shown in the (c-1) and (c-2) series, W J The changes have almost no effect on the switching time of the device, which is attributed to... W J The changes have almost no impact on the device. C GD It does not change the tunneling probability of the device, and therefore does not interfere with the switching characteristics of the device. (From the attached...) Figure 11 From the (d-1) and (d-2) series, it can be seen that, with L Gate The increase in [amount] extends both the turn-off and turn-on times of the device. This is because... L Gate The increase in size reduces the distance between the gate and drain plates. C GD Increased size leads to a longer charging and discharging process.t off , t on extend.

[0053] As attached Figure 11 As shown, the device of the present invention t off = 7.8 ns, t on = 21.5 ns, E sw = E off + E on = 0.29mJ·cm -2 Refer to device Counterpart1. C GD Larger than the device of this invention C GD This is because of the relative permittivity of Si. (11.7), greater than 4H-SiC (9.7) In Counterpart1, the n-CSL2 / n-CSL1 4H-SiC homojunction capacitance is smaller than the n-Si(n-CSL2) / n-4H-SiC(n-CSL1) heterojunction capacitance in this device, while the other capacitances of the two devices are the same; this heterojunction capacitance, connected in series with other capacitances, constitutes the capacitance of this device. C GD The n-CSL2 / n-CSL1 4H-SiC homojunction capacitors, connected in series with other capacitors, constitute Counterpart 1. C GD Therefore, Counterpart1's C GD It is relatively large and has a long charging time. t off =31.5 ns, t on = 46.1 ns, E sw = 0.87 mJ·cm -2 The reference device Counterpart2 does not have an auxiliary gate. C GD It is very small. t off =7.4 ns, t on =10.7 ns, E sw = E off + Eon = 0.21 mJ·cm -2 Refer to device Counterpart3's p. + The polycrystalline Si gate-assisted depletion of the semiconductor adjacent to the gate oxide layer suppresses [the following text is incomplete and likely refers to a different topic:] C GD It has a shorter charging time. t off = 8.0 ns, t on = 14.3 ns, E sw = 0.24 mJ·cm -2 The difference between this and the corresponding value of this device is not significant.

[0054] Implementing the embodiments of the present invention has the following beneficial effects: This invention provides a self-restoring Si / 4H-SiC heterojunction tunneling field-effect transistor and its fabrication method. The doping concentrations of the n-Si carrier extension layer 2 (n-CSL2) and the n-4H-SiC carrier extension layer 1 (n-CSL1) are specified. N CSL2 , N CSL1 ) and the width of the parasitic JFET ( W J ), n + Thickness of polycrystalline Si side gate ( L Gate It has a large tolerance and the process is easy to implement.

[0055] In the device of this invention, the planar main gate oxide layer and the bottom n - -Si layer formation SiO2 / n - -Si heterojunction accumulation layer channel; the auxiliary gate oxide layers on both sides and the inner p-Si bulk region form a SiO2 / p-Si heterojunction inversion layer channel, which transports carriers in parallel; because the SiO2 / Si interface state density is lower than that of the SiO2 / 4H-SiC interface state density, the channel mobility is higher, and the channel resistance and even the total R on,sp Lower, V th Moderate.

[0056] Auxiliary gate voltage ( V GS By adjusting the barrier height, width, and electron tunneling probability of the Si / 4H-SiC heterojunction inside the auxiliary gate, the device's potential can be further reduced. R on,sp This enhances controllability and reliability.

[0057] When the device of the present invention is reverse-current freewheeling, the Si / 4H-SiC heterojunction barrier isolates the n-4H-SiC carrier extension layer 1 (n-CSL1) and n - -4H-SiC drift region (n - The transport paths of tail-state electrons and minority carriers (holes) in the -DR are modified so that the former is extracted from the source and the latter is extracted from the drain, thus avoiding recombination, shortening the reverse recovery time, and reducing reverse recovery loss.

[0058] p in the device of this invention + -4H-SiC shielding layer (p + -SL) can shield the field strength peak at the corner of the auxiliary gate oxide layer, improving the breakdown voltage; at the same time, n - -4H-SiC serves as the drift region (n - -DR), giving full play to its critical breakdown field strength higher than n - The advantages of -Si corresponding values ​​include improved breakdown voltage and reduced device size.

[0059] The above description discloses only preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

[0060] While the invention has been described with reference to several specific embodiments, it should be understood that the invention is not limited to the disclosed specific embodiments. The invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for fabricating a self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor, characterized in that: Includes the following steps: S1. Using hot-wall chemical vapor deposition (HWCVD) technology, in n + Type 4H-SiC substrate (n + -SUB) grows n - Type 4H-SiC drift region (n - -DR); using masking and ion implantation methods, in n - -Aluminum (Al) ions are injected into both sides of the DR to form p + Type 4H-SiC shielding layer (p + -SL); then in n - -DR and p + - Nitrogen (N)-doped n-type 4H-SiC carrier extension layer 1 (n-CSL1) is grown on SL using hot-wall chemical vapor deposition (HWCVD); high-temperature vacuum annealing is used to activate impurities and reduce defects; S2. Using low-pressure chemical vapor deposition (LPCVD) technology, an n-type Si carrier extension layer 2 (n-CSL2) is grown on an n-type 4H-SiC carrier extension layer 1 (n-CSL1) to construct a Si / 4H-SiC heterojunction. S3. Using a masking and ion implantation method, boron (B) ions are implanted on both sides of the n-type Si carrier extension layer 2 (n-CSL2) to form a p-type Si body region; then phosphorus (P) ions are implanted on the p-type Si body region to form an n + Type Si source layer (n + -S) and n - Type Si channel layer (n - -CH); then vacuum annealing to activate impurities and reduce defects; S4. Using mask and inductively coupled plasma (ICP) etching technology, side trenches are formed on both sides of the upper end of the multilayer structure. The top of the multilayer structure and the surface of the side trenches are thermally oxidized to form an oxide layer (SiO2). Then, low-pressure chemical vapor deposition (LPCVD) technology is used to etch the n-type Si carrier extension layer 2 (n-CSL2) and n... - Type Si channel layer (n - n grows on the top oxide layer of -CH) + Type-1 polycrystalline Si main gate; n-type growth on the side slot oxide layer + Polycrystalline Si auxiliary gate; thinning of n-type silicon using chemical mechanical polishing (CMP) method. + Type 4H-SiC substrate (n + -SUB) to target thickness; S5. Using mask and inductively coupled plasma (ICP) etching technology, etch n + Type Si source layer (n + -S) and p-type Si body (p-body) oxide layers (SiO2); using electron beam evaporation, in n + The top of the polycrystalline Si main gate and auxiliary gate, n + Type Si source layer (n + -S) and the top of the p-type Si body region (p-body), 4H-SiC substrate (n + Alloy thin films are deposited on the bottom of the SUB to form ohmic contacts for the main gate (PG), auxiliary gate (AG), source (S), and drain (D); thus creating a self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor.

2. The method for fabricating a self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor as described in claim 1, characterized in that: When the self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor is turned on, the planar main gate oxide layer and the bottom n-type Si channel layer (n-CH) form a SiO2 / n-Si heterojunction accumulation layer channel at the bottom of the main gate; the side auxiliary gate oxide layer and the inner p-type Si body region (p-body) form a SiO2 / p-Si heterojunction inversion layer channel inside the auxiliary gate. The accumulation layer channel and the inversion layer channel transport charge carriers—electrons—in parallel to reduce the channel resistance and the specific on-resistance of the device. R on, sp ).

3. The method for fabricating a self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor as described in claim 1, characterized in that: In the self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor, the side gate voltage applied by the auxiliary gate (AG) is... V GS It is used to control the height and width of the heterojunction barrier formed by the n-type Si carrier extension layer 2 (n-CSL2) and the n-type 4H-SiC carrier extension layer 1 (n-CSL1) below the p-type Si body region (p-body), as well as the probability of electrons tunneling through this heterojunction, thereby controlling the switching of the device.

4. The method for fabricating a self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor as described in claim 1, characterized in that: When the self-restoring Si / 4H-SiC heterojunction tunneling field-effect transistor is turned on in reverse, the n + Type 4H-SiC substrate (n + -SUB), n - Type 4H-SiC drift region (n - -DR), n-type 4H-SiC carrier extension layer 1 (n-CSL1), n-type Si carrier extension layer 2 (n-CSL2), n - Type Si channel layer (n - -CH) and n + Type Si source layer (n + Tail-state electrons in the -S) are extracted from the source (S) by a reverse electric field; while the n-type 4H-SiC carrier extension layer 1 (n-CSL1), n - Type 4H-SiC drift region (n - -DR), n + Type 4H-SiC substrate (n + Minority carriers—holes—are extracted from the drain (D) of the n-type Si carrier extension layer 2 (n-CSL2). - Type Si channel layer (n - -CH) and n + Type Si source layer (n + Minority carriers—holes—in the Si / 4H-SiC heterostructure are blocked by the Si / 4H-SiC heterostructure barrier; p-type Si body region (p-body), p + Type 4H-SiC shielding layer (p + The majority carriers—holes—in the p-body / n-CSL2 Si homojunction are respectively disposed of by the p-body / n-CSL2 Si homojunction and p + -SL / n - The -DR 4H-SiC homojunction barrier prevents electrons and holes from recombining, thus improving the reverse recovery characteristics of the device and reducing reverse recovery loss.

5. The method for fabricating a self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor as described in claim 1, characterized in that: The p + Type 4H-SiC shielding layer (p + -SL) is used to shield the field strength peak at the corner of the auxiliary gate oxide layer to improve the device withstand voltage and control the current distribution.

6. The method for fabricating a self-restoring Si / 4H-SiC heterojunction tunneling field-effect transistor as described in claim 1, characterized in that: In the self-restoring Si / 4H-SiC heterojunction tunneling field-effect transistor, the n + The thickness of the 4H-SiC substrate is 2.0 × 10⁻⁶. -4 cm, width 4.6×10 -4 cm, with a doping concentration of 1.0 × 10⁻⁶. 20 cm -3 The n - The thickness of the 4H-SiC drift region is 15.0 × 10⁻⁶. -4 cm, width 4.6×10 -4 cm, with a doping concentration of 6.0 × 10⁻⁶. 15 cm -3 The p + The thickness of the 4H-SiC shielding layer is 1.0 × 10⁻⁶. -4 cm, width 1.1×10 -4 cm, with a doping concentration of 8.0 × 10⁻⁶. 17 cm -3 The thickness of the n-type 4H-SiC carrier extension layer 1 (n-CSL1) is 0.7 × 10⁻⁶. -4 cm, width 3.6×10 -4 cm, with a doping concentration of 5.0 × 10⁻⁶. 15~ 17 cm -3 The thickness of the n-Si carrier extension layer 2 (n-CSL2) is 1.7 × 10⁻⁶. -4 cm, width 3.6×10 -4 cm, with a doping concentration of 1.0 × 10⁻⁶. 15~17 cm -3 The thickness of the p-Si bulk region is 1.0 × 10⁻⁶. -4 cm, width is (1.2~1.6)×10 -4 cm, with a doping concentration of 1×10 17 cm -3 The thickness of the parasitic JFET channel is 1.2 × 10⁻⁶. -4 cm, width is (0.4~1.2)×10 -4 cm, with a doping concentration of 5.0 × 10⁻⁶. 16 cm -3 The n - The thickness of the Si channel layer is 2.0 × 10⁻⁶. -5 cm, width 0.6×10 -4 cm, with a doping concentration of 1.0 × 10⁻⁶. 16 cm -3 The n + The thickness of the Si source layer is 2.0 × 10⁻⁶. -5 cm, width is (0.2~0.4)×10 -4 cm, with a doping concentration of 1.0 × 10⁻⁶. 20 cm -3 The n + The thickness of the polycrystalline Si gate is 5.0 × 10⁻⁶. -5 cm, width 2.0 × 10 -4 cm, with a doping concentration of 1.0 × 10⁻⁶. 20 cm -3 The n + The thickness of the polycrystalline Si auxiliary gate is 2.4~3.2×10⁻⁶. -4 cm, width 5.0 × 10 -5 cm, with a doping concentration of 1.0 × 10⁻⁶. 20 cm -3 The thickness of the gate oxide layer is 5.0 × 10⁻⁶. -6 cm.

7. A self-healing Si / 4H-SiC heterojunction tunneling field-effect transistor, characterized in that: It is manufactured using the method for preparing a self-recovering Si / 4H-SiC heterojunction tunneling field-effect transistor as described in any one of claims 1-6.

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