Algalnp light emitting diode epitaxial wafer and preparation method thereof

Abstract

This invention relates to the field of light-emitting diode (LED) technology, and discloses an AlGaInP LED epitaxial wafer and its fabrication method. The fabrication method of the AlGaInP LED epitaxial wafer includes the following steps: S1, providing a substrate; S2, sequentially depositing a buffer layer, an N-type confinement layer, an N-type waveguide layer, an active layer, a P-type waveguide layer, a P-type confinement layer, and a P-type window layer on the substrate; S3, depositing an ohmic contact layer on the P-type window layer; S4, dry etching the ohmic contact layer to retain the nanomaterial at the target location, forming multiple nanopillars, with grooves formed between the nanopillars; S5, fabricating a composite repair layer on the inner surface of the grooves; the composite repair layer includes a sequentially stacked in-situ passivation layer, an AlGaAs transition layer, and an AlAs layer. Implementing this invention can improve crystal quality, repair etching defects, enhance radiative recombination to improve internal quantum efficiency, and improve device reliability.

Description

Technical Field

[0001] This invention relates to the field of light-emitting diode technology, and in particular to an AlGaInP light-emitting diode epitaxial wafer and its fabrication method. Background Technology

[0002] Quaternary AlGaInP LEDs, with their superior optoelectronic properties of high luminous efficiency, wide color gamut, and high brightness, have become the core preferred device in the visible light band of optoelectronic devices, and are widely used in many fields such as display backlighting, smart lighting, optical communication, and high-density integrated optoelectronic devices. In the existing technology, the epitaxial structure of quaternary AlGaInP LEDs adopts a mature longitudinal directional growth design. The typical structure along the growth direction includes, in sequence, a substrate, a buffer layer, an N-type confinement layer, an N-type waveguide layer, an active quantum well structure, a P-type waveguide layer, a P-type confinement layer, a P-type current spreading layer, and an ohmic contact layer.

[0003] The existing fabrication processes and structural designs of quaternary AlGaInP LEDs are no longer adequate for the performance requirements of precision integrated applications, revealing numerous technical shortcomings in device fabrication and array integration. Firstly, during device fabrication, numerous dangling bonds and defects remain on the sidewalls after etching. Simply covering these with a SiO2 thin film cannot effectively passivate these dangling bonds and defect sites, turning the etched sidewalls into leakage channels for light emission. This significantly increases the probability of nonradiative recombination within the device, preventing photogenerated carriers from effectively participating in luminescent recombination and directly causing a decrease in the device's quantum efficiency. Secondly, crosstalk problems are particularly prominent in high-density integrated optoelectronic applications of quaternary AlGaInP LEDs. Lateral propagation and scattering of photons easily occur between adjacent devices in the integrated array, while carriers undergo random migration between devices. Both factors contribute to severe signal interference, significantly affecting the device's integration accuracy, operational stability, and optoelectronic performance. Furthermore, during the fabrication of quaternary AlGaInP precision devices, the high etching bombardment energy can damage the crystal structure of AlGaInP, causing significant lattice distortion and further inducing a large number of crystal defects.

[0004] Therefore, developing a quaternary AlGaInP LED that can effectively reduce etching lattice damage, fully passivate etching sidewall defects, and suppress crosstalk in the integrated array, thereby achieving a dual improvement in both the optoelectronic performance and the integration performance of the device, has become an urgent technical problem to be solved. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide an AlGaInP light-emitting diode epitaxial wafer and its preparation method, which can improve crystal quality, repair etching defects, improve radiative recombination to increase internal quantum efficiency, and improve device reliability.

[0006] To address the aforementioned technical problems, the first aspect of this invention provides a method for fabricating an AlGaInP light-emitting diode epitaxial wafer, comprising the following steps: S1. Provide a substrate; S2. Sequentially deposit a buffer layer, an N-type confinement layer, an N-type waveguide layer, an active layer, a P-type waveguide layer, a P-type confinement layer, and a P-type window layer on the substrate. S3. Deposit an ohmic contact layer on the P-type window layer; S4. Dry etching is performed on the ohmic contact layer to retain the nanomaterial at the target location, forming multiple nanopillars, and grooves are formed between the multiple nanopillars. S5. Prepare a composite repair layer on the inner surface of the groove; The composite repair layer comprises an in-situ passivation layer, an AlGaAs transition layer, and an AlAs layer stacked sequentially.

[0007] As an improvement to the above solution, step S5 involves preparing a composite repair layer on the inner surface of the groove, specifically including: S51. In a mixed atmosphere of AsH3 and H2, an in-situ passivation layer is formed on the inner surface of the groove by in-situ reaction. S52. Introduce Al source, Ga source and As source, and grow AlGaAs transition layer on the in-situ passivation layer; S53. Introduce Al source and As source to grow AlAs layer on AlGaAs transition layer; S54. Annealing treatment is carried out in an AsH3 atmosphere.

[0008] As an improvement to the above scheme, in step S51, when the in-situ passivation layer is formed in situ on the inner surface of the groove, the temperature of the reaction chamber is controlled at 550℃-650℃, the pressure is 50 torr-200 torr, and a mixed gas of AsH3 and H2 is introduced for 10s-120s.

[0009] As an improvement to the above scheme, in the mixed atmosphere of AsH3 and H2, the volumetric flow rate ratio of AsH3 and H2 is 1:100-1:200; The thickness of the in-situ passivation layer is 1nm-20nm.

[0010] As an improvement to the above scheme, the proportion of Al component in the AlGaAs transition layer increases along the growth direction.

[0011] As an improvement to the above scheme, along the growth direction, the proportion of Al component in the AlGaAs transition layer is increased from 0.2 to 0.8.

[0012] As an improvement to the above scheme, the growth thickness of the AlGaAs transition layer is 5nm-30nm; The AlAs layer has a growth thickness of 1 nm to 20 nm.

[0013] As an improvement to the above scheme, when growing the AlAs layer on the AlGaAs transition layer, the temperature of the reaction chamber is controlled at 580℃-600℃ and the pressure is controlled at 50 torr-200 torr.

[0014] As an improvement to the above solution, the annealing temperature is 600℃-620℃ and the time is 30s-200s.

[0015] A second aspect of the present invention also provides an AlGaInP light-emitting diode epitaxial wafer, which is prepared according to the preparation method described above.

[0016] Implementing this invention has the following beneficial effects: In this invention, by forming a composite repair layer in situ on the inner surface of the groove, the composite repair layer includes an in-situ passivation layer, an AlGaAs transition layer, and an AlAs layer stacked sequentially, which can improve crystal quality, repair defects caused by etching process in situ, significantly reduce non-radiative recombination centers, reduce surface recombination rate, reduce interface leakage current, thereby improving the luminous efficiency of the device, reducing leakage current, stabilizing the emission wavelength, and significantly improving lifetime and high-temperature reliability. Attached Figure Description

[0017] Figure 1 : A schematic diagram of the structure of an AlGaInP light-emitting diode epitaxial wafer in this invention.

[0018] Figure reference numerals: 1-substrate; 2-buffer layer; 3-N-type confinement layer; 4-N-type waveguide layer; 5-active layer; 6-P-type waveguide layer; 7-P-type confinement layer; 8-P-type window layer; 9-ohmic contact layer; 10-nanopillar; 11-groove; 12-composite repair layer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments.

[0020] In the description of this application, it is necessary to understand that the orientation or positional relationship indicated by terms such as "upper", "lower", "top", "bottom", "inner", and "outer" are based on the orientation or positional relationship shown in the accompanying drawings. They are intended only to facilitate the description of the present invention and to simplify the description, and are not intended to indicate or imply that the components referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention.

[0021] The "range" disclosed in this application is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of the particular range. The range defined in this way can include or exclude endpoints and can be arbitrarily combined; that is, any lower limit can be combined with any upper limit to form a range.

[0022] To address the above problems, the first aspect of this invention provides a method for fabricating an AlGaInP light-emitting diode epitaxial wafer, comprising the following steps: S1, Provide a substrate 1; S2. Buffer layer 2, N-type confinement layer 3, N-type waveguide layer 4, active layer 5, P-type waveguide layer 6, P-type confinement layer 7 and P-type window layer 8 are sequentially deposited on the substrate 1. S3. Deposit an ohmic contact layer 9 on the P-type window layer 8; S4. Dry etching is performed on the ohmic contact layer 9 to retain the nanomaterial at the target location, forming a plurality of nanopillars 10, and grooves 11 are formed between the plurality of nanopillars 10. S5. A composite repair layer 12 is formed in situ on the inner surface of the groove 11; The composite repair layer 12 comprises an in-situ passivation layer, an AlGaAs transition layer, and an AlAs layer stacked sequentially.

[0023] In this invention, by forming a composite repair layer 12 in situ on the inner surface of the groove 11, the composite repair layer 12 includes an in-situ passivation layer, an AlGaAs transition layer and an AlAs layer stacked sequentially, which can improve crystal quality, repair defects caused by etching process in situ, significantly reduce non-radiative recombination centers, reduce surface recombination rate, reduce interface leakage current, thereby improving the luminous efficiency of the device, reducing leakage current, stabilizing the emission wavelength, and significantly improving lifetime and high-temperature reliability.

[0024] The in-situ passivation layer can precisely fill the As vacancies, P vacancies, and metal dangling bonds generated on the sidewalls and bottom of the groove 11 after dry etching, while effectively removing surface carbon, oxygen, and polymer residues, thereby reducing the surface defect density by more than an order of magnitude, significantly reducing non-radiative recombination centers, lowering the surface recombination rate, and improving the device's luminous efficiency. The AlGaAs transition layer can avoid the strong lattice mismatch stress, dislocations, and cracks introduced by directly growing Al component layers. The AlAs layer can form strong Type-I quantum confinement, significantly suppressing carrier leakage. Moreover, AlAs has a band gap much larger than AlGaInP, which can form a high barrier in both the conduction band and valence band, achieving strong quantum confinement of both electrons and holes. This effectively confines carriers within the AlGaInP core region, greatly reducing carrier leakage to the sidewalls, interfaces, and surface defect regions. Furthermore, the overlap of carrier wave functions is significantly improved, enhancing the radiative recombination probability, and thus significantly improving the device's internal quantum efficiency.

[0025] Specifically, in step S1, the substrate 1 can be a GaAs substrate. GaAs substrates have mature fabrication processes, high stability, and high cost-effectiveness.

[0026] Specifically, in step S2, the deposition thickness of the buffer layer 2 is 50nm-500nm, and the buffer layer 2 can be a Si-doped GaAs buffer layer, wherein the Si doping concentration is 1×10⁻⁶. 17 atoms / cm 3 -1×10 19 atoms / cm 3 .

[0027] Furthermore, the deposition process of the buffer layer 2 is as follows: the temperature of the reaction chamber is controlled at 600℃-700℃, the pressure is 50 torr-100 torr, and Ga source, As source and Si source are introduced to grow a Si-doped GaAs buffer layer.

[0028] Preferably, the deposition thickness of the N-type confinement layer 3 is 250 nm-450 nm, and the N-type confinement layer 3 can be a Si-doped AlInP confinement layer, wherein the Si doping concentration is 1 × 10⁻⁶. 17 atoms / cm 3 -1×10 19 atoms / cm 3 .

[0029] Furthermore, the deposition process of the N-type confinement layer 3 is as follows: the temperature of the reaction chamber is controlled at 700℃-750℃, the pressure is 40mbar-60mbar, and Al source, In source, P source and Si source are introduced to grow a Si-doped AlInP confinement layer.

[0030] Preferably, the deposition thickness of the N-type waveguide layer 4 is 100nm-300nm, and the N-type waveguide layer 4 can be an AlGaAs waveguide layer.

[0031] Furthermore, the deposition process of the N-type waveguide layer 4 is as follows: the temperature of the reaction chamber is controlled at 600℃-700℃, the pressure is 40mbar-60mbar, and Al source, Ga source and As source are introduced to grow the N-type AlGaAs waveguide layer.

[0032] Preferably, the active layer 5 is a superlattice multi-quantum structure layer formed by periodically alternating growth of AlGaInP layers and GaInP layers, wherein the AlGaInP layer is a quantum barrier layer with a deposition thickness of 60Å-200Å, the GaInP layer is a quantum well layer with a deposition thickness of 30Å-80Å, and the number of alternating growth periods is 8-18.

[0033] Furthermore, the deposition process of the active layer 5 is as follows: the temperature of the reaction chamber is controlled at 620℃-720℃ and the pressure is 40mbar-60mbar. Ga source, In source and P source are introduced to grow GaInP quantum well layer; then Al source, Ga source, In source and P source are introduced to grow AlGaInP quantum barrier layer to form one cycle. Then the above steps are repeated to grow until the preset number of cycles is reached, that is, the growth of the active layer 5 is completed.

[0034] Preferably, the deposition thickness of the P-type waveguide layer 6 is 100nm-300nm, and the P-type waveguide layer 6 can be an AlGaAs waveguide layer.

[0035] Furthermore, the deposition process of the P-type waveguide layer 6 is as follows: the temperature of the reaction chamber is controlled at 600℃-700℃, the pressure is 40mbar-60mbar, and Al source, Ga source and As source are introduced to grow the P-type AlGaAs waveguide layer.

[0036] Preferably, the deposition thickness of the P-type confinement layer 7 is 100 nm-400 nm; the P-type confinement layer 7 is a P-type doped AlInP confinement layer, wherein the P-type doping concentration is 1 × 10⁻⁶. 17 atoms / cm 3 -1×10 19 atoms / cm 3 It is understood that the doping elements of the p-type doping include, but are not limited to, Mg and Zn.

[0037] Furthermore, the deposition process of the P-type confinement layer 7 is as follows: the temperature of the reaction chamber is controlled at 700℃-800℃, the pressure is 40mbar-60mbar, Al source, In source, P source and P-type dopant are introduced, and a P-type doped AlInP confinement layer is grown.

[0038] Preferably, the deposition thickness of the P-type window layer 8 is 3 μm-50 μm; the P-type window layer 8 can be a Mg-doped GaP window layer, wherein the Mg doping concentration is 1×10⁻⁶. 18 atoms / cm 3 -1×10 19 atoms / cm 3 .

[0039] Furthermore, the deposition process of the P-type window layer 8 is as follows: the temperature of the reaction chamber is controlled at 780℃-850℃, the pressure is 40mbar-60mbar, and Ga source, P source and Mg source are introduced to grow Mg-doped GaP window layer.

[0040] Specifically, in step S3, the deposition thickness of the ohmic contact layer 9 is 30nm-150nm; the ohmic contact layer 9 can be a carbon (C) doped GaP layer, with a C doping concentration of 7×10⁻⁶. 19 atoms / cm 3 -2×10 20 atoms / cm 3 .

[0041] Furthermore, the deposition process of the ohmic contact layer 9 is as follows: the temperature of the reaction chamber is controlled at 580℃-630℃, the pressure is 40mbar-60mbar, Ga source, P source and C source are introduced, and a C-doped GaP ohmic contact layer is grown.

[0042] Understandably, the buffer layer 2, N-type confinement layer 3, N-type waveguide layer 4, active layer 5, P-type waveguide layer 6, P-type confinement layer 7, P-type window layer 8, and ohmic contact layer 9 are all grown using existing processes and raw materials, and will not be further described in this invention.

[0043] It should be noted that in this invention, TMGa (trimethylgallium) is used as the Ga source, AsH3 (arsine) as the As source, TMAl (trimethylaluminum) as the Al source, PH3 (phosphorus trihydrogenate) as the P source, TMIn (trimethylindium) as the In source, Si2H6 (disilane) as the Si source, CP2Mg as the Mg source, and C3H8 (propane) as the C source.

[0044] Specifically, in step S4, the ohmic contact layer 9 is etched to form nanopillars 10, including: (41) A SiO2 layer is deposited on the surface of the ohmic contact layer 9, and a photoresist is coated on the surface of the SiO2 layer. The photoresist is then exposed and developed, etched, and removed to form a patterned mask. In this step, the deposited SiO2 layer can be used as a hard mask. The deposition thickness of the SiO2 layer is 100nm-500nm. The deposition process of the SiO2 layer includes, but is not limited to, plasma-enhanced chemical vapor deposition (PECVD). The growth temperature of the SiO2 layer is 250℃-300℃, and the growth pressure is 800mtorr-1200mtorr.

[0045] In some specific and preferred embodiments, step (41) specifically includes: spin-coating positive photoresist on the surface of the SiO2 layer, heating and curing it, exposing it to the mask, immersing it in developer, rinsing it with deionized water, and drying it with nitrogen to obtain a photoresist pattern; then using dry etching to etch the SiO2 layer, transferring the photoresist pattern onto the SiO2 layer, and using O2 plasma ashing to remove residual photoresist to obtain a nanopillar patterned mask.

[0046] Optionally, the coating thickness of the positive photoresist is 1μm-3μm, the spin coating speed is 3000rpm-6000rpm, the curing temperature is 90℃-110℃, and the curing time is 60s-90s. An exemplary positive photoresist may be AZ5214E; the exposure energy may be 50mJ / cm². 2 -150mJ / cm 2 The soaking time of the developer can be 30s-90s; the developer can be, for example, AZ 400K (1:4).

[0047] Optionally, when dry etching is used to etch the SiO2 layer, the etching gases are CF3 and Ar, the volumetric flow rate ratio of CF3 to Ar is 1:2 to 1:4, the etching power is 200W to 500W, and the pressure is 5mTorr to 20mTorr. The dry etching includes, but is not limited to, RIE etching and ICP etching.

[0048] (42) Perform nanoimprint patterning on the patterned mask to obtain an etched mask; In this step, a SiO2 nanopillar patterned mask is used as a rigid template for nanoimprint patterning to obtain an etching mask. The pressure during the nanoimprint patterning process can be 5MPa-10MPa.

[0049] (43) A mixture of CH4 and H2 is introduced to dry etch the sample obtained in step S3 to retain the nanomaterial at the target location and remove the etching mask to form multiple nanopillars 10, and grooves 11 are formed between the multiple nanopillars 10. In this step, the sample obtained in step (42) is etched using dry etching to obtain nanopillars 10, wherein dry etching can be one or more of N-electrode etching, ICP etching, and RIE etching.

[0050] Further, the sample obtained in step (42) can be etched using RIE etching to obtain nanopillars 10. In some specific embodiments, the sample obtained in step (42) is placed in a RIE chamber, a mixture of CH4 and H2 is introduced, and the sample is etched downwards until the N-type confinement layer 3 is exposed, retaining the N-type confinement layer 3 and all the nanomaterials disposed above it, forming multiple nanopillars 10, and grooves 11 penetrating into the N-type confinement layer 3 are formed between the multiple nanopillars 10. In other specific embodiments, the sample obtained in step (42) is placed in a RIE chamber, a mixture of CH4 and H2 is introduced, and the sample is etched downwards until the buffer layer 2 is exposed, retaining the buffer layer 2 and all the nanomaterials disposed above it, forming multiple nanopillars 10, and grooves 11 penetrating into the buffer layer 2 are formed between the multiple nanopillars 10.

[0051] In some specific and preferred embodiments, the total flow rate of the mixed gas is 30 sccm-40 sccm, wherein the volumetric flow rate ratio of CH4 to H2 is (1.5-2.5):1, the etching power is 190W-210W, and the pressure is 2Pa-3Pa.

[0052] In some specific and preferred embodiments, the etching depth of the nanopillar 10 is 750nm-900nm, and can be 750nm, 775nm, 800nm, 825nm, 850nm, 875nm, or 900nm, but is not limited thereto.

[0053] Specifically, in step S5, a composite repair layer 10 is prepared on the inner surface of the groove 11, which specifically includes: S51. In a mixed atmosphere of AsH3 and H2, an in-situ passivation layer is formed on the inner surface of the groove 11 by in-situ reaction. In this step, the mixed gas of AsH3 and H2 is subjected to high-temperature treatment, which decomposes AsH3 to generate active As atoms, filling As vacancies, P vacancies, and metal dangling bonds on the inner surface of the groove 11. This in-situ reaction forms an in-situ passivation layer on the inner surface of the groove 11, saturating the defect states. Simultaneously, the active H atoms generated by the decomposition of H2 remove surface impurities, forming an As-rich clean surface. Compared with traditional wet cleaning or passivation, the in-situ reaction to form an in-situ passivation layer can reduce the surface defect density by more than an order of magnitude, significantly reduce non-radiative recombination centers, lower the surface recombination rate, and improve the device's luminous efficiency.

[0054] Furthermore, by controlling the temperature of the reaction chamber to 550℃-650℃, the pressure to 50 torr-200 torr, and the time to 10s-120s, a clean passivated surface rich in As, free of oxidation, and with low defects can be obtained. For example, the temperature in the reaction chamber can be controlled at 550℃, 560℃, 570℃, 580℃, 600℃, 620℃, 640℃, or 650℃, but is not limited to these; the pressure in the reaction chamber can be controlled at 50 torr, 100 torr, 150 torr, or 200 torr, but is not limited to these; and the time can be controlled at 10s, 20s, 30s, 40s, 50s, 60s, 70s, 80s, 90s, 100s, 110s, or 120s, but is not limited to these.

[0055] Furthermore, in the mixed atmosphere of AsH3 and H2, the volumetric flow rate ratio of AsH3 and H2 is 1:100-1:200, which can be 1:100, 1:120, 1:140, 1:160, 1:180, or 1:200, but is not limited thereto.

[0056] In some specific and preferred embodiments, the thickness of the in-situ passivation layer is 1nm-20nm, and can be 1nm, 2nm, 5nm, 10nm, 15nm, or 20nm, but is not limited thereto.

[0057] S52. Introduce Al source, Ga source and As source, and grow AlGaAs transition layer on the in-situ passivation layer; Preferably, the proportion of Al composition in the AlGaAs transition layer increases along the growth direction. The AlGaAs transition layer allows for a continuous and gradual change in Al composition from low to high. On the one hand, it achieves a smooth transition of the lattice constant from AlGaInP to AlAs, avoiding the strong lattice mismatch stress, dislocations, and cracks introduced by directly growing a high Al composition layer. On the other hand, it achieves a continuous and gradual change in the band gap and band structure, eliminating band spikes and barrier inflection points caused by abrupt heterojunctions, avoiding carrier accumulation, scattering, and heat generation at the interface, and significantly reducing interface leakage current.

[0058] Furthermore, along the growth direction, the proportion of Al composition in the AlGaAs transition layer increases from 0.2 to 0.8, which can further alleviate the stress and dislocations caused by lattice mismatch, eliminate band spikes and carrier accumulation caused by abrupt interface changes, and reduce interface scattering and heat generation.

[0059] In this step, the flow rates of the Al and Ga sources can be continuously adjusted to gradually increase the Al composition from low to high. For example, the AlGaAs transition layer can be made to transition from Al... 0.2 Ga 0.8 As gradually transitions to Al 0.8 Ga 0.2 As, but not limited to.

[0060] Furthermore, the growth thickness of the AlGaAs transition layer is 5nm-30nm, and can be, for example, 5nm, 10nm, 15nm, 20nm, 25nm, or 30nm, but is not limited thereto.

[0061] In some specific implementations, when growing the AlGaAs transition layer on the in-situ passivation layer, the temperature of the reaction chamber is controlled at 550℃-650℃ and the pressure at 50 torr-200 torr.

[0062] S53. Introduce Al source and As source to grow AlAs layer on AlGaAs transition layer; In this step, the temperature of the reaction chamber is controlled at 580℃-600℃ and the pressure at 50 torr-200 torr, which allows the Al source and As source to react and generate AlAs. The AlAs layer formed is aligned with the AlGaInP sidewalls in a Type-I bandgap configuration. Moreover, AlAs material has a wider bandgap, forming a high barrier in both the conduction and valence bands, which strongly confines both electrons and holes within the AlGaInP core region, significantly suppressing carrier overflow, sidewall leakage, and nonradiative recombination, thereby improving internal quantum efficiency.

[0063] Furthermore, the growth thickness of the AlAs layer is 1nm-20nm, and can be 1nm, 5nm, 10nm, 15nm, or 20nm, but is not limited thereto.

[0064] S54. Annealing treatment is carried out in an AsH3 atmosphere; In this step, annealing in an AsH3 atmosphere promotes interfacial atomic migration and rearrangement, further eliminating defects, passivating interfacial states, reducing interfacial roughness, and releasing lattice stress accumulated during growth. Simultaneously, the As atmosphere prevents AlAs decomposition and As desorption, ensuring the integrity of the barrier structure, thereby reducing device leakage current, achieving more stable emission wavelength, and significantly improving lifetime and high-temperature reliability.

[0065] Furthermore, the annealing treatment is performed at a temperature of 600℃-620℃ for a time of 30s-200s, which can further eliminate defects, smooth the interface, and release lattice stress. For example, the annealing temperature can be 600℃, 605℃, 610℃, 615℃, or 620℃, but is not limited to these; the annealing time can be 30s, 40s, 70s, 100s, 150s, or 200s, but is not limited to these.

[0066] Accordingly, the present invention also provides an AlGaInP light-emitting diode epitaxial wafer, prepared according to the aforementioned preparation method, the structure of which is as follows. Figure 1 As shown.

[0067] The present invention will be further described below with reference to specific embodiments: Example 1 This embodiment provides an AlGaInP light-emitting diode epitaxial wafer, the preparation method of which includes: (1) Provide a GaAs substrate; (2) A Si-doped GaAs buffer layer, a Si-doped AlInP confinement layer, an N-type AlGaAs waveguide layer, a GaInP / AlGaInP active layer, a P-type AlGaAs waveguide layer, a Mg-doped AlInP confinement layer, and a Mg-doped GaP window layer are sequentially deposited on a GaAs substrate. (3) Deposit a C-doped GaP ohmic contact layer on the P-type window layer; (4) A SiO2 layer is deposited on the surface of the ohmic contact layer, and photoresist is coated on the surface of the SiO2 layer. The layer is exposed and developed, and then etched by dry etching and the photoresist is removed to form a patterned mask. The etching gas is CF3 and Ar, the volume flow rate ratio of CF3 and Ar is 1:3, the etching power is 350W, and the pressure is 15mTorr. The patterned mask is patterned using nanoimprinting to obtain an etched mask; A mixture of CH4 and H2 gas was introduced, and the resulting sample was etched by RIE until the Si-doped AlInP confinement layer was exposed. The etching mask was then removed to form multiple nanopillars, with grooves formed between the nanopillars. The etching depth of the nanopillars was 830 nm. The total flow rate of the mixed gas was 35 sccm, with a CH4 to H2 volume flow rate ratio of 2:1. The etching power was 200 W, and the pressure was 2.5 Pa.

[0068] (5) In a reaction chamber at a temperature of 580℃ and a pressure of 100 torr, a mixture of AsH3 and H2 gas (the volume flow rate ratio of AsH3 and H2 is 1:120) is introduced for 45s to form an in-situ passivation layer on the inner surface of the groove. Al source, Ga source and As source are introduced to grow an AlGaAs transition layer on the in-situ passivation layer. The temperature of the reaction chamber is adjusted to 590℃, and Al source and As source are introduced to grow an AlAs layer on the AlGaAs transition layer.

[0069] The AlGaAs transition layer has a growth thickness of 15 nm, and the AlAs layer has a growth thickness of 10 nm.

[0070] Example 2 This embodiment provides an AlGaInP light-emitting diode epitaxial wafer, the preparation method of which is basically the same as that in Embodiment 1, except that: In step (5), a mixed gas of AsH3 and H2 (the volume flow rate ratio of AsH3 and H2 is 1:150) is introduced for 30 seconds, and an in-situ passivation layer is formed by in-situ reaction. The AlGaAs transition layer has a growth thickness of 5 nm, and the AlAs layer has a growth thickness of 3 nm.

[0071] Example 3 This embodiment provides an AlGaInP light-emitting diode epitaxial wafer, the preparation method of which is basically the same as that in Embodiment 1, except that: In step (5), a mixed gas of AsH3 and H2 (the volume flow rate ratio of AsH3 and H2 is 1:180) is introduced for 60 seconds, and an in-situ passivation layer is formed by in-situ reaction. The AlGaAs transition layer has a growth thickness of 30 nm, and the AlAs layer has a growth thickness of 20 nm.

[0072] Example 4 This embodiment provides an AlGaInP light-emitting diode epitaxial wafer, the preparation method of which is basically the same as that in Embodiment 1, except that: In step (5), along the growth direction, the proportion of Al component in the AlGaAs transition layer increases from 0.2 to 0.8.

[0073] Example 5 This embodiment provides an AlGaInP light-emitting diode epitaxial wafer, the preparation method of which is basically the same as that in Embodiment 1, except that: Step (5) also includes: annealing at 610°C in an AsH3 atmosphere for 120 seconds.

[0074] Comparative Example 1 This comparative example provides an AlGaInP light-emitting diode epitaxial wafer, the preparation method of which is basically the same as that of Example 1, except that step (5) is not included, that is, no AlAs film is formed in situ on the inner surface of the groove.

[0075] The interfacial stress on the inner surface of the groove in the AlGaInP LED epitaxial wafer obtained in the examples and comparative examples was tested. The AlGaInP LED epitaxial wafers obtained in the examples and comparative examples were fabricated into 10mil×24mil chips using the same chip process conditions. 300 LED chips were selected from each chip and tested at a current of 120mA to measure the luminous efficiency and crosstalk rate.

[0076] The specific test results are shown in Table 1.

[0077] Table 1 Performance test results of the examples and comparative examples

[0078] As can be seen from the above results, in this invention, by forming a composite repair layer in situ on the inner surface of the groove, the composite repair layer includes an in-situ passivation layer, an AlGaAs transition layer and an AlAs layer stacked sequentially, which can improve crystal quality, enhance radiative recombination and improve internal quantum efficiency, thereby improving luminescence efficiency and crosstalk rate.

[0079] The above description is merely a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.

Claims

1. A method for fabricating an AlGaInP light-emitting diode epitaxial wafer, characterized in that, Includes the following steps: S1. Provide a substrate; S2. Sequentially deposit a buffer layer, an N-type confinement layer, an N-type waveguide layer, an active layer, a P-type waveguide layer, a P-type confinement layer, and a P-type window layer on the substrate. S3. Deposit an ohmic contact layer on the P-type window layer; S4. Dry etching is performed on the ohmic contact layer to retain the nanomaterial at the target location, forming multiple nanopillars, and grooves are formed between the multiple nanopillars. S5. Prepare a composite repair layer on the inner surface of the groove; The composite repair layer comprises an in-situ passivation layer, an AlGaAs transition layer, and an AlAs layer stacked sequentially.

2. The method for fabricating an AlGaInP light-emitting diode epitaxial wafer as described in claim 1, characterized in that, Step S5 involves preparing a composite repair layer on the inner surface of the groove, specifically including: S51. In a mixed atmosphere of AsH3 and H2, an in-situ passivation layer is formed on the inner surface of the groove by in-situ reaction. S52. Introduce Al source, Ga source and As source, and grow AlGaAs transition layer on the in-situ passivation layer; S53. Introduce Al source and As source to grow AlAs layer on AlGaAs transition layer; S54. Annealing treatment is carried out in an AsH3 atmosphere.

3. The method for fabricating an AlGaInP light-emitting diode epitaxial wafer as described in claim 2, characterized in that, In step S51, when an in-situ passivation layer is formed on the inner surface of the groove through in-situ reaction, the temperature of the reaction chamber is controlled at 550℃-650℃, the pressure is controlled at 50 torr-200 torr, and a mixed gas of AsH3 and H2 is introduced for 10s-120s.

4. The method for fabricating an AlGaInP light-emitting diode epitaxial wafer as described in claim 3, characterized in that, In the mixed atmosphere of AsH3 and H2, the volumetric flow rate ratio of AsH3 and H2 is 1:100-1:200; The thickness of the in-situ passivation layer is 1nm-20nm.

5. The method for fabricating an AlGaInP light-emitting diode epitaxial wafer as described in claim 1 or 2, characterized in that, Along the growth direction, the proportion of Al component in the AlGaAs transition layer shows an increasing trend.

6. The method for fabricating an AlGaInP light-emitting diode epitaxial wafer as described in claim 5, characterized in that, Along the growth direction, the proportion of Al component in the AlGaAs transition layer increases from 0.2 to 0.

8.

7. The method for fabricating an AlGaInP light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The growth thickness of the AlGaAs transition layer is 5nm-30nm; The AlAs layer has a growth thickness of 1 nm to 20 nm.

8. The method for fabricating an AlGaInP light-emitting diode epitaxial wafer as described in claim 1 or 2, characterized in that, When growing the AlAs layer on the AlGaAs transition layer, the temperature of the reaction chamber is controlled at 580℃-600℃ and the pressure is controlled at 50 torr-200 torr.

9. The method for fabricating an AlGaInP light-emitting diode epitaxial wafer as described in claim 2, characterized in that, The annealing process is performed at a temperature of 600℃-620℃ for a time of 30s-200s.

10. An AlGaInP light-emitting diode epitaxial wafer, characterized in that, It is prepared according to any one of claims 1-9.

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