A method for optimizing heat dissipation of a UV LED module

Abstract

The application relates to a heat dissipation optimization method of an ultraviolet light-emitting diode module in the field of information technology, and the method comprises the following steps: acquiring heat distribution data of the ultraviolet light-emitting diode module and determining a quantitative index of uneven temperature distribution; according to the quantitative index, a target area of heat path optimization is determined, and a heat resistance reduction scheme is obtained; through the heat resistance reduction scheme, the substrate structure design is adjusted, and the heat conduction capacity is enhanced; according to the uniform heat dissipation distribution model, the heat path parameters are optimized, and a final heat path configuration is obtained; through the final heat path configuration, the heat resistance value in the working state is simulated, and a feasibility evaluation result of power improvement is determined; according to the evaluation result, a heat dissipation system architecture is integrated, and a complete module heat dissipation system design is obtained; for the heat dissipation system design, reliability test simulation is carried out, and long-term performance prediction is determined; through the long-term performance prediction, the heat path optimization effect is verified, and the solution degree of the heat dissipation bottleneck is confirmed.

Description

Technical Field

[0001] This invention relates to the field of information technology, and more particularly to ultraviolet light-emitting diode (UV) modules, specifically to a heat dissipation optimization method for UV light-emitting diode modules. Background Technology

[0002] As a highly integrated packaging form, UV LED COB modules play an increasingly important role in industrial applications such as UV curing, surface sterilization, and precision printing. Their ability to output powerful UV energy within a limited volume directly determines production efficiency and processing results. However, with the increasing demands for power density, the heat dissipation capacity of this packaging method has become a core bottleneck restricting its further development. Currently, most UV LED COB modules still use the traditional planar substrate heat dissipation path. Heat must pass through the die-bonding layer and substrate material from the bottom junction region of the chip to the heat sink on the back, relying on the sequential conduction of multiple layers. Due to interfacial thermal resistance between layers and the relatively weak lateral thermal conductivity of the substrate itself, when multiple chips are arranged closely in an array, the heat generated by the chip in the central region of the module is difficult to dissipate rapidly to the surrounding areas. It can only be conducted vertically downwards, causing the temperature in the center to continuously accumulate and rise, while the temperature in the edge areas remains relatively low, resulting in a significant temperature gradient within the module. This uneven temperature phenomenon directly leads to two interconnected and serious consequences. On the one hand, because the central chip is always at a higher junction temperature, its internal materials age significantly faster than those of the edge chips. This causes a significant decrease in the overall module's light output power within a short period, especially under high-power continuous operation. Uneven light decay leads to an imbalance in ultraviolet energy distribution, affecting the uniformity of downstream processes. On the other hand, because heat cannot be quickly and systematically dissipated from each heat source, the overall thermal resistance of the module remains high. Even with highly efficient external heat sinks, it is difficult to fundamentally change the high-temperature environment actually experienced by the chips, limiting the module's upgrade towards higher power and higher reliability. How to ensure that the heat generated by each UVLED chip can be quickly and systematically collected and dissipated to the external heat dissipation area with the shortest path and lowest thermal resistance under high-density chip integration, thereby completely eliminating localized overheating and severe temperature unevenness within the module, has become a key problem that current UVLEDCOB packaging technology urgently needs to overcome. Summary of the Invention

[0003] This invention provides a heat dissipation optimization method for ultraviolet light-emitting diode modules, mainly including:

[0004] The thermal distribution data of the ultraviolet light-emitting diode module is acquired to determine the quantitative index of temperature non-uniformity. Based on the quantitative index, the target area for thermal path optimization is determined to obtain a thermal resistance reduction scheme. The substrate structure design is adjusted using the thermal resistance reduction scheme to enhance thermal conductivity. Thermal simulation is performed on the substrate structure design to determine the heat dissipation path efficiency and construct a uniform heat dissipation distribution model. Based on the uniform heat dissipation distribution model, the thermal path parameters are optimized to obtain the final thermal path configuration. The thermal resistance value under operating conditions is simulated using the final thermal path configuration to determine the feasibility assessment result of power improvement. Based on the assessment result, the heat dissipation system architecture is integrated to obtain a complete module heat dissipation system design. Reliability test simulations are performed on the heat dissipation system design to determine long-term performance predictions. The long-term performance predictions are used to verify the thermal path optimization effect and confirm the degree to which the heat dissipation bottleneck is resolved. Furthermore, the step of acquiring the thermal distribution data of the ultraviolet light-emitting diode module and determining the quantitative index of temperature non-uniformity includes: acquiring temperature field distribution data of the module under working conditions using an infrared thermal imager; importing the temperature field distribution data into finite element simulation software, setting the heat sink material distribution and boundary conditions, and calculating the temperature of the central chip and the edge chip; performing a subtraction operation between the central chip temperature and the edge chip temperature to obtain the temperature difference; if the temperature difference is greater than a preset threshold, it is determined to be a temperature non-uniformity distribution, and the quantitative index of the temperature non-uniformity distribution is obtained; based on the quantitative index, the thermal distribution characteristics of the module are recorded for subsequent thermal path optimization analysis; and based on the thermal distribution characteristics and the temperature difference data, an initial thermal distribution model is constructed to determine the specific areas of temperature non-uniformity distribution. Furthermore, determining the target region for thermal path optimization based on the quantified indicators to obtain a thermal resistance reduction scheme includes: extracting the target region for the thermal path from the chip temperature distribution using the quantified indicators of temperature non-uniformity; importing the target region data into finite element analysis software, setting boundary conditions, and simulating the heat flow path; adjusting the heat sink material distribution and radiation coating application for the heat flow path to calculate potential thermal resistance reduction schemes; extracting the temperature difference calculation results from the potential thermal resistance reduction schemes, and if they exceed a preset threshold, performing a non-uniformity judgment to obtain module operating status data; constructing a multi-layer thermal conductivity structure design based on the module operating status data to simulate the thermal resistance reduction path; and determining the target region expansion scheme for thermal path optimization based on the thermal resistance reduction path.Furthermore, the step of adjusting the substrate structure design and enhancing thermal conductivity through the thermal resistance reduction scheme includes: acquiring the temperature data of the central chip and determining whether the temperature data exceeds a preset threshold; if the temperature data exceeds the preset threshold, adjusting the substrate material parameters through the thermal resistance reduction scheme to obtain the material thermal conductivity and thickness combination; enhancing the lateral thermal conductivity based on the adjusted substrate material parameters and performing thermal flow simulation verification; obtaining a heat distribution map using the finite element analysis method through the thermal flow simulation verification; analyzing the improvement effect of the lateral thermal conductivity based on the heat distribution map and determining the optimized substrate structure design; and extracting key parameters from the optimized substrate structure design for subsequent thermal simulation verification of multi-chip arrays. Furthermore, the step of performing thermal simulation verification on the substrate structure design to determine the heat dissipation path efficiency and construct a uniform heat dissipation distribution model includes: obtaining the multi-chip array arrangement layout through preset substrate material parameters to determine the initial heat source distribution data; verifying the heat conduction path using the finite element method based on the initial heat source distribution data, and calculating the thermal resistance value of each chip to dissipate heat to the outside; obtaining the path efficiency index using the reciprocal of the thermal resistance value; if the path efficiency index is lower than a preset threshold, adjusting the cooling channel spacing in the substrate structure to obtain optimized arrangement parameters; constructing a heat distribution grid model based on the optimized arrangement parameters to determine the balanced heat transfer path between chips; and performing iterative simulation calibration on the heat distribution grid model to obtain the uniform heat dissipation distribution model. Furthermore, the step of optimizing the thermal path parameters based on the uniform heat dissipation distribution model to obtain the final thermal path configuration includes: obtaining initial thermal path parameters from the uniform heat dissipation distribution model and constructing a simulation environment through the heat conduction equation; optimizing the initial thermal path parameters using a genetic algorithm, outputting optimized parameters, and determining the material aging rate; if the material aging rate is higher than a preset threshold, extracting the path length and interface thermal resistance from the initial thermal path parameters and performing iterative adjustments; obtaining thermal resistance distribution equilibrium data through the iterative adjustments and calculating the equilibrium heat flow distribution; determining the aging prediction simulation results based on the equilibrium heat flow distribution; and further optimizing the path length and interface thermal resistance using a genetic algorithm based on the aging prediction simulation results, outputting the adjusted thermal path parameters, and integrating them to form the final thermal path configuration.Furthermore, the step of simulating the thermal resistance value under operating conditions through the final thermal path configuration to determine the feasibility assessment result of power improvement includes: obtaining the final thermal path configuration, extracting parameters for high-power application scenarios, and determining the heat distribution analysis results under continuous operating conditions; calculating the overall thermal resistance value of the module using temperature monitoring point data based on the heat distribution analysis results; obtaining a heat sink optimization configuration scheme through the overall thermal resistance value; simulating the heat flow path under load conditions based on the heat sink optimization configuration scheme to determine the feasibility assessment index of power improvement; extracting the selection criteria for heat dissipation materials from the feasibility assessment index; judging the assessment result based on the selection criteria for heat dissipation materials, and recording the feasibility data of power improvement for subsequent heat dissipation system architecture integration. Furthermore, the step of integrating the heat dissipation system architecture based on the evaluation results to obtain a complete module heat dissipation system design includes: obtaining the feasibility evaluation results of the power increase; determining the efficiency threshold by quickly exporting the efficiency and comparing it with a preset threshold; if the efficiency threshold is lower than the preset threshold, integrating the heat sink interface and thermal path matching design, and obtaining an integrated design scheme by aligning the interface size and matching the path thermal conduction; performing thermal simulation verification of the interface matching path for the integrated design scheme, and extracting verification data from the heat flow distribution simulation; determining the material compatibility check results based on the verification data; integrating the module heat dissipation system elements based on the material compatibility check results to obtain a system architecture integration scheme; adjusting the complete architecture parameters based on the system architecture integration scheme, extracting the adjustment values, and obtaining the complete module heat dissipation system design. Furthermore, the reliability test simulation for the heat dissipation system design to determine long-term performance prediction includes: obtaining the complete module heat dissipation system design and extracting heat transfer paths and component material parameters; setting a reliability test simulation environment based on the heat transfer paths and component material parameters to determine the thermal stress distribution under excessively high temperatures; simulating the material aging trend for the thermal stress distribution to obtain the rate of change of the aging mechanism in a high-temperature environment; constructing an aging prediction model based on the rate of change and calculating the aging acceleration effect using a temperature acceleration factor; determining the performance degradation curve of the module during long-term operation based on the aging acceleration effect; evaluating the module durability based on the performance degradation curve to obtain the long-term performance prediction for subsequent optimization effect verification.Furthermore, the step of verifying the thermal path optimization effect and confirming the degree of heat dissipation bottleneck resolution through the long-term performance prediction includes: acquiring initial thermal distribution parameters from the module through performance data acquisition, calculating the temperature gradient using thermal distribution simulation, and determining the non-uniform distribution characteristics; obtaining thermal stress analysis results based on the non-uniform distribution characteristics; adjusting path parameters using thermal path optimization based on the thermal stress analysis results, and obtaining material fatigue prediction values; establishing a reliability model based on the material fatigue prediction values, and outputting a performance degradation curve; judging the optimization effect based on the performance degradation curve and the long-term performance prediction, and obtaining elimination effect verification indicators; identifying bottleneck locations based on the elimination effect verification indicators, and if the indicators exceed a preset threshold, reconstructing the heat flow path to determine the degree of heat dissipation bottleneck resolution.

[0005] The technical solutions provided by the embodiments of the present invention may include the following beneficial effects:

[0006] This invention discloses an optimization method for the thermal distribution of ultraviolet light-emitting diode (UV) COB modules, aiming to solve the business challenges of excessive temperature difference between the center and edge chips, low heat dissipation efficiency, and accelerated material aging caused by heat concentration in high-power applications of multi-chip arrays. This invention quantifies the uneven temperature distribution using simulation software, determines the target area for thermal path optimization using finite element analysis, proposes a thermal resistance reduction scheme, and adjusts the substrate material parameters to enhance lateral thermal conductivity when the center chip temperature exceeds a threshold, designing and optimizing the substrate structure. Subsequently, a genetic algorithm is used to iteratively adjust the thermal path parameters and integrate the heat sink interface design to form a complete heat dissipation system architecture. Finally, reliability testing simulations and long-term performance predictions verify the effectiveness of the thermal path optimization and confirm that the heat dissipation bottleneck has been resolved. This invention significantly improves the uniformity of module heat dissipation and the feasibility of power increase, extends service life, and ensures stability under continuous high-power operation. Attached Figure Description

[0007] Figure 1 This is a flowchart of a heat dissipation optimization method for an ultraviolet light-emitting diode module according to the present invention. Detailed Implementation

[0008] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0009] like Figure 1 The heat dissipation optimization method for an ultraviolet light-emitting diode module in this embodiment may specifically include:

[0010] S101. Obtain the thermal distribution data of the ultraviolet light-emitting diode COB module, calculate the temperature difference between the central chip and the edge chip using simulation software, and obtain the quantitative index of the uneven temperature distribution.

[0011] Thermal distribution data of the ultraviolet light-emitting diode (COB) module is acquired using an infrared thermal imager to obtain the temperature field distribution of the module under operating conditions. This temperature field distribution is then imported into finite element simulation software to set the heat sink material distribution and boundary conditions, and the temperatures of the central and edge chips are calculated. The temperature difference is obtained by subtracting the central and edge chip temperatures. If the temperature difference exceeds a preset threshold, it is determined to be a non-uniform distribution, and a quantitative index of the temperature non-uniformity is obtained.

[0012] In one implementation, thermal distribution data of the ultraviolet light-emitting diode COB module is first acquired.

[0013] Specifically, a COB module refers to an ultraviolet light-emitting diode assembly in which the chip is directly packaged on a substrate, used for lighting or disinfection applications. Temperature field data is collected by an infrared thermal imager when the module is in operation.

[0014] For example, the module is placed in a constant-temperature environment and powered on. A thermal imager scans the surface temperature distribution, generating thermal image data. This data includes the temperature values ​​at each chip location for subsequent analysis. Furthermore, simulation software is used to calculate the temperature difference between the central chip and the edge chips.

[0015] For example, a three-dimensional thermal model of the module is constructed using finite element analysis software. This model considers the chip heat source, the thermal conductivity of the substrate material, and the heat dissipation structure. The simulation process involves inputting actual heat distribution data as boundary conditions and then running the heat conduction equation to solve for the temperature field. Specifically, the central chip, typically located at the geometric center of the module, experiences concentrated heat and has a higher temperature; the edge chips, closer to the boundary, experience faster heat diffusion. Through iterative calculations using software, the steady-state temperature of each chip is obtained; for example, the center temperature is 80 degrees Celsius, and the edge temperature is 65 degrees Celsius, a difference of 15 degrees Celsius. This calculation quantifies the thermal non-uniformity.

[0016] Preferably, in another implementation, the simulation parameters are adjusted to cover different scenarios.

[0017] For example, in high-power ultraviolet COB modules, by adding a chip density model, simulation software calculates that the difference between the center and edge of the display increases to 20 degrees Celsius, reflecting the impact of power on heat distribution. This approach demonstrates the versatility of the technical solution within the same field.

[0018] It should be noted that the quantitative index of uneven temperature distribution is obtained directly from the difference.

[0019] Specifically, this index is defined as the ratio of the maximum temperature difference to the average temperature. For example, when the difference is 15 degrees Celsius and the average is 70 degrees Celsius, the index is 0.214, which is used to evaluate the thermal management performance of the module.

[0020] In one possible implementation, the simulation results are verified by combining experiments.

[0021] For example, thermal testing is performed on actual modules, comparing the simulated differences with the measured values ​​to ensure accuracy. This verification process involves multiple iterative simulations, adjusting model parameters such as thermal resistance to match the measured data. Furthermore, this method can be applied to low-power UV COB module scenarios. Simulation software calculations show that the center-to-edge difference is reduced to 10 degrees Celsius, with an index of 0.15, indicating a more uniform heat distribution under low load, thus supporting module design optimization.

[0022] Understandably, by quantifying temperature unevenness through the above steps, data support can be provided for module heat dissipation design, such as guiding the addition of heat sink structures to reduce the difference.

[0023] For example, in the packaging optimization embodiment, the simulated introduction of a thermally conductive adhesive layer reduced the difference to 12 degrees Celsius after calculation, demonstrating the improved performance and application effect of the technology in the field of thermal management.

[0024] S102. Based on the quantitative index of uneven temperature distribution, determine the target area for thermal path optimization, use the finite element analysis method to simulate the heat flow path, and obtain potential thermal resistance reduction schemes.

[0025] By using temperature non-uniformity indicators, the target region of the thermal path is obtained from the chip temperature distribution. This region is then imported into a finite element analysis simulation with defined boundary conditions to obtain the heat flow path. For this heat flow path, the application of the radiation coating is optimized using heat sink materials, and potential thermal resistance schemes are calculated. The temperature difference calculation results are extracted from these potential thermal resistance schemes. If the difference exceeds a preset threshold, non-uniformity distribution is assessed to obtain module operating status data. Based on this module operating status data, a multi-layer thermal conductivity structure design is constructed to simulate a thermal resistance reduction path. The thermal resistance reduction path is then obtained, and the target region expansion scheme for thermal path optimization is determined.

[0026] For example, in the field of thermal management of ultraviolet light-emitting diode (UV) COB modules, the target area of ​​the thermal path is first obtained from the chip temperature distribution using a temperature non-uniformity index. This index is based on previously calculated temperature differences, such as using the ratio of the difference to the average temperature as a quantification standard, to identify areas of concentrated heat.

[0027] In one possible implementation, finite element analysis simulation is used to set boundary conditions and obtain the heat flow path.

[0028] Specifically, finite element analysis (FEM) simulation is a numerical method used to solve complex heat conduction problems. It discretizes the module structure into a finite number of element meshes, such as modeling the substrate and chip as a three-dimensional mesh. Each element defines a heat source and material properties like thermal conductivity. Boundary conditions, including ambient temperature and convection coefficient, are then set. The simulation is run to solve the heat balance equations, tracing the path of heat diffusion from the center of the chip to the edges. For example, the path shows that heat mainly flows along the substrate material, avoiding high-resistivity regions, thus obtaining a visualized thermal flow diagram. This detailed process ensures the accuracy of the path and supports subsequent optimization.

[0029] In one possible implementation, for the heat flow path, the application of the radiation coating is optimized using heat sink material, and the potential thermal resistance scheme is calculated.

[0030] Specifically, heat sink materials such as aluminum alloys or copper radiators reduce thermal resistance by increasing the contact area, while radiation coatings such as black oxide layers enhance thermal radiation. The optimization process involves iteratively adjusting the coating thickness in simulations, for example, from 0.1 mm to 0.5 mm, calculating the equivalent thermal resistance of each scheme, and calculating the total resistance through a series and parallel thermal resistance network model. For example, the total value of the scheme is obtained by adding the series thermal resistances in the path, thereby extracting multiple potential schemes, such as scheme one with a thermal resistance of 2 K / W and scheme two with 1.5 K / W. This calculation reveals the impact of material adjustments on heat flow.

[0031] In one possible implementation, the temperature difference calculation result is extracted from the potential thermal resistance scheme. If it is greater than a preset threshold, a non-uniform distribution judgment is made to obtain the module working status data.

[0032] Specifically, a preset threshold, such as 10 degrees Celsius, is used to compare the extracted results. If the difference of 12 degrees Celsius is greater than the threshold, it is judged as uneven, and then working status data such as current and ambient temperature are collected.

[0033] In one possible implementation, a multi-layer thermal conductivity structure design is constructed based on the module's operating status data to simulate a path for reducing thermal resistance.

[0034] Specifically, in multi-layered structures, such as those with added thermal conductive and insulating layers, the simulation is run with input state data to obtain a reduced path, such as heat being uniformly diffused through multiple layers.

[0035] In one possible implementation, the thermal resistance reduction path is obtained, and a target area expansion scheme for thermal path optimization is determined, thereby improving the overall thermal performance of the module.

[0036] S103. By considering potential thermal resistance reduction schemes, if the temperature of the central chip exceeds a preset threshold, the substrate material parameters are adjusted to enhance the lateral thermal conductivity, thereby obtaining an optimized substrate structure design.

[0037] The temperature of the central chip is obtained, and it is determined whether the temperature exceeds a preset threshold. If the temperature exceeds the preset threshold, the substrate material parameters are adjusted using a potential thermal resistance reduction scheme. This scheme obtains the material's thermal conductivity and thickness combination from thermal resistance calculations. For the adjusted substrate material parameters, the lateral thermal conductivity is enhanced, and heat flow simulation verification is performed. The verification uses finite element analysis to obtain a heat distribution map. From the enhanced lateral thermal conductivity, an optimized substrate structure design is obtained.

[0038] In one implementation, potential thermal resistance reduction methods first require evaluating the heat conduction paths within the chip substrate. This involves analyzing various possible sources of thermal resistance, such as the thermal conductivity and thickness of the substrate material, as well as interfacial contact resistance.

[0039] Specifically, potential thermal resistance reduction schemes refer to identifying and quantifying factors that may lead to heat accumulation, such as optimizing lateral paths when longitudinal thermal resistance is too high. Thermal resistance values ​​are calculated using simulation tools, such as assessing heat flux density based on Fourier's law of thermal conduction, to determine potential paths to reduce thermal resistance. This assessment helps provide a basis for subsequent temperature judgments, ensuring the scheme remains efficient in the application of thermal management in electronic devices. Further, determining whether the central chip temperature exceeds a preset threshold is a critical step. During chip operation, temperature sensors are used to monitor the temperature data of the central region in real time. The preset threshold can be set according to chip specifications, for example, 85 degrees Celsius in high-performance computing devices. If the monitored temperature exceeds this threshold, an adjustment mechanism is triggered. This judgment process includes data acquisition and comparison, such as acquiring temperature signals through embedded sensors and comparing them numerically with the threshold to avoid performance degradation or damage caused by overheating. This step ensures the reliability of the triggering conditions for the optimization process in semiconductor substrate design.

[0040] Preferably, if the temperature of the central chip exceeds a preset threshold, the substrate material parameters are adjusted to enhance lateral thermal conductivity. Specifically, the substrate material parameters include thermal conductivity, material composition, and layer thickness. For example...

[0041] In one possible implementation, the substrate is changed from standard silicon to a composite material with an added copper layer to improve lateral thermal conductivity. Iterative calculations simulate the heat distribution under different parameter combinations; for example, increasing the copper layer thickness can reduce lateral thermal resistance by 20%, thereby dispersing central heat. This adjustment process involves finite element analysis, progressively optimizing parameters until thermal equilibrium is achieved.

[0042] It should be noted that this adjustment to enhance lateral thermal conductivity is limited to the chip packaging field, ensuring heat dissipation to the surrounding area, and is applicable to scenarios such as mobile phone processors or server chips. For example.

[0043] In one embodiment, the optimized substrate structure design is achieved by integrating the aforementioned steps. First, an initial structure is simulated based on a thermal resistance scheme. Then, parameters are adjusted when the temperature exceeds a threshold, such as increasing the substrate's thermal conductivity from 1.5 W / m·K to 3.0 W / m·K, ultimately resulting in a design drawing. This design demonstrates versatility, for example, by applying the same optimization logic to chips with different power levels. In another embodiment, the potential thermal resistance reduction scheme can be extended to multilayer substrate structures.

[0044] Specifically, the thermal resistance between layers is analyzed, such as the interface between the upper chip and the lower heat sink. By calculating the thermal resistance network, bottleneck paths are identified and mitigation measures are proposed, such as adding thermal bridging materials to connect laterally. This expansion enhances the flexibility of the approach in integrated circuit design. Furthermore, temperature judgments can be optimized by incorporating historical data to refine threshold settings.

[0045] For example, machine learning algorithms can be used to analyze past operating data and dynamically adjust thresholds to adapt to different loads, thereby improving the accuracy of judgments.

[0046] For example, adjusting material parameters may also include changing the substrate geometry, such as adding lateral trenches to guide heat flow. This adjustment was verified in simulations to improve lateral thermal conductivity.

[0047] Understandably, the optimized substrate structure design is ultimately validated through prototype testing, such as measuring temperature distribution in a laboratory environment to confirm the stability improvement resulting from reduced thermal resistance.

[0048] In one embodiment, the entire process is applied to a power amplifier chip, demonstrating a complete flow from thermal resistance assessment to structural optimization, ensuring thermal management efficiency at high frequencies.

[0049] S104. Obtain the optimized substrate structure design, perform thermal simulation verification for the multi-chip array arrangement, determine the path efficiency of heat dissipation from each chip to the outside, and obtain a uniform heat dissipation distribution model.

[0050] By using preset substrate material parameters, the multi-chip array arrangement is obtained to acquire initial heat source distribution data. Based on this initial heat source distribution data, a finite element method is used to verify the heat conduction path and determine the thermal resistance value of each chip for external heat dissipation. From these thermal resistance values, a path efficiency index is obtained by calculating the reciprocal of the thermal resistance value. If the efficiency index is lower than a preset threshold, the spacing of the cooling channels in the substrate structure is adjusted to obtain optimized arrangement parameters. Based on the optimized arrangement parameters, a heat distribution grid model is constructed to obtain a balanced heat transfer path between chips. Iterative simulation calibration is performed on the heat distribution grid model to determine a uniform heat dissipation distribution model.

[0051] In one implementation, the substrate structure design is optimized for multi-chip arrays, first considering the substrate material selection and stack-up structure. The substrate typically uses a high thermal conductivity material, such as a copper-based or ceramic substrate, to improve thermal conductivity.

[0052] Specifically, heat distribution is achieved by adjusting the thickness of the substrate and the chip mounting position.

[0053] For example, in a multi-chip array, the chips are arranged in a grid pattern to ensure uniform spacing between adjacent chips and avoid hot spot concentration. This design helps to initially control the path of heat transfer from the chips to the substrate. Further, during thermal simulation verification, finite element analysis software is used to simulate the thermal behavior of the multi-chip array. Thermal simulation verification refers to simulating the heat flow process using numerical methods, with input parameters including chip power, ambient temperature, and material thermal conductivity.

[0054] It should be noted that finite element analysis divides the substrate and chip model into mesh elements and calculates the temperature gradient of each element to verify the thermal performance of the design.

[0055] In one possible implementation, the simulation process begins with the chip's heat source and traces the diffusion path of heat to the substrate and the external environment.

[0056] For example, determining the efficiency of the path for heat dissipation from each chip to the outside requires analyzing a thermal resistance network (RTN). An RTN is a modeling approach that represents the heat dissipation path as a resistance chain and calculates the thermal resistance from the chip to the outside. The process involves identifying the primary paths, such as conduction through the substrate, convection through solder joints, and radiation, and then quantifying the efficiency, i.e., the proportion of heat transferred.

[0057] For example, for a chip, path efficiency can be estimated using a formula to determine the ratio of heat flux density to total heat, ensuring a balanced contribution from each path. This analysis helps identify inefficient paths and optimize the design.

[0058] Preferably, in the thermal simulation verification, boundary conditions such as forced convection cooling are introduced to simulate the actual working environment.

[0059] In one embodiment, for high-density multi-chip arrays, the verification process showed that adding heat dissipation fins could improve path efficiency by more than 20%. This verification not only confirmed the uniformity of heat distribution but also provided data support for subsequent optimization. Furthermore, based on the verification results, a uniform heat dissipation distribution model was constructed.

[0060] It is understandable that the uniform heat dissipation distribution model is a mathematical representation obtained by fitting simulation data, which describes the spatial distribution of temperature on the substrate.

[0061] Specifically, the model uses a Gaussian distribution function, and the parameters are calculated based on path efficiency.

[0062] For example, in multi-chip array scenarios, the model ensures that the temperature difference between the central chip and the edge chips is less than 5 degrees Celsius, achieving uniform heat dissipation. The model construction process includes data acquisition, curve fitting, and iterative verification, helping designers predict thermal performance under different arrangements. In another implementation, for chip arrays with uneven power distribution, heat pipes can be embedded to enhance the conduction path when optimizing the substrate structure. A heat pipe is a heat transfer device that utilizes the principle of phase change, installed inside the substrate to rapidly guide heat from the heat source to the cooling end. Specifically, the evaporation end of the heat pipe absorbs heat from the chip, and the vapor flows to the condensation end to release heat, thereby improving path efficiency. This method is suitable for high-power applications, and simulation verification shows that it can make heat dissipation distribution more uniform. Further, the detailed steps of thermal simulation verification include model building, mesh generation, and iterative solution. During model building, the geometry and material properties are defined; mesh generation ensures computational accuracy; and the iterative solution uses Newton's method to handle nonlinear thermal equations. This process clearly explains the core of the simulation and helps to understand the quantification of path efficiency.

[0063] For example, a typical array demonstrates that a path-efficient design reduces thermal stress and improves chip reliability.

[0064] In one embodiment, the obtained uniform heat dissipation distribution model can be applied to actual production. By guiding substrate layout adjustments using the model, heat paths can be optimized, ultimately resulting in a highly efficient heat dissipation solution. This technology reduces chip failure rates and improves system stability.

[0065] It should be noted that, in all implementations, the substrate design remains universal, such as being suitable for arrays of different chip sizes, without altering the core thermal management area.

[0066] S105. Based on the uniform heat dissipation distribution model, the thermal path parameters are optimized using a genetic algorithm. If the material aging rate is higher than the preset threshold, the path length and interface thermal resistance are iteratively adjusted to obtain the final thermal path configuration.

[0067] Initial thermal path parameters are obtained from a pre-defined uniform heat dissipation distribution model, constructed using a heat conduction equation. A genetic algorithm is used to optimize these parameters, with the initial thermal path parameters as input and optimized parameters as output. The material aging rate is determined by simulating thermal stress. If the aging rate exceeds a preset threshold, the path length and interface thermal resistance are obtained from the initial thermal path parameters and iteratively adjusted using gradual modifications to these parameters. Through this iterative adjustment, a balanced thermal resistance distribution is achieved, calculated using balanced heat flow. The aging prediction simulation result is then determined, derived from a thermal aging equation. Based on the aging prediction simulation result, a genetic algorithm is used to optimize the path length and interface thermal resistance, with the path length and interface thermal resistance as input and optimized values ​​as output, resulting in adjusted thermal path parameters. The final thermal path configuration is obtained by integrating these adjusted parameters.

[0068] In one implementation, a uniform heat dissipation distribution model is used to simulate the heat transfer process inside an electronic device. This model assumes that heat is uniformly distributed in the material and predicts the temperature gradient by establishing a heat flow equation.

[0069] Specifically, the model takes into account the location of the heat source, the thermal conductivity of the material, and the boundary conditions to generate a heat distribution map to guide subsequent optimization.

[0070] For example, in a chip heat dissipation system, this model can simulate the process of heat flowing from the chip core to the heat sink, ensuring that heat does not concentrate in a single area, thereby reducing the risk of localized overheating. Furthermore, a genetic algorithm is used to optimize the thermal path parameters. A genetic algorithm is a biomimetic optimization method that simulates the natural selection process, including population initialization, fitness evaluation, selection, crossover, and mutation steps. In this embodiment, a set of thermal path parameters, such as initial values ​​for path length and interface thermal resistance, is first initialized. Then, the heat dissipation efficiency under each parameter combination is calculated as the fitness. Through multiple iterations, parameters with high fitness are selected for crossover to generate new parameter sets.

[0071] For example, in the thermal management of electronic devices, this algorithm can optimize the heat pipe path, improve heat transfer efficiency, and is suitable for the heat dissipation design of mobile phones or computers.

[0072] It is important to note that determining the material aging rate is a crucial step in the optimization process. The material aging rate refers to the rate at which the material's performance degrades under high-temperature conditions, typically estimated based on the Arrhenius equation, taking into account both temperature and time factors. If the calculated aging rate exceeds a preset threshold, such as a decay rate exceeding 0.01% per hour, it indicates that the current thermal path configuration may lead to premature material failure.

[0073] In one possible implementation, the aging rate is calculated by monitoring simulated temperature data and compared with a threshold to determine whether to proceed with iterative adjustments.

[0074] Specifically, if the material aging rate exceeds a preset threshold, the path length and interfacial thermal resistance are iteratively adjusted. Path length refers to the physical distance of heat transfer, while interfacial thermal resistance represents the resistance to heat transfer at the material contact surface. The adjustment process includes gradually increasing the path length to disperse heat, or reducing the interfacial thermal resistance by improving the contact materials.

[0075] For example, in the iteration, the path length is first extended by 10%, and the heat dissipation distribution is re-simulated. If the aging rate is still high, the interfacial thermal resistance is reduced, such as from 0.5 K / W to 0.3 K / W, and the genetic algorithm optimization is repeated. This process is repeated until the aging rate is below a threshold, thereby obtaining a stable thermal path configuration. In the field of electronic devices, this adjustment can be applied to server cooling systems to ensure material reliability during long-term operation. Preferably.

[0076] In one embodiment, for heat dissipation optimization of high-power electronic modules, an initial thermal map is first constructed using a uniform heat dissipation distribution model. Then, a genetic algorithm is used to generate multiple candidate thermal path parameter schemes. When determining the material aging rate, real-time temperature sensor data is introduced as input. If a threshold is exceeded, iterative adjustments involve multiple rounds of parameter fine-tuning, such as progressively optimizing the path length from 50mm to 80mm, while simultaneously monitoring changes in interface thermal resistance. This method demonstrates versatility within the same field, such as for LED lighting devices of different specifications, ensuring that the thermal path configuration adapts to various power levels.

[0077] For example, in another embodiment, for thermal management of portable electronic devices, a uniform heat dissipation distribution model can integrate ambient temperature variables, while a genetic algorithm prioritizes optimizing interface thermal resistance to minimize thermal resistance under volume constraints. Once the aging rate exceeds a threshold, the iterative process focuses on dynamically shortening the path length, combined with thermal resistance adjustment, to achieve a compact configuration. This embodiment highlights the applicability of the technical solution in confined space scenarios and can effectively extend material lifespan.

[0078] Understandably, after obtaining the final thermal path configuration through the above steps, its effectiveness can be further verified. In simulation tests, the heat dissipation uniformity under this configuration is improved, and the material aging rate is controlled within the threshold, providing a reliable thermal management solution for electronic devices. In one implementation, the population size of the genetic algorithm can be set to 50 to 100 to balance computational efficiency and optimization accuracy, further enhancing the iterative adjustment process of thermal path parameters.

[0079] S106. By configuring the final thermal path, the continuous working state under high-power application scenarios is simulated to determine the overall thermal resistance value of the module and obtain the feasibility assessment results of power improvement.

[0080] A preset thermal path configuration is obtained, and high-power application scenario parameters are extracted from this configuration to determine the heat distribution analysis results under continuous operating conditions. Based on the heat distribution analysis results, temperature monitoring point data obtained from monitoring equipment is used to determine the overall thermal resistance value of the module, resulting in an optimized heat sink configuration scheme. Using this optimized heat sink configuration scheme, the heat flow path under the load conditions extracted from the application scenario is simulated to determine the feasibility evaluation indicators for power improvement. From these feasibility evaluation indicators, the basis for selecting heat dissipation materials is obtained, and the evaluation results are determined.

[0081] In one implementation, the heat conduction path of the module is first optimized through the final thermal path configuration.

[0082] Specifically, thermal path configuration refers to the placement and connection method of heat sources, heat sinks, and thermally conductive materials in the power module to minimize thermal resistance.

[0083] For example, in the context of electronic power modules, heat sources such as power transistors are tightly integrated with a heat dissipation substrate, and the gaps are filled with high-thermal-conductivity thermal grease to ensure efficient heat transfer to the external environment. This configuration is based on the fundamental law of heat conduction: heat flows from high-temperature areas to low-temperature areas. By optimizing the path and reducing heat loss, the overall thermal management capability of the module is improved. In actual business operations, the key heat source components of the module are first identified, and then the path length and material selection are calculated based on the heat flux density, such as using copper heat-conducting plates to improve conduction efficiency. This method is applicable to various power converter scenarios, ensuring the versatility of the configuration. Furthermore, based on the above thermal path configuration, continuous operation under high-power application scenarios is simulated.

[0084] In one possible implementation, a thermal model of the module is constructed using finite element analysis software, and a high-power load, such as a continuous input power of 1000 watts, is input to simulate the temperature distribution of the module during long-term operation.

[0085] It's important to note that continuous operation refers to the module's thermal equilibrium process under uninterrupted high load. For example, in industrial frequency converter applications, the simulated ambient temperature is 40 degrees Celsius, and the module operates for over 8 hours to observe the heat accumulation effect. The simulation process involves setting boundary conditions, such as convective heat dissipation coefficient and radiative heat loss, and then iteratively calculating the temperature field. The innovation of this simulation lies in accurately predicting thermal bottlenecks, helping to avoid overheating failures. In business applications, this leads to stable performance output, such as in power supply systems, ensuring that the module does not experience thermal failure under peak loads, thereby supporting higher power density designs.

[0086] Preferably, the overall thermal resistance value of the module is determined by calculation based on simulation results.

[0087] Specifically, the thermal resistance is defined as the temperature difference divided by the thermal power, i.e., Rth = (Tj - Ta) / P, where Tj is the junction temperature, Ta is the ambient temperature, and P is the power.

[0088] For example, after simulation, temperature data of key nodes is extracted. For instance, if the power device junction temperature is 150 degrees Celsius, the ambient temperature is 25 degrees Celsius, and the power is 500 watts, the calculated thermal resistance is approximately 0.25 degrees Celsius per watt. This calculation process needs to consider the series and parallel combination of multiple thermal paths, such as the superposition of substrate thermal resistance and heat sink thermal resistance. In this way, the thermal performance limits of the module are evaluated, and in similar fields such as power modules for electric vehicles, it is verified whether the thermal resistance is below a threshold to support safe operation.

[0089] For example, in another embodiment, simulation parameters are adjusted for different high-power scenarios, such as increasing the load to 1500 watts, and the change in thermal resistance under continuous operation is observed. Furthermore, this assessment reveals the feasibility of power increases; for example, if the thermal resistance value is below 0.2 degrees Celsius per watt, it indicates that the module can withstand a 20% power increase without exceeding the temperature limit. In practice, this involves comparing the thermal resistance differences between the baseline model and the optimized model to ensure the objectivity of the assessment.

[0090] Understandably, the feasibility assessment results for the power increase are based on thermal resistance values ​​and simulation data.

[0091] Specifically, by plotting a power-temperature curve, the maximum allowable power of the module under a given thermal path configuration can be determined.

[0092] For example, in continuous operation simulations, if the temperature remains below 120 degrees Celsius, it is assessed as feasible, with a power potential increase of up to 15%. This assessment is based on the thermal balance equation, ensuring the module's reliability in high-power applications such as server power supplies. In one implementation, an alternative heat dissipation path is introduced as an optional feature to further reduce thermal resistance and support a wider power range. In practical applications, the above method can be extended to the thermal management of similar power modules, such as by repeating the simulation process in renewable energy inverters, demonstrating the versatility of the technology. Through these steps, a comprehensive evaluation of the module's thermal performance is achieved.

[0093] S107. Obtain the feasibility assessment results of power improvement, and determine if the rapid export efficiency is lower than the preset threshold. Then, integrate the heat sink interface design to match the thermal path and obtain the complete module heat dissipation system architecture.

[0094] The feasibility assessment results for power enhancement are obtained by comparing the rapidly derived efficiency with a preset threshold to determine the efficiency threshold. If the efficiency threshold is lower than the threshold, the heat sink interface and thermal path matching design are integrated. An integrated design scheme is obtained through interface size alignment and path thermal conduction matching. Thermal simulation verification is performed on the interface matching path using this integrated design scheme. Verification data is extracted from the heat flow distribution simulation to determine the material compatibility check results. Based on the material compatibility check results, the elements of the module heat dissipation system are integrated. A system architecture integration scheme is obtained through element thermal capacity balancing. The complete architecture parameters are adjusted using this system architecture integration scheme. Adjustment values ​​are extracted from parameter thermal resistance optimization to obtain the complete module heat dissipation system architecture.

[0095] In one implementation, the feasibility assessment results of the power increase are first obtained.

[0096] Specifically, the evaluation process is achieved by collecting the module's current power data and environmental parameters.

[0097] For example, the power output of the electronic module is measured, taking into account operating temperature and load conditions. Simulation tools are used to analyze the heat generation after a power increase to determine its feasibility. This assessment ensures a foundation for subsequent steps, avoiding blind optimization. Furthermore, based on the assessment results, it is determined whether the rapid heat dissipation efficiency is below a preset threshold. Rapid heat dissipation efficiency refers to the rate at which heat is dissipated from the module's interior to the exterior, typically expressed as the heat transfer coefficient. The preset threshold can be set according to the module type, for example, a specific value in high-power electronic devices. If the efficiency is below the threshold, it indicates that the existing heat dissipation path is insufficient, requiring further intervention. This judgment step is performed by comparing the calculated value with the threshold, ensuring the accuracy of the decision.

[0098] Preferably, if the determination result indicates that the rapid export efficiency is lower than a preset threshold, the heat sink interface design is integrated to match the thermal path. Heat sink interface design involves selecting suitable materials and structures, such as using a high thermal conductivity alloy to fabricate the interface surface. Thermal path matching refers to optimizing the heat flow channels to align with the heat source distribution of the module. The specific process includes analyzing the module's thermal distribution map and adjusting the interface's position and size to achieve efficient heat conduction. For example...

[0099] In one possible implementation, finite element analysis is used to simulate the thermal path, confirming that the interface design can uniformly direct heat to the heat sink, thereby reducing the module temperature. This integration step is the core innovation, significantly improving the system's thermal management capabilities.

[0100] In one embodiment, the construction of the complete module thermal system architecture is based on the aforementioned integration results.

[0101] Specifically, the integrated heat sink interface is combined with the module body to form a closed thermal management system.

[0102] For example, for a power amplifier module, the possibility of boosting the power to a specified level is first assessed. If the efficiency of rapid output is below a threshold, the interface is designed to match the main thermal path, such as the heat flow channel from the chip to the casing. The final architecture includes heat sources, interfaces, and heat sink components to ensure overall stability. This architecture is common in the field of electronic devices and can adapt to different load scenarios.

[0103] It should be noted that the above process can be extended to various scenarios, such as applying similar evaluation and integration in communication modules.

[0104] For example, power enhancement assessments are performed on RF modules, and interfaces are integrated after efficiency evaluation to obtain an optimized architecture. This method improves flexibility through modular design. Furthermore, in another implementation, the assessment results can be obtained in conjunction with real-time monitoring.

[0105] For example, sensors are used to collect temperature data to calculate the feasibility of power increases. This step is linked to the decision-making process, ensuring logical continuity from assessment to architecture construction.

[0106] For example, multi-parameter analysis can be introduced to determine the efficiency of fast export.

[0107] Specifically, efficiency calculations consider thermal resistance and environmental factors; if the efficiency falls below a threshold, interface design adjustments are triggered. This detailed analysis helps in understanding the causes and consequences of business processes, such as how low efficiency leads to overheating risks, and how matching thermal paths can achieve stable output.

[0108] In one embodiment, the specific implementation of integrating the heatsink interface includes selecting the interface geometry to optimize the thermal path.

[0109] For example, using a tapered interface increases the contact area and matches the linear thermal path of the module. This design effectively reduces heat concentration points and provides reliable heat dissipation support.

[0110] Understandably, the emphasis on system integration within a complete architecture is evident.

[0111] For example, by integrating the interface with the existing module framework to form a unified system, thermal equilibrium can be achieved in high-power applications.

[0112] Preferably, the threshold parameters of this technical solution can be adjusted during implementation to adapt to different module types and ensure the versatility of the architecture.

[0113] S108. Based on the complete module heat dissipation system architecture, conduct reliability test simulations to determine the material aging trend under excessively high temperature conditions and obtain long-term performance predictions of module reliability.

[0114] A complete module heat dissipation system architecture is obtained, and heat transfer paths and component material parameters are extracted from this architecture. A reliability test simulation environment is set using these heat transfer paths and component material parameters to determine the thermal stress distribution under excessively high temperatures. Material aging trend simulation is performed on this thermal stress distribution to obtain the rate of change of the aging mechanism in a high-temperature environment. An Arrhenius model is constructed from this rate of change, and the aging acceleration effect is calculated using the model's temperature acceleration factor to determine the module's performance degradation curve during long-term operation. The module's durability is evaluated based on the performance degradation curve, resulting in a long-term reliability performance prediction.

[0115] In one implementation, the complete module heat dissipation system architecture is first obtained.

[0116] Specifically, this architecture is constructed by integrating module components and heat dissipation paths. For example, in a power electronics module, heat sources such as chips are connected to heat sinks to form an overall framework, facilitating the subsequent extraction of key parameters. Furthermore, heat transfer paths and component material parameters are extracted from this architecture. Heat transfer paths refer to the channels through which heat flows from the heat source to the outside, typically including a thermally conductive layer and a convection layer; component material parameters involve properties such as thermal conductivity and specific heat capacity.

[0117] For example, in RF module applications, the heat flow distribution from the circuit board to the housing is analyzed during heat path extraction, while the thermal conductivity value of the aluminum alloy material (approximately 200 W / m·K) and density parameters are recorded to support the setting of the simulation environment. The reliability test simulation environment is then set using the aforementioned heat transfer path and component material parameters to determine the thermal stress distribution under excessively high temperature conditions.

[0118] Specifically, the reliability testing simulation environment is a virtual scene constructed using finite element method (FEM) software. Input path data, such as thermal resistance, and material parameters, such as elastic modulus, are used to simulate high-temperature environments, such as 150°C. Thermal stress distribution refers to the stress field distribution of a material under thermal expansion. The calculation process involves first defining boundary conditions, such as fixing the edges of the module, then applying thermal loads and solving the stress equations to obtain the distribution map. For example...

[0119] In one possible implementation, the simulation of the communication module sets the path to a chip-substrate-heat sink sequence. The Young's modulus of copper is input as 70 GPa. After running the simulation, the stress peak is determined to occur at the interface at approximately 50 MPa, thus revealing potential crack risks. Detailed analysis of this step helps to understand how thermal stress accumulates due to temperature gradients. The cause is uneven heat transfer leading to localized overheating, and the consequence is accelerated material fatigue. This simulation allows for early identification of problem areas. Material aging trend simulation is then performed on the aforementioned thermal stress distribution to obtain the rate of change of the aging mechanism in a high-temperature environment. The aging trend simulation uses the Monte Carlo method, inputting stress distribution data to predict the degradation process of materials such as polymer insulation layers; the rate of change refers to the rate of aging, such as oxidation or creep, typically expressed as a function of time.

[0120] For example, for a power amplifier module, a simulated input stress diagram is used to calculate that the oxidation rate at 120°C is approximately 0.001 / h, thus quantifying high-temperature accelerated aging. An Arrhenius model is constructed from this rate of change, and the aging acceleration effect is calculated using the model's temperature acceleration factor to determine the module's performance degradation curve during long-term operation. The Arrhenius model is based on the reaction rate equation k=A*exp(-Ea / RT), where Ea is the activation energy, R is the gas constant, and T is the temperature; the temperature acceleration factor AF=exp[(Ea / R)(1 / T1-1 / T0)] is used to compare the aging rates at different temperatures.

[0121] Specifically, during construction, an Ea value, such as 50 kJ / mol, is fitted from rate data, and then AF is calculated. For example, at a reference temperature of 85°C, the AF at 150°C is approximately 100, indicating a 100-fold acceleration in aging. The performance degradation curve is plotted by integrating the AF to show the decrease in output power over time. For example...

[0122] In one possible implementation, a model is constructed for the electronic control module by inputting a change rate of 0.002 / h. After calculating the acceleration effect, a curve showing a 20% power decay after 10,000 hours is used to assess long-term stability. This model connects rate data with predictions, revealing how high temperatures amplify the aging effect. The module's durability is evaluated based on the performance decay curve, yielding a long-term performance prediction of reliability.

[0123] Specifically, the durability assessment compares the curve to a threshold where the degradation does not exceed 10%, and the predicted module lifespan exceeds 50,000 hours. In one implementation, this process can be extended to automotive electronic modules to ensure reliability in high-temperature environments.

[0124] S109. By predicting the long-term performance of module reliability, the effect of thermal path optimization on eliminating uneven distribution is verified, and the final solution to the heat dissipation bottleneck is confirmed.

[0125] By acquiring performance data, initial thermal distribution parameters are obtained from the module. Thermal distribution simulation is used to calculate the temperature gradient in the heat conduction equation, determining the non-uniform distribution characteristics and obtaining thermal stress analysis results. Based on these thermal stress analysis results, thermal path optimization is employed to adjust path parameters for non-uniform distribution, obtaining predicted material fatigue values. A reliability model is established using these predicted fatigue values. This model takes fatigue prediction values ​​and time-series data as input and outputs a performance degradation curve. The optimization effect is assessed from long-term performance predictions, yielding a verification index for the elimination effect. For this verification index, bottleneck locations are identified. If the index exceeds a preset threshold, the heat flow path is reconstructed to determine the degree of heat dissipation bottleneck resolution. Based on the degree of heat dissipation bottleneck resolution and the verification index, overall performance data is obtained from the module's reliability, confirming the thermal path optimization.

[0126] In one embodiment, initial thermal distribution parameters are obtained from the module through performance data acquisition. For example, in an electronic device module, an infrared thermal imager is used to scan the module surface and record the temperature values ​​of each component, thereby obtaining initial thermal distribution parameters such as average temperature and hot spot locations.

[0127] In one embodiment, the temperature gradient in the heat conduction equation is calculated using heat distribution simulation to determine the non-uniform distribution characteristics and obtain the thermal stress analysis results.

[0128] Specifically, a simulation model is first established based on Fourier's law of heat conduction, where the heat conduction equation represents the propagation of heat in the material. Initial heat distribution parameters are input into finite element analysis software to calculate the temperature gradient, i.e., the rate at which temperature changes spatially. For example, in the chip region of the module, the temperature decreases from the center to the edge, forming a gradient value. Then, the non-uniform distribution characteristics are analyzed, such as identifying localized high-temperature zones caused by heat concentration along specific paths. Next, the stress distribution is evaluated using a thermal stress formula, where thermal stress originates from the expansion differences caused by the temperature gradient. The results, such as the stress peak value of the material in the high-temperature zone, reveal potential thermal fatigue risks. This method, by simulating a real operating environment, helps predict the stability of the module under high loads.

[0129] In one embodiment, based on the thermal stress analysis results, for non-uniform distribution, thermal path optimization is used to adjust the path parameters and obtain the material fatigue prediction value, for example, by adding a thermally conductive material layer to balance the heat flow.

[0130] In one embodiment, a reliability model is established using the predicted fatigue values ​​of the material. The reliability model takes fatigue prediction values ​​and time series data as inputs and outputs a performance degradation curve. The optimization effect is judged from the long-term performance prediction to obtain the elimination effect verification index.

[0131] Specifically, the reliability model is built based on the Weibull distribution, which takes fatigue prediction values, such as crack propagation rate under a certain number of cycles, and time series data, such as temperature records of continuous operation hours, as input. The model calculates the decay curve through Monte Carlo simulation, that is, the trajectory of performance parameters decreasing over time, such as the curve of module efficiency decreasing from 100% to 80%. Then, indicators such as mean time between failures are extracted from the curve to determine the slowdown of the decay rate after optimization, thereby obtaining the elimination effect verification indicator such as the percentage improvement. The application of this model can effectively evaluate the long-term benefits of thermal path optimization.

[0132] In one embodiment, the bottleneck location is identified based on the elimination effect verification index. If the index exceeds a preset threshold, the heat flow path is reconstructed to determine the degree of heat dissipation bottleneck resolution. For example, if the improvement percentage is less than 50%, the path layout is adjusted.

[0133] In one embodiment, by assessing the degree to which the heat dissipation bottleneck is resolved and combining the elimination effect verification indicators, overall performance data is obtained from the module reliability to confirm the thermal path optimization. For example, comprehensive data confirms successful optimization, thereby improving the module's durability.

[0134] The aforementioned personal information processing rules should include, but are not limited to, the name and contact information of the personal information processor, the specific purpose of personal information processing, the processing method, the types of personal information processed, the retention period, and the methods and procedures for individuals to exercise their relevant rights.

[0135] The above description is merely a specific implementation of this specification. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, modules, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here. It should be understood that the scope of protection of this specification is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this specification, and these modifications or substitutions should all be covered within the scope of protection of this specification.

Claims

1. A method for optimizing heat dissipation of an ultraviolet light-emitting diode module, characterized in that, include: S101, Obtain the thermal distribution data of the ultraviolet light-emitting diode module and determine the quantitative index of the uneven temperature distribution; S102, Based on the quantified indicators, determine the target area for thermal path optimization to obtain a thermal resistance reduction scheme; S103, Adjust the substrate structure design using the thermal resistance reduction scheme to enhance thermal conductivity; S104, Perform thermal simulation verification on the substrate structure design to determine the heat dissipation path efficiency and construct a uniform heat dissipation distribution model; S105, Optimize the thermal path parameters based on the uniform heat dissipation distribution model to obtain the final thermal path configuration; S106, Simulate the thermal resistance value under operating conditions using the final thermal path configuration to determine the feasibility assessment result for power improvement; S107, Based on the assessment result, integrate the heat dissipation system architecture to obtain a complete module heat dissipation system design; S108, Perform reliability test simulation on the heat dissipation system design to determine long-term performance prediction. S109, The effect of thermal path optimization is verified through the long-term performance prediction, and the degree of resolution of the heat dissipation bottleneck is confirmed.

2. The heat dissipation optimization method for an ultraviolet light-emitting diode module as described in claim 1, characterized in that, Step S101 further includes: acquiring temperature field distribution data of the module under working conditions using an infrared thermal imager; importing the temperature field distribution data into finite element simulation software, setting the heat sink material distribution and boundary conditions, and calculating the temperature of the central chip and the edge chip; performing a subtraction operation between the central chip temperature and the edge chip temperature to obtain a temperature difference; if the temperature difference is greater than a preset threshold, it is determined to be a non-uniform temperature distribution, and a quantitative index of the non-uniform temperature distribution is obtained; based on the quantitative index, the thermal distribution characteristics of the module are recorded for subsequent thermal path optimization analysis; and using the thermal distribution characteristics, combined with the temperature difference data, an initial thermal distribution model is constructed to determine the specific areas of non-uniform temperature distribution.

3. The heat dissipation optimization method for an ultraviolet light-emitting diode module as described in claim 1, characterized in that, Step S102 further includes: extracting the target region of the thermal path from the chip temperature distribution using the quantitative index of the temperature non-uniformity distribution; importing the target region data into finite element analysis software, setting boundary conditions, and simulating the heat flow path; adjusting the heat sink material distribution and radiation coating application for the heat flow path, and calculating potential thermal resistance reduction schemes; extracting the temperature difference calculation results from the potential thermal resistance reduction schemes, and if they are greater than a preset threshold, performing non-uniformity distribution judgment and obtaining module operating status data; constructing a multi-layer thermal conductivity structure design based on the module operating status data, and simulating the thermal resistance reduction path; and determining the target region expansion scheme for thermal path optimization through the thermal resistance reduction path.

4. The heat dissipation optimization method for an ultraviolet light-emitting diode module as described in claim 1, characterized in that, Step S103 further includes: acquiring the temperature data of the central chip and determining whether the temperature data exceeds a preset threshold; if the temperature data exceeds the preset threshold, adjusting the substrate material parameters through the thermal resistance reduction scheme to obtain the material thermal conductivity and thickness combination; enhancing the lateral thermal conductivity of the adjusted substrate material parameters and performing thermal flow simulation verification; obtaining a heat distribution map using the finite element analysis method through the thermal flow simulation verification; analyzing the improvement effect of the lateral thermal conductivity based on the heat distribution map to determine the optimized substrate structure design; and extracting parameters from the optimized substrate structure design for subsequent thermal simulation verification of the multi-chip array.

5. The heat dissipation optimization method for an ultraviolet light-emitting diode module as described in claim 1, characterized in that, Step S104 further includes: obtaining the multi-chip array arrangement layout through preset substrate material parameters to determine initial heat source distribution data; verifying the heat conduction path using the finite element method based on the initial heat source distribution data, and calculating the thermal resistance value of each chip to dissipate heat to the outside; obtaining the path efficiency index using the reciprocal calculation method of the thermal resistance value; if the path efficiency index is lower than a preset threshold, adjusting the cooling channel spacing in the substrate structure to obtain optimized arrangement parameters; constructing a heat distribution grid model based on the optimized arrangement parameters to determine the heat balanced transmission path between chips; and performing iterative simulation calibration on the heat distribution grid model to obtain the uniform heat dissipation distribution model.

6. The heat dissipation optimization method for an ultraviolet light-emitting diode module as described in claim 1, characterized in that, Step S105 further includes: obtaining initial thermal path parameters from the uniform heat dissipation distribution model, constructing a simulation environment through the heat conduction equation; optimizing the initial thermal path parameters using a genetic algorithm, outputting optimized parameters, and determining the material aging rate; if the material aging rate is higher than a preset threshold, extracting the path length and interface thermal resistance from the initial thermal path parameters and performing iterative adjustments; obtaining thermal resistance distribution equilibrium data through the iterative adjustments and calculating the equilibrium heat flow distribution; determining the aging prediction simulation results based on the equilibrium heat flow distribution; and further optimizing the path length and interface thermal resistance using a genetic algorithm based on the aging prediction simulation results, outputting the adjusted thermal path parameters, and integrating them to form the final thermal path configuration.

7. The heat dissipation optimization method for an ultraviolet light-emitting diode module as described in claim 1, characterized in that, Step S106 further includes: obtaining the final thermal path configuration, extracting high-power application scenario parameters, and determining the thermal distribution analysis results under continuous working conditions; calculating the overall thermal resistance value of the module using temperature monitoring point data based on the thermal distribution analysis results; obtaining a heat sink optimization configuration scheme through the overall thermal resistance value; simulating the heat flow path under load conditions based on the heat sink optimization configuration scheme, and determining the feasibility evaluation index for power improvement; extracting the selection basis for heat dissipation materials from the feasibility evaluation index; judging the evaluation result based on the selection basis for heat dissipation materials, and recording the feasibility data for power improvement for subsequent heat dissipation system architecture integration.

8. The heat dissipation optimization method for an ultraviolet light-emitting diode module as described in claim 1, characterized in that, Step S107 further includes: obtaining the feasibility assessment result of the power increase; comparing the efficiency with a preset threshold value by quickly exporting the efficiency to determine the efficiency threshold judgment; if the efficiency threshold judgment is lower than the preset threshold, integrating the heat sink interface and thermal path matching design, and obtaining an integrated design scheme by aligning the interface size and matching the path heat conduction; performing thermal simulation verification of the interface matching path for the integrated design scheme, and extracting verification data from the heat flow distribution simulation; determining the material compatibility check result based on the verification data; integrating the module heat dissipation system elements based on the material compatibility check result to obtain a system architecture integration scheme; adjusting the complete architecture parameters based on the system architecture integration scheme, extracting the adjustment values, and obtaining the complete module heat dissipation system design.

9. The heat dissipation optimization method for an ultraviolet light-emitting diode module as described in claim 1, characterized in that, Step S108 further includes: obtaining the complete module heat dissipation system design, extracting heat transfer paths and component material parameters; setting a reliability test simulation environment using the heat transfer paths and component material parameters, and determining the thermal stress distribution under excessively high temperature conditions; performing material aging trend simulation based on the thermal stress distribution, and obtaining the rate of change of the aging mechanism in a high-temperature environment; constructing an aging prediction model based on the rate of change, and calculating the aging acceleration effect using a temperature acceleration factor; determining the performance degradation curve of the module during long-term operation based on the aging acceleration effect; evaluating the module durability based on the performance degradation curve, and obtaining the long-term performance prediction for subsequent optimization effect verification.

10. The heat dissipation optimization method for an ultraviolet light-emitting diode module as described in claim 1, characterized in that, Step S109 further includes: acquiring initial thermal distribution parameters from the module through performance data acquisition, calculating the temperature gradient using thermal distribution simulation, and determining non-uniform distribution characteristics; obtaining thermal stress analysis results based on the non-uniform distribution characteristics; adjusting path parameters using thermal path optimization based on the thermal stress analysis results, and obtaining material fatigue prediction values; establishing a reliability model using the material fatigue prediction values, and outputting a performance degradation curve; judging the optimization effect based on the performance degradation curve and the long-term performance prediction, and obtaining elimination effect verification indicators; identifying bottleneck locations based on the elimination effect verification indicators, and if the indicators exceed a preset threshold, reconstructing the heat flow path to determine the degree of resolution of the heat dissipation bottleneck.

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