Eml optical chip packaging structure with soa and packaging method thereof

Abstract

The application relates to an EML optical chip packaging structure with an SOA and a packaging method thereof, which comprises a base 1 and a substrate 2 vertically arranged in the middle of the base 1 and penetrating through the base 1; an EML optical chip with an SOA 3 is arranged on the front surface of the substrate 2, the EML optical chip with an SOA 3 is flip-chip soldered on the corresponding electrode of the substrate 2, and the EML optical chip with an SOA 3 is electrically connected with other components through the microstrip line 200 deposited on the substrate 2; a TEC 4 is attached to the back surface of the substrate 2, and a heat dissipation block 5 is attached to the other surface of the TEC 4; a pipe cap 6 is arranged on the base 1, the pipe cap 6 and the base 1 form a sealed cavity containing the heat dissipation block 5, the TEC 4, the EML optical chip with an SOA 3 and part of the substrate 2. The application can make the TEC attachment closer to the active region of the optical chip, effectively cool the laser chip, make the TEC play a better role and reduce the power consumption.

Description

Technical Field

[0001] This invention relates to the field of optical communication technology, and in particular to an EML optical chip packaging structure with SOA and its packaging method. Background Technology

[0002] Electro-absorption modulated laser (EML) chips are integrated circuit chips widely used in electronic devices. EML chips use electro-absorption modulation technology to modulate light, enabling high-speed and efficient optical signal transmission. Semiconductor optical amplifiers (SOA) are simple in structure and small in size, fully utilizing existing semiconductor laser technology. They have mature manufacturing processes, low cost, long lifespan, low power consumption, and are easy to integrate with other optical devices.

[0003] EML optical chips with integrated SOA have excellent features such as high modulation capability, low driving voltage, long transmission distance and high signal quality, and are widely used in the field of optical communication. EMLs packaged in the form of transistor outline (TO) are used on a large scale in access networks due to their mature technology and low cost.

[0004] In current designs, the EML is used in conjunction with a Thermo Electric Cooler (TEC). The TEC has dynamic temperature control capabilities, effectively solving the problem of wavelength drift caused by high temperatures during laser chip operation. It can also transfer heat from the active area of ​​the optical chip, reducing reliability risks. The mainstream TO packaging structure currently involves mounting the TEC flat on a base, with the heat sink vertically mounted on the top surface of the TEC. The front surface of the heat sink is fitted with a COC substrate (COC stands for Chip Carrier, meaning chip mounted on a carrier; COC technology is a packaging technology that directly mounts the chip onto a carrier, also called a packaging substrate or packaging plate). Filter capacitors and thermistors are mounted next to the transition substrate on the front surface of the heat sink as needed. Components inside the TO are electrically connected via gold wires, while electrical connections between the outside and inside of the TO are achieved through metal pins penetrating the TO base. The entire optoelectronic system is enclosed by a metal cap with a lens, creating an hermetically sealed environment.

[0005] The existing design described above has the following shortcomings:

[0006] 1. EML chips with SOA generate a lot of heat when they are working, and this heat will be concentrated near the active area. The active area is located on the upper surface of the chip. In the current design, the active area is far away from the TEC, the heat conduction path is long, the power consumption required for temperature control is very high, and the temperature of the active area will be higher than the temperature control value when it is working, which will cause chip reliability risks.

[0007] 2. EML chips with SOA are based on indium phosphide (InP), which has lower thermal conductivity than the substrate. When the chip is mounted upright on a COC substrate, heat is difficult to conduct quickly from the chip to the substrate. Therefore, there are limitations to the upright chip at high power output, because increasing the output power will result in more accumulated heat, insufficient heat dissipation, and ultimately affect the chip's lifespan.

[0008] 3. The Electro Absorption (EA) terminal uses gold wire for electrical connection. The thinness of the gold wire results in a large inductance, and high-speed signals will be lost when passing through the gold wire, affecting the transmission efficiency.

[0009] 4. Because the electrical system involves many components, the number of gold wires required is 20-30, making the gold wire bonding process difficult and resulting in a low yield.

[0010] Therefore, overcoming the shortcomings of the existing technology and solving at least one of the above-mentioned technical problems is a difficult problem that urgently needs to be solved in this technical field. Summary of the Invention

[0011] To address the aforementioned technical issues, this invention provides an EML optical chip packaging structure with SOA and its packaging method. This allows the TEC (Digital Transistor Array) to be mounted closer to the active region of the optical chip, effectively cooling the laser chip and enabling the TEC to function better while reducing power consumption. Furthermore, all electrical connections in this invention are achieved using microstrip lines deposited on the substrate. Compared to the traditional method using gold wires, microstrip line design is more flexible and can improve signal transmission quality and efficiency, meeting the requirements of future high-speed networks. Moreover, the TO (Top-of-Package) packaging structure of this invention greatly simplifies the manufacturing process, eliminating the gold wire bonding process and requiring only surface mount technology (SMT) throughout.

[0012] This invention is implemented as follows:

[0013] In a first aspect, the present invention provides an EML optical chip packaging structure with SOA, including a base 1 and a substrate 2 vertically disposed in the middle of the base 1 and penetrating the base 1; an EML optical chip 3 with SOA is disposed on the front side of the substrate 2, the EML optical chip 3 with SOA is flip-chip bonded to the corresponding electrode of the substrate 2, and the EML optical chip 3 with SOA is electrically connected to other components through a microstrip line 200 deposited on the substrate 2; a TEC 4 is mounted on the back side of the substrate 2, and a heat sink 5 is mounted on the other side of the TEC 4; a cap 6 is disposed on the base 1, and the cap 6 and the base 1 form a sealed cavity that accommodates the heat sink 5, the TEC 4, the EML optical chip 3 with SOA, and part of the substrate 2.

[0014] In some embodiments, the front side of the substrate 2 is further provided with a thermistor 7, a first filter capacitor 8, and a second filter capacitor 9, and the thermistor 7, the first filter capacitor 8, and the second filter capacitor 9 are cured at corresponding positions on the substrate 2 by heating with silver paste.

[0015] In some embodiments, the microstrip line 200 forms a plurality of pins at the bottom end of the substrate 2; the pins include SOA electrode pins 201, the SOA electrode pins 201 are connected to the first filter capacitor 8 and the SOA electrode 301 of the EML optical chip 3 with SOA through the microstrip line 200, so that the first filter capacitor 8 and the SOA of the EML optical chip 3 with SOA form a parallel circuit.

[0016] In some embodiments, the pin includes a DFB electrode pin 202, which is connected to the second filter capacitor 9 and the DFB electrode 302 of the EML optical chip 3 with SOA via the microstrip line 200, so that the second filter capacitor 9 and the DFB of the EML optical chip 3 with SOA form a parallel circuit.

[0017] In some embodiments, the pin includes an EA electrode pin 203, which is connected to the EA electrode 303 of the SOA-equipped EML optical chip 3 via the microstrip line 200 to supply a modulation current signal to the EA of the SOA-equipped EML optical chip 3; a thin film resistor 204 is also deposited on the front side of the substrate 2, and the thin film resistor 204 is connected in parallel with the EA of the SOA-equipped EML optical chip 3.

[0018] In some embodiments, the pin includes a thermistor electrode pin 205, which is connected to the thermistor 7 via the microstrip line 200; a gold layer is deposited on both sides of the thermistor 7 to achieve electrical connection with the thermistor electrode pin 205 and the GND electrode of the EML optical chip 3 with SOA.

[0019] In some embodiments, the pin includes a first GND electrode pin 206 and a second GND electrode pin 207, which are distributed in parallel on both sides of the EA electrode pin 203.

[0020] In some embodiments, the pins include a first TEC electrode pin 208 and a second TEC electrode pin 209, and a through hole is provided at the electrode of the TEC 4 to add power to the TEC 4 through the first TEC electrode pin 208 and the second TEC electrode pin 209.

[0021] In some embodiments, the substrate 2 is fixed in the middle of the base 1 by a glass insulator, the EML optical chip 3 with SOA is connected to the corresponding electrode of the substrate 2 by a solder block, the cold side of the TEC 4 is bonded to the back of the substrate 2 by thermally conductive silver paste, the hot side of the TEC 4 is bonded to the side wall of the heat sink 5 by thermally conductive silver paste, the bottom of the heat sink 5 is bonded to the base 1 by thermally conductive silver paste, and the cap 6 is welded to the base 1 by resistance welding in a nitrogen atmosphere.

[0022] In a second aspect, the present invention provides a packaging method for an EML optical chip packaging structure with SOA, applied to the EML optical chip packaging structure with SOA described in the first aspect, the method comprising:

[0023] The EML optical chip 3 with SOA is soldered to the corresponding position on the substrate 2 using gold-tin solder pads. The soldering temperature is 310-350℃, the soldering time is 5-10 seconds, and a preset pressure is applied during soldering.

[0024] The second filter capacitor 9 connected in parallel with DFB, the first filter capacitor 8 connected in parallel with SOA, and the thermistor 7 are mounted on the corresponding positions of the substrate 2 using thermally conductive silver paste. After mounting, they are baked in an oven at a preset temperature for a preset time to cure.

[0025] The TEC 4 cold side is bonded to the back of the substrate 2 using thermally conductive silver paste. After mounting, it is baked in an oven at a preset temperature for a preset time to cure.

[0026] Heat sink 5 is attached to the hot surface of TEC 4 using thermally conductive silver paste. At the same time, the bottom surface of heat sink 5 is attached to base 1 using thermally conductive silver paste. After attachment, it is baked in an oven at a preset temperature for a preset time to cure.

[0027] Resistance welding of a lens-equipped pipe cap 6 in a nitrogen protective atmosphere.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] 1. In the packaging method of the structure provided in the embodiments of the present invention, since the TEC cold side is directly attached to the substrate, and the laser chip (i.e., the EML optical chip with SOA) is set on the other side of the substrate, the TEC cold side is closer to the active area of ​​the laser chip. When the chip is working, the heat generated in the active area can be better conducted out, effectively reducing the temperature of the active area, extending the life of the laser chip, improving the temperature control efficiency of the TEC, and reducing power consumption.

[0030] 2. In this embodiment of the invention, microstrip lines are used instead of gold wires for all electrical connections, thereby reducing parasitic inductance and improving the conduction of high-frequency signals. Furthermore, the entire process uses surface mount technology (SMT) without the need for wire bonding, simplifying the process flow.

[0031] 3. Compared to gold wire, microstrip lines have higher bandwidth and more flexible design, meeting a variety of mounting requirements.

[0032] 4. A substrate that runs through the base is used, and pins are formed at the ends of the substrate through microstrip lines to realize internal and external electrical connections, replacing the traditional method of using metal pins to realize internal and external electrical connections. This design is more convenient for production and reduces the scrapping of TO due to deformation of metal pins. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a front view of an EML optical chip packaging structure with SOA provided in an embodiment of the present invention when it is not capped.

[0035] Figure 2 This is a side view of an EML optical chip packaging structure with SOA provided in an embodiment of the present invention when it is not capped.

[0036] Figure 3This is a top view of an EML optical chip packaging structure with SOA provided in an embodiment of the present invention when it is not capped.

[0037] Figure 4 This is a front view of an EML optical chip packaging structure with SOA after being capped, provided in an embodiment of the present invention.

[0038] Figure 5 This is a perspective view of an EML optical chip packaging structure with SOA after being capped, provided in an embodiment of the present invention.

[0039] Figure 6 This is a schematic diagram of the front side of the substrate provided in an embodiment of the present invention;

[0040] Figure 7 This is a schematic diagram of the back side of the substrate provided in an embodiment of the present invention;

[0041] Figure 8 This is a schematic diagram of an EML optical chip with SOA provided in an embodiment of the present invention;

[0042] Figure 9 A flowchart illustrating a packaging method for an EML optical chip packaging structure with SOA provided in an embodiment of the present invention;

[0043] Figure 10 Assembly diagram for the existing solution;

[0044] Figure 11 A schematic diagram of the heat conduction path after assembly of the existing solution;

[0045] Figure 12 This is a schematic diagram of the heat conduction path after assembly, as provided in an embodiment of the present invention. Detailed Implementation

[0046] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as openly inclusive, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples; that is, although they may be incorporated into embodiments or examples using the above terms for reasons such as order and position, it does not limit them to be incorporated in combination by a single embodiment or example.

[0047] In the description of this invention, the terms "inner", "outer", "longitudinal", "lateral", "upper", "lower", "left", "right", "top", "bottom", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and do not require that this invention must be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0048] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention. These all fall within the scope of protection of the present invention.

[0049] It should be noted that, unless otherwise defined, the various features in the embodiments of the present invention can be combined with each other, all of which are within the protection scope of this application. Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology and location descriptions used in this specification are for the purpose of describing specific embodiments only and are not intended to limit the invention.

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0051] Example 1

[0052] refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 As shown, Embodiment 1 of the present invention provides an EML optical chip packaging structure with SOA, including a base 1 and a substrate 2 vertically disposed in the middle of the base 1 and penetrating the base 1. An EML optical chip 3 with SOA is disposed on the front side of the substrate 2. The EML optical chip 3 with SOA is flip-chip bonded to the corresponding electrode of the substrate 2, and the EML optical chip 3 with SOA is electrically connected to other components through a microstrip line 200 deposited on the substrate 2. A TEC 4 is attached to the back side of the substrate 2, and a heat sink 5 is attached to the other side of the TEC 4. A cap 6 is disposed on the base 1, and the cap 6 and the base 1 form a sealed cavity that accommodates the heat sink 5, the TEC 4, the EML optical chip 3 with SOA, and part of the substrate 2.

[0053] Through the above-described configuration, this invention allows the TEC (Diode Transformer Acrylic Array) to be mounted closer to the active region of the optical chip, effectively cooling the laser chip and enabling the TEC to function better while reducing power consumption. Furthermore, all electrical connections in this invention are achieved using microstrip lines deposited on the substrate. Compared to the traditional method using gold wires, microstrip line design is more flexible and can improve signal transmission quality and efficiency, meeting the requirements of future high-speed networks. Moreover, the TO (Top-of-Package) packaging structure of this invention greatly simplifies the manufacturing process, eliminating the gold wire bonding process and requiring only surface mount technology (SMT) throughout.

[0054] In some embodiments, the base 1 is a metal TO base; the substrate 2 is a ceramic substrate, and the material of the substrate 2 is selected from at least one or more of AlN ceramic, Al2O3 ceramic, diamond, and SiC; the cap 6 is a metal cap with a lens; the EML optical chip 3 with SOA (i.e., laser chip) is a flip-chip, and both the positive and negative electrodes are designed on the P-side of the chip.

[0055] In some embodiments, the substrate 2 is fixed in the middle of the base 1 by a glass insulator, the EML optical chip 3 with SOA is connected to the corresponding electrode of the substrate 2 by a solder block, the cold side of the TEC 4 is bonded to the back of the substrate 2 by thermally conductive silver paste, the hot side of the TEC 4 is bonded to the side wall of the heat sink 5 by thermally conductive silver paste, the bottom of the heat sink 5 is bonded to the base 1 by thermally conductive silver paste, and the cap 6 is welded to the base 1 by resistance welding in a nitrogen atmosphere.

[0056] In some embodiments, the front side of the substrate 2 is further provided with a thermistor 7, a first filter capacitor 8, and a second filter capacitor 9, and the thermistor 7, the first filter capacitor 8, and the second filter capacitor 9 are cured at corresponding positions on the substrate 2 by heating with silver paste.

[0057] In some embodiments, the solder block uses a gold-tin solder block, the thermally conductive silver paste is composed of silver-epoxy resin-curing agent components, and good thermal conductivity is a key requirement; the microstrip line 200 is formed by depositing three layers of titanium, platinum and gold metals with thicknesses of 0.1 / 0.1 / 0.4 micrometers respectively.

[0058] refer to Figure 6 and Figure 7As shown, in some embodiments, the microstrip line 200 forms a plurality of pins at the bottom end of the substrate 2; the pins may include: SOA electrode pin 201, DFB electrode pin 202, EA electrode pin 203, thermistor electrode pin 205, first GND electrode pin 206, second GND electrode pin 207, first TEC electrode pin 208, and second TEC electrode pin 209. DFB stands for Distributed Feedback Laser. It should be noted that in this embodiment, SOA electrode pin 201, DFB electrode pin 202, EA electrode pin 203, thermistor electrode pin 205, first TEC electrode pin 208, and second TEC electrode pin 209 are negative pins.

[0059] refer to Figure 8 As shown, in some embodiments, the EML optical chip 3 with SOA is provided with an SOA electrode 301, a DFB electrode 302, an EA electrode 303, and a GND electrode. The GND electrode may include a first GND electrode 304 and a second GND electrode 305. It should be noted that in this embodiment, the SOA electrode 301, DFB electrode 302, and EA electrode 303 are positive electrodes. The SOA electrode 301 and DFB electrode 302 are disposed on one side, and the first GND electrode 304, second GND electrode 305, and EA electrode 303 are disposed on the other side, with the EA electrode 303 positioned between the first GND electrode 304 and the second GND electrode 305.

[0060] In some embodiments, the SOA electrode pin 201 is connected to the first filter capacitor 8 and the SOA electrode 301 of the EML optical chip 3 with SOA via the microstrip line 200, so that the first filter capacitor 8 and the SOA of the EML optical chip 3 with SOA form a parallel circuit; thereby reducing the interference of high-frequency noise on the SOA end and realizing stable optical amplification function.

[0061] In some embodiments, the DFB electrode pin 202 is connected to the second filter capacitor 9 and the DFB electrode 302 of the EML optical chip 3 with SOA via the microstrip line 200, so that the second filter capacitor 9 and the DFB of the EML optical chip 3 with SOA form a parallel circuit; thereby reducing the interference of high-frequency noise on the DFB terminal.

[0062] In some embodiments, the EA electrode pin 203 is connected to the EA electrode 303 of the SOA-equipped EML optical chip 3 via the microstrip line 200 to supply a modulation current signal to the EA of the SOA-equipped EML optical chip 3; a thin film resistor 204 is also deposited on the front side of the substrate 2, and the thin film resistor 204 is connected in parallel with the EA of the SOA-equipped EML optical chip 3; thereby adjusting the impedance and reducing the loss caused by impedance mismatch during high-frequency signal transmission.

[0063] In some embodiments, the thermistor electrode pin 205 is connected to the thermistor 7 via the microstrip line 200; a gold layer is deposited on both sides of the thermistor 7 to achieve electrical connection with the thermistor electrode pin 205 and the GND electrode of the EML optical chip 3 with SOA.

[0064] In some embodiments, the first GND electrode pin 206 and the second GND electrode pin 207 are distributed in parallel on both sides of the EA electrode pin 203. This design can reduce parasitic capacitance, improve signal transmission quality, and the three microstrip lines are arranged along an arc at the bend to avoid right-angle bends, thereby reducing the loss of high-frequency signals in the transmission path.

[0065] In some embodiments, the pins include a first TEC electrode pin 208 and a second TEC electrode pin 209. A through hole is provided at the electrode of the TEC 4. In this design, the TEC 4 can be charged through the first TEC electrode pin 208 and the second TEC electrode pin 209 on the back side of the substrate 2.

[0066] With the above configuration, in this embodiment of the invention, a substrate 2 with deposited microstrip lines 200 and thin-film resistors 204 penetrates through a base 1. An EML optical chip 3 with SOA, a thermistor 7, a first filter capacitor 8, and a second filter capacitor 9 are all mounted on the front side of the substrate 2. The back side of the substrate 2 is mounted to the cold side of a TEC 4, and a heat sink 5 is mounted on the hot side of the TEC 4 to dissipate heat from the base 1. Finally, a lens-capped tube 6 seals all structures within the cavity. The core of this embodiment is to flip-chip bond the EML optical chip 3 with SOA to the corresponding electrode on the substrate 2, and to achieve electrical connection between the laser chip and other components through the microstrip lines 200 deposited on the substrate 2. The substrate 2 penetrates through the base 1, achieving electrical connection between the inside and outside of the TO. The TEC 4 is vertically mounted on the back side of the substrate 1 to achieve better heat dissipation.

[0067] In summary, the embodiments of the present invention provide an EML optical chip packaging structure with SOA, which has the following advantages:

[0068] 1. In the packaging method of the structure provided in the embodiments of the present invention, since the TEC cold side is directly attached to the substrate, and the laser chip (i.e., the EML optical chip with SOA) is set on the other side of the substrate, the TEC cold side is closer to the active area of ​​the laser chip. When the chip is working, the heat generated in the active area can be better conducted out, effectively reducing the temperature of the active area, extending the life of the laser chip, improving the temperature control efficiency of the TEC, and reducing power consumption.

[0069] 2. In this embodiment of the invention, microstrip lines are used instead of gold wires for all electrical connections, thereby reducing parasitic inductance and improving the conduction of high-frequency signals. Furthermore, the entire process uses surface mount technology (SMT) without the need for wire bonding, simplifying the process flow.

[0070] 3. Compared to gold wire, microstrip lines have higher bandwidth and more flexible design, meeting a variety of mounting requirements.

[0071] 4. A substrate that runs through the base is used, and pins are formed at the ends of the substrate through microstrip lines to realize internal and external electrical connections, replacing the traditional method of using metal pins to realize internal and external electrical connections. This design is more convenient for production and reduces the scrapping of TO due to deformation of metal pins.

[0072] Example 2

[0073] refer to Figure 9 As shown, this embodiment provides a packaging method for an EML optical chip packaging structure with SOA, applied to the EML optical chip packaging structure with SOA described in Embodiment 1. The method includes the following steps.

[0074] Step 100: The EML optical chip 3 with SOA is soldered to the corresponding position on the substrate 2 using gold-solder pads. The soldering temperature is 310-350℃, the soldering time is 5-10 seconds, and a preset pressure is applied during soldering. For example, a pressure of 200g is applied during soldering.

[0075] Step 200: The second filter capacitor 9 connected in parallel with the DFB, the first filter capacitor 8 connected in parallel with the SOA, and the thermistor 7 are mounted on the corresponding positions of the substrate 2 using thermally conductive silver paste. After mounting, they are baked in an oven at a preset temperature for a preset time to cure. For example, after mounting, they are baked in an oven at 180°C for 90 minutes to cure. In addition, the paste is applied to both sides of the component electrodes to ensure that the silver paste on the bottom of the components does not stick.

[0076] Step 300: Attach the TEC 4 cold side to the back of substrate 2 using thermally conductive silver paste. After mounting, bake in an oven at a preset temperature for a preset time to cure. For example, cure in an oven at 180°C for 90 minutes after mounting.

[0077] Step 400: Mount the heat sink 5 onto the hot surface of the TEC 4 using thermally conductive silver paste. Simultaneously, attach the bottom surface of the heat sink 5 to the base 1 using thermally conductive silver paste. After mounting, bake in an oven at a preset temperature for a preset time to cure. For example, with a mounting pressure of 200g, cure the silver paste in an oven at 180℃ for 90 minutes after mounting.

[0078] Step 500: Resistance weld the lens-equipped pipe cap 6 in a nitrogen protective atmosphere. Refer to the image after capping. Figure 4 and Figure 5 As shown.

[0079] After the above steps, the TO package of the EML optical chip 3 with SOA is completed. By applying a suitable current to the pins below the TO base, the modulated and amplified laser can be emitted.

[0080] Example 3

[0081] The advantages of the present invention will be illustrated below by comparing the heat conduction paths of existing solutions with those of the embodiments of the present invention.

[0082] refer to Figure 10 As shown, in the existing TO package structure, the TEC 01 is flatly mounted on the base 02, and the heat sink 03 is vertically mounted on the upper surface of the TEC 01. The COC substrate 05 with the optical chip 04 is mounted on the front surface of the heat sink 03. Also on the front surface of the heat sink 03, the filter capacitor 06 and the thermistor 07 are mounted next to the transition substrate as needed. The internal components of the TO are electrically connected by gold wires, and the electrical connection between the outside and inside of the TO is completed by metal pins that pass through the TO base.

[0083] refer to Figure 11 As shown, Figure 11 The middle arrow points to the heat conduction path in the existing design, which needs to be transferred from the optical chip 04 to the COC substrate 05, then to the heat sink 03, and finally to the TEC 01. In this process, the route is curved and long, which is not conducive to heat dissipation.

[0084] refer to Figure 12 As shown, Figure 12 The middle arrow points to the heat conduction path in this embodiment of the invention, where heat is directly transferred from the EML optical chip 3 with SOA along the substrate 2 to the TEC 4; in this process, the route is straight and short, resulting in better heat dissipation.

[0085] In summary, this invention provides a packaging method for an EML optical chip package structure with SOA, allowing TEC mounting closer to the active area of ​​the optical chip. This effectively cools the laser chip, allowing the TEC to function better while reducing power consumption. Furthermore, all electrical connections in this invention are achieved using microstrip lines deposited on the substrate. Compared to the traditional method using gold wires, microstrip line design is more flexible and can improve signal transmission quality and efficiency, meeting the requirements of future high-speed networks. Moreover, the TO package structure in this invention greatly simplifies the process flow, eliminating the gold wire bonding process and requiring only surface mount technology (SMT) throughout.

[0086] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; under the concept of the present invention, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the present invention as described above. For the sake of brevity, they are not provided in detail; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. An EML optical chip packaging structure with SOA, characterized in that, The system includes a base (1) and a substrate (2) vertically disposed in the middle of the base (1) and penetrating the base (1); an EML optical chip (3) with SOA is disposed on the front side of the substrate (2), the EML optical chip (3) with SOA is flip-chip soldered to the corresponding electrode of the substrate (2), and the EML optical chip (3) with SOA is electrically connected to other components through a microstrip line (200) deposited on the substrate (2); a TEC (4) is attached to the back side of the substrate (2), and a heat sink (5) is attached to the other side of the TEC (4); a cap (6) is disposed on the base (1), and the cap (6) and the base (1) form a sealed cavity that accommodates the heat sink (5), the TEC (4), the EML optical chip (3) with SOA and part of the substrate (2).

2. The EML optical chip packaging structure with SOA according to claim 1, characterized in that, The front side of the substrate (2) is also provided with a thermistor (7), a first filter capacitor (8) and a second filter capacitor (9), and the thermistor (7), the first filter capacitor (8) and the second filter capacitor (9) are cured on the corresponding positions of the substrate (2) by heating with silver paste.

3. The EML optical chip packaging structure with SOA according to claim 2, characterized in that, The microstrip line (200) forms a plurality of pins at the bottom end of the substrate (2); the pins include SOA electrode pins (201), the SOA electrode pins (201) are connected to the first filter capacitor (8) and the SOA electrode (301) of the EML optical chip (3) with SOA through the microstrip line (200), so that the first filter capacitor (8) and the SOA of the EML optical chip (3) with SOA form a parallel circuit.

4. The EML optical chip packaging structure with SOA according to claim 3, characterized in that, The pin includes a DFB electrode pin (202), which is connected to the second filter capacitor (9) and the DFB electrode (302) of the EML optical chip (3) with SOA via the microstrip line (200), so that the second filter capacitor (9) and the DFB of the EML optical chip (3) with SOA form a parallel circuit.

5. The EML optical chip packaging structure with SOA according to claim 3, characterized in that, The pins include an EA electrode pin (203), which is connected to the EA electrode (303) of the SOA-equipped EML optical chip (3) via the microstrip line (200) to supply a modulation current signal to the EA of the SOA-equipped EML optical chip (3); a thin film resistor (204) is also deposited on the front side of the substrate (2), and the thin film resistor (204) is connected in parallel with the EA of the SOA-equipped EML optical chip (3).

6. The EML optical chip packaging structure with SOA according to claim 3, characterized in that, The pins include a thermistor electrode pin (205), which is connected to the thermistor (7) via the microstrip line (200); gold layers are deposited on both sides of the thermistor (7) to achieve electrical connection with the thermistor electrode pin (205) and the GND electrode of the EML optical chip (3) with SOA.

7. The EML optical chip packaging structure with SOA according to claim 5, characterized in that, The pins include a first GND electrode pin (206) and a second GND electrode pin (207), which are distributed in parallel on both sides of the EA electrode pin (203).

8. The EML optical chip packaging structure with SOA according to claim 3, characterized in that, The pins include a first TEC electrode pin (208) and a second TEC electrode pin (209). The electrodes of the TEC (4) are provided with through holes to add points to the TEC (4) through the first TEC electrode pin (208) and the second TEC electrode pin (209).

9. The EML optical chip packaging structure with SOA according to any one of claims 1-8, characterized in that, The substrate (2) is fixed in the middle of the base (1) by a glass insulator. The EML optical chip (3) with SOA is connected to the corresponding electrode of the substrate (2) by a solder block. The cold side of the TEC (4) is bonded to the back of the substrate (2) by thermally conductive silver paste. The hot side of the TEC (4) is bonded to the side wall of the heat sink (5) by thermally conductive silver paste. The bottom of the heat sink (5) is bonded to the base (1) by thermally conductive silver paste. The cap (6) is welded to the base (1) by resistance welding in a nitrogen atmosphere.

10. A packaging method for an EML optical chip package structure with SOA, applied to the EML optical chip package structure with SOA as described in any one of claims 1-9, characterized in that, include: The EML optical chip (3) with SOA is soldered to the corresponding position on the substrate (2) through gold solder pads. The soldering temperature is 310-350℃ and the soldering time is 5-10 seconds. A preset pressure is applied during soldering. The second filter capacitor (9) connected in parallel with DFB, the first filter capacitor (8) connected in parallel with SOA, and the thermistor (7) are mounted on the corresponding positions of the substrate (2) using thermally conductive silver paste. After mounting, they are baked in an oven at a preset temperature for a preset time to cure. The cold side of TEC (4) is bonded to the back side of the substrate (2) with thermally conductive silver paste. After mounting, it is baked in an oven at a preset temperature for a preset time to cure. Heat sink (5) is attached to the hot surface of TEC (4) with thermally conductive silver paste. At the same time, the bottom surface of heat sink (5) is attached to the base (1) with thermally conductive silver paste. After attachment, it is baked in an oven at a preset temperature for a preset time to cure. Resistance welding of a lens-equipped cap (6) in a nitrogen protective atmosphere.

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