A soft and hard switching control method, a direct current conversion circuit and a direct current converter

Abstract

The present application relates to the technical field of power electronic conversion, and particularly relates to a soft and hard switching control method, a direct current conversion circuit and a direct current converter. In the hard switching mode, the primary side bridge arm group is only controlled by the first driving signal and the second driving signal with a dead time. When it is needed to switch to the soft switching mode to reduce the switching loss and electromagnetic interference under heavy load, the system responds to the high level instruction of the preset control signal, and the first auxiliary signal and the second auxiliary signal originally used for the secondary side synchronous rectification are connected to the control end of the primary side first lower bridge arm and the primary side second lower bridge arm respectively, so that the primary side lower bridge arm can be triggered to be turned on by the auxiliary signal in the dead time after the upper bridge arm is turned off. At this time, the resonant network is formed by the resonant inductance or the transformer leakage inductance in the circuit and the parasitic capacitance of the switch tube, the conduction of the lower bridge arm provides a path for the resonant current, so that the voltage across the upper bridge arm switch tube is pulled down, and the zero voltage turn-on condition is achieved.

Description

Technical Field

[0001] This invention relates to the field of power electronic conversion technology, and in particular to a soft and hard switching control method, a DC-DC conversion circuit, and a DC-DC converter. Background Technology

[0002] High-power DC / DC converters are widely used in industries such as communications, aerospace, and shipbuilding, and their performance directly affects the stability and reliability of related systems. Traditional switching power supply solutions are typically designed to operate in a single mode: one approach uses hard-switching technology across the entire load range, which has a relatively simple structure but generates significant switching losses and electromagnetic interference during MOSFET switching, especially under heavy load conditions, where efficiency limitations become prominent. Another approach uses soft-switching technologies such as zero-voltage switching, introducing resonant networks to reduce MOSFET switching losses. However, this increases system complexity and cost, and under light load conditions, the resonant network may induce additional circulating current losses, leading to a decrease in energy efficiency.

[0003] In existing technologies, these solutions all lack a flexible, user- or system-configurable mode-switching mechanism, making it difficult for DC-DC converters to adapt to wide load ranges or diverse application scenarios. They also cannot dynamically optimize operating states based on real-time efficiency, cost, or electromagnetic interference requirements. Specifically, traditional DC-DC converters are designed with a single hard-switching or soft-switching mode, and cannot be switched or reconfigured after leaving the factory according to actual application scenarios, resulting in poor flexibility. Fixed hard-switching solutions suffer from high MOSFET switching losses and high electromagnetic interference under heavy loads, while fixed soft-switching solutions exhibit significant MOSFET circulating current losses under light loads. Furthermore, the system complexity and cost remain consistently high, limiting the adaptability and overall performance optimization of DC-DC power supply equipment under varying operating conditions. Summary of the Invention

[0004] The present invention aims to provide a soft-hard switching control method, a DC-DC converter circuit, and a DC-DC converter, so as to provide a solution that can control the DC-DC converter circuit to switch between hard-switching mode and soft-switching mode, and solve the technical problem that the current DC-DC power supply circuit cannot switch between hard-switching mode and soft-switching mode according to the actual application scenario, resulting in poor flexibility.

[0005] To achieve the above objectives, the first aspect of the present invention provides a soft-hard switching control method applicable to a DC-DC converter circuit. The DC-DC converter circuit includes a primary-side full-bridge sub-circuit, a transformer module, and a secondary-side rectifier sub-circuit. The primary-side full-bridge sub-circuit includes a first primary upper bridge arm, a second primary upper bridge arm, a first primary lower bridge arm, and a second primary lower bridge arm, all of which are activated when a high-level signal is received. The first primary upper bridge arm and the second primary lower bridge arm form a primary-side first bridge arm group, and the second primary upper bridge arm and the first primary lower bridge arm form a primary-side second bridge arm group. The secondary-side rectifier sub-circuit includes a secondary-side first bridge arm group and a secondary-side second bridge arm group, both of which are activated when a high-level signal is received. The method includes the following steps: A first drive signal and a second drive signal are generated. The first drive signal and the second drive signal are complementary, and there is a dead time between the first drive signal and the second drive signal. The first driving signal controls the first primary side bridge arm group, and the second driving signal controls the second primary side bridge arm group, so that the first primary side bridge arm group and the second primary side bridge arm group are alternately turned on, thereby enabling the first primary side bridge arm group and the second primary side bridge arm group to perform AC conversion on the input DC power in a hard-switching working state and output AC power to the transformer module. The secondary side first bridge arm group is controlled to turn on or off in accordance with the primary side second bridge arm group by a preset first auxiliary signal, and the secondary side second bridge arm group is controlled to turn on or off in accordance with the primary side first bridge arm group by a preset second auxiliary signal, thereby enabling the secondary side first bridge arm group and the secondary side second bridge arm group to synchronously rectify the AC power input to the transformer module in accordance with the primary side second bridge arm group and the primary side first bridge arm group; In response to a preset control signal, when the control signal switches to a high level: The second auxiliary signal is connected to the control terminal of the second lower bridge arm on the primary side, and the first auxiliary signal is connected to the control terminal of the first lower bridge arm on the primary side, so that the second lower bridge arm and the first lower bridge arm on the primary side are turned on during the dead time, thereby causing the first bridge arm group and the second bridge arm group to form a resonant network during the dead time, thereby causing the first bridge arm group and the second bridge arm group on the primary side to switch to soft switching operation state to perform AC conversion on the input DC power.

[0006] The aforementioned soft-hard switching control method achieves seamless switching from hard switching to soft switching operating mode by reusing the auxiliary signal of the secondary rectifier circuit to change the driving logic of the lower bridge arm of the primary full-bridge circuit.

[0007] In hard-switching mode, the primary side bridge arm group is only controlled by complementary first and second drive signals with dead time, and operates in a conventional PWM manner. The circuit control is simple and there is no additional resonant circulating current loss under light load.

[0008] When it is necessary to switch to soft-switching mode to reduce switching losses and electromagnetic interference under heavy load, the system responds to the high-level command of the preset control signal and connects the first auxiliary signal and the second auxiliary signal, which were originally used for secondary-side synchronous rectification, to the control terminals of the primary-side first lower bridge arm and the primary-side second lower bridge arm, respectively.

[0009] Because the pulse width of the auxiliary signal is configured to completely cover the conduction time of the corresponding primary-side bridge arm group, the lower primary-side bridge arm can be triggered to conduct by the auxiliary signal within the corresponding dead time. At this point, a resonant network is formed using the resonant inductance or transformer leakage inductance in the circuit and the parasitic capacitance of the switching transistor. The conduction of the lower bridge arm provides a path for the resonant current, thereby pulling down the voltage across the upper bridge arm switching transistor, achieving zero-voltage turn-on (ZVS). Ultimately, without adding additional complex drive circuitry, the advantages of hard switching under light loads and the high efficiency of soft switching under heavy loads can be combined simply by switching logic signals, significantly improving the adaptability and overall energy efficiency of the DC-DC converter over a wide load range.

[0010] Furthermore, the first auxiliary signal and the second auxiliary signal are generated based on the first driving signal and the second driving signal, including: A first auxiliary signal is generated such that the pulse width of the first auxiliary signal completely covers the pulse width of the second driving signal, and the pulse width of the first auxiliary signal is within the low level time of the first driving signal, so that the first auxiliary signal can control the secondary side first bridge arm group to be turned on or off following the primary side second bridge arm group. The low-level time of the first auxiliary signal is configured to be greater than the pulse width time of the first driving signal, and the pulse width time of the first auxiliary signal is made less than the low-level time of the first driving signal, so that the first auxiliary signal can enable the primary side first bridge arm group and the primary side second bridge arm group to form a resonant network during the dead time. A second auxiliary signal is generated such that the pulse width of the second auxiliary signal completely covers the pulse width of the first driving signal, and the pulse width of the second auxiliary signal is within the low level time of the second driving signal, so that the second auxiliary signal can control the secondary side second bridge arm group to be turned on or off following the primary side first bridge arm group. The low-level time of the second auxiliary signal is configured to be greater than the pulse width time of the second driving signal, and the pulse width time of the second auxiliary signal is made less than the low-level time of the second driving signal, so that the second auxiliary signal can enable the primary side first bridge arm group and the primary side second bridge arm group to form a resonant network during the dead time. The first auxiliary signal and the second auxiliary signal have a high-level overlap time.

[0011] In this implementation, the accuracy and safety of switching between soft and hard switching modes are ensured by precisely configuring the timing relationship between the first auxiliary signal and the second auxiliary signal and the first driving signal and the second driving signal.

[0012] Specifically, the pulse widths of the first and second auxiliary signals completely cover the pulse widths of the second and first drive signals, respectively, ensuring that in hard-switching mode, the secondary bridge arm group can accurately follow the primary bridge arm group's on / off state, thus achieving synchronous rectification.

[0013] Simultaneously, by configuring the pulse width of the auxiliary signal to be greater than that of the corresponding drive signal, and by making the rising edge of the auxiliary signal lead the rising edge of the corresponding drive signal and the falling edge lag behind the falling edge of the corresponding drive signal, the corresponding auxiliary signal is in a high-level active state during the dead time when the primary-side drive signal is at a low level and in the period near that time. When switching to soft-switching mode, this high-level auxiliary signal is applied to the primary-side lower bridge arm, causing the primary-side lower bridge arm to conduct during the dead time of the first and second drive signals, thereby utilizing the time difference between the auxiliary signal and the drive signal to construct a resonant network.

[0014] A second aspect of the present invention provides a DC-DC converter circuit applicable to a soft-hard switching control method as described in the first aspect of the present invention. The DC-DC converter circuit includes a logic control sub-circuit, a primary-side full-bridge sub-circuit, a transformer module, and a secondary-side rectifier sub-circuit. The primary-side full-bridge sub-circuit includes a first primary-side upper bridge arm, a second primary-side upper bridge arm, a first primary-side lower bridge arm, and a second primary-side lower bridge arm that are turned on when a high-level signal is received. The first primary-side upper bridge arm and the second primary-side lower bridge arm form a primary-side first bridge arm group, and the second primary-side upper bridge arm and the first primary-side lower bridge arm form a primary-side second bridge arm group. The secondary-side rectifier sub-circuit includes a secondary-side first bridge arm group and a secondary-side second bridge arm group that are turned on when a high-level signal is received. Wherein: The primary side first bridge arm group and the primary side second bridge arm group are used to convert the input DC power into AC power and output AC power to the transformer module; the secondary side first bridge arm group and the secondary side second bridge arm group are used to synchronously rectify the AC power input to the transformer module in accordance with the primary side second bridge arm group and the primary side first bridge arm group. The control terminal of the primary side first upper bridge arm is used to receive a first driving signal, the control terminal of the primary side second upper bridge arm is used to receive a second driving signal, and the control terminal of the secondary side first bridge arm group is used to receive a first auxiliary signal. The logic control sub-circuit includes a first AND gate, a second AND gate, a first OR gate, and a second OR gate; The first input terminal of the second AND gate is used for a control signal, the second input terminal of the second AND gate is used to receive a second auxiliary signal, and the output terminal of the second AND gate is electrically connected to the first input terminal of the first OR gate. The second input terminal of the first OR gate is used to receive the first driving signal, and the output terminal of the first OR gate is electrically connected to the control terminal of the primary side second lower bridge arm. The first input terminal of the first AND gate is used to receive a control signal, the second terminal of the first AND gate is used to receive a first auxiliary signal, and the output terminal of the first AND gate is electrically connected to the first input terminal of the second OR gate. The second input terminal of the second OR gate is used to receive the second drive signal, and the output terminal of the second OR gate is electrically connected to the control terminal of the first lower bridge arm of the primary side.

[0015] In this implementation, the logic control sub-circuit constructs an efficient signal selection and switching network through a combination of AND and OR gates, achieving hardware-level mode reconfiguration.

[0016] Specifically, when the preset control signal is low, both the first AND gate and the second AND gate are blocked, and a low-level signal is output. At this time, the first OR gate only outputs the first drive signal to the second lower bridge arm of the primary side, and the second OR gate only outputs the second drive signal to the first lower bridge arm of the primary side. The primary side full-bridge sub-circuit fully follows the standard complementary drive logic, and the circuit operates in a simple hard-switching state.

[0017] When the preset control signal flips to a high level, the first AND gate and the second AND gate open, allowing the first auxiliary signal and the second auxiliary signal to pass through, respectively. At this time, the first OR gate performs a logical OR operation between the "first drive signal" and the "second auxiliary signal," and the second OR gate performs a logical OR operation between the "second drive signal" and the "first auxiliary signal." Since the auxiliary signal is high during the dead time of the two drive signals, the OR gate logic will automatically select the high-level auxiliary signal output during the dead time, thereby controlling the primary side lower bridge arm to conduct during the dead time. This circuit structure can complete the complex synthesis and switching of drive signals using simple logic gate circuits, which not only has low hardware cost and fast response speed, but also greatly improves the reliability of the system switching between two working modes.

[0018] Further, the primary-side full-bridge circuit includes a resonant inductor, the primary-side first upper bridge arm includes a first NMOS transistor, the primary-side second upper bridge arm includes a second NMOS transistor, the primary-side first lower bridge arm includes a third NMOS transistor, the primary-side second lower bridge arm includes a fourth NMOS transistor, the secondary-side first bridge arm group includes a fifth and an eighth NMOS transistor, the secondary-side second bridge arm group includes a sixth and a seventh NMOS transistor, and the transformer module includes a magnetizing inductor and a transformer, wherein: The first end of the resonant inductor is electrically connected to the positive input terminal of the primary side of the transformer; The drain of the first NMOS transistor is used to receive the input DC power, the source of the first NMOS transistor is electrically connected to the negative input terminal of the primary side of the transformer, and the gate of the first NMOS transistor is used to receive the first drive signal. The drain of the second NMOS transistor is used to receive the input DC power, the source of the second NMOS transistor is electrically connected to the second terminal of the resonant inductor, and the gate of the second NMOS transistor is used to receive the second drive signal. The drain of the third NMOS transistor is electrically connected to the negative input terminal of the primary side of the transformer, the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is electrically connected to the output terminal of the second OR gate. The drain of the fourth NMOS transistor is electrically connected to the second terminal of the resonant inductor, the source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is electrically connected to the output terminal of the first OR gate. The drain of the fifth NMOS transistor is used to output rectified DC power, the source of the fifth NMOS transistor is electrically connected to the positive output terminal of the secondary side of the transformer, and the gate of the fifth NMOS transistor is used to receive the first auxiliary signal. The drain of the sixth NMOS transistor is used to output rectified DC power, the source of the sixth NMOS transistor is electrically connected to the negative output terminal of the secondary side of the transformer, and the gate of the sixth NMOS transistor is used to receive the second auxiliary signal. The drain of the seventh NMOS transistor is electrically connected to the positive output terminal of the secondary side of the transformer, the source of the seventh NMOS transistor is grounded, and the gate of the seventh NMOS transistor is used to receive the second auxiliary signal. The drain of the eighth NMOS transistor is electrically connected to the negative output terminal of the secondary side of the transformer, the source of the eighth NMOS transistor is grounded, and the gate of the eighth NMOS transistor is used to receive the first auxiliary signal. One end of the magnetizing inductor is electrically connected to the positive input terminal of the primary side of the transformer, and the other end of the magnetizing inductor is electrically connected to the negative input terminal of the primary side of the transformer.

[0019] In this implementation, both the primary-side full-bridge circuit and the secondary-side rectifier circuit use NMOS transistors, and all switching transistors turn on when a high-level signal is received. The resonant inductor connected in series on the primary side is the key component for achieving soft switching. It works in conjunction with the parasitic capacitance of the switching transistors during the dead time, and uses the resonant current generated by the lower bridge arm control by the auxiliary signal to charge and discharge the junction capacitance of the switching transistors, thereby achieving zero-voltage turn-on.

[0020] The secondary-side rectifier circuit uses NMOS transistors to form a full-bridge structure. To achieve correct synchronous rectification, the first auxiliary signal on the secondary side must remain high when the second bridge arm group on the primary side is turned on, and the second auxiliary signal must remain high when the first bridge arm group on the primary side is turned on. This satisfies the requirement in soft-switching mode that the high-level portion of the secondary-side auxiliary signal is used to drive the lower bridge arm on the primary side. Furthermore, the magnetizing inductor is connected in parallel with the transformer to participate in energy storage and transmission, ensuring the continuity of magnetic flux during mode switching. This topology fully utilizes the characteristics of the devices, supporting synchronous rectification while achieving efficient soft-switching control through multiplexing of drive signal paths, thus optimizing the system's size and cost.

[0021] Furthermore, the DC-DC converter circuit further includes a filter sub-circuit, which comprises a filter inductor and a filter capacitor, wherein: The drains of the fifth NMOS transistor and the sixth NMOS transistor are respectively electrically connected to the first terminal of the filter inductor, and the second terminal of the filter inductor is used to output DC power to an external load. The first terminal of the filter capacitor is electrically connected to the second terminal of the filter inductor, and the second terminal of the filter capacitor is grounded.

[0022] In this implementation, the filter sub-circuit employs a classic LC filter structure composed of an inductor and a capacitor to smooth the pulse voltage after transformer isolation and secondary-side rectification. The filter inductor, acting as an energy storage element, smooths the current flowing through the load and suppresses current ripple; the filter capacitor, through its charging and discharging action, stabilizes the amplitude of the output DC voltage and filters out high-frequency switching noise. Regardless of whether in hard-switching or soft-switching mode, the waveform output by the secondary-side rectifier sub-circuit contains abundant switching harmonics. This filter sub-circuit effectively absorbs these harmonic energies, ensuring a stable and clean DC output to the external load. This not only improves the power quality of the DC-DC converter but also protects sensitive downstream loads from voltage fluctuations and spikes, enhancing the system's power supply reliability and stability.

[0023] A third aspect of the present invention provides a DC-DC converter, comprising a DC-DC conversion circuit and a digital signal processor; the DC-DC conversion circuit includes a primary-side full-bridge sub-circuit, a transformer module, and a secondary-side rectifier sub-circuit; the primary-side full-bridge sub-circuit includes a first primary-side upper bridge arm, a second primary-side upper bridge arm, a first primary-side lower bridge arm, and a second primary-side lower bridge arm that are turned on when a high-level signal is received; the first primary-side upper bridge arm and the second primary-side lower bridge arm form a primary-side first bridge arm group, and the second primary-side upper bridge arm and the first primary-side lower bridge arm form a primary-side second bridge arm group; the secondary-side rectifier sub-circuit includes a secondary-side first bridge arm group and a secondary-side second bridge arm group that are turned on when a high-level signal is received; the digital signal processor is used to generate a first drive signal, a second drive signal, a first auxiliary signal, a second auxiliary signal, and a control signal; wherein: The first drive signal and the second drive signal are complementary, and there is a dead time between the first drive signal and the second drive signal; The digital signal processor controls the primary side first bridge arm group through the first drive signal and controls the primary side second bridge arm group through the second drive signal, so that the primary side first bridge arm group and the primary side second bridge arm group are alternately turned on, thereby enabling the primary side first bridge arm group and the primary side second bridge arm group to perform AC conversion on the input DC power in a hard-switching working state and output AC power to the transformer module. The digital signal processor controls the secondary side first bridge arm group to be turned on or off in accordance with the primary side second bridge arm group through the first auxiliary signal, and controls the secondary side second bridge arm group to be turned on or off in accordance with the primary side first bridge arm group through the second auxiliary signal, thereby enabling the secondary side first bridge arm group and the secondary side second bridge arm group to synchronously rectify the AC power input to the transformer module in accordance with the primary side second bridge arm group and the primary side first bridge arm group; The DC-DC converter circuit responds to the control signal, and when the control signal switches to a high level: The second auxiliary signal is connected to the control terminal of the second lower bridge arm on the primary side, and the first auxiliary signal is connected to the control terminal of the first lower bridge arm on the primary side, so that the second lower bridge arm and the first lower bridge arm on the primary side are turned on during the dead time, thereby causing the first bridge arm group and the second bridge arm group to form a resonant network during the dead time, thereby causing the first bridge arm group and the second bridge arm group on the primary side to switch to soft switching operation state to perform AC conversion on the input DC power. Attached Figure Description

[0024] Figure 1 This is a flowchart of a soft / hard switch switching control method provided in an embodiment of the present invention; Figure 2 This is a waveform diagram of a driving signal and an auxiliary signal provided in an embodiment of the present invention; Figure 3 This is a structural diagram of a logic control sub-circuit provided in an embodiment of the present invention; Figure 4 This is a structural diagram of a DC-DC converter circuit provided in an embodiment of the present invention; Figure 5 This is a waveform diagram of a driving signal and an auxiliary signal provided in an embodiment of the present invention; Figure 6 This is a source-drain voltage waveform diagram of an NMOS transistor provided in an embodiment of the present invention; Figure 7 This is a waveform diagram of the primary current of a transformer provided in an embodiment of the present invention; Figure 8 This is a load current waveform diagram provided in an embodiment of the present invention; Figure 9 This is a structural diagram of a DC-DC converter provided in an embodiment of the present invention. Detailed Implementation

[0025] The present invention will now be described in detail with reference to the accompanying drawings and embodiments. It should be noted that the following detailed descriptions are exemplary and intended to provide further detailed explanation of the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein in the specification is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms "comprising" and "having," and any variations thereof, in the specification, claims, and foregoing drawings, are intended to cover non-exclusive inclusion. The terms "first," "second," etc., in the specification, claims, or foregoing drawings are used to distinguish different objects, not to describe a particular order.

[0026] Please refer to Figure 1 The first aspect of this invention provides a soft-hard switching control method applicable to a DC-DC converter circuit 100. The DC-DC converter circuit 100 includes a primary-side full-bridge sub-circuit 110, a transformer module 120, and a secondary-side rectifier sub-circuit 130. The primary-side full-bridge sub-circuit 110 includes a primary-side first upper bridge arm, a primary-side second upper bridge arm, a primary-side first lower bridge arm, and a primary-side second lower bridge arm that are turned on when a high-level signal is received. The primary-side first upper bridge arm and the primary-side second lower bridge arm form a primary-side first bridge arm group, and the primary-side second upper bridge arm and the primary-side first lower bridge arm form a primary-side second bridge arm group. The secondary-side rectifier sub-circuit 130 includes a secondary-side first bridge arm group and a secondary-side second bridge arm group that are turned on when a high-level signal is received. The method includes the following steps: S1. Generate a first driving signal and a second driving signal, wherein the first driving signal and the second driving signal are complementary and there is a dead time between the first driving signal and the second driving signal; S2. Control the first primary side bridge arm group through the first driving signal and control the second primary side bridge arm group through the second driving signal, so that the first primary side bridge arm group and the second primary side bridge arm group are alternately turned on, thereby enabling the first primary side bridge arm group and the second primary side bridge arm group to perform AC conversion on the input DC power in a hard switching working state and output AC power to the transformer module 120. S3. By controlling the secondary side first bridge arm group to turn on or off in accordance with the primary side second bridge arm group through a preset first auxiliary signal, and by controlling the secondary side second bridge arm group to turn on or off in accordance with the primary side first bridge arm group through a preset second auxiliary signal, thereby enabling the secondary side first bridge arm group and the secondary side second bridge arm group to synchronously rectify the AC power input to the transformer module 120 in accordance with the primary side second bridge arm group and the primary side first bridge arm group; S4. In response to a preset control signal, when the control signal switches to a high level: The second auxiliary signal is connected to the control terminal of the second lower bridge arm on the primary side, and the first auxiliary signal is connected to the control terminal of the first lower bridge arm on the primary side, so that the second lower bridge arm and the first lower bridge arm on the primary side are turned on during the dead time, thereby causing the first bridge arm group and the second bridge arm group to form a resonant network during the dead time, thereby causing the first bridge arm group and the second bridge arm group on the primary side to switch to soft switching operation state to perform AC conversion on the input DC power.

[0027] The above-mentioned soft and hard switching control method changes the driving logic of the lower bridge arm of the primary full-bridge circuit 110 by reusing the auxiliary signal of the secondary rectifier circuit 130, thereby realizing the seamless switching of the circuit from hard switching to soft switching operating mode.

[0028] In hard-switching mode, the primary side bridge arm group is only controlled by complementary first and second drive signals with dead time, and operates in a conventional PWM manner. The circuit control is simple and there is no additional resonant circulating current loss under light load.

[0029] When it is necessary to switch to soft-switching mode to reduce switching losses and electromagnetic interference under heavy load, the system responds to the high-level command of the preset control signal and connects the first auxiliary signal and the second auxiliary signal, which were originally used for secondary-side synchronous rectification, to the control terminals of the primary-side first lower bridge arm and the primary-side second lower bridge arm, respectively.

[0030] Because the pulse width of the auxiliary signal is configured to completely cover the conduction time of the corresponding primary-side bridge arm group, the lower primary-side bridge arm can be triggered to conduct by the auxiliary signal within the corresponding dead time. At this point, a resonant network is formed using the resonant inductance or transformer leakage inductance in the circuit and the parasitic capacitance of the switching transistor. The conduction of the lower bridge arm provides a path for the resonant current, thereby pulling down the voltage across the upper bridge arm switching transistor, achieving zero-voltage turn-on (ZVS). Ultimately, without adding additional complex drive circuitry, the advantages of hard switching under light loads and the high efficiency of soft switching under heavy loads can be combined simply by switching logic signals, significantly improving the adaptability and overall energy efficiency of the DC-DC converter over a wide load range.

[0031] In one possible implementation of the above embodiments, the digital signal processor 200 (DSP) generates a control signal and a multi-path pulse width modulation (PWM) drive signal according to a preset program or instructions; wherein, the control signal is used to characterize the target operating mode of the system: a high level corresponds to a soft switching mode, and a low level corresponds to a hard switching mode.

[0032] The control signal and the multiple PWM drive signals are input to the logic control sub-circuit 140. The logic control sub-circuit 140 performs hardware-level gating, shielding and synthesis processing on the input multiple PWM drive signals according to the logic level of the control signal. The synthesized final drive signal is output to the isolation drive circuit, which in turn drives the switching devices in the DC-DC converter circuit 100 to operate in the hard switching or soft switching mode set by the control signal.

[0033] The DC-DC converter circuit 100 is a full-bridge DC / DC converter topology, including a primary-side full-bridge sub-circuit 110 composed of four MOSFETs, a transformer, and a secondary-side rectifier sub-circuit 130 composed of four MOSFETs.

[0034] When the control signal is high, the logic control sub-circuit 140 allows multiple PWM signals to pass through according to the preset ZVS timing, drives the primary-side full-bridge switching transistors, and uses the resonance during the dead time to achieve zero-voltage switching; when the control signal is low, the logic control sub-circuit 140 will shield or reassemble part of the PWM signals, causing the resonant network to stop working and the system to return to the traditional hard-switching state.

[0035] Please refer to Figure 2 , Figure 2In this diagram, Control corresponds to the control signal; A1 corresponds to the signal received by the first NMOS transistor A1 (primary side first upper bridge arm), i.e., the first drive signal; A2 corresponds to the signal received by the second NMOS transistor A2 (primary side second upper bridge arm), i.e., the second drive signal; A3 corresponds to the combined signal received by the third NMOS transistor A3 (primary side first lower bridge arm); A4 corresponds to the combined signal received by the fourth NMOS transistor A4 (primary side second lower bridge arm); B1 corresponds to the signals received by the fifth NMOS transistor B1 and the eighth NMOS transistor B4 (secondary side first bridge arm group), i.e., the first auxiliary signal; and B2 corresponds to the signals received by the sixth NMOS transistor B2 and the seventh NMOS transistor B3 (secondary side second bridge arm group), i.e., the second auxiliary signal. Further, the first auxiliary signal and the second auxiliary signal are generated based on the first drive signal and the second drive signal, including: A first auxiliary signal is generated such that the pulse width of the first auxiliary signal completely covers the pulse width of the second driving signal, and the pulse width of the first auxiliary signal is within the low level time of the first driving signal, so that the first auxiliary signal can control the secondary side first bridge arm group to be turned on or off following the primary side second bridge arm group. The low-level time of the first auxiliary signal is configured to be greater than the pulse width time of the first driving signal, and the pulse width time of the first auxiliary signal is made less than the low-level time of the first driving signal, so that the first auxiliary signal can enable the primary side first bridge arm group and the primary side second bridge arm group to form a resonant network during the dead time. A second auxiliary signal is generated such that the pulse width of the second auxiliary signal completely covers the pulse width of the first driving signal, and the pulse width of the second auxiliary signal is within the low level time of the second driving signal, so that the second auxiliary signal can control the secondary side second bridge arm group to be turned on or off following the primary side first bridge arm group. The low-level time of the second auxiliary signal is configured to be greater than the pulse width time of the second driving signal, and the pulse width time of the second auxiliary signal is made less than the low-level time of the second driving signal, so that the second auxiliary signal can enable the primary side first bridge arm group and the primary side second bridge arm group to form a resonant network during the dead time. The first auxiliary signal and the second auxiliary signal have a high-level overlap time.

[0036] In this implementation, the accuracy and safety of switching between soft and hard switching modes are ensured by precisely configuring the timing relationship between the first auxiliary signal and the second auxiliary signal and the first driving signal and the second driving signal.

[0037] Specifically, the pulse widths of the first and second auxiliary signals completely cover the pulse widths of the second and first drive signals, respectively, ensuring that in hard-switching mode, the secondary bridge arm group can accurately follow the primary bridge arm group's on / off state, thus achieving synchronous rectification.

[0038] Simultaneously, by configuring the pulse width of the auxiliary signal to be greater than that of the corresponding drive signal, and by making the rising edge of the auxiliary signal lead the rising edge of the corresponding drive signal and the falling edge lag behind the falling edge of the corresponding drive signal, the corresponding auxiliary signal is in a high-level active state during the dead time when the primary-side drive signal is at a low level and in the period near that time. When switching to soft-switching mode, this high-level auxiliary signal is applied to the primary-side lower bridge arm, causing the lower bridge arm to conduct during the dead time of the first and second drive signals, thereby utilizing the time difference between the auxiliary signal and the drive signal to construct a resonant network.

[0039] Please refer to Figure 3 , Figure 3 In this configuration, terminal OUTA1 is electrically connected to the control terminal of the first upper bridge arm on the primary side, terminal OUTB1 is electrically connected to the control terminal of the second lower bridge arm on the primary side, terminal OUTC1 is electrically connected to the control terminal of the second upper bridge arm on the primary side, and terminal OUTD1 is electrically connected to the control terminal of the first lower bridge arm on the primary side. Here, EPWM2A represents the first drive signal, EPWM3A represents the second drive signal, EPWM2B represents the first auxiliary signal, EPWM3B represents the second auxiliary signal, and CONTROL represents the control signal. A second aspect of the present invention provides a DC-DC converter circuit 100, applicable to a soft-hard switching control method as described in the first aspect of the present invention. The DC-DC converter circuit 100 includes a logic control sub-circuit 140, a primary-side full-bridge sub-circuit 110, a transformer module 120, and a secondary-side rectifier sub-circuit 130. The primary-side full-bridge sub-circuit 110 includes a primary-side first upper bridge arm, a primary-side second upper bridge arm, a primary-side first lower bridge arm, and a primary-side second lower bridge arm that are turned on when a high-level signal is received. The primary-side first upper bridge arm and the primary-side second lower bridge arm form a primary-side first bridge arm group, and the primary-side second upper bridge arm and the primary-side first lower bridge arm form a primary-side second bridge arm group. The secondary-side rectifier sub-circuit 130 includes a secondary-side first bridge arm group and a secondary-side second bridge arm group that are turned on when a high-level signal is received. The primary side first bridge arm group and the primary side second bridge arm group are used to convert the input DC power into AC power and output AC power to the transformer module 120; the secondary side first bridge arm group and the secondary side second bridge arm group are used to synchronously rectify the AC power input to the transformer module 120 in accordance with the primary side first bridge arm group and the primary side second bridge arm group. The control terminal of the primary side first upper bridge arm is used to receive a first driving signal, the control terminal of the primary side second upper bridge arm is used to receive a second driving signal, and the control terminal of the secondary side first bridge arm group is used to receive a first auxiliary signal. The logic control sub-circuit 140 includes a first AND gate G11, a second AND gate G12, a first OR gate G21, and a second OR gate G22; The first input terminal of the second AND gate G12 is used for a control signal, the second input terminal of the second AND gate G12 is used to receive a second auxiliary signal, and the output terminal of the second AND gate G12 is electrically connected to the first input terminal of the first OR gate G21. The second input terminal of the first OR gate G21 is used to receive the first drive signal, and the output terminal of the first OR gate G21 is electrically connected to the control terminal of the primary side second lower bridge arm. The first input terminal of the first AND gate G11 is used to receive a control signal, the second terminal of the first AND gate G11 is used to receive a first auxiliary signal, and the output terminal of the first AND gate G11 is electrically connected to the first input terminal of the second OR gate G22. The second input terminal of the second OR gate G22 is used to receive the second drive signal, and the output terminal of the second OR gate G22 is electrically connected to the control terminal of the first lower bridge arm of the primary side.

[0040] In this implementation, the logic control sub-circuit 140 constructs an efficient signal selection and switching network through a combination of AND and OR gates, thereby achieving hardware-level mode reconfiguration.

[0041] Specifically, when the preset control signal is low, both the first AND gate G11 and the second AND gate G12 are blocked, and a low-level signal is output. At this time, the first OR gate G21 only outputs the first drive signal to the second lower bridge arm of the primary side, and the second OR gate G22 only outputs the second drive signal to the first lower bridge arm of the primary side. The primary side full-bridge sub-circuit 110 fully follows the standard complementary drive logic, and the circuit operates in a simple hard-switching state.

[0042] When the preset control signal flips to a high level, the first AND gate G11 and the second AND gate G12 are turned on, allowing the first auxiliary signal and the second auxiliary signal to pass through, respectively. At this time, the first OR gate G21 performs a logical OR operation between the "first drive signal" and the "second auxiliary signal", and the second OR gate G22 performs a logical OR operation between the "second drive signal" and the "first auxiliary signal". Since the auxiliary signal is high during the dead time of the two drive signals, the OR gate logic will automatically select the high-level auxiliary signal output during the dead time, thereby controlling the primary side lower bridge arm to conduct during the dead time. This circuit structure can complete the complex synthesis and switching of drive signals using simple logic gate circuits, which not only has low hardware cost and fast response speed, but also greatly improves the reliability of the system switching between two working modes.

[0043] Please refer to Figure 4 , Figure 4 The circuit includes a DC power supply U1, where EPWM2A represents the first drive signal, EPWM3A represents the second drive signal, EPWM2B represents the first auxiliary signal, EPWM3B represents the second auxiliary signal, and CONTROL represents the control signal. Further, the primary-side full-bridge circuit 110 includes a resonant inductor, the primary-side first upper bridge arm includes a first NMOS transistor A1, the primary-side second upper bridge arm includes a second NMOS transistor A2, the primary-side first lower bridge arm includes a third NMOS transistor A3, the primary-side second lower bridge arm includes a fourth NMOS transistor A4, the secondary-side first bridge arm group includes a fifth NMOS transistor B1 and an eighth NMOS transistor B4, the secondary-side second bridge arm group includes a sixth NMOS transistor B2 and a seventh NMOS transistor B3, and the transformer module 120 includes a magnetizing inductor and a transformer, wherein: The first end of the resonant inductor is electrically connected to the positive input terminal of the primary side of the transformer; The drain of the first NMOS transistor A1 is used to receive the input DC power, the source of the first NMOS transistor A1 is electrically connected to the negative input terminal of the primary side of the transformer, and the gate of the first NMOS transistor A1 is used to receive the first drive signal. The drain of the second NMOS transistor A2 is used to receive the input DC power, the source of the second NMOS transistor A2 is electrically connected to the second terminal of the resonant inductor, and the gate of the second NMOS transistor A2 is used to receive the second drive signal. The drain of the third NMOS transistor A3 is electrically connected to the negative input terminal of the primary side of the transformer, the source of the third NMOS transistor A3 is grounded, and the gate of the third NMOS transistor A3 is electrically connected to the output terminal of the second OR gate G22. The drain of the fourth NMOS transistor A4 is electrically connected to the second terminal of the resonant inductor, the source of the fourth NMOS transistor A4 is grounded, and the gate of the fourth NMOS transistor A4 is electrically connected to the output terminal of the first OR gate G21. The drain of the fifth NMOS transistor B1 is used to output rectified DC power, the source of the fifth NMOS transistor B1 is electrically connected to the positive output terminal of the secondary side of the transformer, and the gate of the fifth NMOS transistor B1 is used to receive the first auxiliary signal. The drain of the sixth NMOS transistor B2 is used to output rectified DC power, the source of the sixth NMOS transistor B2 is electrically connected to the negative output terminal of the secondary side of the transformer, and the gate of the sixth NMOS transistor B2 is used to receive the second auxiliary signal. The drain of the seventh NMOS transistor B3 is electrically connected to the positive output terminal of the secondary side of the transformer, the source of the seventh NMOS transistor B3 is grounded, and the gate of the seventh NMOS transistor B3 is used to receive the second auxiliary signal. The drain of the eighth NMOS transistor B4 is electrically connected to the negative output terminal of the secondary side of the transformer, the source of the eighth NMOS transistor B4 is grounded, and the gate of the eighth NMOS transistor B4 is used to receive the first auxiliary signal. One end of the magnetizing inductor is electrically connected to the positive input terminal of the primary side of the transformer, and the other end of the magnetizing inductor is electrically connected to the negative input terminal of the primary side of the transformer.

[0044] In this implementation, both the primary-side full-bridge circuit 110 and the secondary-side rectifier circuit 130 use NMOS transistors, and all switching transistors turn on when a high-level signal is received. The resonant inductor connected in series on the primary side is a key component for achieving soft switching. It works in conjunction with the parasitic capacitance of the switching transistors during the dead time, and uses the resonant current generated by the lower bridge arm conduction controlled by the auxiliary signal to complete the charging and discharging of the junction capacitance of the switching transistors, thereby achieving zero-voltage turn-on.

[0045] The secondary-side rectifier circuit 130 uses NMOS transistors to form a full-bridge structure. To achieve correct synchronous rectification, the first auxiliary signal (fifth NMOS transistor B1) on the secondary side must remain high when the second bridge arm group (second NMOS transistor A2 and third NMOS transistor A3) on the primary side is turned on, and the second auxiliary signal (sixth NMOS transistor B2) must remain high when the first bridge arm group (first NMOS transistor A1 and fourth NMOS transistor A4) on the primary side is turned on. This satisfies the requirement in soft-switching mode that the high-level portion of the secondary-side auxiliary signal is used to drive the lower bridge arm on the primary side. Furthermore, the magnetizing inductor is connected in parallel with the transformer to participate in energy storage and transmission, ensuring the continuity of magnetic flux during mode switching. This topology fully utilizes the characteristics of the devices, supporting synchronous rectification while achieving efficient soft-switching control through multiplexing the drive signal path, thus optimizing the system's size and cost.

[0046] Please refer to Figure 4 Furthermore, the DC-DC converter circuit 100 further includes a filter sub-circuit 150, which includes a filter inductor Lo and a filter capacitor Co, wherein: The drain of the fifth NMOS transistor B1 and the drain of the sixth NMOS transistor B2 are respectively electrically connected to the first terminal of the filter inductor Lo, and the second terminal of the filter inductor Lo is used to output DC power to an external load. The first terminal of the filter capacitor Co is electrically connected to the second terminal of the filter inductor Lo, and the second terminal of the filter capacitor Co is grounded.

[0047] In this implementation, the filter sub-circuit 150 employs a classic LC filter structure composed of an inductor and a capacitor to smooth the pulse voltage after transformer isolation and secondary-side rectification. The filter inductor Lo, acting as an energy storage element, smooths the current flowing through the load and suppresses current ripple; the filter capacitor Co, through its charging and discharging action, stabilizes the amplitude of the output DC voltage and filters out high-frequency switching noise. Regardless of whether in hard-switching or soft-switching mode, the waveform output by the secondary-side rectifier sub-circuit 130 contains abundant switching harmonics. The filter sub-circuit 150 effectively absorbs these harmonic energies, ensuring a stable and clean DC output to the external load. This not only improves the power quality of the DC-DC converter but also protects sensitive downstream loads from voltage fluctuations and spikes, enhancing the system's power supply reliability and stability.

[0048] Please refer to Figure 4 Furthermore, the DC-DC converter circuit 100 also includes an input capacitor Ci, the drains of the first NMOS transistor A1 and the second NMOS transistor A2 are electrically connected to the first terminal of the input capacitor Ci, and the second terminal of the input capacitor Ci is grounded.

[0049] To further illustrate the technical effects of this invention, please refer to the following: Figure 2 and Figure 5 .exist Figure 2 and Figure 5In the diagram, A1 corresponds to the signal received by the gate of the first NMOS transistor A1, i.e., the first drive signal; A2 corresponds to the signal received by the gate of the second NMOS transistor A2, i.e., the second drive signal; A3 corresponds to the combined signal received by the gate of the third NMOS transistor A3; A4 corresponds to the combined signal received by the gate of the fourth NMOS transistor A4; B1 corresponds to the signals received by the gates of the fifth NMOS transistor B1 and the eighth NMOS transistor B4, i.e., the first auxiliary signal; B2 corresponds to the signals received by the gates of the sixth NMOS transistor B2 and the seventh NMOS transistor B3, i.e., the second auxiliary signal. EPWM2A represents the first drive signal, EPWM3A represents the second drive signal, EPWM2B represents the first auxiliary signal, EPWM3B represents the second auxiliary signal, and CONTROL represents the control signal.

[0050] In one specific embodiment of the present invention, when the control signal is high, the system enters a soft-switching working mode.

[0051] Based on Figure 2 and Figure 5 The principle of the soft-switching operating mode is explained in detail using a segment of the waveform as an example. At a certain first moment when the control signal Control is high, the first drive signal is high, turning on the first NMOS transistor A1. Simultaneously, the control signal for the fourth NMOS transistor A4, synthesized by the logic control sub-circuit 140, is high, turning on the primary-side fourth NMOS transistor A4. The first NMOS transistor A1 and the fourth NMOS transistor A4 form the conduction path of the first bridge arm group on the primary side. At this time, the second auxiliary signal is high, controlling the sixth NMOS transistor B2 and the seventh NMOS transistor B3 of the second bridge arm group on the secondary side to conduct. The input DC power is converted into AC power by the first bridge arm group on the primary side and transmitted to the secondary side through a transformer, where it is synchronously rectified and output by the second bridge arm group on the secondary side.

[0052] During the dead time period from the first time point to the second time point, the first drive signal of the first NMOS transistor A1 is turned off and becomes low, while the second drive signal of the second NMOS transistor A2 remains low, and all primary-side upper bridge arms are cut off. Since the control signal is high, the logic control sub-circuit 140 introduces the second auxiliary signal of the sixth NMOS transistor B2, causing the control signal of the fourth NMOS transistor A4 to continue to remain high; at the same time, it introduces the first auxiliary signal of the fifth NMOS transistor B1, causing the control signal of the third NMOS transistor A3 to become high during the period from the second time point to the third time point.

[0053] During the period from the second to the third time point, the control signals of the third NMOS transistor A3 and the fourth NMOS transistor A4 are both at a high level. Both the third NMOS transistor A3 and the fourth NMOS transistor A4 on the primary side are turned on, forming a resonant network together with the primary side resonant inductor. This network charges and discharges the junction capacitance of the primary side switching transistors, creating a zero-voltage turn-on condition for the bridge arm that is about to be turned on.

[0054] Subsequently, during the period from the third to the fourth time point, the control signal of the fourth NMOS transistor A4 is turned off, the control signal of the third NMOS transistor A3 remains at a high level, and at the same time, the first auxiliary signal of the fifth NMOS transistor B1 becomes high, controlling the fifth NMOS transistor B1 and the eighth NMOS transistor B4 of the first bridge arm group on the secondary side to turn on.

[0055] During the fourth to fifth time intervals, the second drive signal of the second NMOS transistor A2 becomes high, and the second NMOS transistor A2 of the second upper bridge arm on the primary side is turned on. Together with the already turned-on third NMOS transistor A3, it forms the conduction path of the second bridge arm group on the primary side, completing the energy transfer of the other half cycle. The fifth NMOS transistor B1 and the eighth NMOS transistor B4 of the first bridge arm group on the secondary side continue to conduct for rectification.

[0056] Symmetrically, the soft-switching operation of the other half-cycle is implemented based on the same principle described above.

[0057] In the above embodiment, the first and second primary-side bridge arms are alternately turned on. During the dead time between the turn-off of one bridge arm and the turn-on of the other, thanks to the establishment of the resonant network, the drain-source voltage waveform of the switch about to be turned on exhibits decaying oscillations and crosses zero resonantly before its drive signal arrives. During the dead time, the transformer leakage inductance or resonant inductance and the parasitic capacitance (junction capacitance) of the primary-side switch form a resonant circuit. The resonant current discharges the junction capacitance of the switch about to be turned on and charges the junction capacitance of the switch about to be turned off, thereby reducing its drain-source voltage to zero. The switch current rises from zero or transitions from the freewheeling current of the body diode at the turn-on moment, achieving zero-voltage turn-on. The voltage and current overlap area at the turn-on moment is almost zero, therefore the switching losses and electromagnetic interference are extremely low.

[0058] The auxiliary signals of the first and second bridge arms on the secondary side are strictly synchronized with the driving signal on the primary side, and maintain the correct freewheeling state during the dead zone of the primary side to maintain the energy transfer path and participate in the resonance process.

[0059] When the control signal is low, the system operates in hard-switching mode. Based on... Figure 2 and Figure 5 The principle of the hard-switching operating mode is explained in detail using a segment of the waveform as an example. At a certain first moment when the control signal Control is low, the state is the same as that of the soft-switching mode, and the first bridge arm group on the primary side (the first NMOS transistor A1 and the fourth NMOS transistor A4) and the second bridge arm group on the secondary side (the sixth NMOS transistor B2 and the seventh NMOS transistor B3) are turned on.

[0060] During the dead time between the first and second moments, the first drive signal of the first NMOS transistor A1 is turned off. Since the control signal is low, the output of the logic control sub-circuit 140 keeps the control signals of the third NMOS transistor A3 and the fourth NMOS transistor A4 low, and the primary side lower bridge arm is not turned on. The primary side current completes the commutation by charging and discharging the parasitic capacitance of the switching transistor.

[0061] During the period from the second time point to the third time point, the state of the primary side bridge arm remains unchanged, and the first auxiliary signal of the fifth NMOS transistor B1 becomes high, controlling the first bridge arm group of the secondary side (the fifth NMOS transistor B1 and the eighth NMOS transistor B4) to conduct, thus completing the commutation of the secondary side rectifier.

[0062] During the period from the fourth to the fifth time point, the second drive signal of the second NMOS transistor A2 goes high, turning on the second bridge arm group on the primary side (the second NMOS transistor A2 and the third NMOS transistor A3) for energy transfer, while the first bridge arm group on the secondary side (the fifth NMOS transistor B1 and the eighth NMOS transistor B4) continues to conduct for rectification. Subsequent timing changes are symmetrical, and during each dead time, the lower bridge arm on the primary side does not conduct simultaneously, thus preventing the formation of a resonant network and maintaining hard-switching operation.

[0063] In the above embodiment, the dead time between bridge arm switching is significantly shortened by adjusting the signal through the logic control sub-circuit 140. The purpose is to avoid generating sufficient resonant time so that the switch is driven to turn on before the drain-source voltage drops to zero. When the drive signal arrives, the drain-source voltage of the switch is still at a high level. The switch turns on under high voltage, and the current begins to rise, resulting in significant voltage-current overlap. Insufficient current drop before voltage rise during turn-off also generates turn-off losses. The voltage-current crossover area at the moment of turn-on and turn-off directly represents the switching losses and also generates high-frequency ringing and strong electromagnetic interference. The timing of the secondary-side synchronous rectification signal is adjusted accordingly to match the non-resonant hard switching timing of the primary side. Its core function is simple rectification and freewheeling; it does not participate in constructing the resonant condition.

[0064] In a preferred embodiment, the DC-DC converter 100 employs a classic full-bridge isolated DC / DC topology. The primary side consists of a full-bridge sub-circuit 110 composed of the first NMOS transistor A1, the second NMOS transistor A2, the third NMOS transistor A3, and the fourth NMOS transistor A4. The secondary side consists of a secondary rectifier sub-circuit 130 composed of the fifth NMOS transistor B1, the sixth NMOS transistor B2, the seventh NMOS transistor B3, and the eighth NMOS transistor B4. The digital signal processor 200 acts as the system controller, responsible for executing all control algorithms.

[0065] The core innovation of this invention lies in the signal processing link between the digital signal processor 200 and the DC-DC converter circuit 100. The digital signal processor 200 not only generates four PWM drive signals for directly controlling the switching transistors—namely, the first drive signal, the first auxiliary signal, the second drive signal, and the second auxiliary signal—but also generates a critical control signal according to system configuration requirements. All these signals are fed into the logic control sub-circuit 140, which is constructed using OR gate chips and AND gate chips.

[0066] The original PWM drive signals generated by the digital signal processor 200, such as the first drive signal, the second drive signal, the first auxiliary signal, the second auxiliary signal, and the control signal, are sent together to the logic control sub-circuit 140.

[0067] When the control signal is high, the system operates in soft-switching mode; when the control signal is low, the system operates in hard-switching mode. When the control signal is high (soft-switching mode), the logic control sub-circuit 140 allows the PWM drive signal to pass through according to ZVS timing, and synthesizes it into four final drive signals that meet the zero-voltage turn-on requirement. The waveforms show a drive timing sequence with sufficient dead time, allowing resonance to occur.

[0068] When the control signal is low (hard switching operation state), the logic control sub-circuit 140 hardware shields part of the PWM drive signal path, reorganizes the drive timing, and outputs a drive signal with no resonant dead time or an extremely short dead time, so that the switching transistor operates in the traditional hard switching state.

[0069] Figure 2 and Figure 5 As can be clearly seen, before and after the control signal transition, the driving waveform timing of the first NMOS transistor A1, the second NMOS transistor A2, the third NMOS transistor A3, the fourth NMOS transistor A4, the fifth NMOS transistor B1, the sixth NMOS transistor B2, the seventh NMOS transistor B3, and the eighth NMOS transistor B4 undergoes significant changes. In particular, the length of the dead time and the presence or absence of the resonant window directly reflect the hardware-level switching function of the logic control sub-circuit 140 on the working mode.

[0070] When the system is configured in soft-switching mode, the control signal is high. At this time, the objective of the logic control sub-circuit 140, composed of the first AND gate G11, the second AND gate G12, the first OR gate G21, and the second OR gate G22, is to synthesize four final drive signals with specific "dead time" and "overlapping region" based on the original PWM drive signal to meet the timing requirements of zero-voltage switching. The signal of the first bridge arm group on the primary side is not directly provided by the first drive signal, but is generated by combining the first drive signal, the second auxiliary signal, and the control signal through AND gates. The high level of the control signal acts as an "enable" condition, allowing specific original PWM drive signal paths to pass.

[0071] Similarly, the signal driving the second bridge arm group on the primary side is generated by combining the second driving signal, the first auxiliary signal, and other signals under the enable of the control signal. The logic control sub-circuit 140, through the above combination, ensures that the signals driving the upper and lower transistors of the same bridge arm, i.e., the first NMOS transistor A1 and the second NMOS transistor A2, will never be high simultaneously, and inserts a fixed-width dead time determined by the original signal phase difference and logic processing between their state transitions. During this dead time, all four final driving signals are low, all primary-side switches are turned off, providing a time window for resonance.

[0072] The four final drive signals synthesized by the logic control sub-circuit 140 present as interleaved drive waveforms with obvious dead time. The signals driving the first bridge arm group of the primary side are synchronized, and the signals driving the second bridge arm group of the primary side are synchronized, with sufficient dead time between the two groups of signals.

[0073] When the system is configured for hard-switching operation, the control signal is low. At this time, the objective of the logic control sub-circuit 140 becomes: to shield or modify the specific timing path required for soft switching, generating complementary drive signals with extremely short or near-zero dead time. The low-level input of the control signal to the AND gate used to synthesize the soft-switching timing directly forces the output of that AND gate to low, thereby shielding the signal path used to generate the ZVS dead time at the hardware level.

[0074] Simultaneously, other paths such as OR gates in the logic control sub-circuit 140 are activated, directly or simply recombining the first and second drive signals before outputting them. For example, the first drive signal is directly mapped to the signal driving the first NMOS transistor A1 and the fourth NMOS transistor A4, and the second drive signal is directly mapped to the signal driving the second NMOS transistor A2 and the third NMOS transistor A3, significantly reducing or eliminating the intermediate dead time. The same set of original PWM drive signals is input.

[0075] The final drive signal output after being reorganized by the logic control sub-circuit 140 has a significantly shortened or eliminated dead time. The signals driving the upper and lower transistors of the same bridge arm are almost complementary square waves. The overlap or interval at the moment of switching is extremely small, forcing the switching transistor to turn on before the voltage drops to zero, which is a typical hard switching waveform.

[0076] The logic control sub-circuit 140 works as follows: the control signal acts as a "key," controlling the "channel" of the PWM drive signal. When the digital signal processor 200 sets the control signal to a high level, the high level of the control signal makes one input of all related AND gates high. At this time, the PWM drive signal can pass smoothly through the AND gates, and subsequent circuits combine them into four final drive signals that meet the ZVS timing requirements.

[0077] The four final drive signals output by the logic control sub-circuit 140 are respectively connected to and drive the MOSFET switches in the DC-DC converter circuit 100. After passing through the isolation drive circuit, these signals cause the switches in the primary-side full-bridge sub-circuit 110 to operate according to the ZVS timing, achieving zero-voltage turn-on using resonance during the dead time.

[0078] When the digital signal processor 200 sets the control signal to a low level (hard-switching operation), the low level of the control signal forces the outputs of all related AND gates to be low, thereby hardware-shielding the specific PWM drive signal path upon which ZVS operation depends. The logic control sub-circuit 140 recombines the remaining valid signals through OR gates, etc., to generate a different drive timing sequence. This timing sequence causes the circuit to exit the resonant state, and the MOSFET operates under hard-switching conditions.

[0079] Throughout the process, the mode switching decision originates from the programmable logic of the digital signal processor 200, while the switching action is reliably executed by the hardware logic control sub-circuit 140, balancing flexibility and reliability. The first auxiliary signal and the second auxiliary signal on the secondary side are directly generated by the digital signal processor 200, and their timing is adjusted accordingly by the internal logic of the digital signal processor 200 based on the mode indicated by the control signal to match the primary side's operating mode.

[0080] Please refer to Figure 6 , Figure 6 yes Figure 4 The diagram shows the source-drain voltage waveform of a certain NMOS transistor in the primary-side full-bridge sub-circuit 110. The horizontal axis represents time t in seconds (s), and the vertical axis represents voltage Vds in volts (V). Figure 6It can be seen that in soft-switching mode, the source-drain voltage Vds of the NMOS transistor resonates and crosses zero during the dead time.

[0081] Please refer to Figure 7 , Figure 7 yes Figure 4 The waveform of the primary current of the transformer is shown. The horizontal axis of the waveform graph represents time t in seconds (s), and the vertical axis represents current I in amperes (A).

[0082] Please refer to Figure 8 , Figure 8 This is a waveform diagram of the load current Io. The horizontal axis of the waveform diagram represents time t in seconds (s), and the vertical axis represents current I in amperes (A). As can be seen from the diagram, the output load current is DC, but there is a certain ripple. The filter circuit 150 is used to smooth this current.

[0083] Please refer to Figure 9 A third aspect of the present invention provides a DC-DC converter, comprising a DC-DC converter circuit 100 and a digital signal processor 200; the DC-DC converter circuit 100 includes a primary-side full-bridge sub-circuit 110, a transformer module 120, and a secondary-side rectifier sub-circuit 130; the primary-side full-bridge sub-circuit 110 includes a primary-side first upper bridge arm, a primary-side second upper bridge arm, a primary-side first lower bridge arm, and a primary-side second lower bridge arm that are turned on when a high-level signal is received; the primary-side first upper bridge arm and the primary-side second lower bridge arm form a primary-side first bridge arm group, and the primary-side second upper bridge arm and the primary-side first lower bridge arm form a primary-side second bridge arm group; the secondary-side rectifier sub-circuit 130 includes a secondary-side first bridge arm group and a secondary-side second bridge arm group that are turned on when a high-level signal is received; the digital signal processor 200 is used to generate a first drive signal, a second drive signal, a first auxiliary signal, a second auxiliary signal, and a control signal; wherein: The first drive signal and the second drive signal are complementary, and there is a dead time between the first drive signal and the second drive signal; The digital signal processor 200 controls the primary side first bridge arm group through the first drive signal and controls the primary side second bridge arm group through the second drive signal, so that the primary side first bridge arm group and the primary side second bridge arm group are alternately turned on, thereby enabling the primary side first bridge arm group and the primary side second bridge arm group to perform AC conversion on the input DC power in a hard-switching working state and output AC power to the transformer module 120. The digital signal processor 200 controls the secondary side first bridge arm group to be turned on or off in accordance with the primary side second bridge arm group through the first auxiliary signal, and controls the secondary side second bridge arm group to be turned on or off in accordance with the primary side first bridge arm group through the second auxiliary signal, thereby enabling the secondary side first bridge arm group and the secondary side second bridge arm group to synchronously rectify the AC power input to the transformer module 120 in accordance with the primary side first bridge arm group and the primary side second bridge arm group; The DC-DC converter circuit 100 responds to the control signal, and when the control signal switches to a high level: The second auxiliary signal is connected to the control terminal of the second lower bridge arm on the primary side, and the first auxiliary signal is connected to the control terminal of the first lower bridge arm on the primary side, so that the second lower bridge arm and the first lower bridge arm on the primary side are turned on during the dead time, thereby causing the first bridge arm group and the second bridge arm group to form a resonant network during the dead time, thereby causing the first bridge arm group and the second bridge arm group on the primary side to switch to soft switching operation state to perform AC conversion on the input DC power.

[0084] The term "embodiment" as used herein means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a mutually exclusive, independent, or alternative embodiment. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described; however, any combination of these technical features that does not contradict each other should be considered within the scope of this specification.

[0085] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this application. It should be noted that those skilled in the art can make various improvements and substitutions without departing from the concept of this application, and these improvements and substitutions should also be considered within the scope of protection of this invention. Therefore, the scope of protection of this application should be determined by the appended claims.

Claims

1. A method for controlling soft and hard switching, characterized in that, A DC-DC converter circuit is applicable to a DC-DC converter circuit, comprising a primary-side full-bridge sub-circuit, a transformer module, and a secondary-side rectifier sub-circuit. The primary-side full-bridge sub-circuit includes a first primary upper bridge arm, a second primary upper bridge arm, a first primary lower bridge arm, and a second primary lower bridge arm that are turned on when a high-level signal is received. The first primary upper bridge arm and the second primary lower bridge arm form a primary-side first bridge arm group, and the second primary upper bridge arm and the first primary lower bridge arm form a primary-side second bridge arm group. The secondary-side rectifier sub-circuit includes a secondary-side first bridge arm group and a secondary-side second bridge arm group that are turned on when a high-level signal is received. The method includes the following steps: A first drive signal and a second drive signal are generated. The first drive signal and the second drive signal are complementary, and there is a dead time between the first drive signal and the second drive signal. The first driving signal controls the first primary side bridge arm group, and the second driving signal controls the second primary side bridge arm group, so that the first primary side bridge arm group and the second primary side bridge arm group are alternately turned on, thereby enabling the first primary side bridge arm group and the second primary side bridge arm group to perform AC conversion on the input DC power in a hard-switching working state and output AC power to the transformer module. The secondary side first bridge arm group is controlled to turn on or off in accordance with the primary side second bridge arm group by a preset first auxiliary signal, and the secondary side second bridge arm group is controlled to turn on or off in accordance with the primary side first bridge arm group by a preset second auxiliary signal, thereby enabling the secondary side first bridge arm group and the secondary side second bridge arm group to synchronously rectify the AC power input to the transformer module in accordance with the primary side second bridge arm group and the primary side first bridge arm group; In response to a preset control signal, when the control signal switches to a high level: The second auxiliary signal is connected to the control terminal of the second lower bridge arm of the primary side, and the first auxiliary signal is connected to the control terminal of the first lower bridge arm of the primary side, so that the second lower bridge arm and the first lower bridge arm of the primary side are turned on during the dead time, thereby causing the first bridge arm group and the second bridge arm group of the primary side to form a resonant network during the dead time, thereby causing the first bridge arm group and the second bridge arm group of the primary side to switch to soft switching operation state to perform AC conversion on the input DC power.

2. The soft / hard switch switching control method according to claim 1, characterized in that, The first auxiliary signal and the second auxiliary signal are generated based on the first driving signal and the second driving signal, including: A first auxiliary signal is generated such that the pulse width of the first auxiliary signal completely covers the pulse width of the second driving signal, and the pulse width of the first auxiliary signal is within the low level time of the first driving signal, so that the first auxiliary signal can control the secondary side first bridge arm group to be turned on or off following the primary side second bridge arm group. The low-level time of the first auxiliary signal is configured to be greater than the pulse width time of the first driving signal, and the pulse width time of the first auxiliary signal is made less than the low-level time of the first driving signal, so that the first auxiliary signal can enable the primary side first bridge arm group and the primary side second bridge arm group to form a resonant network during the dead time. A second auxiliary signal is generated such that the pulse width of the second auxiliary signal completely covers the pulse width of the first driving signal, and the pulse width of the second auxiliary signal is within the low level time of the second driving signal, so that the second auxiliary signal can control the secondary side second bridge arm group to be turned on or off following the primary side first bridge arm group. The low-level time of the second auxiliary signal is configured to be greater than the pulse width time of the second driving signal, and the pulse width time of the second auxiliary signal is made less than the low-level time of the second driving signal, so that the second auxiliary signal can enable the primary side first bridge arm group and the primary side second bridge arm group to form a resonant network during the dead time. The first auxiliary signal and the second auxiliary signal have a high-level overlap time.

3. A DC-DC converter circuit, characterized in that, A soft-hard switching control method as described in claim 1 or 2 is applicable, wherein the DC-DC converter circuit includes a logic control sub-circuit, a primary-side full-bridge sub-circuit, a transformer module, and a secondary-side rectifier sub-circuit; the primary-side full-bridge sub-circuit includes a primary-side first upper bridge arm, a primary-side second upper bridge arm, a primary-side first lower bridge arm, and a primary-side second lower bridge arm that are turned on when a high-level signal is received; the primary-side first upper bridge arm and the primary-side second lower bridge arm form a primary-side first bridge arm group, and the primary-side second upper bridge arm and the primary-side first lower bridge arm form a primary-side second bridge arm group; the secondary-side rectifier sub-circuit includes a secondary-side first bridge arm group and a secondary-side second bridge arm group that are turned on when a high-level signal is received; wherein: The primary side first bridge arm group and the primary side second bridge arm group are used to convert the input DC power into AC power and output AC power to the transformer module; the secondary side first bridge arm group and the secondary side second bridge arm group are used to synchronously rectify the AC power input to the transformer module in accordance with the primary side second bridge arm group and the primary side first bridge arm group. The control terminal of the primary side first upper bridge arm is used to receive a first driving signal, the control terminal of the primary side second upper bridge arm is used to receive a second driving signal, and the control terminal of the secondary side first bridge arm group is used to receive a first auxiliary signal. The logic control sub-circuit includes a first AND gate, a second AND gate, a first OR gate, and a second OR gate; The first input terminal of the second AND gate is used for a control signal, the second input terminal of the second AND gate is used to receive a second auxiliary signal, and the output terminal of the second AND gate is electrically connected to the first input terminal of the first OR gate. The second input terminal of the first OR gate is used to receive the first driving signal, and the output terminal of the first OR gate is electrically connected to the control terminal of the primary side second lower bridge arm. The first input terminal of the first AND gate is used to receive a control signal, the second terminal of the first AND gate is used to receive a first auxiliary signal, and the output terminal of the first AND gate is electrically connected to the first input terminal of the second OR gate. The second input terminal of the second OR gate is used to receive the second drive signal, and the output terminal of the second OR gate is electrically connected to the control terminal of the first lower bridge arm of the primary side.

4. A DC-DC converter circuit according to claim 3, characterized in that, The primary-side full-bridge circuit includes a resonant inductor; the first upper arm of the primary side includes a first NMOS transistor; the second upper arm of the primary side includes a second NMOS transistor; the first lower arm of the primary side includes a third NMOS transistor; the second lower arm of the primary side includes a fourth NMOS transistor; the first group of secondary-side bridge arms includes a fifth and an eighth NMOS transistor; the second group of secondary-side bridge arms includes a sixth and a seventh NMOS transistor; and the transformer module includes a magnetizing inductor and a transformer, wherein: The first end of the resonant inductor is electrically connected to the positive input terminal of the primary side of the transformer; The drain of the first NMOS transistor is used to receive the input DC power, the source of the first NMOS transistor is electrically connected to the negative input terminal of the primary side of the transformer, and the gate of the first NMOS transistor is used to receive the first drive signal. The drain of the second NMOS transistor is used to receive the input DC power, the source of the second NMOS transistor is electrically connected to the second terminal of the resonant inductor, and the gate of the second NMOS transistor is used to receive the second drive signal. The drain of the third NMOS transistor is electrically connected to the negative input terminal of the primary side of the transformer, the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is electrically connected to the output terminal of the second OR gate. The drain of the fourth NMOS transistor is electrically connected to the second terminal of the resonant inductor, the source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is electrically connected to the output terminal of the first OR gate. The drain of the fifth NMOS transistor is used to output rectified DC power, the source of the fifth NMOS transistor is electrically connected to the positive output terminal of the secondary side of the transformer, and the gate of the fifth NMOS transistor is used to receive the first auxiliary signal. The drain of the sixth NMOS transistor is used to output rectified DC power, the source of the sixth NMOS transistor is electrically connected to the negative output terminal of the secondary side of the transformer, and the gate of the sixth NMOS transistor is used to receive the second auxiliary signal. The drain of the seventh NMOS transistor is electrically connected to the positive output terminal of the secondary side of the transformer, the source of the seventh NMOS transistor is grounded, and the gate of the seventh NMOS transistor is used to receive the second auxiliary signal. The drain of the eighth NMOS transistor is electrically connected to the negative output terminal of the secondary side of the transformer, the source of the eighth NMOS transistor is grounded, and the gate of the eighth NMOS transistor is used to receive the first auxiliary signal. One end of the magnetizing inductor is electrically connected to the positive input terminal of the primary side of the transformer, and the other end of the magnetizing inductor is electrically connected to the negative input terminal of the primary side of the transformer.

5. A DC-DC converter circuit according to claim 4, characterized in that, It also includes a filter sub-circuit, which comprises a filter inductor and a filter capacitor, wherein: The drains of the fifth NMOS transistor and the sixth NMOS transistor are respectively electrically connected to the first terminal of the filter inductor, and the second terminal of the filter inductor is used to output DC power to an external load. The first terminal of the filter capacitor is electrically connected to the second terminal of the filter inductor, and the second terminal of the filter capacitor is grounded.

6. A DC-DC converter, characterized in that, The system includes a DC-DC converter circuit and a digital signal processor. The DC-DC converter circuit includes a primary-side full-bridge sub-circuit, a transformer module, and a secondary-side rectifier sub-circuit. The primary-side full-bridge sub-circuit includes a first primary upper bridge arm, a second primary upper bridge arm, a first primary lower bridge arm, and a second primary lower bridge arm, all of which are activated when a high-level signal is received. The first primary upper bridge arm and the second primary lower bridge arm form a primary-side first bridge arm group, and the second primary upper bridge arm and the first primary lower bridge arm form a primary-side second bridge arm group. The secondary-side rectifier sub-circuit includes a secondary-side first bridge arm group and a secondary-side second bridge arm group, both of which are activated when a high-level signal is received. The digital signal processor generates a first drive signal, a second drive signal, a first auxiliary signal, a second auxiliary signal, and a control signal. Wherein: The first drive signal and the second drive signal are complementary, and there is a dead time between the first drive signal and the second drive signal; The digital signal processor controls the primary side first bridge arm group through the first drive signal and controls the primary side second bridge arm group through the second drive signal, so that the primary side first bridge arm group and the primary side second bridge arm group are alternately turned on, thereby enabling the primary side first bridge arm group and the primary side second bridge arm group to perform AC conversion on the input DC power in a hard-switching working state and output AC power to the transformer module. The digital signal processor controls the secondary side first bridge arm group to be turned on or off in accordance with the primary side second bridge arm group through the first auxiliary signal, and controls the secondary side second bridge arm group to be turned on or off in accordance with the primary side first bridge arm group through the second auxiliary signal, thereby enabling the secondary side first bridge arm group and the secondary side second bridge arm group to synchronously rectify the AC power input to the transformer module in accordance with the primary side second bridge arm group and the primary side first bridge arm group; The DC-DC converter circuit responds to the control signal, and when the control signal switches to a high level: The second auxiliary signal is connected to the control terminal of the second lower bridge arm of the primary side, and the first auxiliary signal is connected to the control terminal of the first lower bridge arm of the primary side, so that the second lower bridge arm and the first lower bridge arm of the primary side are turned on during the dead time, thereby causing the first bridge arm group and the second bridge arm group of the primary side to form a resonant network during the dead time, thereby causing the first bridge arm group and the second bridge arm group of the primary side to switch to soft switching operation state to perform AC conversion on the input DC power.

7. A DC-DC converter according to claim 6, characterized in that, The first auxiliary signal and the second auxiliary signal are generated by the digital signal processor based on the first driving signal and the second driving signal, and include: A first auxiliary signal is generated such that the pulse width of the first auxiliary signal completely covers the pulse width of the second driving signal, and the pulse width of the first auxiliary signal is within the low level time of the first driving signal, so that the first auxiliary signal can control the secondary side first bridge arm group to be turned on or off following the primary side second bridge arm group. The low-level time of the first auxiliary signal is configured to be greater than the pulse width time of the first driving signal, and the pulse width time of the first auxiliary signal is made less than the low-level time of the first driving signal, so that the first auxiliary signal can enable the primary side first bridge arm group and the primary side second bridge arm group to form a resonant network during the dead time. A second auxiliary signal is generated such that the pulse width of the second auxiliary signal completely covers the pulse width of the first driving signal, and the pulse width of the second auxiliary signal is within the low level time of the second driving signal, so that the second auxiliary signal can control the secondary side second bridge arm group to be turned on or off following the primary side first bridge arm group. The low-level time of the second auxiliary signal is configured to be greater than the pulse width time of the second driving signal, and the pulse width time of the second auxiliary signal is made less than the low-level time of the second driving signal, so that the second auxiliary signal can enable the primary side first bridge arm group and the primary side second bridge arm group to form a resonant network during the dead time. The first auxiliary signal and the second auxiliary signal have a high-level overlap time.

8. A DC-DC converter according to claim 6 or 7, characterized in that, The DC-DC converter circuit includes a logic control sub-circuit, which includes a first AND gate, a second AND gate, a first OR gate, and a second OR gate. The first input terminal of the second AND gate is used for a control signal, the second input terminal of the second AND gate is used to receive a second auxiliary signal, and the output terminal of the second AND gate is electrically connected to the first input terminal of the first OR gate. The second input terminal of the first OR gate is used to receive the first driving signal, and the output terminal of the first OR gate is electrically connected to the control terminal of the primary side second lower bridge arm. The first input terminal of the first AND gate is used to receive a control signal, the second terminal of the first AND gate is used to receive a first auxiliary signal, and the output terminal of the first AND gate is electrically connected to the first input terminal of the second OR gate. The second input terminal of the second OR gate is used to receive the second drive signal, and the output terminal of the second OR gate is electrically connected to the control terminal of the first lower bridge arm of the primary side.

9. A DC-DC converter according to claim 8, characterized in that, The primary-side full-bridge circuit includes a resonant inductor; the first upper arm of the primary side includes a first NMOS transistor; the second upper arm of the primary side includes a second NMOS transistor; the first lower arm of the primary side includes a third NMOS transistor; the second lower arm of the primary side includes a fourth NMOS transistor; the first group of secondary-side bridge arms includes a fifth and an eighth NMOS transistor; the second group of secondary-side bridge arms includes a sixth and a seventh NMOS transistor; and the transformer module includes a magnetizing inductor and a transformer, wherein: The first end of the resonant inductor is electrically connected to the positive input terminal of the primary side of the transformer; The drain of the first NMOS transistor is used to receive the input DC power, the source of the first NMOS transistor is electrically connected to the negative input terminal of the primary side of the transformer, and the gate of the first NMOS transistor is used to receive the first drive signal. The drain of the second NMOS transistor is used to receive the input DC power, the source of the second NMOS transistor is electrically connected to the second terminal of the resonant inductor, and the gate of the second NMOS transistor is used to receive the second drive signal. The drain of the third NMOS transistor is electrically connected to the negative input terminal of the primary side of the transformer, the source of the third NMOS transistor is grounded, and the gate of the third NMOS transistor is electrically connected to the output terminal of the second OR gate. The drain of the fourth NMOS transistor is electrically connected to the second terminal of the resonant inductor, the source of the fourth NMOS transistor is grounded, and the gate of the fourth NMOS transistor is electrically connected to the output terminal of the first OR gate. The drain of the fifth NMOS transistor is used to output rectified DC power, the source of the fifth NMOS transistor is electrically connected to the positive output terminal of the secondary side of the transformer, and the gate of the fifth NMOS transistor is used to receive the first auxiliary signal. The drain of the sixth NMOS transistor is used to output rectified DC power, the source of the sixth NMOS transistor is electrically connected to the negative output terminal of the secondary side of the transformer, and the gate of the sixth NMOS transistor is used to receive the second auxiliary signal. The drain of the seventh NMOS transistor is electrically connected to the positive output terminal of the secondary side of the transformer, the source of the seventh NMOS transistor is grounded, and the gate of the seventh NMOS transistor is used to receive the second auxiliary signal. The drain of the eighth NMOS transistor is electrically connected to the negative output terminal of the secondary side of the transformer, the source of the eighth NMOS transistor is grounded, and the gate of the eighth NMOS transistor is used to receive the first auxiliary signal. One end of the magnetizing inductor is electrically connected to the positive input terminal of the primary side of the transformer, and the other end of the magnetizing inductor is electrically connected to the negative input terminal of the primary side of the transformer.

10. A DC-DC converter according to claim 9, characterized in that, It also includes a filter sub-circuit, which comprises a filter inductor and a filter capacitor, wherein: The drains of the fifth NMOS transistor and the sixth NMOS transistor are respectively electrically connected to the first terminal of the filter inductor, and the second terminal of the filter inductor is used to output DC power to an external load. The first terminal of the filter capacitor is electrically connected to the second terminal of the filter inductor, and the second terminal of the filter capacitor is grounded.

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