Circuit board and electronic device

Abstract

This application discloses a circuit board and an electronic device. The circuit board includes a motherboard layer, a first frame layer, a first sub-board layer, a first device, and a second device. The motherboard layer has a cutout area, a first layout area, and a second layout area, which are located on opposite sides of the cutout area. The first frame layer is stacked on the first layout area, and the first sub-board layer is stacked on the side of the first frame layer facing away from the motherboard layer. The first device is disposed on the motherboard layer, and the second device is disposed on the first sub-board layer. By stacking a first sub-board layer on the motherboard layer, this application can obtain a larger layout area in the Z-direction space through a stacking method, that is, increase the layout area of ​​the circuit board. At this time, the first device can be disposed on the motherboard layer and the second device can be disposed on the first sub-board layer, thereby satisfying the layout and wiring requirements of devices and circuits.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, specifically to a circuit board and an electronic device comprising the circuit board. Background Technology

[0002] Because electronic devices (such as mobile phones and tablets) typically have a fixed size and thickness, the space available for assembling the motherboard is limited, preventing the motherboard from being made too large. However, as electronic devices become more powerful and their motherboards more complex, with an increasing number of components and circuits, the current motherboard size is insufficient to accommodate the layout of these components and circuits. Summary of the Invention

[0003] In order to overcome the problems existing in the prior art, the main objective of this application is to provide a circuit board that can meet the layout requirements of devices and circuits.

[0004] To achieve the above objectives, this application specifically adopts the following technical solution: In a first aspect, this application provides a circuit board for use in an electronic device, the circuit board comprising: The motherboard layer has a cutout area, a first layout area and a second layout area, with the first layout area and the second layout area located on opposite sides of the cutout area; A first frame plate layer is stacked on the first layout area; The first sub-board layer is stacked on the side of the first frame plate layer facing away from the main board layer; A first device, wherein the first device is disposed on the motherboard layer; and The second device is disposed on the first sub-board layer.

[0005] In some embodiments, the motherboard layer transmits signals to the first sub-board layer via signal lines disposed inside the first frame board layer.

[0006] In some embodiments, the first frame plate layer has an annular structure, and the periphery of the first sub-plate layer is flush with the periphery of the first frame plate layer.

[0007] In some embodiments, the circuit board further includes a third frame layer and a second sub-board layer, the third frame layer being stacked on the side of the first sub-board layer opposite to the first frame layer, and the second sub-board layer being stacked on the side of the third frame layer opposite to the first sub-board layer, the second sub-board layer being provided with at least one of the second devices.

[0008] Secondly, this application also provides a circuit board for use in electronic devices, the circuit board comprising: Motherboard layer; A first frame plate layer is stacked on the main plate layer; The first sub-board layer is stacked on the side of the first frame plate layer facing away from the main board layer; A first device, wherein the first device is disposed on the motherboard layer; and The second device is disposed on the first sub-board layer.

[0009] This embodiment stacks a first sub-board layer on the motherboard layer, thereby gaining a larger layout area in the Z-direction space through stacking, which increases the layout area of ​​the circuit board. At this time, the first device can be placed on the motherboard layer and the second device can be placed on the first sub-board layer, thus meeting the layout and wiring requirements of the devices and circuits.

[0010] In some embodiments, the motherboard layer has a cutout area, a first layout area, and a second layout area, with the first layout area and the second layout area located on opposite sides of the cutout area. The circuit board further includes a wiring layer and a second frame plate layer, with the first frame plate layer, the second frame plate layer, and the wiring layer stacked alternately in the first layout area. The wiring layer is located between the first frame plate layer and the second frame plate layer, extending from the first layout area to the second layout area. The first sub-board layer is stacked on the first frame plate layer and the second frame plate layer. Because this embodiment includes a wiring layer extending from the first layout area to the second layout area, signals between the first and second layout areas can be connected through the wiring layer, satisfying the signal connection requirements of the left and right sides of the motherboard layer.

[0011] In some embodiments, the first sub-board layer is stacked on the side of the first frame board layer away from the main board layer and extends to the second frame board layer. In this embodiment, because the first sub-board layer is stacked on the side of the first frame board layer opposite to the main board layer and extends to the second frame board layer, the signal lines within the first sub-board layer can electrically connect the various second devices located on the first sub-board layer without requiring the signal lines connecting the second devices on the first sub-board layer to pass through the first and second frame board layers. This results in shorter connections and fewer through-holes between the second devices, thereby reducing signal insertion loss.

[0012] In some embodiments, the first frame layer and the second frame layer have the same thickness, and the wiring layer has a thickness less than the thicknesses of the first frame layer and the second frame layer. This embodiment, by making the first frame layer and the second frame layer the same thickness, allows the first sub-board layer to be positioned parallel to the main board layer, enhancing the support stability of the first frame layer and the second frame layer for the first sub-board layer. By making the wiring layer thinner than the thicknesses of the first frame layer and the second frame layer, contact between the wiring layer and the first sub-board layer is avoided, preventing mutual interference, while also fully utilizing the space between the wiring layer and the first sub-board layer for device placement.

[0013] In some embodiments, the first frame plate layer has a ring structure. By setting the first frame plate layer to a ring structure, this embodiment can more stably support the first sub-plate layer and reduce the volume of the first frame plate layer, thereby reducing costs.

[0014] In some embodiments, the circuit board further includes a third frame layer and a second sub-board layer. The third frame layer is stacked on the side of the first sub-board layer facing away from the first frame layer, and the second sub-board layer is stacked on the side of the third frame layer facing away from the first sub-board layer. The second sub-board layer is provided with at least one of the second devices. This embodiment, by providing a second sub-board layer, further increases the layout area of ​​the circuit board by stacking the components to gain a larger layout area in the Z-direction.

[0015] In some embodiments, the third frame plate layer has a ring structure. This embodiment, by setting the third frame plate layer to a ring structure, can more stably support the second sub-plate layer and reduce the volume of the third frame plate layer, thus lowering costs.

[0016] In some embodiments, the first sub-board layer includes a first portion and a second portion, the first portion being stacked on the side of the first frame board layer facing away from the main board layer, and the second portion being stacked on the side of the second frame board layer facing away from the main board layer, wherein the first portion and the second portion are respectively provided with at least one second device.

[0017] In some embodiments, the circuit board further includes a third frame layer and a second sub-board layer, the third frame layer being stacked on the side of the first portion opposite to the first frame layer, and the second sub-board layer being stacked on the side of the third frame layer opposite to the first portion, and the second sub-board layer further comprising at least one of the second devices.

[0018] In some embodiments, the first device includes at least one of a system-on-a-chip, a general-purpose flash memory chip, a power management unit, a fast charging chip, an audio codec chip, an audio amplifier, a screen driver chip, a board-to-board connector, a resistor, a capacitor, and an inductor; the second device includes at least one of a radio frequency transceiver, a power amplifier, a low-noise amplifier, a combiner switch, a filter, a duplexer, a wire-opening switch, and a wire-opening spring.

[0019] Accordingly, this application also provides an electronic device, the electronic device comprising: The outer casing surrounds and forms a receiving cavity; A circuit board is disposed within the receiving cavity, and the circuit board includes a main board layer, a first frame board layer, a first sub-board layer, a first device, and a second device. The first frame board layer is stacked on the main board layer, the first sub-board layer is stacked on the side of the first frame board layer facing away from the main board layer, the first device is disposed on the main board layer, and the second device is disposed on the first sub-board layer.

[0020] This embodiment stacks a first sub-board layer on the motherboard layer, thereby gaining a larger layout area in the Z-axis space inside the electronic device by stacking. This allows for full utilization of the internal space of the electronic device to meet the layout and wiring requirements of devices and circuits. At the same time, it can save more space in the X and Y axes for the layout of a larger battery, thereby meeting the user's battery life requirements for the electronic device.

[0021] In some embodiments, a camera assembly is further included. The housing has a light-transmitting hole, and the motherboard layer has a cutout area, a first layout area, and a second layout area. The first layout area and the second layout area are located on opposite sides of the cutout area. The first frame plate layer is stacked on the first layout area, and the camera assembly is mounted in the cutout area, opposite to the light-transmitting hole. This embodiment, by providing a cutout area on the motherboard layer and mounting the camera assembly in the cutout area, can fully utilize the Z-axis space inside the electronic device to mount the camera assembly, avoiding the impact of the camera assembly's height in the Z-axis on the thickness of the electronic device.

[0022] In some embodiments, the circuit board further includes a wiring layer and a second frame layer. The first frame layer, the second frame layer, and the wiring layer are stacked at intervals in the first layout area, and the wiring layer is located between the first frame layer and the second frame layer. The wiring layer extends from the first layout area to the second layout area, and the first sub-board layer is stacked on the first frame layer and the second frame layer. Because this embodiment includes a wiring layer extending from the first layout area to the second layout area, signals between the first and second layout areas can be connected through the wiring layer, satisfying the signal connection requirements of the left and right sides of the motherboard layer.

[0023] In some embodiments, the first sub-board layer is stacked on the first frame board layer and extends to the second frame board layer. In this embodiment, since the first sub-board layer is stacked on the side of the first frame board layer facing away from the main board layer and extends to the second frame board layer, the signal lines within the first sub-board layer can electrically connect the various second devices located on the first sub-board layer. This eliminates the need for the signal lines connecting the second devices on the first sub-board layer to pass through the first and second frame board layers, resulting in shorter connections and fewer through-holes between the second devices, thereby reducing signal insertion loss.

[0024] In some embodiments, the first sub-board layer includes a first portion and a second portion, the first portion being stacked on the side of the first frame board layer facing away from the main board layer, and the second portion being stacked on the side of the second frame board layer facing away from the main board layer, wherein the first portion and the second portion are respectively provided with at least one second device.

[0025] In some embodiments, the circuit board further includes a third frame layer and a second sub-board layer, the third frame layer being stacked on the side of the first sub-board layer opposite to the first frame layer, and the second sub-board layer being stacked on the side of the third frame layer opposite to the first sub-board layer, the second sub-board layer being provided with at least one of the second devices.

[0026] In some embodiments, the camera assembly includes a camera decorative element and a camera module. The camera decorative element is mounted on the light-transmitting hole, and the camera module is mounted on the cut-out area. The position of the camera module corresponds to the position of the camera decorative element. At least a portion of the third frame board layer, the second sub-board layer, and the second device disposed on the second sub-board layer are located within the internal space of the camera decorative element. This embodiment, by having at least a portion of the third frame board layer, the second sub-board layer, and the second device disposed on the second sub-board layer of the circuit board located within the internal space of the camera decorative element, can fully utilize the internal space of the electronic device and avoid wasting the empty space of the electronic device.

[0027] The circuit board of this application includes a main board layer, a first frame board layer, a first sub-board layer, a first device, and a second device. The main board layer has a cutout area, a first layout area, and a second layout area, which are located on opposite sides of the cutout area. The first frame board layer is stacked on the first layout area, and the first sub-board layer is stacked on the side of the first frame board layer facing away from the main board layer. The first device is disposed on the main board layer, and the second device is disposed on the first sub-board layer. Compared with related technologies, this application, by stacking a first sub-board layer on the main board layer, can obtain a larger layout area in the Z-direction space through a stacking method, that is, increase the layout area of ​​the circuit board. At this time, the first device can be disposed on the main board layer and the second device can be disposed on the first sub-board layer, thereby satisfying the layout and routing requirements of devices and circuits. Attached Figure Description

[0028] Figure 1 This is a top view of the circuit board provided in Embodiment 1 of this application.

[0029] Figure 2 This is a perspective view of the circuit board provided in Embodiment 1 of this application.

[0030] Figure 3 for Figure 1 The cross-sectional view at EE in the diagram.

[0031] Figure 4 This is a top view of the circuit board provided in Embodiment 2 of this application.

[0032] Figure 5 This is a perspective view of the circuit board provided in Embodiment 2 of this application.

[0033] Figure 6 for Figure 4 The cross-sectional view at EE in the diagram.

[0034] Figure 7 This is a top view of the circuit board provided in Embodiment 3 of this application.

[0035] Figure 8 This is a perspective view of the circuit board provided in Embodiment 3 of this application.

[0036] Figure 9 for Figure 7 The cross-sectional view at EE in the diagram.

[0037] Figure 10 This is a top view of the circuit board provided in Embodiment 4 of this application.

[0038] Figure 11 This is a perspective view of the circuit board provided in Embodiment 4 of this application.

[0039] Figure 12 for Figure 10 The cross-sectional view at EE in the diagram.

[0040] Figure 13 This is a top view of the circuit board provided in Embodiment 5 of this application.

[0041] Figure 14 This is a perspective view of the circuit board provided in Embodiment 5 of this application.

[0042] Figure 15 for Figure 13 The cross-sectional view at EE in the diagram.

[0043] Figure 16 This is a top view of the circuit board provided in Embodiment Six of this application.

[0044] Figure 17 This is a perspective view of the circuit board provided in Embodiment Six of this application.

[0045] Figure 18 for Figure 16 The cross-sectional view at EE in the diagram.

[0046] Figure 19 This is a diagram of the signal hole structure on the circuit board.

[0047] Figure 20 A top view of the electronic device provided in the embodiments of this application.

[0048] Figure 21 for Figure 20 Cross-sectional view at FF.

[0049] Attached image labels: 1. Mainboard layer; 11. Cutout area; 12. First layout area; 13. Second layout area; 2. First frame board layer; 3. Second frame board layer; 4. Third frame board layer; 5. Wiring layer; 6. First sub-board layer; 61. First part; 62. Second part; 7. Second sub-board layer; 8. First component; 9. Second component; 10. Shielding cover; 100. Circuit board; 101. Signal hole; 102. Ground hole; 200. Housing; 201. Light-transmitting hole; 300. Camera assembly; 301. Camera decorative part; 302. Camera module; 400. Screen module. Detailed Implementation

[0050] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0051] In the description of this application, unless otherwise expressly specified and limited, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance; unless otherwise specified or explained, the term "multiple" refers to two or more; the terms "connected," "fixed," etc., should be interpreted broadly. For example, "connected" can be a fixed connection, a detachable connection, an integral connection, or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0052] In the description of this specification, it should be understood that the directional terms such as "upper" and "lower" used in the embodiments of this application are used to describe the position relative to the screen. When the circuit board is installed in the housing of the electronic device, the side of each board layer closer to the screen is the upper surface, and the side farther from the screen is the lower surface. In addition, in the context, it should also be understood that when it is mentioned that one element is connected to another element "upper" or "lower", it can not only be directly connected to the other element "upper" or "lower", but also indirectly connected to the other element "upper" or "lower" through an intermediate element.

[0053] Electronic devices, such as mobile phones and tablets, typically include components such as a casing, screen, battery, circuit board, and camera assembly. The casing and screen are connected to form a housing cavity, within which the battery and circuit board are installed. The battery provides power to the entire electronic device, the circuit board controls its operation, and the screen displays relevant information. The casing also has a light-transmitting hole, and the camera assembly is installed inside the casing, opposite to this hole. The camera assembly enables the electronic device to perform a shooting function. The camera assembly includes a camera module and a camera decorative element. The camera decorative element is installed in the light-transmitting hole of the casing, and the camera module is mounted on the circuit board, corresponding to the camera decorative element.

[0054] In current technology, mobile phone camera components are generally centered, and their specifications are becoming increasingly sophisticated. This results in a larger cutout in the central area of ​​the motherboard due to the camera component, leading to narrower routing channels on the left and right sides of the motherboard. Furthermore, since numerous signals need to be interconnected between modules on the left and right sides of the motherboard, the routing channels connecting these signals directly through the motherboard are insufficient. Raised boards or sandwich solutions are needed to address this issue. Simultaneously, as smartphone hardware specifications increase, battery life demands grow, leading to larger batteries. However, due to limited internal space, the motherboard cannot be enlarged, resulting in a persistently limited available layout area. Therefore, multi-layer PCB stacking is required to gain more layout area by utilizing Z-axis spatial arrangement. The RF module layout sub-board has high requirements for signal insertion loss, especially from the RF signal common terminal to the antenna. To minimize signal insertion loss, traces need to be as short as possible and vias minimized.

[0055] Reference Figures 1 to 3 As shown, Figure 1 This is a top view of the circuit board provided in Embodiment 1 of this application. Figure 2 This is a perspective view of the circuit board provided in Embodiment 1. Figure 3 Figure 1 A cross-sectional view at EE. An embodiment of this application discloses a circuit board 100, which includes a main board layer 1, a first frame board layer 2, a first sub-board layer 6, first devices 8, and second devices 9. The main board layer 1 has a cutout area 11, a first layout area 12, and a second layout area 13. The cutout area 11 can be used to install a camera assembly. The first layout area 12 and the second layout area 13 are located on opposite sides of the cutout area 11 and can be used to lay out devices and circuits. The first frame board layer 2 is stacked on the first layout area 12 of the main board layer 1, and the first sub-board layer 6 is stacked on the side of the first frame board layer 2 facing away from the main board layer 1. There can be multiple first devices 8, each disposed on the main board layer 1. There can also be multiple second devices 9, each disposed on the first sub-board layer 6, and at least some of the second devices 9 located on the first sub-board layer 6 can be electrically connected via signal lines C. Among them, the first device 8 can be a baseband device of an electronic device, such as a system on a chip (SOC), a universal flash storage chip (UFS), a power management unit (PMU), a fast charging chip, a codec chip (audio codec chip), an audio amplifier, an LCD (screen) driver chip, a board-to-board connector (BTB connector), resistors, capacitors, inductors, etc.; the second device 9 can be a radio frequency transceiver (RFIC), a radio frequency PA (power amplifier), a low noise amplifier (LNA), a combiner switch, a filter, a duplexer, an antenna switch, an antenna spring, etc. The wiring layer 5 can be laid out with the board-to-board connector of the camera and other peripheral supporting devices, etc.

[0056] In this embodiment, since each second device 9 is disposed on the first sub-board layer 6, the second devices 9 can be electrically connected through the signal lines within the first sub-board layer 6. If some of the second devices 9 are disposed on the first sub-board layer 6 and some on the main board layer 1, the signal lines between the second devices 9 on the first sub-board layer 6 and the second devices 9 on the main board layer 1 would need to pass through the first frame layer 2. However, in this embodiment, the signal lines used to electrically connect the second devices 9 do not need to pass through the first frame layer 2, thereby making the connection between the second devices 9 shorter, reducing the number of signal vias, and lowering the signal insertion loss (insertion loss is used to describe the degree of signal attenuation during transmission). At the same time, by stacking the first sub-board layer 6 on the main board layer 1, this embodiment can obtain a larger layout area in the Z-direction space by stacking, thereby increasing the layout area of ​​the circuit board. At this time, the first device 8 can be disposed on the main board layer 1 and the second device 9 can be disposed on the first sub-board layer 6, thereby satisfying the layout and wiring requirements of the devices and lines.

[0057] Continue to refer to Figure 3 As shown, the motherboard layer 1 and the first sub-board layer 6 are connected by a first frame layer 2. That is, the first sub-board layer 6 is elevated above the motherboard layer 1 via the first frame layer 2, and the motherboard layer 1 can transmit signals to the first sub-board layer 6 through signal lines provided inside the first frame layer 2. For example, vias can be provided in the first frame layer 2, with wires inside the vias, so that at least some of the first devices 8 on the motherboard layer 1 can be electrically connected to at least some of the second devices 9 on the first sub-board layer 6 through the wires; or vias can be provided in the first frame layer 2, with conductive layers on the inner walls of the vias, so that at least some of the first devices 8 on the motherboard layer 1 can be electrically connected to at least some of the second devices 9 on the first sub-board layer 6 through the conductive layers. This forms a sandwich PCB stack structure. With the circuit board area remaining unchanged, by extending the circuit board in the Z direction (the thickness extension direction of the circuit board), the layout area of ​​the circuit board is increased because electronic devices can be placed not only on the motherboard layer 1 but also on the first sub-board layer 6.

[0058] Specifically, the first frame plate layer 2 is at least partially annular, and the periphery of the first sub-plate layer 6 is flush with the periphery of the first frame plate layer 2. Thus, the first frame plate layer 2 with an annular structure can more stably support the first sub-plate layer 6. At the same time, setting the first frame plate layer 2 as an annular structure can reduce the volume of the first frame plate layer 2 and increase the device layout area while reducing weight.

[0059] In some embodiments, refer to Figures 4 to 6 As shown, Figure 4 This is a top view of the circuit board provided in Embodiment 2 of this application. Figure 5 This is a perspective view of the circuit board provided in Embodiment 2. Figure 6 Figure 4A cross-sectional view at EE. In this embodiment, the circuit board 100 includes a main board layer 1, a first frame board layer 2, a second frame board layer 3, a wiring layer 5, a first sub-board layer 6, a first device 8, and a second device 9. The first sub-board layer 6 is divided into two parts: a first part 61 and a second part 62. The main board layer 1 has a cutout area 11, a first layout area 12, and a second layout area 13. The cutout area 11 can be used to assemble camera components. The first layout area 12 and the second layout area 13 are located on opposite sides of the cutout area 11 and are used for laying out devices and circuits. The first frame board layer 2, the wiring layer 5, and the second frame board layer 3 are stacked at intervals on the first layout area 12 of the main board layer 1, with the wiring layer 5 located between the first frame board layer 2 and the second frame board layer 3, extending from the first layout area 12 to the second layout area 13. The first part 61 is stacked on the side of the first frame board layer 2 facing away from the main board layer 1, and the second part 62 is stacked on the side of the second frame board layer 3 facing away from the main board layer 1. Multiple first devices 8 may be provided, and multiple first devices 8 are respectively provided on the motherboard layer 1; multiple second devices 9 may be provided, and multiple second devices 9 are respectively provided on the first part 61 and the second part 62, and at least some of the second devices 9 located in the first part 61 and at least some of the second devices 9 located in the second part 62 can be electrically connected through signal line C.

[0060] In this embodiment, since a wiring layer 5 is provided extending from the first layout area 12 of the motherboard layer 1 to the second layout area 13, the signals between the first layout area 12 and the second layout area 13 of the motherboard layer 1 can be connected through the wiring layer 5, thus satisfying the signal connection requirements of the left and right sides of the motherboard layer 1.

[0061] In some embodiments, refer to Figures 7 to 9 As shown, Figure 7 This is a top view of the circuit board provided in Embodiment 3 of this application. Figure 8 This is a perspective view of the circuit board provided in Embodiment 3. Figure 9 Figure 7A cross-sectional view at EE. In this embodiment, the circuit board 100 includes a main board layer 1, a first frame board layer 2, a second frame board layer 3, a wiring layer 5, a first sub-board layer 6, a first device 8, and a second device 9. The main board layer 1 has a cutout area 11, a first layout area 12, and a second layout area 13. The cutout area 11 can be used to install a camera assembly. The first layout area 12 and the second layout area 13 are located on opposite sides of the cutout area 11 and can be used to lay out devices and circuits. The first frame board layer 2, the second frame board layer 3, and the wiring layer 5 are stacked at intervals in the first layout area 12 of the main board layer 1, and the wiring layer 5 is located between the first frame board layer 2 and the second frame board layer 3, extending from the first layout area 12 of the main board layer 1 to the second layout area 13. The first sub-board layer 6 is stacked on the side of the first frame board layer 2 facing away from the main board layer 1 and extends to the second frame board layer 3. Multiple first devices 8 may be provided, and multiple first devices 8 are respectively provided on the main board layer 1; multiple second devices 9 may be provided, and multiple second devices 9 are respectively provided on the first sub-board layer 6, and at least some of the second devices 9 can be electrically connected through signal lines C provided in the first sub-board layer 6.

[0062] In this embodiment, since a wiring layer 5 extending from the first layout area 12 of the motherboard layer 1 to the second layout area 13 is provided, the signals between the first layout area 12 and the second layout area 13 of the motherboard layer 1 can be connected through the wiring layer 5, satisfying the signal connection requirements of the left and right sides of the motherboard layer 1. In addition, the first sub-board layer 6 is stacked on the side of the first frame board layer 2 facing away from the motherboard layer 1 and extends to the second frame board layer 3 (the first sub-board layer 6 crosses the wiring layer 5), and each second device 9 is respectively disposed on the first sub-board layer 6. Thus, each second device 9 can be electrically connected through the signal lines in the first sub-board layer 6, without having the signal lines for electrically connecting each second device 9 pass through the first frame board layer 2 and the second frame board layer 3. This results in shorter connections between the second devices 9, fewer connection vias, and reduced signal insertion loss.

[0063] In some embodiments, this application also discloses another specific implementation, referring to... Figures 10 to 12 As shown, Figure 10 This is a top view of the circuit board provided in Embodiment 4 of this application. Figure 11 This is a perspective view of the circuit board provided in Embodiment 4. Figure 12 Figure 10A cross-sectional view at EE. In this embodiment, the circuit board 100 includes a main board layer 1, a first frame board layer 2, a third frame board layer 4, a first sub-board layer 6, a second sub-board layer 7, a first device 8, and a second device 9. The main board layer 1 has a cutout area 11, a first layout area 12, and a second layout area 13. The cutout area 11 can be used to assemble camera components. The first layout area 12 and the second layout area 13 are located on opposite sides of the cutout area 11 and can be used to lay out devices and circuits. The first frame board layer 2 is stacked on the first layout area 12, and the first sub-board layer 6 is stacked on the side of the first frame board layer 2 facing away from the main board layer 1. The third frame board layer 4 is stacked on the side of the first sub-board layer 6 facing away from the first frame board layer 2, and the second sub-board layer 7 is stacked on the side of the third frame board layer 4 facing away from the first sub-board layer 6. Multiple first devices 8 may be provided, and multiple first devices 8 are respectively provided on the motherboard layer 1. Multiple second devices 9 may be provided, and multiple second devices 9 are respectively provided on the first sub-board layer 6 and the second sub-board layer 7. At least a portion of the second devices 9 located on the second sub-board layer 7 and at least a portion of the second devices 9 located on the first sub-board layer 6 can be electrically connected through signal line C.

[0064] In this embodiment, the second device 9 is disposed on the first sub-board layer 6 and the second sub-board layer 7, so that each second device 9 can be electrically connected through the signal lines in the second sub-board layer 7, the third frame board layer 4 and the first sub-board layer 6, without having the signal lines connecting each second device 9 pass through the first frame board layer 2. This makes the connection between the second devices 9 shorter and reduces the number of wire through-holes, thereby reducing signal insertion loss. For example, the combiner switch can be disposed on the second sub-board layer 7 and the antenna can be disposed on the first sub-board layer 6, thereby shortening the signal line from the combiner switch to the antenna and reducing the insertion loss of the RF common terminal signal (the signal from the combiner switch to the antenna can be called the RF common terminal signal).

[0065] In some embodiments, refer to Figures 13 to 15 As shown, Figure 13 This is a top view of the circuit board provided in Embodiment 5 of this application. Figure 14 This is a perspective view of the circuit board provided in Embodiment 5. Figure 15 Figure 13A cross-sectional view at EE. In this embodiment, the circuit board 100 includes a main board layer 1, a first frame board layer 2, a second frame board layer 3, a third frame board layer 4, a wiring layer 5, a first sub-board layer 6, a second sub-board layer 7, a first device 8, and a second device 9. The first sub-board layer 6 is divided into two parts: a first part 61 and a second part 62. The main board layer 1 has a cutout area 11, a first layout area 12, and a second layout area 13. The cutout area 11 can be used to install a camera assembly. The first layout area 12 and the second layout area 13 are located on opposite sides of the cutout area 11 and can be used to lay out devices and circuits. The first frame board layer 2, the wiring layer 5, and the second frame board layer 3 are stacked at intervals on the first layout area 12 of the main board layer 1, with the wiring layer 5 located between the first frame board layer 2 and the second frame board layer 3, extending from the first layout area 12 to the second layout area 13. The first part 61 is stacked on the side of the first frame board layer 2 facing away from the main board layer 1, and the second part 62 is stacked on the side of the second frame board layer 3 facing away from the main board layer 1. The third frame layer 4 is stacked on the side of the first portion 61 facing away from the first frame layer 2, and the second sub-frame layer 7 is stacked on the side of the third frame layer 4 facing away from the first sub-frame layer 6. Multiple first devices 8 may be provided, and these multiple first devices 8 are respectively disposed on the main board layer 1 and the wiring layer 5; multiple second devices 9 may be provided, and these multiple second devices 9 are respectively disposed on the second sub-frame layer 7, the first portion 61, and the second portion 62, and at least some of the second devices 9 located in the first portion 61 and at least some of the second devices 9 located in the second portion 62 can be electrically connected via signal lines C.

[0066] In this embodiment, since a wiring layer 5 is provided extending from the first layout area 12 of the motherboard layer 1 to the second layout area 13, the signals between the first layout area 12 and the second layout area 13 of the motherboard layer 1 can be connected through the wiring layer 5, thus satisfying the signal connection requirements of the left and right sides of the motherboard layer 1.

[0067] In some embodiments, refer to Figures 16 to 18 As shown, Figure 16 This is a top view of the circuit board provided in Embodiment Six of this application. Figure 17 This is a perspective view of the circuit board provided in Embodiment Six. Figure 18 Figure 16A cross-sectional view at EE. In this embodiment, the circuit board 100 includes a main board layer 1, a first frame board layer 2, a second frame board layer 3, a third frame board layer 4, a wiring layer 5, a first sub-board layer 6, a second sub-board layer 7, a first device 8, and a second device 9. The main board layer 1 has a cutout area 11, a first layout area 12, and a second layout area 13. The cutout area 11 can be used to install a camera assembly. The first layout area 12 and the second layout area 13 are located on opposite sides of the cutout area 11 and can be used to lay out devices and circuits. The first frame board layer 2, the second frame board layer 3, and the wiring layer 5 are stacked at intervals in the first layout area 12, and the wiring layer 5 is located between the first frame board layer 2 and the second frame board layer 3, extending from the first layout area 12 to the second layout area 13. The first sub-board layer 6 is stacked on the side of the first frame board layer 2 facing away from the main board layer 1 and extends to the second frame board layer 3. The third frame layer 4 is disposed on the side of the first sub-board layer 6 facing away from the first frame layer 2, and the second sub-board layer 7 is stacked on the side of the third frame layer 4 facing away from the first sub-board layer 6. Multiple first devices 8 may be provided, and these multiple first devices 8 are respectively disposed on the upper and lower surfaces of the main board layer 1 and the wiring layer 5. Multiple second devices 9 may be provided, and these multiple second devices 9 are respectively disposed on the upper and lower surfaces of the first sub-board layer 6 and the lower surface of the second sub-board layer 7. At least a portion of the second devices 9 located on the second sub-board layer 7 and at least a portion of the second devices 9 located on the first sub-board layer 6 can be electrically connected via signal lines C.

[0068] In this embodiment, the motherboard layer 1 and the first sub-board layer 6 are connected by a first frame plate layer 2 and a second frame plate layer 3. That is, the first sub-board layer 6 is elevated above the motherboard layer 1 through the first frame plate layer 2 and the second frame plate layer 3, and the motherboard layer 1 can transmit signals to the first sub-board layer 6 through the first frame plate layer 2. For example, a via can be formed in the first frame plate layer 2, and a wire can be provided in the via, so that at least some of the first devices 8 on the motherboard layer 1 can be electrically connected to at least some of the second devices 9 on the first sub-board layer 6 through the wire; or a via can be formed in the first frame plate layer 2, and a conductive layer is provided on the inner wall of the via, so that at least some of the first devices 8 on the motherboard layer 1 can be electrically connected to at least some of the second devices 9 on the first sub-board layer 6 through the conductive layer. The first sub-board layer 6 and the second sub-board layer 7 are connected by a third frame board layer 4. That is, the second sub-board layer 7 is mounted on the first sub-board layer 6 via the third frame board layer 4, and the second sub-board layer 7 can transmit signals to the first sub-board layer 6 through the third frame board layer 4. For example, a via can be formed in the third frame board layer 4, and a wire can be provided in the via, so that at least some of the second devices 9 on the first sub-board layer 6 can be electrically connected to at least some of the second devices 9 on the second sub-board layer 7 through the wire; or a via can be formed in the third frame board layer 4, and a conductive layer is provided on the inner wall of the via, so that at least some of the second devices 9 on the first sub-board layer 6 can be electrically connected to at least some of the second devices 9 on the second sub-board layer 7 through the conductive layer, thereby forming a five-piece PCB board stack structure. With the circuit board area unchanged, the arable area of ​​the circuit board is increased by extending the circuit board in the Z direction (the thickness extension direction of the circuit board). This is because, at this time, electronic devices can be arranged not only on the main board layer 1, but also on the first sub-board layer 6 and the second sub-board layer 7. In addition, by making the area of ​​the second sub-layer 7 smaller than that of the first sub-layer 6, the space inside the electronic device can be fully utilized.

[0069] Specifically, the first frame layer 2 and the second frame layer 3 have the same thickness, meaning they are set at the same height. The first frame layer 2 is soldered to the motherboard layer 1, and signal lines can be routed within it, allowing the first daughter board layer 6 to be electrically connected to the motherboard layer 1 via the first frame layer 2. The second frame layer 3 provides support, and its solder joints with the motherboard layer 1 and the first daughter board layer 6 are either ground network solder joints or empty network solder joints (non-functional solder joints). No signal lines are routed within them. Ground network solder joints are GND network attribute solder joints connected to the board's GND, while empty network solder joints are dummy network attribute solder joints, not connected to any network on the board; they can also be called dummy network solder joints. The thickness of the wiring layer 5 is less than the thickness of the first frame board layer 2 and the second frame board layer 3. The wiring layer 5 is soldered to the motherboard layer 1, passes between the first frame board layer 2 and the second frame board layer 3, and is located below the first sub-board layer 6. It extends from the first layout area 12 to the second layout area 13. Signal lines can be routed inside it to facilitate signal transmission between the first layout area 12 and the second layout area 13 of the motherboard layer 1.

[0070] Furthermore, both the first frame layer 2 and the third frame layer 4 are annular structures. The periphery of the portion of the first sub-layer 6 stacked on the first frame layer 2 is flush with the periphery of the first frame layer 2, and the periphery of the second sub-layer 7 is flush with the periphery of the third frame layer 4. Thus, the annular structure of the first frame layer 2 can more stably support the first sub-layer 6, and the annular structure of the third frame layer 4 can more stably support the second sub-layer 7. At the same time, making both the first frame layer 2 and the third frame layer 4 annular structures can reduce the volume of the first frame layer 2 and the third frame layer 4, and increase the device layout area while reducing weight.

[0071] In this embodiment, since a wiring layer 5 extending from the first layout area 12 to the second layout area 13 is provided, the signals between the first layout area 12 and the second layout area 13 can be connected through the wiring layer 5, satisfying the signal connection requirements of the left and right sides of the motherboard layer 1. Furthermore, the first sub-board layer 6 is stacked on the side of the first frame board layer 2 facing away from the motherboard layer 1 and extends to the second frame board layer 3 (the first sub-board layer 6 is positioned across the wiring layer 5). The second device 9 is disposed on the first sub-board layer 6 and the second sub-board layer 7, resulting in shorter interconnections and fewer through-holes between the second devices 9, thereby reducing signal insertion loss. For example, a combiner switch can be disposed on the second sub-board layer 7, and the antenna on the first sub-board layer 6, thereby shortening the signal line from the combiner switch to the antenna and reducing the insertion loss of the RF common terminal signal. Insertion loss describes the degree of signal attenuation during transmission.

[0072] For example, if the signal line between the combiner switch located on the second sub-board layer 7 and the antenna located on the first sub-board layer 6 needs to pass through the first frame board layer 2 and the second frame board layer 3, vias need to be opened on the first frame board layer 2 and the second frame board layer 3 to facilitate signal transmission. To ensure impedance continuity at the vias in the frame boards, multiple ground vias 102 are typically provided around the signal via 101. In this embodiment, six ground vias 102 are evenly distributed around the signal via 101. (Refer to...) Figure 19 As shown. Assume the thickness of the first frame layer 2 and the second frame layer 3 is 1.3mm, the solder joint spacing W1 (distance from the center point of the ground hole to the center point of the signal hole) of the first frame layer 2 and the second frame layer 3 is 0.6mm, the pad W2 (diameter of the ground hole or signal hole) is 0.4mm, and the insertion loss of a single via is -0.0328dB@2.2GHz and -0.0611@5GHz, where the insertion loss of a single via refers to the insertion loss of the signal passing through one frame layer. If designed according to the above parameters of the first frame layer 2 and the second frame layer 3, the scheme in which the signal lines of the electrical connector switch and the antenna pass through the first frame layer 2 and the second frame layer 3 have an insertion loss 0.0656dB@2.2GHz and 0.1222@5GHz greater than the scheme in this embodiment.

[0073] Accordingly, embodiments of this application also disclose an electronic device, referring to... Figure 20 and Figure 21 As shown, Figure 20 A top view of the electronic device provided in the embodiments of this application. Figure 21 for Figure 20 A cross-sectional view at the FF position. The electronic device includes a housing 200, a camera assembly 300, a screen module 400, and a circuit board 100 as described in embodiments four to six above. The housing 200 and the screen module 400 are connected to form a receiving cavity, and the housing 200 is provided with a light-transmitting hole 201. The circuit board 100 is disposed within the receiving cavity formed by the housing 200 and the screen module 400. The camera assembly 300 includes a camera decorative element 301 and a camera module 302. The camera decorative element 301 has a ring-shaped structure to form an internal space, and the camera decorative element 301 is fitted into the light-transmitting hole 201 of the housing 200. The camera module 302 is fitted into the cutout area 11 of the circuit board 100, and the position of the camera module 302 corresponds to the position of the camera decorative element 301. At least a portion of the third frame layer 4, the second sub-board layer 7, and the second device 9 disposed on the second sub-board layer 7 of the circuit board 100 are located within the internal space of the camera decorative element 301.

[0074] To prevent electromagnetic interference, the electronic device also includes a shielding cover 10, which covers the electronic components on the circuit board. The shielding cover 10 can shield the influence of external electromagnetic waves on the internal circuit and the electromagnetic waves generated inside from radiating outward, that is, it can shield the components on the circuit board.

[0075] In some embodiments, the electronic device may also include a housing, a camera assembly, and the circuit board 100 described in embodiments one to three above. The housing 200 and the screen module 400 are connected to form a receiving cavity. The circuit board 100 is disposed within the receiving cavity formed by the housing 200 and the screen module 400. The camera assembly 300 includes a camera decorative element 301 and a camera module 302. The camera decorative element 301 is fitted into the light-transmitting hole 201 of the housing 200, and the camera module 302 is fitted into the cutout area 11 of the circuit board 100, with the position of the camera module 302 corresponding to the position of the camera decorative element 301.

[0076] In this embodiment, by providing a third frame board layer 4 and a second sub-board layer 7 on the circuit board 100, the layout area of ​​the circuit board 100 is increased. At the same time, at least part of the third frame board layer 4, the second sub-board layer 7 and the second device 9 disposed on the second sub-board layer 7 are located in the internal space of the camera decoration member 301, thereby making full use of the internal space of the electronic device and avoiding the waste of the internal space of the electronic device.

[0077] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A circuit board used in electronic devices, characterized in that, include: The motherboard layer has a cutout area, a first layout area and a second layout area, with the first layout area and the second layout area located on opposite sides of the cutout area; A first frame plate layer is stacked on the first layout area; The first sub-board layer is stacked on the side of the first frame plate layer facing away from the main board layer; A first device, wherein the first device is disposed on the motherboard layer; as well as The second device is disposed on the first sub-board layer.

2. The circuit board according to claim 1, characterized in that, The motherboard layer transmits signals to the first sub-board layer through signal lines provided inside the first frame board layer.

3. The circuit board according to claim 1, characterized in that, The first frame plate layer has a ring structure, and the periphery of the first sub-plate layer is flush with the periphery of the first frame plate layer.

4. The circuit board according to any one of claims 1 to 3, characterized in that, The circuit board further includes a third frame board layer and a second sub-board layer. The third frame board layer is stacked on the side of the first sub-board layer opposite to the first frame board layer, and the second sub-board layer is stacked on the side of the third frame board layer opposite to the first sub-board layer. The second sub-board layer is provided with at least one second device.

5. A circuit board used in electronic devices, characterized in that, include: Motherboard layer; A first frame plate layer is stacked on the main plate layer; The first sub-board layer is stacked on the side of the first frame plate layer facing away from the main board layer; A first device, wherein the first device is disposed on the motherboard layer; as well as The second device is disposed on the first sub-board layer.

6. The circuit board according to claim 5, characterized in that, The motherboard layer has a cutout area, a first layout area and a second layout area, with the first layout area and the second layout area located on opposite sides of the cutout area; The circuit board further includes a wiring layer and a second frame layer. The first frame layer, the second frame layer and the wiring layer are stacked at intervals in the first layout area, and the wiring layer is located between the first frame layer and the second frame layer. The wiring layer extends from the first layout area to the second layout area, and the first sub-board layer is stacked on the first frame layer and the second frame layer.

7. The circuit board according to claim 6, characterized in that, The first sub-board layer is stacked on the side of the first frame plate layer away from the main board layer and extends to the second frame plate layer.

8. The circuit board according to claim 6, characterized in that, The first frame plate layer and the second frame plate layer have the same thickness, and the wiring layer has a thickness less than the thickness of the first frame plate layer and the second frame plate layer.

9. The circuit board according to claim 5, characterized in that, The first frame plate layer has a ring structure.

10. The circuit board according to any one of claims 6 to 9, characterized in that, The circuit board further includes a third frame board layer and a second sub-board layer. The third frame board layer is stacked on the side of the first sub-board layer opposite to the first frame board layer, and the second sub-board layer is stacked on the side of the third frame board layer opposite to the first sub-board layer. The second sub-board layer is provided with at least one second device.

11. The circuit board according to claim 10, characterized in that, The third frame plate layer has a ring structure.

12. The circuit board according to claim 6, characterized in that, The first sub-board layer includes a first part and a second part. The first part is stacked on the side of the first frame board layer facing away from the main board layer, and the second part is stacked on the side of the second frame board layer facing away from the main board layer. The first part and the second part are each provided with at least one second device.

13. The circuit board according to claim 12, characterized in that, The circuit board further includes a third frame board layer and a second sub-board layer. The third frame board layer is stacked on the side of the first portion opposite to the first frame board layer, and the second sub-board layer is stacked on the side of the third frame board layer opposite to the first portion. The second sub-board layer is also provided with at least one second device.

14. The circuit board according to claim 5, characterized in that, The first device includes at least one of a system-on-a-chip, a general-purpose flash memory chip, a power management unit, a fast charging chip, an audio codec chip, an audio amplifier, a screen driver chip, a board-to-board connector, a resistor, a capacitor, and an inductor; the second device includes at least one of a radio frequency transceiver, a power amplifier, a low-noise amplifier, a combiner switch, a filter, a duplexer, a wire-opening switch, and a wire-opening spring.

15. An electronic device, characterized in that, include: The outer casing surrounds and forms a receiving cavity; A circuit board is disposed within the receiving cavity, and the circuit board includes a main board layer, a first frame board layer, a first sub-board layer, a first device, and a second device. The first frame board layer is stacked on the main board layer, the first sub-board layer is stacked on the side of the first frame board layer facing away from the main board layer, the first device is disposed on the main board layer, and the second device is disposed on the first sub-board layer.

16. The electronic device according to claim 15, characterized in that, It also includes a camera assembly. The housing is provided with a light-transmitting hole. The motherboard layer is provided with a cutout area, a first layout area and a second layout area. The first layout area and the second layout area are respectively located on opposite sides of the cutout area. The first frame plate layer is stacked on the first layout area. The camera assembly is assembled in the cutout area and is opposite to the light-transmitting hole.

17. The electronic device according to claim 16, characterized in that, The circuit board further includes a wiring layer and a second frame layer. The first frame layer, the second frame layer and the wiring layer are stacked at intervals in the first layout area, and the wiring layer is located between the first frame layer and the second frame layer. The wiring layer extends from the first layout area to the second layout area, and the first sub-board layer is stacked on the first frame layer and the second frame layer.

18. The electronic device according to claim 17, characterized in that, The first sub-board layer is stacked on the first frame board layer and extends to the second frame board layer.

19. The electronic device according to claim 17, characterized in that, The first sub-board layer includes a first part and a second part. The first part is stacked on the side of the first frame board layer facing away from the main board layer, and the second part is stacked on the side of the second frame board layer facing away from the main board layer. The first part and the second part are each provided with at least one second device.

20. The electronic device according to any one of claims 16 to 19, characterized in that, The circuit board further includes a third frame board layer and a second sub-board layer. The third frame board layer is stacked on the side of the first sub-board layer opposite to the first frame board layer, and the second sub-board layer is stacked on the side of the third frame board layer opposite to the first sub-board layer. The second sub-board layer is provided with at least one second device.

21. The electronic device according to claim 20, characterized in that, The camera assembly includes a camera decorative element and a camera module. The camera decorative element is mounted on the light-transmitting hole, and the camera module is mounted on the hollowed-out area. The position of the camera module corresponds to the position of the camera decorative element. At least a portion of the third frame plate layer, the second sub-plate layer, and the second device disposed on the second sub-plate layer are located in the internal space of the camera decorative element.

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