A high-precision multi-channel TDC circuit applied to a laser radar
Through a three-level cascaded quantization architecture and signal synchronization design, the problem of insufficient resolution and nonlinear error in existing TDC in lidar is solved, realizing high-precision ranging and multi-target measurement, and adapting to the multi-channel integration requirements of lidar.
Patent Information
- Application Number
- CN202610457272.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-04-08
- Publication Date
- 2026-07-10
Smart Images
Figure CN122362770A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of mixed-signal integrated circuit technology, specifically to a high-precision multi-channel TDC (Time-to-Digital Converter) circuit for use in lidar. Background Technology
[0002] LiDAR calculates the distance to a target object by measuring the time interval (Time of Flight, ToF) between the emitted laser pulse and the reflected pulse received by the target. Its ranging accuracy is directly determined by the accuracy of the time interval measurement. In high-precision LiDAR applications such as autonomous driving, industrial surveying, and security monitoring, a time measurement resolution of less than 50 ps is typically required, along with support for a large dynamic range, continuous measurement of multiple targets, and strong anti-interference capabilities.
[0003] Existing TDC solutions mainly fall into two categories, both of which have unsolvable technical flaws: The first type is the TDC solution based on FPGA / CPLD. This type of solution has a short development cycle and simple structure and principle, but it has fatal shortcomings: the resolution of FPGA-TDC based on direct counting method can only reach the 5ns level, and the highest resolution of the optimized solution based on interpolation method can only reach 200ps, which cannot meet the high-precision ranging requirements of lidar. At the same time, this type of solution does not effectively compensate for nonlinear error and misalignment error, resulting in poor measurement stability, high error rate, and difficulty in achieving multi-channel integration.
[0004] The second type is the secondary structure TDC scheme based on CMOS technology, which adopts an architecture of "coarse counting + interpolation fine measurement". Although it can improve the measurement accuracy to a certain extent, it still has the following technical defects: 1. The charge pump of the delay phase-locked loop (DLL) suffers from current mismatch, charge injection, and charge shunting problems. The phase output of the voltage-controlled delay chain is not uniform, which introduces severe differential nonlinearity (DNL) and integral nonlinearity (INL), causing the measurement results to drift with temperature and voltage fluctuations. 2. The input pulse and the quantization clock are asynchronous, which can easily cause metastability of the trigger, leading to integer cycle counting errors (non-alignment errors), causing the ranging results to jump, which poses a serious safety hazard in vehicle autonomous driving scenarios; 3. The resolution of the two-level quantization architecture is limited by the process technology and cannot exceed 50ps, which cannot meet the requirements of high-precision lidar. 4. It cannot support continuous measurement of multiple received pulses, has a long measurement dead time, and cannot be adapted to multi-target ranging scenarios. Summary of the Invention
[0005] The purpose of this invention is to overcome the shortcomings of the prior art and provide a high-precision multi-channel TDC circuit for lidar, solving the technical problems of insufficient resolution, large nonlinear error, inability to eliminate misalignment error, small dynamic range, long dead time, and weak anti-interference capability of existing TDC circuits.
[0006] To achieve the above objectives, the technical solution of the present invention is implemented as follows: A high-precision multi-channel TDC circuit for lidar includes a delay phase-locked loop, an asynchronous counter, a phase detection circuit, a third-stage vernier measurement circuit, a decoding circuit, a data readout circuit, and a multi-event distribution circuit. The clock input terminal of the delay phase-locked loop is connected to an external 200MHz quantization clock, and the 16-channel phase-splitting clock output terminal is connected to the sampling clock input terminal of the phase detection circuit. This is used to divide the 200MHz quantization clock into 16 phases to generate 16 phase-splitting clocks with equal phase differences, which serve as the reference clock for the second-stage interpolation quantization. The clock terminal of the asynchronous counter is connected to a 200MHz quantization clock, and the start / stop control terminal is connected to the synchronous output terminal of the phase detection circuit to complete the first stage of coarse quantization of the time interval and expand the measurement dynamic range. The signal input terminal of the phase detection circuit is connected to the pulse output terminal of the multi-event distribution circuit, the one-hot code output terminal is connected to the input terminal of the decoding circuit, and the synchronization output terminal is simultaneously connected to the start / stop control terminal of the asynchronous counter and the first input terminal of the third-stage vernier measurement circuit, which is used to complete the second-stage interpolation quantization and synchronize the asynchronous transmit and receive pulse signals with the quantization clock to eliminate misalignment errors. The second input terminal of the third-level vernier measurement circuit is connected to the pulse output terminal of the multi-event distribution circuit, and the quantization result output terminal is connected to the first input terminal of the data readout circuit. This circuit is used to perform third-level fine quantization on the small time difference between the transmit and receive pulses and the rising edge of the adjacent phase clock, thereby achieving a measurement resolution of less than 50 ps. The output of the decoding circuit is connected to the second input of the data reading circuit, and is used to convert the 16-bit one-hot code into 4-bit binary data. The third input terminal of the data readout circuit is connected to the counting output terminal of the asynchronous counter, and is used to perform logical operations and splicing on the three-level quantization results to output the final time interval quantization result. The input terminal of the multi-event distribution circuit is connected to the transmitted pulse signal and the received pulse signal of the lidar, and the output terminal is simultaneously connected to the signal input terminal of the phase detection circuit and the third-level vernier measurement circuit, so as to realize continuous measurement of one transmitted pulse corresponding to multiple received pulses and reduce the measurement dead time.
[0007] Furthermore, the delay phase-locked loop includes a frequency and phase detector, a source-switched charge pump, a loop filter, a voltage-controlled delay chain, and a clock soft-start circuit, all cascaded in sequence. An operational amplifier is connected between the current mirror of the source-switched charge pump and the output node. Negative feedback ensures that the voltage of the current mirror and the output node are equal, guaranteeing accurate replication of the charging and discharging current. Each delay unit of the voltage-controlled delay chain adopts a differential structure, with built-in latches aligned with the upper and lower edges of the clock. Redundant delay units are added at both ends of the delay chain to reduce phase interval errors and differential nonlinearity.
[0008] Furthermore, the source-switched charge pump employs a source-switched structure to isolate the switching transistor and the current-source MOSFET, eliminating the charge injection problem of the switching digital signal; the drain of the current source is always connected to the output terminal, and the switching MOSFET is directly connected to the power supply and ground to form a low-impedance path, solving the charge shunting problem; a decoupling capacitor is connected between the gate of the current mirror MOSFET and the gate of the output node MOSFET to reduce current ripple; the input loop of the operational amplifier is equipped with a Miller capacitor and a zero-adjustment resistor for zero-pole compensation, improving the stability of the feedback loop.
[0009] Furthermore, each stage of the voltage-controlled delay chain consists of two parallel time-adjustable inverters and a latch composed of two inverters connected end to end; 2 to 3 redundant delay units are added to the beginning and end of the delay chain as load matching and buffering, and each stage of the phase clock output is equipped with a buffer. The buffer adopts a multi-stage inverter cascade structure, and the width-to-length ratio of each stage inverter is twice that of the previous stage.
[0010] Furthermore, the phase detection circuit is a three-stage cascaded D flip-flop array; wherein the clock terminal of the first-stage D flip-flop is connected to the 16-channel split-phase clock output of the delay phase-locked loop, and the input terminal is connected to the pulse output of the multi-event distribution circuit; the input terminal of the second-stage D flip-flop is connected to the output terminal of the first-stage D flip-flop, and the clock terminal is uniformly connected to a 200MHz quantization clock; the input terminal of the third-stage D flip-flop is connected to the output terminal of the second-stage D flip-flop, and the output terminal outputs a 16-bit one-hot code; the first output terminal of the first-stage D flip-flop serves as a synchronous output terminal and is connected to the start / stop control terminal of the asynchronous counter.
[0011] Furthermore, the third-stage vernier measurement circuit includes a delay circuit, a signal selection circuit, and a dual-channel vernier delay chain cascaded in sequence; the delay circuit is used to align the edges of the transmit and receive pulse signals with the synchronous clock signal output by the phase detection circuit; the signal selection circuit is used to extract the phase clock signals adjacent to the transmit and receive pulses; the dual-channel vernier delay chain uses the delay difference between the two delay units as the quantization step size to complete the fine quantization of small time differences.
[0012] Furthermore, the multi-event allocation circuit includes a pulse edge detection unit, a FIFO buffer unit, and a channel allocation unit cascaded in sequence; the pulse edge detection unit is used to identify the rising edge of multiple continuously input received pulses, the FIFO buffer unit is used to buffer the pulse signal, and the channel allocation unit is used to sequentially allocate multiple received pulses to the phase detection circuit and the third-stage vernier measurement circuit to achieve continuous measurement.
[0013] Furthermore, the asynchronous counter is a 9-bit asynchronous counter with a quantization step size of 5ns, which can cover the maximum time interval corresponding to 200-meter laser ranging; both the decoding circuit and the data readout circuit are written in Verilog hardware description language, and the output of the data readout circuit is parallel binary data, which can be directly connected to the main control FPGA chip of the lidar.
[0014] Beneficial effects: This invention adopts a three-level cascaded quantization architecture, balancing a large dynamic range and ultra-high resolution, ultimately achieving a measurement resolution of less than 50 ps, meeting the high-precision ranging requirements of lidar; this invention optimizes the architecture of the delay phase-locked loop, significantly suppressing nonlinear distortion, reducing differential nonlinearity error, and improving quantization clock accuracy and measurement stability; this invention uses a synchronized phase detection circuit to completely eliminate misalignment errors, avoid integer period counting errors caused by metastability, and reduce the measurement error rate; this invention has a built-in multi-event allocation circuit, supporting continuous measurement with one transmitter and multiple receivers, greatly reducing the measurement dead time, and is suitable for multi-target ranging scenarios of lidar; the circuit topology of this invention is simple, easy to integrate into multiple channels and apply on a large scale, has excellent noise immunity, and is compatible with CMOS technology and FPGA platforms. Attached Figure Description
[0015] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the high-precision multi-channel TDC circuit applied to lidar as described in an embodiment of the present invention; Figure 2 This is a schematic diagram illustrating the principle of the Nat interpolation method used in this invention; Figure 3 This is a schematic diagram of the delayed phase-locked loop in this invention; Figure 4 This is a schematic diagram of the charge pump used in the delayed phase-locked loop of this invention; Figure 5 This is a schematic diagram of the delay unit structure of the voltage-controlled delay chain of the delay phase-locked loop in this invention; Figure 6 This is a schematic diagram of the voltage-controlled delay chain of the delay phase-locked loop in this invention; Figure 7 This is a schematic diagram of the simulation results of the delay phase-locked loop in this invention; Figure 8 This is a schematic diagram of the phase detection circuit of the present invention; Figure 9 This is the simulation result of the present invention for the function of eliminating misalignment error; Figure 10 This is a schematic diagram of the third-stage vernier measurement circuit structure of the present invention; Figure 11 This is the first result of the overall functional test of the TDC of this invention; Figure 12 This is the second result of the overall functional test of the TDC of this invention; Figure 13 This is the third result of the overall functional test of the TDC of this invention; Figure 14 This is the fourth result of the overall functional test of the TDC of this invention; Figure 15 This is the fifth result of the overall functional test of the TDC of this invention. Detailed Implementation
[0016] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0017] Example 1 See Figures 1-15 A high-precision multi-channel TDC circuit for lidar includes a delay phase-locked loop 10, an asynchronous counter 20, a phase detection circuit 30, a third-stage vernier measurement circuit 40, a decoding circuit 50, a data readout circuit 60, and a multi-event distribution circuit 70. The clock input terminal of the delay phase-locked loop 10 is connected to an external 200MHz quantization clock, and the 16-channel phase-splitting clock output terminal is connected to the sampling clock input terminal of the phase detection circuit 30. This is used to perform 16-channel phase-splitting on the 200MHz quantization clock to generate 16 channels of phase-splitting clocks with equal phase differences, which serve as the reference clock for the second-stage interpolation quantization. The clock terminal of the asynchronous counter 20 is connected to a 200MHz quantization clock, and the start / stop control terminal is connected to the synchronous output terminal of the phase detection circuit 30, which is used to complete the first stage of coarse quantization of the time interval and expand the measurement dynamic range. The signal input terminal of the phase detection circuit 30 is connected to the pulse output terminal of the multi-event distribution circuit 70, the one-hot code output terminal is connected to the input terminal of the decoding circuit 50, and the synchronization output terminal is simultaneously connected to the start / stop control terminal of the asynchronous counter 20 and the first input terminal of the third-stage vernier measurement circuit 40, in order to complete the second-stage interpolation quantization and synchronize the asynchronous transmit and receive pulse signals with the quantization clock to eliminate misalignment errors. The second input terminal of the third-level vernier measurement circuit 40 is connected to the pulse output terminal of the multi-event distribution circuit 70, and the quantization result output terminal is connected to the first input terminal of the data readout circuit 60. This is used to perform third-level fine quantization on the small time difference between the transmit and receive pulses and the rising edge of the adjacent phase clock, so as to achieve a measurement resolution of less than 50 ps. The output of the decoding circuit 50 is connected to the second input of the data reading circuit 60, and is used to convert the 16-bit one-hot code into 4-bit binary data. The third input terminal of the data readout circuit 60 is connected to the counting output terminal of the asynchronous counter 20, and is used to perform logical operations and splicing on the three-level quantization results to output the final time interval quantization result. The input terminal of the multi-event distribution circuit 70 is connected to the transmitted pulse signal and the received pulse signal of the lidar, and the output terminal is simultaneously connected to the signal input terminal of the phase detection circuit 30 and the third-level vernier measurement circuit 40, so as to realize continuous measurement of one transmitted pulse corresponding to multiple received pulses and reduce the measurement dead time.
[0018] like Figure 1 As shown: To simultaneously ensure the dynamic range, measurement accuracy, and power consumption / area of the measurement, this embodiment employs a multi-stage structure based on Nat interpolation, namely integer counting plus interpolation measurement. The interpolation measurement uses a series of clock signals with fixed phase differences generated by the voltage-controlled delay chain of the DLL to measure the TDC transmit and receive signals, namely the Start and Stop signals. Its LSB is the clock period divided by the number of phases, such as... Figure 2 As shown, first, the number of integer cycles between the Start and Stop signals is calculated, and the integer part is read out. Then, the position in the periodic clock is determined by the phase split of the reference clock, and the fractional part is read out. Therefore, the final time interval is:
[0019] However, TDC based on Nat interpolation has a fatal flaw in practical applications, namely misalignment error, which will lead to integer-level errors.
[0020] The first stage uses the most basic direct counting method as the coarse counting part, mainly to provide high dynamic range. Compared with the direct counting method used alone, it does not require an excessively high frequency clock input. A 200MHz clock is proposed as the counting clock, i.e., a quantization scale value (bin size) of 5ns. The required measurement distance is 200 meters, and through simple calculation, the counter bit depth can be determined to be 9 bits.
[0021] Based on the direct counting method, the second stage further subdivides the time quantization scale using a phase-splitting technique based on DLLs. This stage further refines the scale while applying a symmetrical structure of a voltage-controlled delay chain to reduce nonlinear errors caused by interpolation stages. However, as the number of phases increases, the integral nonlinearity of the TDC gradually accumulates. Therefore, the number of phases cannot be excessive to ensure a small nonlinear error. The reference clock is divided into 16 phases by the voltage-controlled delay chain, meaning the clock is delayed by 1 / 16 phase sequentially through 16 delay units, resulting in a bin size of 5ns / 16 = 312.5ps. However, this still does not achieve the design requirement of a measurement accuracy below 50ps, so a third stage is needed to further reduce the scale.
[0022] To overcome the limitations of process technology and further improve the resolution to below the gate circuit delay level, a vernier method can generally be used. This involves chaining the Start / Stop signal and the adjacent phase clock through two delay units with different delays. In this case, the TDC resolution is the difference in delay between the two delay units, easily meeting the requirement of less than 50 ps. The first two stages have already reduced the range requiring vernier measurement; therefore, this embodiment does not require excessive chip resources and area.
[0023] The start / stop function is detected by the phase detection circuit, which controls the start and stop of the counter. The phase detection circuit sends the results of 16 phase detections to the decoder for decoding, thereby reading out the fractional part. Finally, the integer and fractional parts are input to terminals such as FPGAs via a serial interface for reading and calculation.
[0024] In summary, this embodiment adopts a three-level cascaded quantization + end-to-end signal synchronization workflow, and the signal flow and working logic are as follows: Front-end input: A 200MHz quantization clock is sent to a delay phase-locked loop, and the transmit / receive pulses of the lidar are sent to a multi-event distribution circuit for front-end processing; First-stage coarse quantization: The asynchronous counter uses a 200MHz clock as a reference and is controlled by the synchronization signal of the phase detection circuit to start and stop, completing the integer period counting of the time interval and covering a large dynamic measurement range; Second-stage interpolation quantization: The delay phase-locked loop divides the 200MHz clock into 16 phases to generate 16 equal-phase-difference reference clocks; the phase detection circuit compares the phase of the transmit and receive pulses with the phase-divided clocks, outputs a coarse value of the fractional part in one-hot code form, and synchronizes the asynchronous pulses with the quantization clock to eliminate misalignment errors; The third level of fine quantization: The vernier measurement circuit performs final quantization on the remaining tiny time difference between the transmit and receive pulses and the adjacent phase clock, achieving an ultra-high resolution of less than 50 ps; Output: The decoding circuit converts the one-hot code into binary data, the data readout circuit merges the three-level quantization results, and outputs the final time interval measurement value.
[0025] This embodiment is the first to combine a three-level architecture of coarse counting + DLL interpolation + vernier fine quantization with a multi-event distribution circuit, while taking into account a large dynamic range, ultra-high resolution and continuous measurement capability, thus solving the technical defect of existing TDCs that "accuracy and range cannot be achieved simultaneously". It clarifies the signal synchronization design of the entire link, and solves the misalignment error and integer count jump problem caused by asynchronous signals at the architecture level, which significantly reduces the measurement error rate. The connection relationship between modules and the signal flow are completely closed loop, the topology is simple, easy to integrate into multiple channels and fabricate with CMOS process technology, and adapts to the miniaturization and high integration requirements of LiDAR.
[0026] In a specific example, the delay phase-locked loop 10 includes a frequency and phase detector, a source-switched charge pump, a loop filter, a voltage-controlled delay chain, and a clock soft-start circuit, all cascaded in sequence. An operational amplifier is connected between the current mirror and the output node of the source-switched charge pump. Negative feedback ensures that the voltage of the current mirror and the output node are equal, guaranteeing accurate replication of the charging and discharging current. Each delay unit in the voltage-controlled delay chain adopts a differential structure, with a built-in latch aligned to the rising and falling edges of the clock. Redundant delay units are added at both ends of the delay chain to reduce phase interval errors and differential nonlinearity. The source-switched charge pump uses a source-switching structure to isolate the switching transistor and the current source MOSFET, eliminating charge injection problems in the switching digital signal. The drain of the current source is always connected to the output terminal, and the switching MOSFET and... The power supply and ground are directly connected to form a low-impedance path, solving the charge shunting problem; a decoupling capacitor is connected between the gate of the current mirror MOSFET and the gate of the output node MOSFET to reduce current ripple; the input loop of the operational amplifier is equipped with a Miller capacitor and a zero-adjustment resistor for zero-pole compensation, improving the stability of the feedback loop; each stage of the voltage-controlled delay chain consists of two parallel time-adjustable inverters and a latch composed of two inverters connected end to end; 2-3 stages of redundant delay units are added at the beginning and end of the delay chain for load matching and buffering; each stage of the phase-splitting clock output is equipped with a buffer, which adopts a multi-stage inverter cascade structure, and the width-to-length ratio of each stage inverter is twice that of the previous stage.
[0027] It should be noted that the structure of the delay phase-locked loop in this embodiment is as follows: Figure 3 As shown, a TDC based on a DLL structure can effectively mitigate the impact of PVT variations, thereby improving the stability and accuracy of the TDC. However, DLLs still have lock-out issues and require ensuring small static errors in the input and output clocks and uniformity of each output phase to reduce nonlinear errors. Simultaneously, while addressing these issues, the steady-state settling time should be minimized as much as possible.
[0028] Therefore, the delay phase-locked loop in this embodiment has been structurally improved as follows: Charge pump structure as follows Figure 4As shown, this structure isolates the switching transistor and the current source, thus eliminating the charge injection problem of the switching digital signal. Furthermore, the drain of the current source is always connected to the output, and the switching MOS is always directly connected to the power supply and ground, forming a low-impedance path and solving the charge shunting problem. In addition, the speed of the charge pump is improved because the drain and gate of the current source are always well biased, and the source impedance is low, meaning the charge pump has a high speed. However, the problem of PMOS and NMOS current mismatch still remains unresolved. Directly increasing the output impedance can indeed improve this problem, but it will increase the requirements of the circuit; for example, using a common-source, common-gate current source requires a higher power supply voltage. A better approach is to use the negative feedback of the op-amp to make the UP and DOWN voltages track each other, thus ensuring that the UP and DOWN currents accurately track the reference current of the current source, making them unaffected by the output voltage. Simultaneously, to further reduce the current ripple of the current mirror and the output, capacitor-connected NMOS transistors are added at the gates of the current mirror MOS and the output node MOS as decoupling capacitors, ensuring that the voltage at this node remains stable when the digital signal arrives, thereby ensuring the stability of the current mirror output current. To further improve the current tracking performance, a Miller capacitor and a zero-adjustment resistor can be added to the left loop of the operational amplifier to compensate for the zeros and poles, thereby increasing the stability of the feedback loop.
[0029] The voltage-controlled delay unit and the delay chain structure it forms are as follows: Figure 5 and Figure 6 As shown, the voltage-controlled delay chain (VDC) consists of multiple VDC delay units, each of which can change its propagation delay via voltage. Each VDC unit comprises two parallel, delay-adjustable inverters and a latch consisting of two inverters connected end-to-end. The resolution is based on the gate-level delay, i.e., the inverter's delay. The differential signal propagates through these two inverters, improving noise immunity compared to a single-ended structure. The latch better aligns the rising and falling edges, maintaining the phase difference between the two differential signals, resulting in more uniform rising edges in subsequent units and significantly reducing the static phase error of the DLL and the nonlinearity error of the TDC.
[0030] Based on the aforementioned delay units, they are connected in series to form a delay chain. Since the external input and output signals have different loads than the clock signals propagating in the delay chain, to further improve consistency and reduce nonlinearity and static phase errors, two to three more delay units are added at the beginning and end of the delay chain as buffers and loads, respectively. The 16 clock signals in the chain are used as interpolation stage outputs, and a buffer is added to each stage output. The width-to-length ratio of each inverter in the buffer is twice that of the previous stage, thereby ensuring sufficient driving capability.
[0031] In a specific example, the phase detection circuit 30 is a three-stage cascaded D flip-flop array; wherein the clock terminal of the first-stage D flip-flop is connected to the 16 phase-splitter clock outputs of the delay phase-locked loop 10, and the input terminal is connected to the pulse output terminal of the multi-event distribution circuit 70; the input terminal of the second-stage D flip-flop is connected to the output terminal of the first-stage D flip-flop, and the clock terminal is uniformly connected to a 200MHz quantization clock; the input terminal of the third-stage D flip-flop is connected to the output terminal of the second-stage D flip-flop, and the output terminal outputs a 16-bit one-hot code; the first output terminal of the first-stage D flip-flop serves as a synchronous output terminal and is connected to the start / stop control terminal of the asynchronous counter 20.
[0032] The first-stage D flip-flop array in this embodiment has 16 flip-flops whose clock terminals are respectively connected to 16 phase-splitting clocks, and whose input terminals are connected to transmit and receive pulses to achieve phase comparison between the pulses and the phase-splitting clocks, thus completing the first-stage sampling. Second-stage D flip-flop array: The sampling result of the first stage is resampled twice, and the asynchronous pulse signal is synchronized with the 200MHz system clock to restore the normal logic level under metastability and avoid flip-flop metastability; The third-level D flip-flop array latches the resampling result and generates a stable 16-bit one-hot code, corresponding to the position of the pulse within 16 phase clock intervals; The first output of the first-stage flip-flop is used as a synchronous start / stop signal and sent to the asynchronous counter to keep the start / stop of the counter at a fixed phase difference with the system clock, thus avoiding counting jumps.
[0033] The three-stage D flip-flop resampling structure in this embodiment completely eliminates misalignment errors caused by asynchronous signals, solves the most fatal integer cycle counting error problem in existing TDCs, and provides measurement results without jumps, significantly improving reliability. The pure sequential logic design has lower latency, smaller layout area, and stronger anti-interference capability compared to traditional combinational logic phase detection circuits. It directly outputs standard one-hot codes, which can be sent to the decoding circuit without additional conversion circuits, simplifying the design of subsequent circuit stages.
[0034] In a specific example, the third-stage vernier measurement circuit 40 includes a delay circuit, a signal selection circuit, and a dual-channel vernier delay chain cascaded in sequence; the delay circuit is used to align the edges of the transmit and receive pulse signals with the synchronous clock signal output by the phase detection circuit 30; the signal selection circuit is used to extract the phase clock signal adjacent to the transmit and receive pulses; the dual-channel vernier delay chain uses the delay difference between the two delay units as the quantization step size to complete the fine quantization of small time differences.
[0035] Delay circuit: Delays the transmit and receive pulse signals by a fixed duration to align them with the edge of the synchronous clock signal output by the phase detection circuit, ensuring timing matching of the two signals to be quantized; Signal selection circuit: Extracts the phase clock replacement signal adjacent to the transmit and receive pulses, locks the small time difference interval that needs to be quantized, and the maximum quantization range does not exceed 312.5ps; Dual-channel vernier delay chain: Two signals are fed into two delay chains with slightly different delay units. Quantization stops when the rising edges of the two signals coincide. The final resolution is the delay difference between the two delay units. The precise value of the tiny time difference is calculated by counting the number of delay units.
[0036] The fine quantization design based on the vernier method in this embodiment breaks through the limitation of process gate delay, and can achieve an ultra-high resolution of <50ps without advanced process, which greatly reduces the chip implementation cost. The first two stages of quantization have reduced the quantization range to within 312.5ps. The vernier delay chain does not require a large number of delay units, and the chip area and power consumption are significantly reduced, making it easy to integrate multiple channels. The signal edge alignment and adjacent clock extraction design ensure the accuracy of the quantization range, avoid quantization blind spots, and the measurement results are free of dead zones.
[0037] In a specific example, the multi-event allocation circuit includes a pulse edge detection unit, a FIFO buffer unit, and a channel allocation unit cascaded in sequence; the pulse edge detection unit is used to identify the rising edge of multiple continuously input received pulses, the FIFO buffer unit is used to buffer the pulse signal, and the channel allocation unit is used to allocate the multiple received pulses to the phase detection circuit and the third-stage vernier measurement circuit in sequence to achieve continuous measurement.
[0038] Pulse edge detection unit: Real-time identification of the rising edges of multiple consecutive reflected pulses returned from the LiDAR receiving optical path, and marking the arrival time of each received pulse; FIFO buffer unit: buffers multiple continuously input received pulse signals in a first-in-first-out manner to avoid pulse loss and solves the problem of "the next pulse cannot be measured before the previous measurement is completed" in traditional TDC; Channel allocation unit: It sequentially distributes multiple buffered received pulses to the phase detection circuit and the third-level quantization circuit, so as to realize continuous measurement of one transmitted pulse corresponding to multiple received pulses, and can start the next measurement without waiting for the previous measurement to be completed.
[0039] This embodiment achieves continuous measurement with one transmitter and multiple receivers, compressing the measurement dead time of the TDC to less than 10ns, perfectly adapting to multi-target ranging scenarios of LiDAR, and can simultaneously identify multiple obstacles at near and far distances; the FIFO buffer design avoids the loss of continuous pulses, greatly improving the measurement response speed, and adapting to the application requirements of high-speed scanning LiDAR; the circuit structure is simple, can be seamlessly connected with multi-channel TDC arrays, and is easy to expand to dozens or even hundreds of channels, adapting to the application requirements of area array LiDAR.
[0040] In a specific example, the asynchronous counter 20 is a 9-bit asynchronous counter with a quantization step size of 5ns, which can cover the maximum time interval corresponding to 200-meter laser ranging; the decoding circuit 50 and the data readout circuit 60 are both written in Verilog hardware description language, and the output of the data readout circuit 60 is parallel binary data, which can be directly connected to the main control FPGA chip of the lidar.
[0041] The 9-bit asynchronous counter in this embodiment uses a quantization step size of 5ns, which can cover a time interval of up to 2560ns, corresponding to a laser ranging distance of over 380 meters, fully covering the 200-meter ranging requirement of conventional lidar. The decoding circuit and data readout circuit are written in Verilog hardware description language and can be directly implemented in FPGA / ASIC. The three-level quantization results are logically operated and concatenated to output standard parallel binary data. The output data can be directly connected to the main control FPGA chip of the lidar without additional conversion circuits, and has extremely strong compatibility with existing lidar systems.
[0042] The parameter design of the 9-bit counter in this embodiment perfectly matches the ranging requirements of a 200-meter lidar, balancing the range and chip area, with no redundancy and lower power consumption. The digital circuit implemented in Verilog is highly portable, and can be fabricated into a dedicated chip based on CMOS technology or deployed directly on an FPGA platform to adapt to different productization needs. The standard parallel binary output seamlessly integrates with existing lidar main control platforms, significantly reducing system integration difficulty and shortening product development cycles.
[0043] Simulation data verification: In the specific implementation, the transient and static phase difference simulation results of the delay phase-locked loop are as follows: Figure 7 As shown, the input and output clocks are basically aligned, with a static phase difference of only about 1.5ps, which can be used as a high-precision quantization clock for TDC.
[0044] The phase detection circuit structure is as follows: Figure 8 As shown, the phase detection circuit reads out the measurement results of the interpolation stage. The final output data should be a one-hot code, which is transmitted to the decoding circuit to read out the fractional part of the value.
[0045] Because the Start / Stop signal and the clock signal in this design are asynchronous, and since they are independent of each other, the counter and the interpolation stage are also independent. When the rising edge of the counter is close to the rising edge of the clock signal, or when clock jitter causes errors that bring the two edges close together, the counter's flip-flops will be in a metastable state. This will inevitably result in an integer cycle error, i.e., the misalignment error mentioned earlier. This design is based on a sequential logic structure and uses a resampling structure. Because the Stop / Start signal and the CLK clock signal may overlap, causing the D flip-flops to be in a metastable state, the second-stage D flip-flops are used to restore the normal logic level. The last-stage flip-flop performs the logic function, ensuring that the sampling result is output as a correct one-hot code.
[0046] When the Start / Stop signal is between two clock phases, the last stage D flip-flop controlled by the subsequent clock signal always outputs a high level, while the outputs of the remaining one-hot codes all output a low level. Counting clock CLK <1> The Start / Stop judgment result, Start / Stop_CNT, always has a delay caused by a D flip-flop. This delay transforms the asynchronous signals into synchronous signals via the D flip-flop, ensuring a fixed phase difference between them. This prevents the counter's D flip-flops from exhibiting metastability, ensuring the final counter result conforms to a specific logic and avoids random jumps between consecutive count values, thus eliminating misalignment errors. This structure provides stable output, effectively avoiding sampling errors caused by flip-flop metastability, while significantly reducing delay and layout area compared to combinational logic circuits. Simulation results for the misalignment error elimination function are as follows: Figure 9 As shown.
[0047] The third-stage vernier measurement circuit in this embodiment is as follows: Figure 10As shown, what needs further quantization is the time difference between the rising edge of Start / Stop and the subsequent adjacent phase clock. OUT1 is the replacement clock to be extracted. The delay ΔT1 between the two is one reference clock cycle plus the delay of one D flip-flop. Therefore, the Start / Stop signal needs to be delayed by ΔT1 before being input together with OUT1 into the third stage for quantization. One cycle delay is completed by the Delay circuit in the figure, and the selection extraction function is completed by the Select circuit. To ensure accurate identification and extraction of OUT1, the selection circuit design adopts a structure similar to an OR gate, connecting 16 OUT1 signals. When the first rising edge arrives, it can immediately judge and output. The Start / Stop signal is delayed using a DLL voltage-controlled delay chain and a D flip-flop, and is connected to the same discrimination circuit as OUT1, ensuring the delay matching of the two signals. Subsequently, the signal OUT_CLK extracted by the discrimination circuit and ST are input to the cursor structure for quantization. The τ1 delay is slightly greater than τ2. The final resolution is the delay difference between the two delay units. The result of the third-stage quantization is the product of the delay difference and the number of delay units experienced when the flip-flop output is low.
[0048] The functional tests of the above-mentioned TDC overall circuit were performed, and the results are as follows: Figure 11-15 As shown, the quantization of TDC in this embodiment is divided into three levels. Therefore, when a set of START and STOP signals are input, the quantization of the time interval between the rising edges of these two signals is divided into three parts: integer counting, interpolation layer, and cursor layer. During simulation testing, the rising edge of the START signal arrives at 1000ns, and the rising edge of the STOP signal arrives at 1052ns. According to the quantization logic of TDC, the quantization result is: 55ns-312.5ps 10+0 312.5ps + 9 20ps-1 20 ps = 52.035 ns; Therefore, the actual interval is 52ns, and the final system error is within 50ps.
[0049] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.
Claims
1. A high-precision multi-channel TDC circuit for use in lidar, characterized in that, It includes a delay phase-locked loop (10), an asynchronous counter (20), a phase detection circuit (30), a third-stage vernier measurement circuit (40), a decoding circuit (50), a data readout circuit (60), and a multi-event distribution circuit (70); The clock input terminal of the delay phase-locked loop (10) is connected to an external 200MHz quantization clock, and the 16-channel phase-splitting clock output terminal is connected to the sampling clock input terminal of the phase detection circuit (30) to perform 16-channel phase-splitting on the 200MHz quantization clock, generating 16 channels of phase-splitting clocks with equal phase differences, which serve as the reference clock for the second-stage interpolation quantization. The clock terminal of the asynchronous counter (20) is connected to a 200MHz quantization clock, and the start / stop control terminal is connected to the synchronous output terminal of the phase detection circuit (30) to complete the first stage of coarse quantization of the time interval and expand the measurement dynamic range. The signal input terminal of the phase detection circuit (30) is connected to the pulse output terminal of the multi-event distribution circuit (70), the one-hot code output terminal is connected to the input terminal of the decoding circuit (50), and the synchronization output terminal is simultaneously connected to the start / stop control terminal of the asynchronous counter (20) and the first input terminal of the third-level vernier measurement circuit (40) to complete the second-level interpolation quantization and synchronize the asynchronous transmit and receive pulse signals with the quantization clock to eliminate misalignment errors. The second input terminal of the third-level vernier measurement circuit (40) is connected to the pulse output terminal of the multi-event distribution circuit (70), and the quantization result output terminal is connected to the first input terminal of the data readout circuit (60). It is used to perform third-level fine quantization on the small time difference between the transmit and receive pulses and the rising edge of the adjacent phase clock to achieve a measurement resolution of less than 50 ps. The output of the decoding circuit (50) is connected to the second input of the data reading circuit (60) to convert the 16-bit one-hot code into 4-bit binary data. The third input terminal of the data readout circuit (60) is connected to the counting output terminal of the asynchronous counter (20) for performing logical operations and splicing on the three-level quantization results, and outputting the final time interval quantization result; The input terminal of the multi-event distribution circuit (70) is connected to the transmitted pulse signal and the received pulse signal of the lidar, and the output terminal is simultaneously connected to the signal input terminal of the phase detection circuit (30) and the third-level vernier measurement circuit (40) to realize continuous measurement of one transmitted pulse corresponding to multiple received pulses and reduce the measurement dead time.
2. The TDC circuit according to claim 1, characterized in that, The delay phase-locked loop (10) includes a frequency and phase detector, a source-switched charge pump, a loop filter, a voltage-controlled delay chain, and a clock soft-start circuit, which are cascaded in sequence. An operational amplifier is connected between the current mirror of the source-switched charge pump and the output node. The voltage of the current mirror and the output node are made equal through negative feedback to ensure accurate replication of the charging and discharging current. Each delay unit of the voltage-controlled delay chain adopts a differential structure and has a built-in latch to align the upper and lower edges of the clock. Redundant delay units are added at both ends of the delay chain to reduce phase interval error and differential nonlinearity.
3. The TDC circuit according to claim 2, characterized in that, The source-switched charge pump employs a source-switching structure to isolate the switching transistor and the current-source MOSFET, eliminating the charge injection problem of the switching digital signal. The drain of the current source is always connected to the output terminal, and the switching MOSFET is directly connected to the power supply and ground to form a low-impedance path, solving the charge shunting problem. A decoupling capacitor is connected between the gate of the current mirror MOSFET and the gate of the output node MOSFET to reduce current ripple. The input loop of the operational amplifier is equipped with a Miller capacitor and a zero-adjustment resistor for zero-pole compensation, improving the stability of the feedback loop.
4. The TDC circuit according to claim 2, characterized in that, Each stage of the voltage-controlled delay chain consists of two parallel time-adjustable inverters and a latch composed of two inverters connected end to end. Two to three redundant delay units are added to the beginning and end of the delay chain for load matching and buffering. Each stage of the phase clock output is equipped with a buffer. The buffer adopts a multi-stage inverter cascade structure, and the width-to-length ratio of each inverter is twice that of the previous stage.
5. The TDC circuit according to claim 1, characterized in that, The phase detection circuit (30) is a three-stage cascaded D flip-flop array; The clock terminals of the first-stage D flip-flops are connected to the 16-channel split-phase clock output terminals of the delay phase-locked loop (10), and the input terminals are connected to the pulse output terminals of the multi-event distribution circuit (70). The input of the second-stage D flip-flop is connected to the output of the first-stage D flip-flop, and the clock input is uniformly connected to a 200MHz quantization clock; the input of the third-stage D flip-flop is connected to the output of the second-stage D flip-flop, and the output outputs a 16-bit one-hot code. The first output terminal of the first-stage D flip-flop is used as a synchronous output terminal and connected to the start / stop control terminal of the asynchronous counter (20).
6. The TDC circuit according to claim 1, characterized in that, The third-stage vernier measurement circuit (40) includes a delay circuit, a signal selection circuit, and a dual-channel vernier delay chain cascaded in sequence; the delay circuit is used to align the edges of the transmit and receive pulse signals with the synchronous clock signal output by the phase detection circuit (30); the signal selection circuit is used to extract the phase clock signal adjacent to the transmit and receive pulses; the dual-channel vernier delay chain uses the delay difference between the two delay units as the quantization step size to complete the fine quantization of the small time difference.
7. The TDC circuit according to claim 1, characterized in that, The multi-event distribution circuit (70) includes a pulse edge detection unit, a FIFO buffer unit, and a channel distribution unit cascaded in sequence. The pulse edge detection unit is used to identify the rising edge of multiple continuously input received pulses. The FIFO buffer unit is used to buffer the pulse signal. The channel distribution unit is used to distribute multiple received pulses to the phase detection circuit (30) and the third-level vernier measurement circuit (40) in sequence to achieve continuous measurement.
8. The TDC circuit according to claim 1, characterized in that, The asynchronous counter (20) is a 9-bit asynchronous counter with a quantization step size of 5ns, which can cover the maximum time interval corresponding to 200-meter laser ranging. The decoding circuit (50) and the data reading circuit (60) are both written in Verilog hardware description language. The output of the data reading circuit (60) is parallel binary data, which can be directly connected to the main control FPGA chip of the laser radar.