A verification method and system for connecting a single-port SRAM module with a double AHB interface

Abstract

A verification method and system for connecting a single-port SRAM module by a double AHB interface, comprising the following steps: step 1, judging the rising edge of the AHB clock; step 2, obtaining the state of the transmission start signal and the delay signal, and judging whether there is a data transmission operation; step 3, judging whether the temporary storage queue Q is empty; step 4, temporarily storing or performing data operation when the temporary storage queue is empty; step 5, if the temporary storage queue Q is not empty, taking out the information of the temporary storage queue Q, and then directly entering step 6 when the AHB interface operation is performed; step 6, performing the read-write operation of the high-priority and low-priority AHB interface on the simulation model and verifying the result. By setting the high-priority and low-priority read-write agent modules, the present application simulates the simultaneous operation of multiple AHB interfaces on the single-port SRAM by test cases, realizes the verification of the double AHB interface read-write single-port SRAM, and improves the reliability of the verification.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a verification method and system for connecting a single-port SRAM module with dual AHB interfaces. Background Technology

[0002] Single-port static random access memory (SRAM), also known as single-port SRAM, is a type of memory with only one data access port. Compared to dual-port SRAM, single-port SRAM can only be read or written within a specific time period, making its design relatively simple and cost-effective, and it is commonly used in chip design. The AHB (Advanced High-performance Bus) protocol is one of the AMBA bus architectures proposed by ARM, primarily used in high-performance, high-clock-frequency system architectures, suitable for high-speed memory read / write and DMA transfer. The AHB protocol uses a master-slave architecture, supporting communication between multiple master and slave devices. Therefore, due to the needs of chip design IP modules, two or more AHB interfaces are often used to read and write single-port SRAM. However, common verification methods only verify read / write operations with a single AHB interface, lacking methods for verifying access conflicts when two or more AHB interfaces simultaneously read / write to the single-port SRAM.

[0003] UVM (Universal Verification Methodology) plays an important role in the field of modern integrated circuit design and verification, especially in the development of complex systems. By providing a reusable, modular and standardized verification framework, it accelerates the verification process and improves verification quality.

[0004] Therefore, it is necessary to provide a verification platform and verification method based on UVM for connecting a single-port SRAM module with dual AHB interfaces to solve the above problems. Summary of the Invention

[0005] To address the shortcomings of the existing technology, this invention discloses a verification method for connecting a single-port SRAM module via dual AHB interfaces.

[0006] The verification method for connecting a single-port SRAM module via a dual AHB interface according to the present invention includes the following steps: Step 1. Determine if the rising edge of the AHB clock has arrived. If it has, proceed to Step 2; otherwise, continue with Step 1. Step 2. Obtain the transmission enable signal and delay signal status of the high-priority AHB interface and the low-priority AHB interface, and determine whether there is a data transmission operation on the high-priority and low-priority AHB interfaces; Step 3. Determine if the temporary queue Q is empty. If it is empty, proceed to step 4; otherwise, proceed to step 5. Step 4. If the temporary queue Q is empty and there is only one AHB interface operating on the single-port SRAM, then proceed directly to step 6; If the temporary queue Q is empty and both high-priority and low-priority AHB interfaces are operating on a single-port SRAM simultaneously, then the temporary queue Q stores low-priority data, and then proceeds to step 6. If the temporary queue Q is empty and there are no AHB interface operations, the process will terminate. Step 5. If the temporary queue Q is not empty and there is no AHB interface operation at this time, then retrieve the information of the temporary queue Q and proceed to step 6. If the temporary queue Q is not empty and there is an AHB interface operation, proceed directly to step 6; Step 6. By acquiring the transmission enable signal and delay signal status of the high-priority AHB interface and the low-priority AHB interface, perform read and write operations on the simulation model using the high-priority and low-priority AHB interfaces and verify the results; in Step 6, the operation of the high-priority AHB interface is executed first.

[0007] Preferably, step 6 specifically includes: Step 61. Generate a thread for processing the simulation model, which is used to emulate the single-port SRAM of the device under test; Step 62. Generate a simulated address SHA1 corresponding to the write address HA1 on the single-port SRAM of the device under test; at the same time, generate simulated data SHD1 corresponding to the write data HD1; The write address HA1 and write data HD1 are a set of corresponding addresses and data transmitted by the AHB interface; The simulation model simultaneously reads the write address HA1 and the write data HD1; Step 63. Compare the results of the simulation model with the output results of the single-port SRAM, that is, compare the simulated address with the written address, and the simulated data with the written data. If the comparison results are different, report an error.

[0008] Preferably, step 7 is also included. In the read / write rate detection module, the start and end time and number of data for each transmission are obtained through the imp (receive response) port of TLM (transaction-level modeling) communication, packaged and stored in a queue, and the read / write rate is calculated before the simulation ends. The average read / write speed is calculated and compared with the ideal situation of the module being verified. If the difference exceeds the set threshold, it indicates that the read / write speed does not meet expectations, and an error report is generated.

[0009] This invention also discloses a verification system for connecting a single-port SRAM module with dual AHB interfaces, used to execute the verification method, comprising: The AHB system configuration module is used to configure the addresses, data widths, number of master and slave devices, and component functions used by the AHB protocol and pass them to the AHB system environment module. The AHB system environment module is used for instantiating high-priority read-write agent modules and low-priority read-write agent modules. The high-priority read / write agent module includes a high-priority transmitter, a high-priority driver, and a high-priority monitor that stimulate the AHB system. It also declares the high-priority AHB transmission information generated by the port used for TLM communication and obtains the high-priority AHB interface transmitted by the AHB system configuration module. The low-priority read / write agent module includes a low-priority transmitter, a low-priority driver, and a low-priority monitor that stimulate the AHB system. It also declares the low-priority AHB transmission information generated by the port used for TLM communication and obtains the low-priority AHB interface transmitted by the AHB system configuration module. The SRAM model and comparison module is used to simulate the behavior of high and low priority read and write single-port SRAM in different scenarios, and compare the single-port SRAM of the verified module with the simulation model in real time; at the same time, it detects the timing of the control information during the two AHB read and write operations, as well as the correctness of the timing of the control information during the read and write of the single-port SRAM device. The AHB read / write stimulus module contains four different stimulus sub-modules: high-priority AHB interface write stimulus sub-module, high-priority AHB interface read stimulus sub-module, low-priority AHB interface write stimulus sub-module, and low-priority AHB interface read stimulus sub-module, which enable high-priority and low-priority ports to read and write to a single-port SRAM. The test case module stores different verification schemes.

[0010] Preferably, it also includes a read / write rate detection module, which uses the imp port of TLM communication to receive high-priority AHB transmission information and low-priority AHB transmission information, so as to realize the performance check of reading and writing single-port SRAM by the high-priority AHB interface and the low-priority AHB interface.

[0011] Preferably, in the read / write rate detection module, two queues are used to store the high-priority AHB transmission information and the low-priority AHB transmission information obtained from the imp port, respectively.

[0012] Preferably, in the execution test case module, when there are situations where high-priority AHB interface read / write, low-priority AHB interface read / write, and both high and low priorities are executed in parallel, the event method is used to notify the read / write rate detection module to calculate the read / write rate of single-port SRAM for both high and low priority AHB interfaces respectively.

[0013] Preferably, in the SRAM model and comparison module, an associative array is used as the simulation model.

[0014] This invention achieves verification of reading and writing single-port SRAM using dual AHB interfaces by setting high and low priority read / write proxy modules and simulating multiple AHB interfaces operating on a single-port SRAM simultaneously, thereby improving the reliability of the verification. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a specific embodiment of the verification system described in this invention; Figure 2 This is a schematic flowchart of a specific implementation of the verification method described in this invention; Figure 3 This is a signal timing diagram in a specific embodiment of the present invention. Detailed Implementation

[0016] To more intuitively and clearly describe the specific details of the technical solution of the present invention, a detailed description will be provided below in conjunction with specific embodiments and example drawings.

[0017] The purpose of this invention is to propose a verification platform and method for connecting a single-port SRAM module with dual AHB interfaces based on UVM technology, so as to solve the problem of the lack of verification methods for reading and writing single-port SRAM with dual AHB interfaces in the prior art and improve the reliability of the design.

[0018] To achieve the above objectives, the verification platform comprises the following components: The AHB system configuration module (ahb_sys_cfg) is used to configure the address, data width, number of master and slave devices, and component function configurations used by the AHB protocol. It passes these configurations to the AHB system environment module through the uvm_config_db (UVM configuration parameter passing) mechanism.

[0019] The AHB system environment module (ahb_sys_env) is used for instantiating the high-priority read / write agent module (high_ahb_agent) and the low-priority read / write agent module (low_ahb_agent).

[0020] The high-priority read / write agent module (high_ahb_agent) encapsulates the high-priority sender (high_sequencer), high-priority driver (high_driver), and high-priority monitor (high_monitor) of the AHB system stimulus. It also declares the high-priority AHB transmission information (high_ahb_transaction) generated by the port used for TLM communication and obtains the high-priority AHB interface passed by the AHB system configuration module. The low-priority read / write agent module (low_ahb_agent) encapsulates the low-priority sender (low_sequencer), low-priority driver (low_driver), and low-priority monitor (low_monitor) of the AHB system. It also declares the low-priority AHB transmission information (low_ahb_transaction) generated by the port transmission for TLM communication and obtains the low-priority AHB interface transmitted by the AHB system configuration module. The SRAM model and comparison module (sram_model) is used to simulate the behavior of high and low priority read and write single-port SRAM in different scenarios. It compares the single-port SRAM of the verified module with the simulation model in real time, and at the same time detects the correctness of the timing of the control information such as address and data transfer during the two AHB read and write operations and the timing of the control information such as address and data during the read and write of the single-port SRAM device. The read / write rate detection module (speed_checker) uses the imp port of TLM communication to receive high-priority AHB transmission information (high_ahb_transaction) and low-priority AHB transmission information (low_ahb_transaction). Through calculation, it checks the read / write performance of the single-port SRAM by the high-priority AHB interface and the low-priority AHB interface, respectively. The AHB read / write stimulus module (ahb_sequence) contains four different stimulus sub-modules: high-priority AHB interface write stimulus sub-module (high_write_seq), high-priority AHB interface read stimulus sub-module (high_read_seq), low-priority AHB interface write stimulus sub-module (low_write_seq), and low-priority AHB interface read stimulus sub-module (low_read_seq), which enable high-priority and low-priority ports to read and write to a single-port SRAM. The test case module implements different verification schemes based on different functional points; Preferably, in the SRAM model and comparison module (sram_model), an associative array data type is used as the simulation model. Associative arrays can map addresses to data one-to-one, effectively simulating the physical behavior of a single-port SRAM. They also offer advantages such as saving simulation memory and allowing for addressing within a larger space. After each read / write operation on the AHB interface, the simulation model is immediately compared with the module being verified.

[0021] Preferably, the read / write rate detection module (speed_checker) uses two queues: a high-priority queue (high_ahb_transaction_queue) and a low-priority queue (low_ahb_transaction_queue) to store the high-priority AHB transmission information (high_ahb_transaction) and the low-priority AHB transmission information (low_ahb_transaction) obtained from the imp port, respectively.

[0022] Preferably, in the execution test case module, there are cases where high-priority AHB interface read / write, low-priority AHB interface read / write, and both high and low priorities are executed in parallel. An event mechanism is used to notify the read / write rate detection module (speed_checker) to calculate the read / write rate of single-port SRAM for both high and low priority AHB interfaces.

[0023] The verification platform of this invention is as follows Figure 1 As shown, the address and data bit width of the AHB system are configured through the AHB system configuration module (ahb_sys_cfg) to ensure that the address bit width is two bits wider than the address bit width of the single-port SRAM, while the data bit width remains the same as that of the single-port SRAM. This configuration is then passed to the AHB system environment module (ahb_sys_env) via uvm_config_db::set (UVM configuration parameter passing and sending function). The AHB system environment module (ahb_sys_env) instantiates a high-priority read / write agent module (high_ahb_agent) and a low-priority read / write agent module (low_ahb_agent). The high-priority driver (high_driver) and high-priority monitor (high_monitor) of both the high-priority and low-priority drivers (low_driver) and low-priority monitor (low_monitor) are respectively connected to the high-priority AHB interface (h_ahb) and low-priority AHB interface (l_ahb) of the module under test (DUT).

[0024] When performing write control of a single-port SRAM using the high-priority AHB interface, the operation data and address for the single-port SRAM are generated by the high-priority AHB interface write stimulus submodule (high_write_seq) and passed to the high-priority driver (high_driver) via the high-priority transmitter (high_sequencer). The high-priority driver (high_driver) generates write timing sequences conforming to the AHB protocol. During read control, the operation address for the single port is generated by the high-priority AHB interface read stimulus submodule (high_read_seq), passed to the high-priority driver (high_driver) in the same way, and read timing sequences conforming to the AHB protocol are generated. The operation method for single-port SRAM using the low-priority AHB interface is the same as that of the high-priority AHB interface. The monitor monitors each transmission information, using the TLM communication port to record the number of transmitted data and start / end times, and transmits this information to the read / write rate detection module (speed_checker). The SRAM model and comparison module (sram_model) continuously monitors the AHB operation timing of the verified module and simulates SRAM read / write operations.

[0025] In the SRAM model and comparison module (sram_model), a specific process for simulating the data write and read behavior of a single-port SRAM and the verification method used is as follows: Figure 2 As shown, it specifically includes: Step 1. Determine if the rising edge of the AHB clock has arrived. If it has, proceed to Step 2; otherwise, continue with Step 1. Step 2. Obtain the transmission enable signal and delay signal status of the high-priority AHB interface (h_ahb) and the low-priority AHB interface (l_ahb) to determine the data transmission operation status of the high-priority and low-priority AHB interfaces; Step 3. Determine if the temporary queue Q is empty. If it is empty, proceed to step 4; otherwise, proceed to step 5. Step 4. If the temporary queue is empty and there is only one AHB interface operating on the single-port SRAM, proceed directly to step 6; If the temporary queue Q is empty and both high-priority and low-priority AHB interfaces are operating on a single-port SRAM simultaneously, then the temporary queue Q stores low-priority data, and then proceeds to step 6. If the temporary queue Q is empty and there are no AHB interface operations, the process will terminate. Step 5. If the temporary queue Q is not empty and there is no AHB interface operation at this time, then retrieve the information of the temporary queue Q and proceed to step 6. If the temporary queue Q is not empty and there is an AHB interface operation, proceed directly to step 6.

[0026] Step 6. By acquiring the transmission enable signal and delay signal status of the high-priority AHB interface (h_ahb) and the low-priority AHB interface (l_ahb), perform read and write operations on the simulation model using the high-priority and low-priority AHB interfaces.

[0027] In step 6, the operation of the high-priority AHB interface is executed first. That is, first it is determined whether there is a high-priority AHB interface operation. If so, the high-priority AHB interface operation is executed; otherwise, the low-priority AHB interface operation is executed.

[0028] While reading and writing to the simulation model, the address and data of the AHB interface are compared with the address and data of the single-port SRAM interface inside the module under test to monitor the correctness of the interface timing; the data of the simulation model (mem_model_byte) is compared with the SRAM inside the module under test (ahb_sram) to determine whether the read and write are successful.

[0029] During the verification process, the stimulus signal is generated by the test case execution module, such as... Figure 3 The diagram shows a common read / write timing sequence. The shaded area represents invalid signals, and both the high-priority and low-priority AHB interfaces are for write operations. A specific implementation of the processing flow in the SRAM model and comparison module (sram_model) is as follows: The high and low priority AHB interface signals at the first, second, and third rising edges TL1, TL2, and TL3 are all in an invalid state. In this embodiment, the rising edges of these three invalid states are not considered. At the fourth rising edge of the clock signal, TL4; Step 1. Determine if the rising edge of the AHB clock has arrived; Step 2. Obtain the transmission enable signal and delay signal status of the high-priority AHB interface (h_ahb) and the low-priority AHB interface (l_ahb), and determine them as valid data; Step 3. It is found that the temporary queue Q is empty at this time; and the high and low priority AHB interfaces are operating on a single port SRAM simultaneously; Step 4. Store the write address LA1 of the low-priority AHB interface into the temporary queue Q, and the write address HA1 of the high-priority AHB interface is processed by the single-port SRAM in the next clock cycle TL5. Proceed directly to step 6; Step 6. Perform read and write operations, specifically as follows: Step 61. In sram_model, a thread is created to process the simulation model (mem_model_byte), which is used to emulate the module under test; Step 62. Generate a simulated address SHA1 corresponding to the write address HA1 on the single-port SRAM of the module under test; at the same time, generate simulated data SHD1 corresponding to the write data HD1; The write address HA1 and write data HD1 are a set of corresponding addresses and data transmitted by the AHB interface; The simulation model (mem_model_byte) simultaneously reads the write address HA1 and the write data HD1; Step 63. Compare the results of the simulation model (mem_model_byte) with the single-port SRAM of the module being verified (ahb_sram), i.e., compare HA1 with SHA1, HD1 with SHD1. If the comparison results are different, report an error. At the fifth rising edge of the clock signal, TL5; Similar to handling the fourth rising edge TL4, steps 1 and 2 are performed first. In step 2, the transmission enable signal and delay signal status of the high-priority AHB interface are obtained as 1, while the transmission enable signal and delay signal status of the low-priority AHB interface are both 0. Step 3. It is found that the temporary queue Q contains data LA1 at this time; Step 5. Since the high-priority AHB interface operation exists, the high-priority AHB interface performs another write operation, directly proceeding to step 6.

[0030] In step 6, similar to handling the fourth rising edge TL4, step 61 is performed first; In step 62 of step 6, a simulated address SHA2 corresponding to the write address HA2 is generated on the single-port SRAM of the verified module (ahb_sram); at the same time, simulated data SHD2 corresponding to the write data HD2 is generated. The write address HA2 and write data HD2 are a set of corresponding addresses and data transmitted by the AHB interface; The simulation model (mem_model_byte) simultaneously reads the write address HA2 and the write data HD2; Step 63. Compare the results of the simulation model (mem_model_byte) with the single-port SRAM of the module being verified (ahb_sram), i.e., compare HA2 with SHA2, HD2 with SHD2. If the comparison results are different, report an error. At the sixth rising edge of the clock signal, TL6; Similar to processing the fifth rising edge TL5, first perform steps 1 and 2. In step 2, the delay signal state of the high-priority AHB is obtained as 1, and the transmission enable signal of the high-priority AHB, the transmission enable signal of the low-priority AHB, and the delay signal state are all 0. Step 3. At this time, the temporary queue Q contains data LA1, and there is no AHB interface for write operation. Proceed to step 5. Step 5. LA1 stored in the temporary queue Q is retrieved, proceed to step 6; In step 6, similar to handling the fourth rising edge TL4, step 61 is performed first; In step 62 of step 6, a simulated address SLA1 corresponding to the write address LA1 is generated on the single-port SRAM of the verified module (ahb_sram); at the same time, simulated data SLD1 corresponding to the write data LD1 is generated. The write address LA1 and write data LD1 are a set of corresponding addresses and data transmitted via the AHB interface; The simulation model (mem_model_byte) simultaneously reads the write address LA1 and the write data LD1; Step 63. Compare the results of the simulation model (mem_model_byte) with the single-port SRAM of the module being verified (ahb_sram), that is, compare LA1 with SLA1, LD1 with SLD1. If the comparison results are different, report an error. To ensure the high reliability of the verification results, the simulation model (mem_model_byte) and all data of the single-port SRAM were compared before the verification was completed.

[0031] Step 7. In the read / write rate detection module (speed_checker), the start and end times and number of data transmitted by each transmission monitored by the high-priority monitor (high_monitor) and the low-priority monitor (low_monitor) are obtained through the imp port of TLM communication, packaged, and stored in a queue. Before the simulation ends, the read / write rate is calculated.

[0032] The structure code for packaging is as follows: typedef struct{ time begin_time; time end_time; bit[9:0] data_num; } performance_str; The start time (begin_time) records the start moment of this transmission, the end time (end_time) records the end moment of this transmission, and the number of data transmitted (data_num) records the number of data transmitted. The transmission duration is obtained by subtracting the start time (begin_time) from the end time (end_time). Before the simulation ends, the transmission duration and the number of data items for each queue element are summed to calculate the average read / write rate. This average rate is then compared to the ideal performance of the module being verified. If the difference exceeds a set threshold of 0.01%, it indicates that the read / write rate is not as expected, and an error report is generated. When writing test cases (test_case), the sequence.start(sequencer) function is used to generate and drive the stimulus. In the test case (test_case), fork / join is used to generate two threads. In the two threads, read or write will be randomized, and access to a single-port SRAM address and write data will be randomized. In this way, all read and write scenarios and simultaneous read and write scenarios are verified. The degree of randomization is high and the verification results are more reliable.

[0033] The present invention has been described above in conjunction with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, but should be modified and combined in accordance with the essence of the present invention.

[0034] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0035] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0036] The foregoing descriptions are preferred embodiments of the present invention. Unless there is a clear contradiction between the preferred embodiments or a premise of a particular preferred embodiment, the preferred embodiments can be arbitrarily combined and used. The embodiments and specific parameters described are only for clearly illustrating the inventor's invention verification process and are not intended to limit the scope of patent protection of the present invention. The scope of patent protection of the present invention shall still be determined by its claims. Similarly, any equivalent structural changes made based on the description and drawings of the present invention shall also be included within the scope of protection of the present invention.

Claims

1. A verification method for connecting a single-port SRAM module via dual AHB interfaces, characterized in that, Includes the following steps: Step 1. Determine if the rising edge of the AHB clock has arrived. If it has, proceed to Step 2; otherwise, continue with Step 1. Step 2. Obtain the transmission enable signal and delay signal status of the high-priority AHB interface and the low-priority AHB interface, and determine whether there is a data transmission operation on the high-priority and low-priority AHB interfaces; Step 3. Determine if the temporary queue Q is empty. If it is empty, proceed to step 4; otherwise, proceed to step 5. Step 4. If the temporary queue Q is empty and there is only one AHB interface operating on the single-port SRAM, then proceed directly to step 6; If the temporary queue Q is empty and both high-priority and low-priority AHB interfaces are operating on a single-port SRAM simultaneously, then the temporary queue Q stores low-priority data, and then proceeds to step 6. If the temporary queue Q is empty and there are no AHB interface operations, the process will terminate. Step 5. If the temporary queue Q is not empty and there is no AHB interface operation at this time, then retrieve the information of the temporary queue Q and proceed to step 6. If the temporary queue Q is not empty and there is an AHB interface operation, proceed directly to step 6; Step 6. By acquiring the transmission enable signal and delay signal status of the high-priority AHB interface and the low-priority AHB interface, perform read and write operations on the simulation model using the high-priority and low-priority AHB interfaces and verify the results; in Step 6, the operation of the high-priority AHB interface is executed first.

2. The verification method for connecting a single-port SRAM module to a dual AHB interface as described in claim 1, characterized in that, Step 6 specifically involves: Step 61. Generate a thread for processing the simulation model, which is used to emulate the single-port SRAM of the device under test; Step 62. Generate a simulated address SHA1 corresponding to the write address HA1 on the single-port SRAM of the device under test; at the same time, generate simulated data SHD1 corresponding to the write data HD1; The write address HA1 and write data HD1 are a set of corresponding addresses and data transmitted by the AHB interface; The simulation model simultaneously reads the write address HA1 and the write data HD1; Step 63. Compare the results of the simulation model with the output results of the single-port SRAM, that is, compare the simulated address with the written address, and the simulated data with the written data. If the comparison results are different, report an error.

3. The verification method for connecting a single-port SRAM module via dual AHB interfaces as described in claim 1, characterized in that, It also includes step 7. In the read / write rate detection module, the start and end time and number of data for each transmission are obtained through the imp port of TLM communication, packaged and stored in the queue, and the read / write rate is calculated before the simulation ends. The average read / write speed is calculated and compared with the ideal situation of the module being verified. If the difference exceeds the set threshold, it indicates that the read / write speed does not meet expectations, and an error report is generated.

4. A verification system for connecting a single-port SRAM module via dual AHB interfaces, characterized in that, include: The AHB system configuration module is used to configure the address, data width, number of master and slave devices, and function of components used by the AHB protocol and pass them to the AHB system environment module. The AHB system environment module is used for instantiating high-priority read-write agent modules and low-priority read-write agent modules. The high-priority read / write agent module includes a high-priority transmitter, a high-priority driver, and a high-priority monitor that stimulate the AHB system. It also declares the high-priority AHB transmission information generated by the port used for TLM communication and obtains the high-priority AHB interface transmitted by the AHB system configuration module. The low-priority read / write agent module includes a low-priority transmitter, a low-priority driver, and a low-priority monitor that stimulate the AHB system. It also declares the low-priority AHB transmission information generated by the port used for TLM communication and obtains the low-priority AHB interface transmitted by the AHB system configuration module. The SRAM model and comparison module is used to simulate the behavior of high and low priority read and write single-port SRAM in different scenarios, and compare the single-port SRAM of the verified module with the simulation model in real time; at the same time, it detects the timing of the control information during the two AHB read and write operations, as well as the correctness of the timing of the control information during the read and write of the single-port SRAM device. The AHB read / write stimulus module contains four different stimulus sub-modules: high-priority AHB interface write stimulus sub-module, high-priority AHB interface read stimulus sub-module, low-priority AHB interface write stimulus sub-module, and low-priority AHB interface read stimulus sub-module, which enable high-priority and low-priority ports to read and write to a single-port SRAM. The test case module stores different verification schemes.

5. The verification system for connecting a single-port SRAM module via dual AHB interfaces as described in claim 4, characterized in that, It also includes a read / write rate detection module, which uses the imp port of TLM communication to receive high-priority AHB transmission information and low-priority AHB transmission information, and realizes the performance of reading and writing single-port SRAM by the high-priority AHB interface and the low-priority AHB interface.

6. The verification system for connecting a single-port SRAM module via dual AHB interfaces as described in claim 5, characterized in that, In the read / write rate detection module, two queues are used to store the high-priority AHB transmission information and the low-priority AHB transmission information obtained from the imp port, respectively.

7. The verification system for connecting a single-port SRAM module via dual AHB interfaces as described in claim 5, characterized in that, In the execution test case module, when there are situations where high-priority AHB interface read / write, low-priority AHB interface read / write, and both high and low priorities are executed in parallel, the event method is used to notify the read / write rate detection module to calculate the read / write rate of single-port SRAM for both high and low priority AHB interfaces respectively.

8. The verification system for connecting a single-port SRAM module via dual AHB interfaces as described in claim 4, characterized in that, In the SRAM model and comparison module, an associative array is used as the simulation model.

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