A data manipulation structure and data manipulation method
The request translation unit converts the processor's complex request signals into simple read/write signals, and uses the cache's bypass mode and hit feedback signals to control memory and enable pins. This solves the problems of structural complexity and high power consumption during processor data access, achieving the effects of simplified design and low power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- 青岛本原微电子有限公司
- Filing Date
- 2022-06-24
- Publication Date
- 2026-06-30
AI Technical Summary
Existing processors have complex cache and memory unit structures, high power consumption, and complex memory control logic during data access. In particular, the need to cancel memory access when a cache hit occurs adds additional complexity.
The request translation unit converts the processor's complex request signals into simple read and write signals, and controls the memory through the cache's bypass mode and hit feedback signal, enabling pins, simplifying the interface logic between the cache and memory, and reducing power consumption.
It simplifies the design complexity of cache and memory structures, reduces system power consumption, reduces the complexity of memory control logic, and adapts to low power consumption requirements.
Smart Images
Figure CN115203077B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of processor internal structure technology, specifically, it relates to a data operation structure and a data operation method. Background Technology
[0002] In the current technology, the processor's data access requests include instruction requests on the instruction bus and data requests on the data bus. As shown in Table 1, instruction requests include one form: read instruction requests, while data requests include two forms: read data requests and write data requests. Since there is only one data bus in the system, read data requests and write data requests will not occur simultaneously. This requires the accessed cache and memory to be able to correctly handle these complex signals, which correspondingly increases the complexity of cache and memory unit structure design.
[0003] Table 1
[0004] signal name Signal function Iaddr Instruction bus address Iaddr_valid Instruction bus address valid flag I_cc Cancel instruction bus operation? I_stop Command bus pause Daddr Data bus address Daddr_valid Data bus address valid flag Daddr_wr Data bus read / write enable Ddata_width Together with Daddr, Daddr_valid, and D_cc, they determine the actual width of the read / write operation. D_cc Cancel data bus operation? D_data Write data bus data D_data_valid Write data bus data valid flag D_stop Data bus pause
[0005] Meanwhile, in order to ensure access efficiency, the data path of the internal cache is always open under the existing technology, which increases the power consumption of the system.
[0006] In addition, when a cache hit occurs, existing technologies typically initiate a memory access cancellation operation, which increases the complexity of memory control logic. Summary of the Invention
[0007] To address the above shortcomings, this invention proposes a data operation structure and method. This method uses logic to convert complex processor signals into simple read / write signals, reducing interface design complexity and thus simplifying cache and memory structure design. By setting the internal cache path to a bypassable mode, it adapts to the low-power requirements of some applications. Simultaneously, the cache hit feedback signal controls the enable pins of memory storage units, blocking memory access without requiring a memory access cancellation operation, thereby reducing the design complexity of memory control logic.
[0008] The present invention is implemented using the following technical solutions:
[0009] A data manipulation structure is proposed, characterized by comprising:
[0010] The processor executes instructions and reads and writes data;
[0011] The cache can be bypassed by clearing the cache enable bit in the cache control register, thus not responding to any operation; and it can be restored by setting the cache enable bit in the cache control register.
[0012] Memory, which includes storage units;
[0013] The request translation unit converts the request signal initiated by the processor into a read / write signal according to a set logic, and sends the converted read / write signal to both the cache and memory simultaneously. When the cache does not bypass read requests, if a cache read hit occurs, a hit feedback signal is output to the request translation unit to indicate the validity of the cache data. Simultaneously, the hit feedback signal controls the enable pin of the memory storage unit, preventing the memory storage unit from responding. (If the cache misses, the memory storage unit responds to the read request, sending memory data to the request translation unit, which then returns the memory data to the processor.) After the access is completed, the hit feedback signal becomes invalid, and the memory storage unit regains its responsiveness. When the cache does not bypass write requests, data is written to both the cache and memory simultaneously.
[0014] The setting logic includes:
[0015] No signal is output when there is no request;
[0016] The read instruction request occurs independently and is not canceled; it outputs the read enable signal and the read address signal.
[0017] A read command request occurs alone and is cancelled without outputting any signal;
[0018] A read data request occurs independently and is not canceled; outputs a read enable signal and a read address signal.
[0019] A read data request occurs alone and is then cancelled without outputting any signal;
[0020] Write data requests occur independently and are not canceled, outputting write enable signal, write address signal, write data signal, and write data valid bit signal;
[0021] Write data requests occur independently and are then cancelled without outputting any signals;
[0022] If a read instruction request and a read data request occur simultaneously and are not cancelled, after arbitration, the read instruction request will be issued first in accordance with method 2), while the data bus will be paused; after completion, the data bus will be restored, and the read data request will be issued in accordance with method 4), while the instruction bus will be paused; after completion, the instruction bus will be restored.
[0023] If a read command request and a read data request occur simultaneously and the read command request is cancelled, the handling method is the same as in 4).
[0024] If a read command request and a read data request occur simultaneously and the read data request is cancelled, the handling method is the same as in 2).
[0025] If a read command request and a read data request occur simultaneously and both requests are cancelled, the handling method is the same as in 1).
[0026] Read instruction requests and write data requests occur simultaneously and are not canceled. After arbitration, the write data request is issued first in accordance with method 6), while the instruction bus is paused. After completion, the instruction bus is restored. The read instruction request is issued in accordance with method 2), while the data bus is paused. After completion, the data bus is restored.
[0027] If a read command request and a write data request occur simultaneously and the read command request is cancelled, the handling method is the same as in 6).
[0028] If a read command request and a write data request occur simultaneously and the write data request is cancelled, the handling method is the same as in 2).
[0029] The read command request and the write data request occur simultaneously and both requests are cancelled, which is consistent with the handling method in 1).
[0030] In some embodiments of the present invention, when the cache path is restored by setting the cache enable bit in the cache control register, the flush bit in the cache control register is set to flush the cache.
[0031] A data manipulation method is proposed and applied to the data manipulation structure described above, including:
[0032] The processor initiates a request signal;
[0033] The request conversion unit converts the request signal initiated by the processor into a read / write signal according to the set logic, and sends the converted read / write signal to both the cache and memory at the same time;
[0034] When a cache read request is not bypassed, if a cache hit occurs, a hit feedback signal is output to the request translation unit to indicate the validity of the cache data. At the same time, the hit feedback signal controls the enable pin of the memory storage unit, so that the memory storage unit does not respond. When the access is completed, the hit feedback signal is invalidated, and the memory storage unit resumes its responsiveness. If a cache miss occurs, the memory storage unit responds to the read request and sends the memory data to the request translation unit.
[0035] When write requests are not bypassed in the cache, data is written to both the cache and memory simultaneously.
[0036] When a cache bypass read request is made, the memory storage unit responds to the read request by sending the memory data to the request translation unit, which then sends the memory data to the processor.
[0037] When a write request is bypassed by the cache, the memory responds to the write operation.
[0038] In some embodiments of the present invention, the method further includes:
[0039] When a low-power instruction is received from the application, the cache is bypassed by clearing the cache enable bit in the cache control register, and no operation is responded to.
[0040] When a cache path recovery instruction is received, the cache is recovered by setting the cache enable bit in the cache control register.
[0041] In some embodiments of the present invention, when the cache path is restored by setting the cache enable bit in the cache control register, the flush bit in the cache control register is set to flush the cache.
[0042] Respond to the received request signal.
[0043] Compared with existing technologies, the advantages and positive effects of this invention are as follows: The data operation structure and data operation method proposed in this invention use a request conversion unit as a bridge to associate the processor with the cache and memory. The request conversion unit uses setting logic to convert complex request signals initiated by the processor into simple read and write signals, so that the cache and memory only need to process simple read and write signals, thereby simplifying the interface logic of the cache and memory and simplifying the complexity of the cache and memory structure design. This invention can set the cache to bypass mode by clearing the cache enable bit in the cache control register. The bypassed cache does not respond to any operation, thereby adapting to the low power consumption requirements of some applications. The cache hit feedback signal can be used to directly control the enable pin of the storage unit in memory to block access to memory. When the cache hits, the enable of the storage unit is turned off, without the need to initiate a memory access cancellation operation, reducing the complexity of the memory control logic.
[0044] Other features and advantages of the present invention will become clearer after reading the detailed description of the embodiments of the present invention in conjunction with the accompanying drawings. Attached Figure Description
[0045] Figure 1 This is a schematic diagram of the data operation structure proposed in this invention;
[0046] Figure 2 This is a schematic diagram of the data manipulation method proposed in this invention. Detailed Implementation
[0047] The specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
[0048] like Figure 1 As shown, the data operation structure proposed in this invention includes:
[0049] The processor executes instructions and reads and writes data.
[0050] The cache can be bypassed by clearing the cache enable bit in the cache control register. When bypassed, it does not respond to any operations, and can be restored by setting the cache enable bit in the cache control register. For example... Figure 1 As indicated by the dashed line, bypassing the cache can reduce dynamic power consumption in certain application scenarios.
[0051] Memory includes control logic and storage units.
[0052] The request translation unit converts the request signal initiated by the processor into a read / write signal according to the set logic, and sends the converted read / write signal to both the cache and memory simultaneously. The set logic here is as follows:
[0053] 1) No signal is output when there is no request;
[0054] 2) A read instruction request occurs independently and is not canceled; the read enable signal and read address signal are output.
[0055] 3) A read command request occurs alone and is cancelled without outputting any signal;
[0056] 4) Read data requests occur independently and are not canceled; output read enable signal and read address signal.
[0057] 5) Read data requests occur independently and are cancelled without outputting any signals;
[0058] 6) Write data requests occur independently and are not canceled, outputting write enable signal, write address signal, write data signal, and write data valid bit signal;
[0059] 7) Write data requests occur independently and are cancelled without outputting any signals;
[0060] 8) If a read instruction request and a read data request occur simultaneously and are not cancelled, after arbitration, the read instruction request will be issued first in accordance with method 2), while the data bus will be paused; after completion, the data bus will be restored, and the read data request will be issued in accordance with method 4), while the instruction bus will be paused; after completion, the instruction bus will be restored.
[0061] 9) If a read command request and a read data request occur simultaneously and the read command request is cancelled, the handling method is the same as in 4).
[0062] 10) If a read instruction request and a read data request occur simultaneously and the read data request is cancelled, the handling method is the same as in 2).
[0063] 11) If a read instruction request and a read data request occur simultaneously and both requests are cancelled, the handling method is the same as in 1).
[0064] 12) If a read instruction request and a write data request occur simultaneously and are not cancelled, after arbitration, the write data request will be issued first in accordance with method 6), while the instruction bus will be paused. After completion, the instruction bus will be restored. The read instruction request will be issued in accordance with method 2), while the data bus will be paused. After completion, the data bus will be restored.
[0065] 13) If a read command request and a write data request occur simultaneously and the read command request is cancelled, the handling method is the same as in 6).
[0066] 14) If a read command request and a write data request occur simultaneously and the write data request is cancelled, the handling method is the same as in 2).
[0067] 15) If a read command request and a write data request occur simultaneously and both requests are cancelled, the handling method is the same as in 1).
[0068] Through the above-described logic, the request translation unit acts as a bridge, associating the processor with the cache and memory, and converting complex requests issued by the processor (as shown in Table 1) into simple read / write signals, as shown in Table 2 below:
[0069] Table 2
[0070] signal name Signal function rd Read operation enable signal wr Write operation enable signal addr Address information for read and write operations din Data information for write operations dout Data information read operation mask Used in conjunction with the data information of a write operation, it represents the valid bits in the write operation data information.
[0071] This simplifies the interface logic between the cache and memory, requiring only simple read and write signals to be processed.
[0072] Based on the operational structure provided in this invention, after the read / write signals converted by the request conversion unit are simultaneously sent to the cache and memory, the operation is divided into two cases: cache bypass and cache not bypassed.
[0073] When the cache is not bypassed and the read / write signal is a read request: If a cache read hit occurs, the cache will output a hit feedback signal to the request translation unit to indicate the validity of the cache data. At the same time, the hit feedback signal controls the enable pin of the memory cell, so that the memory cell does not respond. When the access is completed, the hit feedback signal becomes invalid, and the memory cell resumes its responsiveness. If a cache miss occurs, the memory cell responds to the read request and sends the memory data to the request translation unit, which then returns the memory data to the processor.
[0074] When the cache is not bypassed and the read / write signal is a write request: data is written to both the cache and memory simultaneously.
[0075] When the cache is bypassed: The cache does not respond to any operation, and the request translation unit sends the read / write signal to memory instead of sending the translated read / write signal to the cache.
[0076] When it is necessary to restore the cache from the bypass state, the cache enable bit in the cache control register can be set to restore the cache path.
[0077] Since the cache path goes from being closed to being open, the content in memory and the content in the cache may no longer be consistent. In some embodiments of this invention, it is necessary to flush the original content in the cache and refill the cache in subsequent operations to ensure the consistency between the cache and memory data. The cache flushing operation can be completed by setting the flush bit in the cache control register, which will then be cleared to zero.
[0078] Based on the data operation structure proposed above, this invention also proposes a data operation method based on this data operation structure, such as... Figure 2 As shown, it includes:
[0079] S1: The processor initiates a request signal.
[0080] As shown in Table 1, the request signals initiated by the processor include read instruction requests, read data requests, and write data requests.
[0081] S2: The request conversion unit converts the request signal initiated by the processor into a read / write signal according to the set logic, and sends the converted read / write signal to both the cache and the memory at the same time.
[0082] S31: When a cache read request is not bypassed, if a cache hit occurs, the cache data and a hit feedback signal are sent to the request translation unit (RTU), which then returns the cache data to the processor. Simultaneously, a hit feedback signal is sent to the enable pin of the memory storage unit, and the storage unit no longer responds to read request operations issued by the RTU. If a cache miss occurs, the memory storage unit is unaffected, responds normally to read request operations issued by the RTU, and sends the memory data to the RTU, which then returns the memory data to the processor.
[0083] S32: When the cache does not bypass write requests, both memory and cache respond to write request operations.
[0084] S33: When a cache bypass read request occurs, the memory responds to the read request operation by sending the memory data to the request translation unit, which then returns the memory data to the processor.
[0085] S34: When a write request is bypassed by the cache, the memory responds to the write request operation.
[0086] In some embodiments of the present invention, when the application has low power requirements, a low power instruction can be initiated. In response to the low power instruction, the cache is bypassed by clearing the cache enable bit in the cache control register and no operation is responded to.
[0087] When the cache path needs to be restored: the cache is restored by setting the cache enable bit in the cache control register.
[0088] In some embodiments of the present invention, in order to ensure the consistency between cache and memory data, when the cache path is restored by setting the cache enable bit in the cache control register, the flush bit in the cache control register is set to flush the cache; then the received request is responded to.
[0089] Based on the data operation structure and method proposed in this invention, the request conversion unit acts as a bridge to connect the processor with the cache and memory. The request conversion unit uses set logic to convert complex request signals initiated by the processor into simple read / write signals, so that the cache and memory only need to process simple read / write signals, thereby simplifying the interface logic between the cache and memory and reducing the complexity of the cache and memory structure design. This invention can set the cache to bypass mode by clearing the cache enable bit in the cache control register. The bypassed cache does not respond to any operation, thus adapting to the low power consumption requirements of some applications. The cache hit feedback signal can be used to directly control the enable pin of the storage unit in memory to block access to memory. If the cache hits, the enable of the storage unit is turned off, without the need to initiate a memory access cancellation operation, reducing the complexity of the memory control logic.
[0090] It should be noted that the above description is not intended to limit the present invention, and the present invention is not limited to the examples given above. Any changes, modifications, additions or substitutions made by those skilled in the art within the scope of the present invention should also fall within the protection scope of the present invention.
Claims
1. A data manipulation structure, characterized in that, include: The processor executes instructions and reads and writes data; The cache can be bypassed by clearing the cache enable bit in the cache control register, thus not responding to any operation; and it can be restored by setting the cache enable bit in the cache control register. Memory, which includes storage units; The request conversion unit converts the request signal initiated by the processor into a read / write signal according to the set logic. The signal is sent to both the cache and memory, and the converted read / write signal is sent simultaneously. If a cache read hit occurs when the cache does not bypass the read request, a hit feedback signal is output to the request conversion unit to indicate the validity of the cache data. At the same time, the hit feedback signal controls the enable pin of the memory storage unit, so that the memory storage unit does not respond. When the access is completed, the hit feedback signal is invalidated, and the memory storage unit resumes its responsiveness. When write requests are not bypassed in the cache, data is written to both the cache and memory simultaneously. The setting logic includes: No signal is output when there is no request; The read instruction request occurs independently and is not canceled; it outputs the read enable signal and the read address signal. A read command request occurs alone and is cancelled without outputting any signal; A read data request occurs independently and is not canceled; outputs a read enable signal and a read address signal. A read data request occurs alone and is then cancelled without outputting any signal; Write data requests occur independently and are not canceled, outputting write enable signal, write address signal, write data signal, and write data valid bit signal; Write data requests occur independently and are then cancelled without outputting any signals; If a read instruction request and a read data request occur simultaneously and are not cancelled, after arbitration, the read instruction request will be issued first in accordance with method 2), while the data bus will be paused; after completion, the data bus will be restored, and the read data request will be issued in accordance with method 4), while the instruction bus will be paused; after completion, the instruction bus will be restored. If a read command request and a read data request occur simultaneously and the read command request is cancelled, the handling method is the same as in 4). If a read command request and a read data request occur simultaneously and the read data request is cancelled, the handling method is the same as in 2). If a read command request and a read data request occur simultaneously and both requests are cancelled, the handling method is the same as in 1). Read instruction requests and write data requests occur simultaneously and are not canceled. After arbitration, the write data request is issued first in accordance with method 6), while the instruction bus is paused. After completion, the instruction bus is restored. The read instruction request is issued in accordance with method 2), while the data bus is paused. After completion, the data bus is restored. If a read command request and a write data request occur simultaneously and the read command request is cancelled, the handling method is the same as in 6). If a read command request and a write data request occur simultaneously and the write data request is cancelled, the handling method is the same as in 2). The read command request and the write data request occur simultaneously and both requests are cancelled, which is consistent with the handling method in 1).
2. The data operation structure according to claim 1, characterized in that, When the cache path is restored by setting the cache enable bit in the cache control register, the flush bit in the cache control register is set to flush the cache.
3. A data manipulation method, applied to the data manipulation structure as described in any one of claims 1-2. In the structure, the characteristic is that, include: The processor initiates a request signal; The request conversion unit converts the request signal initiated by the processor into a read / write signal according to the set logic, and sends the converted read / write signal to both the cache and memory at the same time; When a cache read request is not bypassed, if a cache hit occurs, a hit feedback signal is output to the request translation unit to indicate the validity of the cache data. At the same time, the hit feedback signal controls the enable pin of the storage unit in memory, so that the storage unit in memory does not respond. When the access is completed, the hit feedback signal becomes invalid, and the storage unit in memory resumes its responsiveness. If a cache miss occurs, the memory storage unit responds to the read request by sending the memory data to the request translation unit; When write requests are not bypassed in the cache, data is written to both the cache and memory simultaneously. When a cache bypass read request is made, the memory storage unit responds to the read request by sending the memory data to the request translation unit, which then sends the memory data to the processor. When a write request is bypassed by the cache, the memory responds to the write operation.
4. The data manipulation method according to claim 3, characterized in that, The method further includes: When a low-power instruction is received from the application, the cache is bypassed by clearing the cache enable bit in the cache control register, and no operation is responded to. When a cache path recovery instruction is received, the cache is recovered by setting the cache enable bit in the cache control register.
5. The data manipulation method according to claim 4, characterized in that, When the cache path is restored by setting the cache enable bit in the cache control register, the flush bit in the cache control register is set to flush the cache. Respond to the received request signal.