FPGA-based biSS-c protocol host interface and implementation method thereof
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2026-04-10
- Publication Date
- 2026-07-10
Smart Images
Figure CN122364142A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of industrial control technology, and in particular to an FPGA-based BiSS-C protocol host interface and its implementation method. Background Technology
[0002] BiSS-C (BiSS Interface Continuous mode) is a high-speed synchronous serial communication protocol designed for industrial real-time control. It is compatible with the RS-422 standard at the physical layer, supports clock rates up to 10 MHz, and has built-in CRC check. It can ensure microsecond-level response while maintaining transmission reliability, and has become one of the commonly used communication interfaces in fields such as robot joint position feedback and servo motor control.
[0003] In existing technologies, the host implementation of the BiSS-C protocol mainly relies on two methods: one is the use of application-specific integrated circuits (ASICs), such as the iC-Haus series of products; the other is a soft-core implementation based on FPGAs. While dedicated ASIC solutions offer stable performance, they lack flexibility, making it difficult to customize communication parameters according to specific application scenarios, and are also costly. Existing FPGA-based implementations suffer from the following shortcomings:
[0004] Limited communication speed: The highest communication speed of existing FPGA implementations is generally below 5 MHz, which is difficult to meet the requirements of modern high-performance servo systems for control frequencies above 10 kHz.
[0005] Limited functionality: Most implementations only support basic angle reading functions and lack support for complete protocol functions such as register reading and writing and CRC verification, making it impossible to configure encoder parameters and monitor their status online.
[0006] Cross-clock domain processing is complex: The host interface needs to handle multiple asynchronous clock domains (such as the FPGA system clock, the clock returned by the external encoder, etc.). Existing solutions are not well designed for cross-clock domain synchronization, which can easily lead to metastability problems and affect communication reliability.
[0007] Poor configurability: The frame format, communication rate and other parameters of the existing solutions are mostly fixed designs, making it difficult to adapt to BiSS-C slave encoders of different manufacturers and specifications.
[0008] Therefore, developing a high-speed, fully functional, highly reliable, and flexibly configurable BiSS-C protocol host interface is of great significance for improving the performance of industrial servo systems. Summary of the Invention
[0009] The purpose of this invention is to provide an FPGA-based BiSS-C protocol host interface and its implementation method to solve the problems of low communication speed, single mode and insufficient flexibility in the prior art.
[0010] To achieve the above objectives, the present invention provides an FPGA-based BiSS-C protocol host interface, comprising:
[0011] The serial port command parsing module is used to receive and parse serial port commands sent by the host computer, identify the command type and extract the associated address parameters and data parameters. The serial port commands include angle read commands, register read commands and register write commands.
[0012] The pulse trigger control module is connected to the serial port instruction parsing module and is used to generate a corresponding number of trigger pulses according to the parsed instruction type. Specifically, a single pulse is generated in response to the read angle instruction, and a continuous multi-pulse sequence is generated in response to the register read instruction or the register write instruction.
[0013] A clock generation module, connected to the pulse trigger control module, is used to generate an MA clock signal conforming to the BiSS-C protocol timing under the drive of the trigger pulse, and to encode the address parameters and / or the data parameters onto the MA clock signal according to the instruction type during the timeout phase specified by the BiSS-C protocol.
[0014] A parameter latching module is connected between the serial port instruction parsing module and the clock generation module. When the register read instruction or the register write instruction is received, the corresponding address parameters and / or data parameters are latched and output to the clock generation module.
[0015] The data decoding module, connected to the clock generation module, is used to sample and decode the SLO signal from the BiSS-C slave under the synchronization of the MA clock signal to obtain position data or register data;
[0016] A CRC check module, connected to the data decoding module, is used to perform cyclic redundancy check on the decoded data. The CRC check module includes a parallel CRC calculation unit, which is used to complete the check calculation of the location data within one system clock cycle.
[0017] Optionally, the pulse trigger control module generates a continuous multi-pulse sequence of 33 consecutive trigger pulses to meet the requirement of 33 consecutive frames of communication for BiSS-C protocol register access.
[0018] Optionally, the read angle instruction includes a first opcode and a terminator, the register write instruction includes a second opcode, a one-byte address, a one-byte data, and a terminator, and the register read instruction includes a third opcode, a one-byte address, and a terminator.
[0019] Optionally, in response to the register read instruction, the data decoding module is configured to acquire the returned data bit by bit from the control and data segments of frames 21 to 28, and latch it as complete 8-bit register data in frame 29.
[0020] Optionally, the CRC verification module includes independent CRC4 calculation units and CRC6 calculation units; the CRC4 calculation unit is the parallel CRC calculation unit, used to perform verification calculations on the location data; the CRC6 calculation unit adopts a serial calculation architecture, used to perform verification calculations on the register data under the drive of the MA clock signal.
[0021] Optionally, the CRC4 calculation unit is used to perform CRC calculation on 11-bit input data within one system clock cycle; the CRC6 calculation unit is used to perform bit-by-bit calculation on 28-bit input data.
[0022] Optionally, the BiSS-C protocol host interface is configured to support a communication rate of up to 10 MHz.
[0023] Based on the same inventive concept, this invention also provides a method for implementing a BiSS-C protocol host interface based on FPGA, comprising:
[0024] Receive and parse serial port commands sent by the host computer, identify the command type and extract the associated address parameters and data parameters. The serial port commands include angle read commands, register read commands and register write commands.
[0025] The corresponding number of trigger pulses are generated according to the parsed instruction type, wherein a single pulse is generated in response to the read angle instruction, and a continuous multi-pulse sequence is generated in response to the register read instruction or the register write instruction;
[0026] Driven by the trigger pulse, an MA clock signal conforming to the BiSS-C protocol timing is generated. During the timeout phase specified by the BiSS-C protocol, the address parameters and / or the data parameters are encoded onto the MA clock signal according to the instruction type.
[0027] Under the synchronization of the MA clock signal, the SLO signal from the BiSS-C slave is sampled and decoded to obtain position data or register data;
[0028] Cyclic redundancy check is performed on the decoded data, wherein at least the check of the location data is completed in parallel computing within one system clock cycle;
[0029] Specifically, upon receiving the register read instruction or the register write instruction, the corresponding address parameters and / or data parameters are latched.
[0030] Optionally, performing cyclic redundancy check on the decoded data includes:
[0031] The location data verification calculation is completed within one system clock cycle using parallel computing; and...
[0032] The verification calculation of the register data is completed through serial calculation, driven by the MA clock signal.
[0033] Based on the same inventive concept, the present invention also provides a readable storage medium having a computer program stored thereon, which, when executed, can implement the FPGA-based BiSS-C protocol host interface implementation method described above.
[0034] The FPGA-based BiSS-C protocol host interface and its implementation method provided in this invention have at least one of the following beneficial effects:
[0035] (1) High communication rate and real-time performance: The protocol timing is implemented through pure hardware logic, and the position data returned by the slave is cyclically redundantly checked using a parallel computing architecture, eliminating software delay and enabling the host interface to stably support a communication rate of up to 10 MHz, meeting the needs of industrial real-time control.
[0036] (2) Rich functionality: It not only supports basic reading angle operations, but also fully implements the register read and write functions specified by the BiSS-C protocol. Through a series of collaborative designs such as generating 33 pulse sequences, encoding parameters during the timeout phase, and decoding data at specific frame positions, it realizes online configuration and status monitoring of encoder parameters, solving the problem of limited functionality in existing solutions;
[0037] (3) High flexibility and configurability: Adopting the architecture of "software instructions defining hardware behavior", the host computer can achieve flexible control and status reading by sending different concise serial port instructions. The instruction format is concise and clear. The same interface IP core can flexibly adapt to BiSS-C slave encoders of different manufacturers and specifications without modifying the hardware code, which solves the problems of poor flexibility and insufficient configurability of application-specific integrated circuits and early field-programmable gate array solutions;
[0038] (4) High reliability: After testing, it can continuously communicate for 50,000 frames at 2.5 MHz, 5 MHz and 10 MHz without errors, and the success rate of register read and write is 100% after 50,000 times, which has industrial-grade reliability. Attached Figure Description
[0039] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:
[0040] Figure 1 This is a block diagram of the overall architecture of a BiSS-C protocol host interface based on FPGA provided in an embodiment of the present invention.
[0041] Figure 2 This is a schematic diagram of the connection between the BiSS-C protocol host interface and the slave encoder provided in an embodiment of the present invention;
[0042] Figure 3 This is a schematic diagram of a host computer serial port debugging command sending interface provided in an embodiment of the present invention;
[0043] Figure 4 The result diagram of 50,000 reading angle tests provided for an embodiment of the present invention (10 MHz MA clock);
[0044] Figure 5 The result diagram of 50,000 register read / write tests provided in an embodiment of the present invention (10 MHz MA clock).
[0045] The attached figures are labeled as follows:
[0046] 100 - Host Interface; 110 - Serial Port Command Parsing Module; 120 - Pulse Trigger Control Module; 130 - Clock Generation Module; 140 - Parameter Latch Module; 150 - Data Decoding Module; 160 - CRC Check Module; 161 - CRC4 Calculation Unit; 162 - CRC6 Calculation Unit; 170 - First-In-First-Out Buffer; 180 - Serial Port Transmission Module; 200 - Host Computer; 300 - Slave Device. Detailed Implementation
[0047] To make the objectives, technical solutions, and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.
[0048] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.
[0049] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are only used to facilitate the description of this invention and to simplify the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0050] Furthermore, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0051] Please refer to Figure 1 This invention provides an FPGA-based BiSS-C protocol host interface. This host interface 100, as an IP core, is integrated within the FPGA (Field-Programmable Gate Array) chip and configured to support a communication rate of up to 10MHz. It mainly includes:
[0052] The serial port command parsing module 110 is used to receive and parse the serial port commands sent by the host computer 200, identify the command type and extract the associated address parameters and data parameters. The serial port commands include angle reading commands, register read commands and register write commands.
[0053] The pulse trigger control module 120 is connected to the serial port instruction parsing module 110 and is used to generate a corresponding number of trigger pulses according to the parsed instruction type. Specifically, a single pulse is generated in response to a read angle instruction, and a continuous multi-pulse sequence is generated in response to a register read instruction or a register write instruction.
[0054] The clock generation module 130 is connected to the pulse trigger control module 120. It is used to generate a MA clock signal that conforms to the BiSS-C protocol timing under the drive of the trigger pulse, and to encode the address parameters and / or data parameters onto the MA clock signal according to the instruction type during the timeout phase specified by the BiSS-C protocol.
[0055] The parameter latch module 140 is connected between the serial port instruction parsing module 110 and the clock generation module 130. It is used to latch the corresponding address parameters and / or data parameters when a register read instruction or register write instruction is received, and output them to the clock generation module 130.
[0056] The data decoding module 150, connected to the clock generation module 130, is used to sample and decode the SLO signal from the BiSS-C slave under the synchronization of the MA clock signal to obtain position data or register data.
[0057] The CRC check module 160 is connected to the data decoding module 150 and is used to perform cyclic redundancy check on the decoded data. The CRC check module 160 includes a parallel CRC calculation unit, which is used to complete the check calculation of the position data within one system clock cycle.
[0058] Each module interacts with signals and works collaboratively through the internal wiring of the field-programmable gate array.
[0059] Specifically, in this embodiment, the physical connection method between the host interface 100 and the external BiSS-C slave 300 (such as an encoder) is as follows: Figure 2 As shown, synchronous serial communication is achieved through the MA clock line and the SLO data line.
[0060] The serial port instruction parsing module 110 receives and parses the serial port instructions sent by the host computer 200. The serial port instructions include an angle read instruction, a register read instruction, and a register write instruction. The angle read instruction includes a first opcode and a first end character. The register write instruction includes a second opcode, a one-byte address, a one-byte data, and a second end character. The register read instruction includes a third opcode, a one-byte address, and a third end character.
[0061] In a preferred embodiment, as shown in Table 1 below, the angle read instruction consists of two bytes, for example, 0xBB followed by 0xAA, where 0xBB is the first opcode and 0xAA is the end marker. It should be noted that the bit width of the angle data can be flexibly configured according to actual needs. In this embodiment, the decoded single-turn and / or multi-turn position values will be combined and stored in a 64-bit wide register. This design natively supports absolute angle decoding up to 64 bits at the hardware level. The register write instruction consists of four bytes, for example, 0xBC followed by a register address byte, a byte of data to be written, and ends with 0xAA; the register read instruction consists of three bytes, for example, 0xB5 followed by a register address byte, and ends with 0xAA. The module internally includes a state machine used to detect the start byte, identify the opcode, extract subsequent address and data bytes according to a predefined format, and finally verify the end marker. After successful parsing, the serial port instruction parsing module 110 will identify the instruction type and extract the associated address and data parameters. This instruction-driven mechanism delegates the complex task of generating protocol timings to the hardware, while the host computer 200 only needs to perform high-level logic control, greatly improving the flexibility of system applications. Alternatively, the byte length and opcode value of the instruction can be redefined according to actual needs, as long as the parsing logic of the serial port instruction parsing module 110 is adjusted accordingly.
[0062] Table 1 Custom Serial Port Read / Write Commands
[0063] Custom instructions Frame header Returned data Reading angle 0xBB+0xAA 64-bit data Register write 0xBC + 1 byte address + 1 byte data + 0xAA No return value Register read 0xB5 + 1 byte address + 0xAA Data in register write mode (1 byte)
[0064] The pulse trigger control module 120 receives the instruction type signal from the serial port instruction parsing module 110. Its core function is to generate a corresponding number of trigger pulses based on different serial port instructions. For an angle read instruction, the module generates a single pulse, corresponding to a single frame or short frame of BiSS-C communication, primarily used for quickly reading position values. For register read or write instructions, the pulse trigger control module 120 generates a series of continuous pulses. In this embodiment, the continuous multi-pulse sequence generated by the pulse trigger control module 120 consists of 33 consecutive trigger pulses to meet the requirement of 33 consecutive frames of communication for BiSS-C protocol register access. This design achieves support for the complete BiSS-C protocol, allowing single angle read operations and complex register operations to be distinguished and executed through different trigger modes.
[0065] The clock generation module 130 initiates a communication transaction on the edge of the trigger pulse output by the pulse trigger control module 120. Internally, the clock generation module 130 implements a sophisticated finite state machine that strictly follows the BiSS-C protocol timing, controlling the host to activate the clock (MA) signal line and sequentially experience the stages of Idle, Acknowledge, Start, Control and Data Segment (CDS), Data, Error, Warning, Cyclic Redundancy Check (CRC), and Timeout.
[0066] During the timeout phase specified in the BiSS-C protocol, the clock generation module 130 encodes address parameters and / or data parameters onto the MA clock signal according to the instruction type. For example, in register read / write operations, when the clock generation module 130 reaches the "timeout" phase of a frame, it determines what information needs to be sent in the control and data segment in the next clock cycle based on the value of its internally maintained "frame counter" and the current operating mode (read / write). At this time, the clock generation module 130 reads the pre-latched register address or data from the parameter latch module 140 and encodes this information by modulating the level of the host activation clock signal line during the timeout phase.
[0067] A parameter latch module 140 is provided between the serial port instruction parsing module 110 and the clock generation module 130. When the serial port instruction parsing module 110 parses a register read or write instruction, it simultaneously outputs the extracted address parameters and data parameters. These parameters need to be temporarily stored for the clock generation module 130 to use frame by frame in the subsequent lengthy 33-frame communication. This ensures the accuracy and consistency of the encoded information and avoids errors caused by parameter changes during communication.
[0068] The data decoding module 150 samples and decodes the SLO signal returned by the slave device 300. It shares the same MA clock signal with the clock generation module 130 for synchronization, ensuring accurate sampling points. At each valid edge of the master activation clock, the data decoding module 150 samples the serial data output signal from the slave device 300 and converts the serial bit stream into parallel data. For angle read operations, the decoded data is the position data of the slave device 300. For register read operations, the returned data from the slave device 300 is embedded in specific fields across multiple consecutive frames.
[0069] In this embodiment, in response to the register read instruction, the data decoding module 150 is configured to acquire the returned data bit by bit from the control and data segments of frames 21 to 28, and latch it into a complete 8-bit register data in frame 29. Specifically, in the 33-frame sequence responding to the register read instruction, the 8-bit register data byte returned by the slave device 300 is distributed in the "control and data segment" of each frame from frame 21 to frame 28, with each frame carrying one data bit. The data decoding module 150 is configured to identify the current frame count. When the frame count enters the range of 21 to 28, it samples the serial data output signal once in the control and data segment of each frame to obtain one data bit. When frame 29 arrives, the module combines the 8 independent data bits acquired in the previous 8 frames (for example, taking the bit acquired in frame 21 as the most significant bit and the bit acquired in frame 28 as the least significant bit), latches it into a complete 8-bit byte, and outputs it as the result of this register read operation. This decoding logic precisely matches the return data format of the BiSS-C protocol.
[0070] The CRC check module 160 receives parallel data from the data decoding module 150 and performs cyclic redundancy check on the decoded data. This embodiment employs a hybrid check architecture to balance speed and resources. The CRC check module 160 comprises two independent units:
[0071] CRC4 Calculation Unit 161: Employs a fully parallel computing architecture, dedicated to verifying the position data returned by slave 300. This means that for a fixed-length input data (e.g., 11-bit position data and its status bits), all its CRC4 calculation logic is completed simultaneously within one system clock cycle, and the calculation result is available at the end of the cycle. This design minimizes the verification latency, ensuring it does not bottleneck continuous data streams up to 10 MHz, and is one of the key technologies supporting the high-speed performance of the interface.
[0072] CRC6 Calculation Unit 162: Used to verify long frame data (typically 28 bits, including command, address, data, CRC bits, etc.) related to register access. It adopts a serial calculation architecture. Driven by the MA clock signal, the calculation shifts and performs calculations bit by bit on the input 28 bits of data, and the verification result is obtained after 28 clock cycles. For register operations, the frequency is usually lower than continuous position reads, and the data is long. Using a serial architecture can save the logic resources of the field-programmable gate array.
[0073] The present invention will now be described in further detail with reference to the accompanying drawings and two specific embodiments.
[0074] Example 1: Angle reading operation
[0075] This embodiment is used to verify the correctness and stability of the host interface 100 of the present invention when continuously and at high speed reading location data. Please refer to... Figure 3 The host computer 200 runs a serial port debugging assistant software, configuring the communication port as COM7 and the baud rate as 1000000, and establishes a connection with the serial port command parsing module 110 implemented in the FPGA. In the sending area, the user inputs the hexadecimal sequence "BB AA", which is the reading angle command defined in this invention. After clicking send, the command is sent to the FPGA via the serial port. The serial port command parsing module 110 recognizes the first byte 0xBB as a reading angle command upon receiving it and then generates the corresponding control signal. The pulse trigger control module 120 responds to this command and generates a single trigger pulse. Under the drive of this pulse, the clock generation module 130 generates a complete BiSS-C protocol communication timing sequence and reads position data from the encoder. The data decoding module 150 decodes the SLO signal returned by the encoder and buffers the obtained position data through the first-in-first-out (FIFO) buffer 170 before sending it back to the host computer 200 via the serial port sending module 180. The above process is automatically repeated 50,000 times. The host computer 200 saves all returned position data and imports it into MATLAB software for processing and visualization. The results are as follows: Figure 4 As shown in the figure, the curves corresponding to the number of mechanical revolutions and the angle value per revolution for 50,000 position data points are displayed respectively. Both curves are continuous and smooth, without any jumps or breaks, which intuitively proves that in 50,000 continuous communications, the host interface 100 module of this invention can correctly and stably decode the data returned by the encoder without any data frame loss or bit errors, demonstrating extremely high communication reliability.
[0076] Example 2: Register read / write operations
[0077] like Figure 3 As shown, the user first sends the hexadecimal sequence "BC 51 02 AA" through the serial port debugging assistant. The serial port instruction parsing module 110 parses this as a register write instruction (opcode 0xBC), with the target register address at 0x51 and the data to be written at 0x02. The interface then performs a complete register write operation. Next, the user sends the sequence "B5 51 AA", which is a register read instruction (opcode 0xB5), requesting to read the register at address 0x51. After performing the read operation, the interface returns the read data through the serial port. Verification confirms that the data is indeed 0x02, indicating that the single register read / write function is correct.
[0078] To achieve high-intensity, comprehensive automated verification, this embodiment designs an automated testing scheme based on MATLAB scripts, the process of which is as follows: Figure 5As shown in the diagram. This scheme first generates 50,000 test vectors, each containing a 7-bit random register address and an 8-bit random write data, ensuring the test covers all possible data combinations. Then, MATLAB sends control commands to the lower-level computer via serial port, controlling the host interface 100 to sequentially execute register write and read operations. The host interface 100 uploads the read data to MATLAB via serial port. The MATLAB script automatically compares the read data bit-by-bit with the original write data and records the comparison results. If a discrepancy is found, error information is immediately recorded, including the address, written data, and read data. The entire process requires no manual intervention. The test system was configured with different communication clocks, and 50,000 complete "write-read-compare" cycles were completed at three rates: 2.5 MHz, 5 MHz, and 10 MHz. Figure 5 The command-line window shows that all tests were completed under a serial port connection with a baud rate of 1,000,000, and the output results are "OK=50000, FAIL=0". This indicates that the success rate was 100% in the three sets of a total of 150,000 register read and write operations.
[0079] The two embodiments above fully demonstrate that the FPGA-based BiSS-C protocol host interface provided by this invention is not only fully functional (supporting position reading and register configuration), but also maintains zero bit error rate and 100% operation success rate in data communication at communication rates up to 10 MHz, achieving the design goals of high speed, high reliability, and high flexibility.
[0080] Based on the same inventive concept, this invention also proposes an implementation method for a BiSS-C protocol host interface based on FPGA, comprising the following steps:
[0081] S1. Receive and parse the serial port commands sent by the host computer 200, identify the command type and extract the associated address parameters and data parameters. The serial port commands include angle read commands, register read commands and register write commands.
[0082] S2. Generate a corresponding number of trigger pulses according to the parsed instruction type, wherein a single pulse is generated in response to a read angle instruction, and a continuous multi-pulse sequence is generated in response to a register read instruction or a register write instruction.
[0083] S3. Driven by the trigger pulse, a MA clock signal conforming to the BiSS-C protocol timing is generated. During the timeout phase specified by the BiSS-C protocol, the address parameters and / or data parameters are encoded onto the MA clock signal according to the instruction type.
[0084] S4. Under the synchronization of the MA clock signal, sample and decode the SLO signal from the BiSS-C slave 300 to obtain position data or register data;
[0085] S5. Perform cyclic redundancy check on the decoded data, wherein at least the location data check is completed in parallel computing within one system clock cycle.
[0086] Specifically, when a register read instruction or register write instruction is received, the corresponding address parameters and / or data parameters are latched.
[0087] Preferably, performing cyclic redundancy check on the decoded data includes:
[0088] The location data verification calculation is completed within one system clock cycle using parallel computing; and...
[0089] The verification calculation of register data is completed through serial calculation driven by the MA clock signal.
[0090] Since the implementation method of the FPGA-based BiSS-C protocol host interface provided by this invention belongs to the same inventive concept as the FPGA-based BiSS-C protocol host interface described above, the implementation method of the FPGA-based BiSS-C protocol host interface provided by this invention has all the advantages of the FPGA-based BiSS-C protocol host interface described above. Therefore, the beneficial effects of the implementation method of the FPGA-based BiSS-C protocol host interface provided by this invention will not be described in detail here.
[0091] Based on the same inventive concept, this embodiment of the invention also proposes a readable storage medium on which a computer program is stored, and when the computer program is executed, it can implement the above-described method for implementing the FPGA-based BiSS-C protocol host interface.
[0092] A readable storage medium can be a tangible device capable of holding and storing instructions for use by an instruction execution device, such as, but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof. The computer programs described herein can be downloaded from the readable storage medium to various computing / processing devices, or downloaded via a network, such as the Internet, local area network, wide area network, and / or wireless network, to an external computer or external storage device. Networks can include copper transmission cables, fiber optic transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. Each computing / processing device's network adapter card or network interface receives and forwards a computer program from the network for storage on a readable storage medium within the respective computing / processing device. The computer program used to perform the operations of this invention can be execution instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, status setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages such as Smalltalk, C++, etc., and conventional procedural programming languages such as "C" or similar languages. The computer program can execute entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computer (e.g., via the Internet using an Internet service provider). In some embodiments, electronic circuits, such as programmable logic circuits, field-programmable gate arrays (FPGAs), or programmable logic arrays (PLAs), are personalized by utilizing state information from a computer program. These electronic circuits can execute computer-readable program instructions, thereby realizing various aspects of the present invention.
[0093] Various aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, systems, and computer program products according to embodiments of the invention. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by a computer program. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus to produce a machine such that, when executed by the processor of the computer or other programmable data processing apparatus, they create means for implementing the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams. These computer programs can also be stored in a readable storage medium that causes a computer, programmable data processing apparatus, and / or other device to operate in a particular manner; thus, the readable storage medium storing the computer program comprises an article of manufacture including instructions for implementing aspects of the functions / actions specified in one or more blocks of the flowchart illustrations and / or block diagrams.
[0094] A computer program may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the computer program executing on the computer, other programmable data processing apparatus, or other device to perform the functions / actions specified in one or more boxes of a flowchart and / or block diagram.
[0095] Since the readable storage medium provided by this invention belongs to the same inventive concept as the above-described FPGA-based BiSS-C protocol host interface implementation method, the readable storage medium provided by this invention has all the advantages of the above-described FPGA-based BiSS-C protocol host interface implementation method. Therefore, the beneficial effects of the readable storage medium provided by this invention will not be described in detail here.
[0096] In summary, this invention provides an FPGA-based BiSS-C protocol host interface and its implementation method, used to achieve high-speed data reading and register configuration of BiSS-C protocol slave encoders. A custom serial port instruction set is used to parse and respond to host computer commands, enabling flexible control and status reading with a concise and clear instruction format. It also supports multiple operating modes such as reading angle and register read / write, and can automatically generate single pulses or 33 pulses according to the instruction type without software intervention. This solves the problems of low communication speed, single mode, and insufficient flexibility in existing solutions, achieving a maximum communication rate of 10 MHz, supporting complete protocol functions, and possessing high reliability.
[0097] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure are within the protection scope of the present invention. Obviously, those skilled in the art can make various modifications and variations to the present invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the present invention and its equivalents, the present invention also intends to include these modifications and variations.
Claims
1. A BiSS-C protocol host interface based on FPGA, characterized in that, include: The serial port command parsing module is used to receive and parse serial port commands sent by the host computer, identify the command type and extract the associated address parameters and data parameters. The serial port commands include angle read commands, register read commands and register write commands. The pulse trigger control module is connected to the serial port instruction parsing module and is used to generate a corresponding number of trigger pulses according to the parsed instruction type. Specifically, a single pulse is generated in response to the read angle instruction, and a continuous multi-pulse sequence is generated in response to the register read instruction or the register write instruction. A clock generation module, connected to the pulse trigger control module, is used to generate an MA clock signal conforming to the BiSS-C protocol timing under the drive of the trigger pulse, and to encode the address parameters and / or the data parameters onto the MA clock signal according to the instruction type during the timeout phase specified by the BiSS-C protocol. A parameter latching module is connected between the serial port instruction parsing module and the clock generation module. When the register read instruction or the register write instruction is received, the corresponding address parameters and / or data parameters are latched and output to the clock generation module. The data decoding module, connected to the clock generation module, is used to sample and decode the SLO signal from the BiSS-C slave under the synchronization of the MA clock signal to obtain position data or register data; A CRC check module, connected to the data decoding module, is used to perform cyclic redundancy check on the decoded data. The CRC check module includes a parallel CRC calculation unit, which is used to complete the check calculation of the location data within one system clock cycle.
2. The FPGA-based BiSS-C protocol host interface according to claim 1, characterized in that, The pulse trigger control module generates a continuous multi-pulse sequence of 33 consecutive trigger pulses to meet the requirement of 33 consecutive frames of communication for BiSS-C protocol register access.
3. The FPGA-based BiSS-C protocol host interface according to claim 1, characterized in that, The read angle instruction includes a first opcode and a first end symbol; the register write instruction includes a second opcode, a one-byte address, a one-byte data, and a second end symbol; and the register read instruction includes a third opcode, a one-byte address, and a third end symbol.
4. The FPGA-based BiSS-C protocol host interface according to claim 1, characterized in that, In response to the register read instruction, the data decoding module is configured to acquire the returned data bit by bit from the control and data segments of frames 21 to 28, and latch it as a complete 8-bit register data in frame 29.
5. The FPGA-based BiSS-C protocol host interface according to claim 1, characterized in that, The CRC verification module includes independent CRC4 and CRC6 calculation units; the CRC4 calculation unit is the parallel CRC calculation unit, used to perform verification calculations on the location data; the CRC6 calculation unit adopts a serial calculation architecture, used to perform verification calculations on the register data under the drive of the MA clock signal.
6. The FPGA-based BiSS-C protocol host interface according to claim 5, characterized in that, The CRC4 calculation unit is used to perform CRC calculation on 11-bit input data within one system clock cycle; the CRC6 calculation unit is used to perform bit-by-bit calculation on 28-bit input data.
7. The FPGA-based BiSS-C protocol host interface according to claim 1, characterized in that, The BiSS-C protocol host interface is configured to support a communication rate of up to 10 MHz.
8. A method for implementing a BiSS-C protocol host interface based on FPGA, characterized in that, include: Receive and parse serial port commands sent by the host computer, identify the command type and extract the associated address parameters and data parameters. The serial port commands include angle read commands, register read commands and register write commands. The corresponding number of trigger pulses are generated according to the parsed instruction type, wherein a single pulse is generated in response to the read angle instruction, and a continuous multi-pulse sequence is generated in response to the register read instruction or the register write instruction; Driven by the trigger pulse, an MA clock signal conforming to the BiSS-C protocol timing is generated. During the timeout phase specified by the BiSS-C protocol, the address parameters and / or the data parameters are encoded onto the MA clock signal according to the instruction type. Under the synchronization of the MA clock signal, the SLO signal from the BiSS-C slave is sampled and decoded to obtain position data or register data; Cyclic redundancy check is performed on the decoded data, wherein at least the check of the location data is completed in parallel computing within one system clock cycle; Specifically, upon receiving the register read instruction or the register write instruction, the corresponding address parameters and / or data parameters are latched.
9. The method for implementing a BiSS-C protocol host interface based on FPGA according to claim 8, characterized in that, The cyclic redundancy check of the decoded data includes: The location data verification calculation is completed within one system clock cycle using parallel computing; and... The verification calculation of the register data is completed through serial calculation, driven by the MA clock signal.
10. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed, it can implement the method for implementing the FPGA-based BiSS-C protocol host interface according to claim 8 or 9.