Memory access method based on memory tag extension mechanism, system on chip and storage medium

Abstract

This application relates to the field of embedded systems and provides a memory access method, on-chip system, and computer-readable storage medium based on a memory tag extension mechanism. The on-chip system includes a memory tag extension unit, memory, and a tag cache. The memory tag extension unit is connected to the memory and the tag cache. The tag cache is used to store tags allocated to memory based on the memory tag extension mechanism. The memory tag extension unit is used to obtain memory access requests based on the memory tag extension mechanism, split the memory access requests based on the memory tag extension mechanism into a first access request to memory and a second access request to tags, execute the first access request to memory, and execute the second access request to the tag cache.

Description

Technical Field

[0001] This application belongs to the field of embedded systems, and in particular relates to a system-on-a-chip. Background Technology

[0002] Memory Tagging Extension (MTE) is a mechanism for checking the correct use of data in memory. MTE assigns a 4-bit tag to every 16 bytes of data in memory. This memory tag is stored along with the data in memory and can be called a physical address tag or physical tag. For any memory access with MTE enabled, the physical tag is checked, and the result of the tag check determines whether an error signal is issued.

[0003] In terms of actual hardware transmission, under the MTE mechanism, for each read operation, in addition to reading the data, the corresponding tag also needs to be read; for each write operation, in addition to writing the corresponding data, the tag matching the data also needs to be attached. Since the data and the corresponding tag are generally stored in different address ranges in memory, an access request based on the MTE mechanism will be split into two memory access requests: one for the data and the other for the tag.

[0004] This splitting mechanism significantly increases the number of memory accesses; at the same time, since the size of the tag data is much smaller than the amount of data in a single memory access, the amount of effective data in the tag access request is very small; the combination of these two factors leads to a significant negative impact on memory efficiency caused by memory access based on the MTE mechanism. Summary of the Invention

[0005] This application provides a system-on-a-chip that can solve the problem that memory access based on the MTE mechanism has a significant negative impact on memory efficiency in related technologies.

[0006] In a first aspect, embodiments of this application provide a system-on-a-chip (SoC) including a memory tag extension unit, memory, and a tag cache. The memory tag extension unit is connected to the memory and the tag cache. The tag cache is used to store tags allocated to memory based on a memory tag extension mechanism. The memory tag extension unit is used to obtain memory access requests based on the memory tag extension mechanism, split the memory access requests based on the memory tag extension mechanism into a first access request to memory and a second access request to tags, execute the first access request to memory, and execute the second access request to the tag cache.

[0007] In one possible implementation of the first aspect, the memory access request based on the memory tag extension mechanism is a memory read request, and the second access request is a tag read request to the tag cache.

[0008] In one possible implementation of the first aspect, the memory access request based on the memory tag extension mechanism is a memory write request of the transfer type, and the second access request is a tag read request to the tag cache.

[0009] In one possible implementation of the first aspect, the memory access request is a transfer-type memory write request, and the second access request is to perform no operation.

[0010] In one possible implementation of the first aspect, the memory access request is an update-type memory write request, and the second access request is a tag write request to the tag cache.

[0011] In one possible implementation of the first aspect, the tag cache is used to arbitrate multiple memory access requests based on the memory tag extension mechanism from multiple memory tag extension units.

[0012] In one possible implementation of the first aspect, the memory tag extension unit belongs to the memory access channel between the processing unit and memory.

[0013] In one possible implementation of the first aspect, the memory tag extension unit is an independent element in the memory access channel.

[0014] Secondly, embodiments of this application provide a memory access method based on a memory tag extension mechanism, applied to a system-on-a-chip (SoC). The SoC includes memory and a tag cache, the tag cache being used to store tags allocated to memory based on the memory tag extension mechanism. The method includes: obtaining a memory access request based on the memory tag extension mechanism; splitting the memory access request based on the memory tag extension mechanism into a first access request to memory and a second access request to tags; executing the first access request to memory and executing the second access request to the tag cache.

[0015] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the memory access method based on the memory tag extension mechanism described in the first aspect.

[0016] Fourthly, embodiments of this application provide a computer program product that, when running on a system-on-a-chip, causes the system-on-a-chip to execute the memory access method based on the memory tag extension mechanism described in the first aspect.

[0017] Fifthly, embodiments of this application provide a vehicle that includes the system-on-a-chip provided in the first aspect of this application.

[0018] The beneficial effects of this application embodiment compared with the prior art are as follows: By providing a system-on-a-chip (SoC) including a memory tag expansion unit, memory, and a tag cache, the memory tag expansion unit connects the memory and the tag cache. The tag cache stores tags allocated to memory based on the memory tag expansion mechanism. The memory tag expansion unit is used to obtain memory access requests based on the memory tag expansion mechanism, split the memory access requests into a first access request to memory and a second access request to tags, execute the first access request to memory, and execute the second access request to the tag cache. In this embodiment, a tag cache is introduced to store tags allocated to memory based on the memory tag expansion mechanism. The memory tag expansion unit transforms the original access request to the tag storage area in memory into a second access request to the tag cache. During the operation of the SoC, based on the principle of locality of reference, the most recently accessed tags are read into the tag cache, making tag operations more likely to hit the tag cache without memory operations, greatly reducing tag access latency, reducing memory access, lowering memory load, and improving memory throughput efficiency. It accelerates memory access based on the memory tag extension mechanism while also improving memory efficiency. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the structure of a system-on-a-chip provided in an embodiment of this application;

[0021] Figure 2 This is a schematic diagram of the structure of a system-on-a-chip provided in another embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the structure of a dual-channel shared label cache in a specific example of the present application system;

[0023] Figure 4 This is a flowchart illustrating a memory access method based on a memory tag extension mechanism provided in an embodiment of this application. Detailed Implementation

[0024] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0025] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0026] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0027] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0028] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0029] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0030] Figure 1The diagram shown is a block diagram of a partial structure of a system-on-a-chip (SoC) provided in an embodiment of this application. A SoC is a chip integration of the core of an information system, integrating key system components onto a single chip. (Reference) Figure 1 The system-on-chip includes a processing unit 10, a bus 20, a memory tag expansion unit 30, memory 40, and a tag cache 50.

[0031] Those skilled in the art will understand that Figure 1 The structure of the system-on-a-chip shown does not constitute a limitation on the system-on-a-chip and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0032] A system-on-a-chip (SoC) can include multiple processing units, such as microprocessors, digital signal processors, graphics processors, and neural network processors, which often share memory.

[0033] The following is combined with Figure 1-3 The various components of the system-on-a-chip are described in detail.

[0034] The processing unit 10 can specifically be a central processing unit (CPU), or other general-purpose processors, microcontroller units (MCUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors, graphics processors, neural network processors, or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be any conventional processor.

[0035] Figure 1 The number of processing units 10 shown is one, but the actual number of processing units 10 can be more, and the types of different processing units 10 can be different. For example, the system-on-a-chip may include multiple processing units 10 such as a microcontroller unit, a digital signal processor, a graphics processor, and a neural network processor. All processing units 10 share memory 40.

[0036] Memory 40, also known as main memory, is a high-speed random access memory (RAM) that can be directly addressed and accessed by each processing unit 10. It is used to temporarily store data required and generated by the executing program. Memory 40 may include at least one of static RAM (SRAM) and dynamic RAM (DRAM). For cost and power consumption considerations, DRAM is commonly used as main memory.

[0037] Each processing unit 10 and memory 40 are connected to bus 20. A memory controller 41 is generally provided between memory 40 and bus 20 to handle access requests to memory 40 from each processing unit 10 and transmitted through bus 20. Bus 20 includes a first interface 21 and a second interface 22. The first interface 21 is used to connect to the processing unit 10, and the second interface 22 is used to connect to the memory controller 41.

[0038] A single processing unit 10 can access memory 40 via bus 20. The processing unit 10, memory 40, and the components used to transmit memory access requests and their feedback results between them form a memory access channel (hereinafter referred to as a channel). These components generally include a first interface 21, a second interface 22, and a memory controller 41. If there is more than one processing unit 10, multiple different channels may exist at the same time. Different channels may share the same components, such as the second interface 22 and the memory controller 41.

[0039] In a channel, processing unit 10 initiates a memory access request, which is transmitted through intermediate elements to reach memory 40. Based on the flow of the memory access request, upstream and downstream elements in the channel can be distinguished. Specifically, for a given element in the channel, the source of the memory access request received by that element is upstream, and the object transmitting the memory access request is downstream. For example, for the second interface 22, its upstream is the first interface 21, and its downstream is the memory controller 41.

[0040] The memory tag extension unit 30 belongs to a channel and can be connected to the memory 40 directly or through other components in the channel. The memory tag extension unit 30 can be a newly added independent component in the channel, for example... Figure 1 An independent component disposed between the processing unit 10 and the first interface 21, or Figure 2 An independent component located between the second interface 22 and the memory controller 41; or an existing component in the channel, for example, using one of the first interface 21, the second interface 22 and the memory controller 41 as a memory tag extension unit 30.

[0041] Tag cache 50 is used to store tags allocated to memory 40 based on the memory tag expansion mechanism. Tag cache 50 is connected to memory tag expansion unit 30. Tag cache 50 is a memory independent of memory 40, and it also belongs to RAM; its specific type is not limited.

[0042] The memory tag extension unit 30 is used to obtain memory access requests based on the memory tag extension mechanism, split the memory access requests based on the memory tag extension mechanism into a first access request to memory 40 and a second access request to tags, then execute the first access request to memory 40 and the second access request to tag cache 50. For the first access request, the memory tag extension unit 30 can transmit it to downstream components to complete execution; for the second access request, the memory tag extension unit 30 can transmit it to tag cache 50 to complete execution.

[0043] Specifically, the memory tag extension unit 30 can obtain memory access requests from its upstream components. Since not all memory accesses may be based on memory tag extension, the memory tag extension unit 30 can, after receiving a memory access request, first determine whether the memory access request is based on the memory tag extension mechanism. If not, there is no need to split it, and the memory access request can be executed directly on the memory 40. If it is, the memory access request is split and then executed separately.

[0044] Memory access requests can be categorized into read requests and write requests to memory 40. When splitting memory access requests, if the memory access request based on the memory tag expansion mechanism is a memory read request, then the first access request is a data read request to memory 40, and the second access request is a tag read request to the tag cache 50. If the memory access request based on the memory tag expansion mechanism is a memory write request, then the first access request is a data write request to memory 40, and the tag type of the memory write request can be further determined.

[0045] Tag types can include transmission and update.

[0046] The transfer type indicates that the carried tag is clean, meaning the tag to be written by processing unit 10 is the same as the tag currently stored in memory 40. In this case, a tag can be written to memory 40, but this operation will not change the stored tag and is therefore invalid. In other words, for a transfer-type memory write request, the tag writing operation can be omitted. Therefore, a transfer-type memory write request can be treated as a normal memory write request without using the memory tag expansion mechanism, i.e., the second access request will not perform any operation; or, the second access request can be a tag read request for tag cache 50, attempting to read the tag from memory 40 into tag cache 50 for subsequent operations.

[0047] The update type indicates that the tag being updated is dirty, meaning that the tag to be written by processing unit 10 is different from the tag currently stored in memory 40. In this case, the second access request is a tag write request to the tag cache 50.

[0048] For a tag read request, tag cache 50 can respond to the request and attempt to read the tag. If a match is found (i.e. the tag exists in tag cache 50), the tag is returned to memory tag extension unit 30. If a match is not found (i.e. the tag does not exist in tag cache 50), the tag is read from memory 40 and returned to memory tag extension unit 30.

[0049] For a tag write request, tag cache 50 can respond by writing the tag to tag cache 50, and write the tag to memory 40 when the write-back condition is met. The write-back condition can be determined according to the working strategy of tag cache 50, such as writing directly to memory 40, or writing to memory 40 when the tag is removed from tag cache 50, etc., and there are no restrictions here.

[0050] Since the operating frequency of memory 40 is significantly lower than that of processing unit 10, memory tag extension unit 30, as a component in the channel, generally includes a queue for temporarily storing access requests. There can be more than one queue. When the number of queues is greater than one, memory tag extension unit 30 can arbitrate multiple memory access requests from different queues based on the memory tag extension mechanism, selecting one for splitting and transmission.

[0051] When multiple channels exist simultaneously, each channel can be configured with an independent tag buffer 50, or multiple channels can share a single tag buffer 50. For example... Figure 3 As shown in the diagram, the processing unit 10, memory tag extension unit 30, first interface 21 and second interface 22, memory controller 41, and memory 40 on the left side of the figure constitute channel 0, with the direction of memory access requests indicated by dashed lines with arrows. The processing unit 10, memory tag extension unit 30, first interface 21 and second interface 22, memory controller 41, and memory 40 on the right side of the figure constitute channel 1, with the direction of memory access requests indicated by dotted lines with arrows. The two channels share the second interface 22 in bus 20 and its downstream memory controller 41 and memory 40, and share the same tag cache 50.

[0052] In a scenario where multiple channels share the tag cache 50, the tag cache 50 can arbitrate multiple memory access requests based on the memory tag extension mechanism from multiple memory tag extension units 30 and select one to respond to.

[0053] In addition to memory 40, the system-on-a-chip may also include non-volatile memory (not shown in the figure), such as flash memory, multimedia cards, card-type memory, etc., for storing operating systems, applications, bootloaders, data and other programs, such as program code of computer programs.

[0054] This embodiment introduces a tag cache to store tags allocated to memory based on a memory tag expansion mechanism. The memory tag expansion unit transforms the original access request to the tag storage area in memory into a secondary access request to the tag cache. During the operation of the on-chip system, based on the principle of locality of reference, the most recently accessed tags are read into the tag cache. This increases the probability that tag operations will hit the tag cache without requiring memory access, significantly reducing tag access latency. Simultaneously, it reduces memory access, lowers memory load, and improves memory throughput. This accelerates memory access based on the memory tag expansion mechanism while also improving memory efficiency.

[0055] The memory access method based on the memory tag extension mechanism provided in this application can be implemented as a computer software program. For example, an embodiment of this application provides a computer program product including a computer program carried on a computer-readable medium, the computer program containing program code for performing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from an external device via a communication interface (not shown in the figure), and / or installed from a removable external storage unit. When the computer program is executed by an element with control functions, it implements the various functions defined in the memory access method based on the memory tag extension mechanism provided in this application.

[0056] Figure 4 The illustration shows a schematic flowchart of a memory access method based on a memory tag extension mechanism according to an embodiment of this application. It is provided as an example and not as a limitation. The method can be applied to the above-described on-chip system and executed by a component with control functions, such as a memory tag extension unit.

[0057] S1: Obtain a memory access request based on the memory tag extension mechanism.

[0058] S2: Split the memory access request based on the memory tag extension mechanism into a first access request to memory and a second access request to the tag.

[0059] S3: Perform the first access request to memory and the second access request to the tag cache.

[0060] This application also provides a vehicle, specifically a wheeled vehicle powered by electricity, fossil fuels, or other similar sources. This vehicle includes the system-on-a-chip (SoC) provided in the foregoing embodiments, which controls the operation of the vehicle.

[0061] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0062] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0063] In the embodiments provided in this application, it should be understood that the disclosed apparatus / network devices and methods can be implemented in other ways. For example, the apparatus / network device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0064] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0065] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A system-on-a-chip, characterized in that, The system-on-a-chip includes a memory tag expansion unit, memory, and a tag cache. The memory tag expansion unit is connected to the memory and the tag cache. The tag cache is used to store tags allocated to the memory based on the memory tag expansion mechanism. The memory tag extension unit is used to obtain memory access requests based on the memory tag extension mechanism, split the memory access requests based on the memory tag extension mechanism into a first access request to memory and a second access request to tags, execute the first access request to the memory, and execute the second access request to the tag cache.

2. The system-on-a-chip as described in claim 1, characterized in that, The memory access request based on the memory tag expansion mechanism is a memory read request, and the second access request is a tag read request for the tag cache.

3. The system-on-a-chip as described in claim 1, characterized in that, The memory access request based on the memory tag extension mechanism is a memory write request of the transfer type, and the second access request is a tag read request for the tag cache.

4. The system-on-a-chip as described in claim 1, characterized in that, The memory access request is a transfer-type memory write request, and the second access request is to perform no operation.

5. The system-on-a-chip as described in claim 1, characterized in that, The memory access request is an update-type memory write request, and the second access request is a tag write request to the tag cache.

6. The system-on-a-chip as described in any one of claims 1-5, characterized in that, The tag cache is used to arbitrate multiple memory access requests based on the memory tag extension mechanism from multiple memory tag extension units.

7. The system-on-a-chip as described in any one of claims 1-5, characterized in that, The memory tag extension unit belongs to the memory access channel between the processing unit and the memory.

8. The system-on-a-chip as described in claim 7, characterized in that, The memory tag extension unit is an independent element in the memory access channel.

9. A memory access method based on a memory tag extension mechanism, characterized in that, The method is applied to a system-on-a-chip, the system-on-a-chip including memory and a tag cache, the tag cache being used to store tags allocated to the memory based on the memory tag expansion mechanism, the method comprising: Obtain memory access requests based on the memory tag extension mechanism; The memory access request based on the memory tag extension mechanism is split into a first access request to memory and a second access request to the tag; The first access request is executed on the memory, and the second access request is executed on the tag cache.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the method as described in claim 9.

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