In-memory digital computation module and array
By performing in-memory digital computation in a non-volatile memory array and utilizing delay decoders and adders, the energy efficiency limitations and logical complexity issues of traditional computing units are solved, achieving low-power and high-efficiency computing.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- CETHIK GRP
- Filing Date
- 2024-12-31
- Publication Date
- 2026-07-10
AI Technical Summary
Traditional digital computing units have limitations in terms of computing power and energy efficiency, and require high memory bandwidth. Sparse operations increase logical complexity and computation timing.
Non-volatile memory arrays are used for in-memory digital computation. Multiplication and addition operations are implemented through delay decoders and adders, reducing the dependence on caches and registers. Sparse characteristics are achieved by using word line level control to reduce power consumption.
It effectively reduces chip area and power consumption, making it particularly suitable for low-bit-level computing. It also reduces input zeroing and data buffering, thereby improving computing efficiency.
Smart Images
Figure CN122364154A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to an in-memory digital computing module and array. Background Technology
[0002] With the rapid development of big data and large model technologies, new challenges have been placed on the computing power of chips, and the demand for data volume and storage has increased significantly. Traditional digital computing units still use a near-memory approach, setting up corresponding shared memory near the computing unit. This does not eliminate data movement power consumption, while setting an upper limit on energy efficiency and a lower limit on the throughput of memory or buffers, thus increasing the bandwidth requirements of memory. Furthermore, when using sparsity to optimize input, additional selection logic needs to be introduced, which undoubtedly prolongs the computation time and increases logical complexity. Summary of the Invention
[0003] The in-memory digital computing module and array provided by this invention can perform in-memory digital computing using a non-volatile memory array, reducing the dependence on cache and registers and lowering chip area and power consumption.
[0004] In a first aspect, the present invention provides an in-memory digital computing module, comprising:
[0005] An in-memory multiplication unit, comprising a non-volatile memory array for storing weight data;
[0006] A delay decoder, wherein the input interface of the delay decoder is used to receive input data, each output interface of the delay decoder is used to be electrically connected to the word line of the corresponding row in the non-volatile memory array, and the delay decoder is used to delay the received input data for a preset time and then select the corresponding output interface to output it.
[0007] An adder, comprising sub-adders corresponding one-to-one with each column of the in-memory multiplication unit, wherein one input interface of the sub-adder is electrically connected to the read interface of the corresponding column in the in-memory multiplication unit, and the other input interface of the sub-adder is used to receive target data;
[0008] The result register includes storage areas corresponding one-to-one with the multiple sub-adders. Each storage area is electrically connected to the output interface of the corresponding sub-adder. The result register is used to receive and store the accumulated result output by the sub-adders.
[0009] Optionally, the delay decoder includes:
[0010] A delay register, the input interface of which is used to receive input data; the control interface of which is used to receive a clock signal, so as to output the stored data according to the clock signal;
[0011] A word line selector, wherein the input interface of the word line selector is electrically connected to the output interface of the delay register, and the multiple output interfaces of the word line selector are electrically connected one-to-one with the word lines of multiple rows of the non-volatile memory array;
[0012] The counter has an input interface electrically connected to the clock signal and an output interface electrically connected to the word line selector, so that the word line selector selects the corresponding word line to output the data based on the output data of the counter.
[0013] Optionally, the non-volatile storage array includes multiple non-volatile storage bits, each non-volatile storage bit storing one bit of binary data after the weight data binary bit decomposition.
[0014] Optionally, the storage bit can be composed of any one or more of the following structures: a single transistor single storage cell structure, a two transistor one storage cell structure, a two transistor two storage cell structure, and a four transistor four storage cell structure.
[0015] Optionally, the storage unit includes any one or more combinations of magnetic random access memory, resistive random access memory, and phase change memory.
[0016] Secondly, the present invention also provides an in-memory digital computing array, comprising:
[0017] A computing array comprising multiple in-memory digital computing modules as described in any of the above embodiments, wherein the input interface of the delay decoder of the in-memory digital computing module is electrically connected to the output interface of the delay decoder of the in-memory digital computing module in the previous column of the current row; and the output interface of the result register of the in-memory digital computing module is electrically connected to the input interface of the adder in the next row of the current column, so as to output target data to the adder in the next row of the current column.
[0018] An accumulation circuit is provided, comprising multiple accumulation sub-circuits, each corresponding to a column of in-memory digital calculation modules. The accumulation sub-circuit is electrically connected to the output interface of the result register of the last in-memory digital calculation module in the corresponding column. The accumulation sub-circuit is used to shift and accumulate the data in the result register.
[0019] Optionally, it also includes:
[0020] An activation module has multiple output interfaces. Each output interface of the activation module is electrically connected to the input interface of the delay decoder of a row of in-memory digital computing modules in the computing array. The activation module is used to transmit input data to multiple rows of in-memory digital computing modules in the computing array according to a preset period.
[0021] Optionally, the activation module is used to start transmitting input data to the in-memory digital calculation module in the nth clock cycle, where n is an integer not less than 0.
[0022] Optionally, the accumulator sub-circuit includes:
[0023] Multiple first shift units are electrically connected one-to-one with multiple storage areas in the corresponding result register. The first shift unit is used to shift the weight of the data bits stored in the corresponding storage area. The first shift unit is used to obtain the first data in the corresponding storage area and shift the first data to the left by m-1 bits, where m is the position number of the storage area corresponding to the current first shift unit in the multiple storage areas in the same result register.
[0024] A plurality of second shift units are electrically connected to a plurality of first shift units in a one-to-one correspondence. The second shift unit is used to shift the data obtained from the corresponding first shift unit to the left by N bits in the (k+N)th cycle. Here, k is the number of rows of the in-memory digital computing array, and N is the counting period of the output data of the corresponding first shift unit and is an integer not less than 0. The second shift unit is used to shift the output data of the corresponding first shift unit in the corresponding output period.
[0025] An accumulation unit is electrically connected to the plurality of second shift units, and the accumulation unit is used to accumulate the data output by the second shift units over multiple cycles.
[0026] Optionally, the accumulation circuit further includes a counter, the input interface of which is used to receive a clock signal, the output interface of which is electrically connected to the second shift unit, and the counter is used to cyclically count based on the clock signal and the number of elements, starting from the kth cycle.
[0027] In the technical solution provided by this invention, weight data is stored in a non-volatile memory array, and data is input to the word lines of the non-volatile memory array periodically. Based on the high and low levels of the word lines and the results stored in the non-volatile memory cells, in-memory digital multiplication calculations can be completed. This technical solution effectively reduces the dependence on caches and registers, lowers the chip area, and is particularly suitable for calculations with low bit counts, such as hybrid memory computing. Furthermore, because in-memory computing inherently possesses sparse input characteristics—that is, when the input is low-level, the word lines are not activated and no output is generated—the need for zero-removal of inputs and data buffering is reduced, effectively lowering power consumption. Attached Figure Description
[0028] Figure 1 This is a schematic diagram of an in-memory digital computing module according to an embodiment of the present invention;
[0029] Figure 2 This is a schematic diagram of a delay decoder for an in-memory digital computing module according to another embodiment of the present invention;
[0030] Figure 3 This is a schematic diagram of an in-memory digital computing array according to another embodiment of the present invention;
[0031] Figure 4 This is a schematic diagram illustrating the connection between adjacent in-memory digital computing modules in an in-memory digital computing array according to another embodiment of the present invention.
[0032] Figure 5 This is a schematic diagram of the accumulation circuit in an in-memory digital computing array according to another embodiment of the present invention;
[0033] Figure 6 This is a schematic diagram illustrating the principle of in-memory digital computing array performing in-memory digital computing according to another embodiment of the present invention. Detailed Implementation
[0034] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0035] This invention provides an in-memory digital computing module, such as... Figure 1 As shown, it includes:
[0036] The in-memory multiplication unit includes a non-volatile memory array for storing weighted data. In some embodiments, taking a magnetic memory cell as an example, the multiplication in the in-memory multiplication unit is achieved by controlling a word line transistor. When the word line transistor is low (input is 0), the word line transistor is off, no induced current is generated, and the output result is '0'. When the word line transistor is high, the output is '1' when the memory cell resistance is high, and '0' when the resistance is low. For example, when the in-memory multiplication unit uses a magnetic tunnel junction memory array, the multiplication truth table of the in-memory multiplication unit can be configured as follows:
[0037] Word line data Storage bit resistance state Read interface output of storage bit 1 H 1 0 H 0 1 L 0 0 L 0
[0038] A delay decoder is provided, wherein the input interface of the delay decoder is used to receive input data, and each output interface of the delay decoder is used to be electrically connected to the word line of the corresponding row in the non-volatile memory array. The delay decoder is used to delay the received input data for a preset time and then select the corresponding output interface for output. In some embodiments, the delay decoder can select word lines of multiple rows of the non-volatile memory array to realize automatic switching of word lines in computing mode, reduce control signal pressure, and realize pipelined computing.
[0039] An adder includes sub-adders corresponding one-to-one with each column of the in-memory multiplication unit. One input interface of each sub-adder is electrically connected to the read interface of the corresponding column in the in-memory multiplication unit, and the other input interface of the sub-adder is used to receive target data. In some embodiments, for an array formed by multiple in-memory digital computing modules, the adder is used to receive the data output by the result register of the previous row of in-memory digital computing modules and add it to the output of the in-memory multiplication unit in this row, and temporarily store the result in the result register.
[0040] A result register includes storage areas corresponding one-to-one with each of the sub-adders. Each storage area is electrically connected to the output interface of the corresponding sub-adder. The result register receives and stores the accumulated result output by the sub-adders. In some embodiments, the result register may include multiple sub-registers, each corresponding to a sub-adder; alternatively, a result register may have multiple fields or areas, each corresponding to a sub-adder. The result register stores the data output by each sub-adder. For an array formed by multiple in-memory digital computing modules, the result register stores the data output by the adders and transfers the stored data to the corresponding sub-adder in the next row.
[0041] In the technical solution provided by this invention, weight data is stored in a non-volatile memory array, and data is periodically input to the word lines of the non-volatile memory array. Based on the high and low levels of the word lines and the results stored in the non-volatile memory cells, in-memory digital multiplication calculations can be completed. The technical solution provided by this invention effectively reduces the dependence on caches and registers, lowers the chip area, and is particularly suitable for calculations with low bit counts, such as hybrid memory computing. Furthermore, because in-memory computing inherently possesses sparse input characteristics—that is, when the input is low-level, the word lines are not activated and no output is generated—the need for zero-removal of inputs and data buffering is reduced, effectively lowering power consumption.
[0042] As an optional implementation method, such as Figure 2 As shown, the delay decoder includes:
[0043] A delay register has an input interface for receiving input data and a control interface for receiving a clock signal to output stored data according to the clock signal. In some embodiments, the delay register is typically composed of several flip-flops for receiving signals and delaying input.
[0044] A word line selector is included, with its input interface electrically connected to the output interface of the delay register. Multiple output interfaces of the word line selector are electrically connected one-to-one with the word lines of multiple rows of the non-volatile memory array. In some embodiments, the word line selector includes several transistor switches for switching the input signal by word lines. A counter works in conjunction with the word line selector to perform row-by-row switching.
[0045] A counter is included, with its input interface electrically connected to the clock signal and its output interface electrically connected to the word line selector. This allows the word line selector to select the corresponding word line for data output based on the counter's output data. In some embodiments, the counter and the delay register may use the same clock signal. The clock signal triggers the delay register to output data, while the counter counts according to the clock signal and outputs the count result to the word line selector, enabling the word line selector to select the word line based on the acquired count data.
[0046] As an optional implementation, the non-volatile memory array includes multiple non-volatile memory bits, each storing one bit of binary data after the weight data is decomposed into binary bits. In some embodiments, a non-volatile memory bit can typically store one bit of binary data. Therefore, when storing weight data, each weight data needs to be decomposed into binary bits, and each non-volatile memory bit stores one bit of the decomposed binary data. Since different bits of binary data for a single weight are stored in different memory bits of the same in-memory computing module, when inputting data, the different bits of binary data for a single input data need to be input sequentially into the in-memory computing unit on a periodic basis, and the output is shifted sequentially.
[0047] As an optional implementation, the storage bit is composed of any one or more of the following: a single transistor single storage cell structure, a two transistor one storage cell structure, a two transistor two storage cell structure, and a four transistor four storage cell structure.
[0048] As an optional implementation, the storage unit includes any combination of one or more of magnetic random access memory, resistive random access memory, and phase change memory.
[0049] This invention also provides an in-memory digital computing array, such as... Figures 3-4 As shown, it includes:
[0050] A computing array comprising multiple in-memory digital computing modules as described in any of the above embodiments, wherein the input interface of the delay decoder of the in-memory digital computing module is electrically connected to the output interface of the delay decoder of the in-memory digital computing module in the previous column of the current row; and the output interface of the result register of the in-memory digital computing module is electrically connected to the input interface of the adder in the next row of the current column, so as to output target data to the adder in the next row of the current column.
[0051] In some embodiments, the input interface of the delay decoder of the current in-memory digital computing module is electrically connected to the output interface of the delay decoder of the in-memory digital computing module in the previous column of the current row, which enables the input signal and part of the control signal of the in-memory computing unit of the current column to be delayed by one clock cycle and fed into the next column in the row direction; the output interface of the result register of the in-memory digital computing module is electrically connected to the input interface of the adder of the next row of the current column, which enables the output of the in-memory computing unit of the current row to be fed into the next row in the column direction and used as the input of the adder of the next row.
[0052] An accumulation circuit includes multiple accumulation sub-circuits, each corresponding to a column of in-memory digital calculation modules. Each accumulation sub-circuit is electrically connected to the output interface of the result register of the last in-memory digital calculation module in its corresponding column. The accumulation sub-circuit is used to shift and accumulate the data in the result register. In some embodiments, the accumulation sub-circuit is used to shift and accumulate the results calculated by the entire column of in-memory digital calculation modules, thereby obtaining the calculation result of the entire calculation array.
[0053] As an optional implementation, continue as follows Figure 3 As shown, it also includes:
[0054] An activation module has multiple output interfaces. Each output interface of the activation module is electrically connected to the input interface of the delay decoder of a row of in-memory digital computing modules in the computing array. The activation module is used to transmit input data to multiple rows of in-memory digital computing modules in the computing array according to a preset period.
[0055] In some embodiments, the multiple output interfaces of the activation module correspond to multiple in-memory calculation modules. During the calculation process, each output interface is used to input data to a single in-memory calculation module so that the single in-memory calculation module can perform in-memory calculation.
[0056] As an optional implementation, the activation module is used to start transmitting input data to the in-memory digital calculation module in the nth clock cycle, where n is an integer not less than 0.
[0057] In some embodiments, the activation module is configured such that, except for the first row, the input of the in-memory computation unit in the current row is one cycle slower than the previous row and one cycle faster than the next row; the first row has no input delay; the input follows a stepped pipeline, and when there is sufficient input data, all in-memory multiplication units are activated after a certain number of cycles.
[0058] As an optional implementation method, such as Figure 5 As shown, the accumulator sub-circuit includes:
[0059] Multiple first shift units are electrically connected one-to-one with multiple storage areas in the corresponding result register. Each first shift unit is used to shift the data stored in the corresponding storage area. The first shift unit is also used to obtain the first data in the corresponding storage area and shift the first data left by m-1 bits, where m is the position number of the storage area corresponding to the current first shift unit within the multiple storage areas of the same result register. In some embodiments, the result register has multiple storage areas, each corresponding to the in-memory multiplication output result of a column of weighted binary bit decomposition data. During the multiplication calculation, the least significant bit does not need to be shifted, and the result needs to be shifted forward by one bit for each increment. Therefore, in this embodiment, m is the position number of the storage area corresponding to the current first shift unit within the multiple storage areas of the same result register, and the position numbers of the multiple storage areas in the same result register should be arranged sequentially from the least significant bit to the most significant bit.
[0060] Multiple second shift units are electrically connected to multiple first shift units in a one-to-one correspondence. Each second shift unit is used to shift the data obtained from the corresponding first shift unit to the left by N bits in the (k+N)th cycle. Here, k is the row number of the in-memory digital computation array, and N is the counting cycle of the output data of the corresponding first shift unit and is an integer not less than 0. The second shift unit is used to shift the output data of the corresponding first shift unit in its corresponding output cycle. In some embodiments, since the input data is input periodically after binary bit decomposition, and since the result needs to be shifted forward by one bit for each bit increment during multiplication, the data output in the first output cycle of the first shift unit needs to be shifted forward by 0 bits, the output data in the second output cycle needs to be shifted forward by 1 bit, and so on, to obtain the number of bits that the output data needs to be shifted in each output cycle. Meanwhile, when the in-memory digital computing array has k rows, since the first input cycle starts inputting data to the first row, the second input cycle starts inputting data to the second row, and the first shift unit can only receive and output data in the kth input cycle, in this embodiment, the data obtained from the corresponding first shift unit will be shifted to the left by N bits in the k+Nth cycle, with N counting from 0.
[0061] An accumulation unit is electrically connected to the plurality of second shift units, and the accumulation unit is used to accumulate the data output by the second shift units over multiple cycles.
[0062] As an optional implementation, continue as follows Figure 5As shown, the accumulation circuit further includes a counter. The input interface of the counter is used to receive a clock signal, and the output interface of the counter is electrically connected to the second shift unit. The counter is used to start from the k-th cycle and perform cyclic counting according to the clock signal and the number of elements.
[0063] In some embodiments, Figure 5 Taking the data processing flow of a single in-memory computing module and the accumulation sub-circuit as an example, the working principle of the accumulation sub-circuit is described. In Figure 5 , B[0], B[1], B[2], and B[3] are binary data stored in different memory bits, respectively, and these binary data are obtained by decomposing the binary bits of the weight data. A[0], A[1], A[2], and A[3] are the binary data after decomposing the input data according to binary bits. When inputting, A[0], A[1], A[2], and A[3] are input sequentially according to the clock cycle. The row below B[0], B[1], B[2], B[3], that is, the row where <<0, <<1, <<2, <<3 are located, is the first shift unit, and the row below the first shift unit, that is, the row where <<N is located, is the second shift unit. In Figure 5 , since an exemplary description is made with a single in-memory computing unit, therefore, that is, the number of elements of the weight vector multiplied by the input data is 1, that is, k = 1. At this time, the counter starts counting from the first cycle of the input data. The in-memory digital computing array is composed of high-precision multipliers and adders. Because the in-memory digital computing module adopts the in-memory computing method, usually a single memory bit in a high-precision non-volatile memory such as MRAM stores 1 bit of data, so it is necessary to map multi-bit multiplication before implementation. In Figure 5 , the multiplication of two 4-bit numbers in a single computing unit is achieved through bit decomposition and shifting. The input multi-bit is realized through multiple cycles and is completed in cooperation with shifting. Different bits of the weight are distributed in different memory bits of the same in-memory digital computing module. After being read simultaneously, they can be used as inputs to different bits of the multi-bit precision adder to achieve shifting.
[0064] As Figure 6 shown, the calculation principle diagram of the in-memory digital computing array of the foregoing embodiments is exemplarily shown as follows:
[0065] In matrix-vector multiplication, the vector [a1, a2, a3] is input periodically to different rows through bit decomposition, with each row being input one cycle later than the previous row. This ensures that when the current row completes its in-memory calculation, the result register of the corresponding in-memory calculation module for the previous row already contains the result. The result can then be added in the current row using the adder of the current row's in-memory calculation module. The output is achieved through a shift-accumulator unit.
[0066] To compare the performance parameters such as latency, power consumption, and area of traditional digital computing arrays and the aforementioned embodiments, a comparison was conducted under the same computing scale (4×4 computing unit array). MRAM arrays with the same storage capacity were used for the comparison. Traditional systolic computing units employ complete MRAM storage modules and double-buffered modules to implement weight input, while the aforementioned embodiments use MRAM storage units of the same capacity distributed across various in-memory digital computing modules to maintain consistent total capacity. Through comparison, traditional digital computing units include multipliers, adders, and registers. Simulation verification and FPGA synthesis showed that the dynamic power consumption of the aforementioned embodiments was 0.016W (ignoring some analog power consumption), while the dynamic power consumption of traditional digital computing units was 0.093W. When considering analog power consumption, the power consumption difference between the aforementioned embodiments and the traditional array is approximately two times. To explore the reasons for the power savings in the aforementioned embodiments, the total area occupied by the aforementioned embodiments and the traditional digital computing units was also compared. In this comparison, the area of analog circuitry during computation was ignored, and the number of devices within the FPGA decreased. Analysis confirmed that the power savings primarily stemmed from reduced buffering and decreased activity due to input sparsity. Compared to traditional digital computing units, the combined area footprint (LUT, FF, etc.) of the aforementioned implementation methods was significantly reduced, mainly due to a decrease in the number of buffers and registers originally used for storing weights; see the table below for details:
[0067] The foregoing embodiments Conventional digital computing unit LUT 12502 34210 LUTRAM 118 256 FF 2497 9126 IO 87 118
[0068] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
Claims
1. An in-memory digital computing module, characterized in that, include: An in-memory multiplication unit, comprising a non-volatile memory array for storing weight data; A delay decoder, wherein the input interface of the delay decoder is used to receive input data, each output interface of the delay decoder is used to be electrically connected to the word line of the corresponding row in the non-volatile memory array, and the delay decoder is used to delay the received input data for a preset time and then select the corresponding output interface to output it. An adder, comprising sub-adders corresponding one-to-one with each column of the in-memory multiplication unit, wherein one input interface of the sub-adder is electrically connected to the read interface of the corresponding column in the in-memory multiplication unit, and the other input interface of the sub-adder is used to receive target data; The result register includes storage areas corresponding one-to-one with the multiple sub-adders. Each storage area is electrically connected to the output interface of the corresponding sub-adder. The result register is used to receive and store the accumulated result output by the sub-adders.
2. The in-memory digital computing module according to claim 1, characterized in that, The delay decoder includes: A delay register, the input interface of which is used to receive input data; the control interface of which is used to receive a clock signal, so as to output the stored data according to the clock signal; A word line selector, wherein the input interface of the word line selector is electrically connected to the output interface of the delay register, and the multiple output interfaces of the word line selector are electrically connected one-to-one with the word lines of multiple rows of the non-volatile memory array; The counter has an input interface electrically connected to the clock signal and an output interface electrically connected to the word line selector, so that the word line selector selects the corresponding word line to output the data based on the output data of the counter.
3. The in-memory digital computing module according to claim 1, characterized in that, The non-volatile storage array includes multiple non-volatile storage bits, each non-volatile storage bit storing one bit of binary data after the weight data binary bit decomposition.
4. The in-memory digital computing module according to claim 3, characterized in that, The storage bit is composed of any one or more of the following: a single transistor single storage cell structure, a two transistor one storage cell structure, a two transistor two storage cell structure, and a four transistor four storage cell structure.
5. The in-memory digital computing module according to claim 4, characterized in that, The storage unit includes any one or more combinations of magnetic random access memory, resistive random access memory, and phase change memory.
6. An in-memory digital computing array, characterized in that, include: A computing array comprising a plurality of in-memory digital computing modules as described in any one of claims 1-5, wherein the input interface of the delay decoder of the in-memory digital computing module is electrically connected to the output interface of the delay decoder of the in-memory digital computing module in the previous column of the current row. The output interface of the result register of the in-memory digital calculation module is electrically connected to the input interface of the adder in the next row of the current column, so as to output the target data to the adder in the next row of the current column; An accumulation circuit is provided, comprising multiple accumulation sub-circuits, each corresponding to a column of in-memory digital calculation modules. The accumulation sub-circuit is electrically connected to the output interface of the result register of the last in-memory digital calculation module in the corresponding column. The accumulation sub-circuit is used to shift and accumulate the data in the result register.
7. The in-memory digital computing array according to claim 6, characterized in that, Also includes: An activation module has multiple output interfaces. Each output interface of the activation module is electrically connected to the input interface of the delay decoder of a row of in-memory digital computing modules in the computing array. The activation module is used to transmit input data to multiple rows of in-memory digital computing modules in the computing array according to a preset period.
8. The in-memory digital computing array according to claim 7, characterized in that, The activation module is used to start transmitting input data to the in-memory digital calculation module in the nth clock cycle, where n is an integer not less than 0.
9. The in-memory digital computing array according to claim 6, characterized in that, The accumulator sub-circuit includes: Multiple first shift units are electrically connected one-to-one with multiple storage areas in the corresponding result register. The first shift unit is used to shift the data stored in the corresponding storage area. The first shift unit is used to obtain the first data in the corresponding storage area and shift the first data to the left by m-1 bits, where m is the position number of the storage area corresponding to the current first shift unit in the multiple storage areas in the same result register. A plurality of second shift units are electrically connected to a plurality of first shift units in a one-to-one correspondence. The second shift unit is used to shift the data obtained from the corresponding first shift unit to the left by N bits in the (k+N)th cycle. Here, k is the number of rows of the in-memory digital computing array, and N is the counting period of the output data of the corresponding first shift unit and is an integer not less than 0. The second shift unit is used to shift the output data of the corresponding first shift unit in the corresponding output period. An accumulation unit is electrically connected to the plurality of second shift units, and the accumulation unit is used to accumulate the data output by the second shift units over multiple cycles.
10. The in-memory digital computing array according to claim 9, characterized in that, The accumulation circuit also includes a counter, the input interface of which is used to receive a clock signal, and the output interface of which is electrically connected to the second shift unit. The counter is used to cyclically count based on the clock signal and the number of elements, starting from the kth cycle.