Protecting data logs in memory devices

Abstract

An apparatus comprising a non-volatile memory for storing a forensic key and data received from a host computing system. A processing device is coupled to the non-volatile memory and is to: allow the data to be written to a region of the non-volatile memory by the host computing system; assert a lock on the region of the non-volatile memory in response to a lock signal received from the host computing system, the lock to cause a restriction on access to the region of the non-volatile memory by an external device; and provide unrestricted access to the region of the non-volatile memory by the external device in response to verification of the forensic key received from the external device.

Description

[0001] This application is a divisional application of application number 201980070496.0, filed on September 17, 2019, entitled 'Protecting Data Logs in Memory Devices'. Related applications

[0002] This application is an international application of U.S. Nonprovisional Patent Application No. 16 / 358,236, filed March 19, 2019, which claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 752,472, filed October 30, 2018, and U.S. Provisional Patent Application No. 62 / 783,477, filed December 21, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to the field of memory devices, and more specifically to protecting data logs or other types of data stored in memory devices. Background Technology

[0004] Non-volatile memories (NVMs) such as ferroelectric RAM (FRAM) and magnetoresistive RAM (MRAM) are used in data logging applications in various fields, including automotive (e.g., black box or operational data), industrial (e.g., storing the position of a robotic arm before a power loss), medical (e.g., storing patient data), and financial applications (e.g., storing critical transaction data), to name just a few. Data logging is performed in NVM devices, allowing the recorded data to persist even after a crash or power outage event. The recorded data can then be examined to help determine the cause of the event. These types of NVM devices can be employed within such devices due to the fast write times of non-volatile memories such as FRAM or MRAM (e.g., the ability to store the last few milliseconds of data into FRAM / MRAM before an event causing a power outage).

[0005] There are instances where these data logs are quite valuable and even used as evidence in litigation. For example, in a car's black box, the recorded data can be used as evidence of events that occurred before an accident or caused a malfunction, such as whether seat belts were fastened, whether airbags deployed, speed, actions taken, engine temperature, and other such sensor data. Because such data logs are valuable, the NVM device storing them is vulnerable to attack or access in order to retrieve and / or alter the data logs. Summary of the Invention

[0006] According to one aspect of this disclosure, an apparatus is provided, comprising: Non-volatile memory for storing forensic keys and data received from a host computing system; and A processing device coupled to the non-volatile memory, wherein the processing device is used for: Allows the host computing system to write the data to at least a first region or a second region of the non-volatile memory; Detect events in the non-volatile memory; In response to the event: Detect a lock signal received from the host computing system, the lock signal including information embedded in the opcode of a Serial Peripheral Interface (SPI) command, the information specifying a restriction on access to the first or second region of the non-volatile memory; Retrieve the information from the opcode of the SPI command; and In the event that the detected event is a crash event, in response to the information, an assertion lock is made on the first region of the non-volatile memory and the writing of data is transferred to the second region, the lock being used to restrict access to the first region of the non-volatile memory by an external device; In the event that the detected event is a power outage, in response to the information, a lock is asserted on the first and second regions of the non-volatile memory, the lock being used to restrict access to both the first and second regions of the non-volatile memory by an external device; and In response to verification of the forensic key received from the external device, unrestricted access by the external device to the first and second regions of the non-volatile memory is provided.

[0007] According to another aspect of the invention, a method is provided, comprising: In response to powering on a non-volatile memory device, a processing device of the non-volatile memory device restricts access to a memory region of the non-volatile memory device, wherein the non-volatile memory device stores a cryptographic key, and wherein the memory region includes a first memory region and a second memory region; The processing device uses the cryptographic key to authenticate secure interactions with the host computing system, wherein the host computing system also stores the cryptographic key; In response to successful authentication, the processing device does not restrict access to the memory regions of the non-volatile memory device; The processing device records the data received from the host computing system within the first memory area of ​​the non-volatile memory device; The processing device detects events in the non-volatile memory device; In response to the event, a lock signal is received from the host computing system, the lock signal including information embedded in the opcode of a Serial Peripheral Interface (SPI) command, the information specifying restrictions on access to the memory region of the non-volatile memory; and In the event that the detected event is a crash event, the processing device restricts access to the first memory region of the non-volatile memory device with restrictions corresponding to the information, and transfers the recorded data to the second memory region; and In the event that the detected event is a power outage, the processing device restricts access to the first memory region and the second memory region of the non-volatile memory device by means of restrictions corresponding to the information.

[0008] According to another aspect of this disclosure, a system is provided, comprising: A non-volatile memory (NVM) device, wherein the NVM device includes a processing device and a non-volatile memory (NVM), wherein the NVM is used to store forensic keys and data; A host computing system coupled to the NVM device, the host computing system including a processor configured to write the data to the NVM until a lock is detected on the NVM device; and The processing device is used for: Detect events in the non-volatile memory; In response to the event, a lock signal received from the host computing system is detected, the lock signal including information embedded in the opcode of a Serial Peripheral Interface (SPI) command, the information specifying a restriction on access to a first region or a second region of the non-volatile memory; In the event that the detected event is a crash event, in response to the information retrieved from the opcode of the SPI command, an assertion lock is made on a first region of the non-volatile memory and the write of data is transferred to a second region, wherein the lock includes the restriction on access; In the event that the detected event is a power failure event, in response to the information, a lock is asserted on the first and second regions of the non-volatile memory, the lock being used to restrict access to both the first and second regions of the non-volatile memory by an external device; Verify the forensic key received from either an external computing device coupled to the NVM device or the host computing system; and in response to the verification of the forensic key, provide unrestricted access by either the host computing system or the external computing device to the NVM of the non-volatile memory device. Attached Figure Description

[0009] This disclosure is illustrated by way of example and not limitation in the accompanying drawings.

[0010] Figure 1 This is a block diagram of a system that uses an NVM device to record data according to various embodiments.

[0011] Figure 2 This is a block diagram of a system employing an NVM device according to an embodiment, wherein the host computing system has an insecure memory controller unit (MCU).

[0012] Figure 3 According to the embodiments, it is used for protection Figure 2 A flowchart of the method for handling data within an NVM device.

[0013] Figure 4A This is a block diagram of a system employing an NVM device according to an embodiment, wherein the host computing system has a secure MCU.

[0014] Figure 4B This illustrates an embodiment in Figure 4A The flowchart illustrates the cryptographic authentication process between the NVM device and the host computing system.

[0015] Figure 5 According to the embodiments, it is used for protection Figure 4A and Figure 4B A flowchart of the method for handling data within an NVM device.

[0016] Figure 6 A graphical representation of a machine is shown as an example of a computing system, within which a set of instructions can be executed to cause the machine to perform any or more of the methods discussed herein. Detailed Implementation

[0017] Because data recorded in non-volatile memory (NVM) such as FRAM and MRAM is valuable, it is a target for attacks. A specific, credible threat is an attack on the FRAM memory bus. For example, on-board diagnostic (OBD) scanning tools used to extract data can be used to retrieve data logs (or other types of data) from a vehicle's black box via the OBD port. The OBD port connects to an onboard computer that monitors emissions, mileage, speed, and other data about the vehicle.

[0018] In this embodiment, the OBD scanning tool retrieves diagnostic codes and can also monitor real-time data such as GPS location, accelerometer data, crash detection, engine temperature, fuel rate, oxygen sensor voltage, battery voltage level, and engine running time. Some OBD scanning tools are Bluetooth® (BT) compliant, allowing them to read data out to mobile or other BT-enabled devices. Anyone can use a widely available OBD scanner to access or modify data stored in the NVM memory of the black box device.

[0019] Therefore, in embodiments, in response to a triggering event (e.g., an accident in a car or airplane, a power outage in a factory, etc.), a memory region of the NVM device storing data logs can be locked by the NVM device. Once locked, the memory contents in that region cannot be erased, overwritten, and / or read (depending on the access permissions associated with the lock, as will be discussed). Different methods or means can be used to apply this locking to the NVM device. Furthermore, different methods or means can be used to securely unlock the NVM device to provide secure access to the data logs by authorized external devices (e.g., devices used by law enforcement or investigators).

[0020] In one embodiment, an apparatus or device includes: non-volatile memory for storing a forensic key and data received from a host computing system; and a processing device (e.g., a microcontroller or memory control unit (MCU)) coupled to the non-volatile memory. In an embodiment, the processing device is configured to: allow data to be written by the host computing system to a region of the non-volatile memory, and assert a lock on the region of the non-volatile memory in response to a lock signal received from the host computing system. The lock may restrict access to the region of the non-volatile memory by an external device. The processing device may further: provide unrestricted access to the region of the non-volatile memory by an external device in response to verification of the forensic key received from the external device. Multiple and different forensic keys may be used individually to provide unrestricted access to different regions of the memory.

[0021] In another embodiment, a method may include: restricting access to a memory region of a non-volatile memory (NVM) device by a processing device of the NVM device in response to powering on the NVM device, wherein the NVM device stores a cryptographic key. The method may further include: authenticating secure interaction with a host computing system using the cryptographic key, wherein the host computing system also stores the cryptographic key. The method may further include: not restricting access to the memory region of the NVM device by the processing device in response to successful authentication. The method may further include: recording data received from the host computing system by the processing device within the memory region of the non-volatile memory device. The method may further include: restricting access to the memory region of the non-volatile memory device by the processing device in response to power failure of the non-volatile memory device.

[0022] Figure 1 This is a block diagram of a system 100 that uses an NVM device 110 to record data, according to various embodiments. In embodiments, system 100 includes a host computing system 102 coupled to the NVM device 110 and an optional external device 140. The host computing system 102 may be coupled to the NVM device 110 via a bus 117 (e.g., a Serial Peripheral Interface (SPI) bus, an Internal Integrated Circuit (I2C) bus, or other types of bus transport protocols). The external device 140 may communicate remotely with the NVM device 110 via a network 115 (e.g., a Local Area Network (LAN), Personal Area Network (PAN), or Wide Area Network (WAN)) to include the Internet. The external device 140 may also communicate directly with the NVM device 110 if it is directly attached to a port (e.g., a diagnostic port) of the NVM device 110.

[0023] In various embodiments, the host computing system 102 includes a processor 104 and a memory control unit 108 (e.g., a memory controller). The NVM device 110 may include its own onboard processing device 118, which may be a microcontroller (or other integrated circuit, such as an MCU), non-volatile memory (NVM) 120 (e.g., FRAM, MRAM, or phase-change memory), and a communication interface 130. The NVM 120 may include at least one memory region 124 writable by the MCU 108, and a cryptographic key 128 for verifying or authenticating access to one or both of the host computing system 102 and the NVM device 110.

[0024] In this embodiment, the communication interface 130 includes: a network adapter 132 for communication via network 115; a read / write port 136 through which the host computing system 102 will be accessed; and an on-board diagnostic (OBD) port 138 through which an external device 140 can directly access the NVM device 110. The external device 140 may include a processor 144, an MCU 148, and a communication interface 150 for communicating with the NVM device 110. The system discussed below may include these various components, even if not explicitly discussed in one of the other figures. In some cases, similar components are similarly labeled.

[0025] Figure 2 This is a block diagram of a system 200 employing an NVM device 210 according to an embodiment, wherein a host computing system 202 has a non-secure MCU 208. In this embodiment, system 200 further includes an optional remote server 240, which can obtain access to the NVM device 210 via network 215. The remote server 240 may include a processor 244 and an MCU 248. The host computing system 202 may further include a processor 204.

[0026] In one embodiment, NVM device 210 includes a lock pin 212, a processing device 218, and an NVM 220. In another embodiment, the processing device 218 includes an authenticator 214 and an access controller 216, and the NVM 220 includes a memory region 224 and an authentication key 228. For example, the memory region 224 may be a series of data logs. The authenticator 214 may be used to verify or authenticate access to the memory region 224 of the NVM 220, for example, by a remote server 240 or an external device 140. For example, after such access has been verified or authenticated by the authenticator 214, the access controller 216 may determine what access permissions are granted to the remote server 240 or the external device 140. In another embodiment, the authentication key 228 is stored in the NVM 220 of the NVM device 210 at manufacturing time and may be used by the authenticator 214 to provide the necessary verification or authentication for access to the NVM 220, for example, after a crash or power outage event. Table 1

[0027] In various embodiments, reference continues to be made. Figure 2Table 1 illustrates the steps associated with detecting a crash or power outage event and locking the NVM 220 in response to that event. Upon powering on system 200, host computing system 202 non-password-enabled access control to the NVM 220 on NVM device 210 (step 1). This is because the non-secure MCU 208 may be a microcontroller that does not support password operations. Host computing system 202 can then be allowed to write data to the data log in memory region 224 of the NVM 220 while in an unlocked state (step 2).

[0028] In various embodiments, while still allowing access to the NVM 220 of the NVM device 210, the host computing system 202 may detect a crash or power failure event (step 3). This detection may include, for example, detection of airbag deployment, detection of critical rapid deceleration by an accelerometer, or other sensor values ​​that may detect an impending power failure or serious malfunction in the host computing system 202. In response to detecting a crash or power failure event, the host computing system 202 may send a lock signal to the NVM device 210 via bus 117 to indicate that the processing device 218 locks the non-volatile memory (NVM) 220 (step 4). Locking may restrict access by external devices to the memory region 224 of the NVM 220. Restrictions on access to the memory region 224 may include disallowing data erasure, write operations, or read operations to the memory region 424. In additional or alternative embodiments, restrictions on access to memory region 224 include any of the following: read-only access, writing only to erased sectors of memory region 224, disallowing erasure of one or more sectors of memory region 224, full access to some sectors of memory region 224 and prohibiting access to other sectors of memory region 224, or restricting access to some sectors of region 224 of NVM 220 and prohibiting access to other sectors of region 224 of NVM 220.

[0029] In various embodiments, the lock signal is a Serial Peripheral Interface (SPI) command or located within such a command. An SPI command may, for example, include an opcode instructing the MCU 218 to assert a lock on memory region 224 of the NVM 220 and specify restrictions on that access. In an alternative embodiment, the lock signal is a combination of an SPI command (which triggers a lock on memory region 224 of the NVM 220) or a memory interface command (which triggers a lock). In yet another embodiment, the lock signal is information embedded within a subfield of an existing command received from the host computing system 202, such as a power-off signal.

[0030] In various embodiments, a lock on memory region 224 can be asserted via a lock signal asserting a lock pin 212 (e.g., a hardware lock pin) on NVM device 210. In other embodiments, a lock is a memory location in memory region 224 of nonvolatile memory 220 to which a lock command within a lock signal is written.

[0031] In this embodiment, the host computing system 202 may lose power due to a crash or power outage event (step 5). The memory region 224 of the NVM 220 remains locked with access restrictions upon power-up after any period of power loss (step 6).

[0032] In an embodiment, to gain access to the data log stored in memory region 224 of NVM 220, the authenticator 214 of processing device 218 will use forensic key 228 to verify (or authenticate) the remote server 240 or external device 140 (or any device attempted to be accessed). To perform verification, authenticator 214 may perform a comparison of forensic key 228 with a second forensic key provided by remote server 240 or external device 140.

[0033] In one embodiment, to authenticate access by remote server 240 (or external device 140), the remote server (or external device) can receive a counter value (e.g., a fresh value) from NVM 210, which is added to the forensic key. The counter value can be combined with the forensic key 228, and the combination is hashed (e.g., using a secure hash algorithm (SHA)) to generate a hash-based message authentication code (HMAC) or other digest. Authenticator 214 can then use its forensic key 228 to generate the same HMAC (or digest) using the same SHA, thereby authenticating the match of the HMAC / digest values. Once verified or authenticated, remote server 240 or external device 140 can send an unlock command to NVM device 210 to read from and / or write to memory region 224. In one embodiment, NVM device 210 is automatically unlocked upon successful verification or authentication.

[0034] Figure 3 According to the embodiments, it is used to protect in Figure 2 The flowchart illustrates a method 300 for processing data within an NVM device. Method 300 can be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions running on a processing device), firmware, or a combination thereof. In one embodiment, method 300 is executed by NVM device 210, and more specifically by processing device 218 of NVM device 210.

[0035] refer to Figure 3 Method 300 begins by storing forensic key 228 (e.g., when the NVM device is manufactured) and data in NVM 220 of NVM device 210 (310). The data may include data logs associated with the operation of host computing system 202 or associated systems coupled to host computing system 202. Method 300 may continue: processing logic allows the host computing system to write data to a region of non-volatile memory (e.g., memory region 224) (320). Method 300 may continue: processing logic asserts a lock on the region of non-volatile memory in response to a lock signal received from host computing system 202, the lock being used to restrict access to the non-volatile memory region by an external device (330). Method 300 may continue: processing logic provides unrestricted access to the region of non-volatile memory by the external device in response to verification of the forensic key received from the external device (340).

[0036] Figure 4A This is a block diagram of a system 400 employing an NVM device 410 according to an embodiment, wherein a host computing system 402 has a secure MCU 408. In this embodiment, the host computing system 402 includes a processor 404 and a secure MCU 408. The secure MCU 408 can store or access a cryptographic key 406. Therefore, the secure MCU 408 is capable of authorized (or secure) access to the NVM 420 of the NVM device 410 as part of normal operation.

[0037] In some embodiments, the NVM device 410 may further include a processing device 418 and a non-volatile memory (NVM) 420. In an embodiment, the processing device 418 includes an authenticator 414 and an access controller 416, and the NVM 420 includes a memory region 424 and a cryptographic key 406. The NVM 420 may further include at least a second memory region 426, which may be separately allocated and protected for reasons explained later.

[0038] Authenticator 414 can authenticate access to NVM 420, for example, by host computing system 402 and external device 140. For example, after such access is authenticated by authenticator 414, access controller 416 can determine which access permissions are granted to host computing system 402 or external device 140. Access permissions are as described with reference to authenticator 214 (…). Figure 2 The access permissions discussed herein. Password key 406 may be stored at manufacturing time in the host computing system 402 and the NVM 420 of the NVM device 410. Table 2

[0039] In various embodiments, reference continues to be made. Figure 4A Table 2 illustrates the steps associated with authentication communication between host computing system 402 and NVM device 410, and with detecting a crash or power failure event and locking NVM 220 in response to such event. When system 400 is powered on, NVM device 410 can lock NVM 420 and restrict access to at least memory region 424 of NVM 420. Different restrictions on access to memory region 424 and different ways of locking memory region 424 are described in reference [reference needed]. Figure 2 System 200 is discussed and can be similarly applied. Figure 4A System 400.

[0040] In various embodiments, as part of or immediately following the startup process, the authenticator 414 can authenticate access made by the security MCU 408 of the host computing system 402, thus facilitating mutual authentication for secure interactions between the host computing system 402 and the NVM device 410 (step 2). Figure 4B This is a flowchart illustrating cryptographic authentication between a host computing system 402 and an NVM device 410 according to an embodiment. In this embodiment, the authenticator 414 can generate a fresh value (e.g., a counter value that can be incremented each time a fresh value is generated) and send the fresh value to the host computing system 402. The security MCU 408 of the host computing system 402 can read the fresh value and generate an HMAC using a combination of a cryptographic key 406 and the fresh value. The host computing system 402 can then send the HMAC to the NVM device 410. Upon receiving the HMAC, the authenticator 414 can authenticate the HMAC as consistent with the HMAC generated by the authenticator 414 of the NVM device 410 using the same cryptographic key 406 and the fresh value. In response to successful mutual authentication, the authenticator 414 can unlock the NVM 420 and allow unrestricted access to the memory region 424.

[0041] In various embodiments, reference is made to Figure 4A According to Table 2, in response to successful mutual authentication, the host computing system 402 can log data to memory area 424 of the NVM 420 (step 3). Because the secure MCU 408 is capable of encrypted data exchange with the NVM device 410, the data recording can also be authenticated using the password key 406. Therefore, the data log can be stored in the NVM 420 in encrypted form.

[0042] The host computing system 402 may detect a crash or power outage event at some point (step 4), as shown in the reference. Figure 2The system discussed in reference system 200. In the event of a power failure or outage, NVM device 410 may apply a lock to memory region 424 of NVM 420 (step 5). This lock allows access controller 416 to impose restrictions on access to memory region 424 by external device 140, such as those discussed in reference system 200. Upon power-on following such a crash or outage event, host computing system 402 and NVM device 410 will re-authenticate with each other before allowing data to be logged to memory region 424 (see...). Figure 5 ).

[0043] In alternative or additional embodiments, processing device 418 partitions the recording area of ​​NVM 420 into memory region 424 (e.g., a first memory region) and at least a second memory region 426. Recording of data (e.g., operational data of the type stored in a black box device) may initially be performed by host computing system 402 only on the first memory region (e.g., memory region 424). A customer may purchase a system 400 with a partitioned NVM, where the partitioning results in the first and second memory regions 426 being divided uniformly or non-uniformly.

[0044] In one embodiment, the locking applied at step 5 in response to a crash event (but without causing a power outage) can be performed by the NVM device 410 invoking a wounding option. The wounding option can reduce the density of the NVM 420 by removing the possibility of physical access to the memory region 424, or at least imposing restrictions on access as previously discussed.

[0045] For example, in one embodiment, the access controller 416 invokes a damage option that imposes access restrictions on a portion of the NVM 420 to effectively reduce the writable portion of the NVM 420. In this embodiment, the access controller 416 can restrict the first memory region while the host computing system 402 can still write to the second memory region 426. In other words, the security MCU 408 can only record data to memory region 424 until a crash event not accompanied by a power outage of the NVM device 410 is detected. While data recording is transferred to the second memory region 426, subsequent locking on the NVM 420 can only enforce access restrictions on memory region 424. If the NVM device 410 detects a subsequent power outage event, the locking can be extended to include imposing access restrictions on both the first and second memory regions 424 and 426. In a further embodiment, as will be understood, the NVM 420 can be further partitioned into a third or subsequent memory region to handle multiple consecutive crash (or manufacturing defect) events and still provide continued data recording until and including subsequent power outage events.

[0046] Figure 5 According to the embodiments, it is used to protect in Figure 4A and Figure 4B A flowchart of a method 500 for processing data within an NVM device 410 is provided. Method 500 can be executed by processing logic, which may include hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions running on a processing device), firmware, or a combination thereof. In one embodiment, method 500 is executed by the NVM device 410, and more specifically by a processing device 418 of the NVM device 410.

[0047] refer to Figure 5 Method 500 may begin with: processing logic restricting access to memory region 424 of a non-volatile memory device, wherein the non-volatile memory device stores a cryptographic key, in response to powering on the NVM device 410 (510). Method 500 may continue with: processing logic using the cryptographic key to authenticate secure interaction with the host computing system 410, wherein the host computing system also stores the cryptographic key (520). Method 500 may continue with: processing logic not restricting access to memory region 424 of the NVM device 410 in response to successful mutual authentication (530). Method 500 may continue with: processing logic recording data received from the host computing system in memory region 424 of the NVM device 410 (540). Method 500 may continue with: processing logic restricting access to memory region 424 of the non-volatile memory device in response to power-off of the NVM device 410 (550).

[0048] For further reference Figure 5 Method 500 may continue: In response to powering on the NVM device 410 after a power outage, the processing logic uses either a cryptographic key or an forensic key to authenticate secure interaction with an external device such as external device 140 (560). Method 500 may continue: In response to successful authentication with external device 140, the processing logic does not restrict access by external device 140 to the memory region 424 of the NVM device 410 (570). Method 500 may continue: The processing logic allows external device 140 to read data recorded in the memory region 424 of the non-volatile memory device (580). The permitted read access may be further extended to allow data to be erased from or written to the memory region 424 of the NVM 420.

[0049] In an additional embodiment, a system includes: a non-volatile memory device for storing cryptographic keys and data, wherein the non-volatile memory device includes one of ferroelectric random access memory (FRAM) or magnetoresistive random access memory (MRAM). The system may further include a processor coupled to the non-volatile memory device, the processor being configured to write data to the non-volatile memory device until a lock is detected on the non-volatile memory device. The system further includes processing means for the non-volatile memory device, the processing means being configured to: assert a lock on the non-volatile memory in response to receiving a lock signal; authenticate a cryptographic key within a message authentication code received from one of the processors or an external computing device coupled to the non-volatile memory device; and, in response to authentication of the cryptographic key, provide unrestricted access to the non-volatile memory device by one of the processors or the external computing device. In one embodiment, the processor is configured to: transmit a lock signal to the processing means in response to one of a power-off event or a crash event detected by the processor.

[0050] Figure 6 A schematic diagram of a machine is shown as an example of a computing system 600, within which a set of instructions can be executed to cause the machine to perform any or more methods discussed herein. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, or the Internet. The machine may operate as a server or client device in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a host computing system or computer, an automotive computing device, a server, a network device for automotive networks (e.g., Controller Area Network (CAN) or Local Interconnect Network (LIN)), or any machine capable of executing a set of instructions (sequential or other instructions) specifying the action to be taken by the machine. Furthermore, although only a single machine is shown, the term "machine" should also be considered to include any set of machines that individually or collectively execute one or more sets of instructions to perform any or more methods discussed herein. Implementations of page and section transitions may be implemented in computing system 600.

[0051] The computing system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or DRAM (RDRAM)), a static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 618, which communicate with each other via a bus 630.

[0052] Processing device 602 represents one or more general-purpose processing devices, such as microprocessor devices, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor device, a Reduced Instruction Set Computer (RISC) microprocessor device, a Very Long Instruction Word (VLIW) microprocessor device, or a processing device implementing other instruction sets, or a processing device implementing a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processing devices (DSPs), network processing devices, etc. In one implementation, processing device 602 may include one or more processing device cores. Processing device 602 is configured to execute instructions 626 to perform the operations discussed herein. In one implementation, processing device 602 may be... Figure 1 , Figure 2 or Figure 4A It is part of the computing system 100, 200, or 400.

[0053] Alternatively, computing system 600 may include other components as described herein. Computing system 600 may further include a network interface device 608 communicatively coupled to network 620. Computing system 600 may also include a video display unit 610 (e.g., a liquid crystal display (LCD)), an alphanumeric input device 612 (e.g., a keyboard), a cursor control device 614 (e.g., a mouse), a signal generation device 616 (e.g., a speaker), or other peripheral devices. Furthermore, computing system 600 may include a graphics processing unit 622, a video processing unit 628, and an audio processing unit 632. In another implementation, computing system 600 may include a chipset (not shown), which refers to a set of integrated circuits or chips designed to work with processing device 602 and control communication between processing device 602 and external devices. For example, a chipset may be a collection of chips on a motherboard that links processing device 602 to high-speed devices (e.g., main memory 604 and a graphics controller) and low-speed peripheral buses (e.g., USB, PCI, or ISA buses) that link processing device 602 to peripheral devices.

[0054] Data storage device 618 may include computer-readable storage medium 624 thereon storing instructions 626 embodying any one or more methods of the functionality described herein. Instructions 626 may also reside wholly or at least partially in main memory 604 as instructions 626, and / or as processing logic in processing device 602 during execution by computing system 600; main memory 604 and processing device 602 also constitute computer-readable storage media.

[0055] Computer-readable storage medium 624 can also be used to utilize processing device 602 (e.g., regarding...) Figure 1 The software library (described herein) and / or containing methods that call the aforementioned applications stores instructions 626. Although computer-readable storage medium 624 is shown as a single medium in the example implementation, the term "computer-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "computer-readable storage medium" should also be considered to include any medium capable of storing, encoding, or carrying a set of instructions for machine execution, and causing the machine to perform any one or more methods of the implementation. Therefore, the term "computer-readable storage medium" should be considered to include, but is not limited to, solid-state memory and optical and magnetic media.

[0056] Numerous details have been set forth in the foregoing description. However, it will be apparent to those skilled in the art who will benefit from this disclosure that embodiments of the disclosure can be practiced without these specific details. In some instances, well-known structures and devices have been shown in block diagram form rather than in detail in order to avoid obscuring the description.

[0057] As used herein, a module refers to any combination of hardware, software, and / or firmware. As an example, a module includes hardware (e.g., a microcontroller) associated with a non-transitory medium to store code suitable for execution by the microcontroller. Therefore, in one implementation, a reference to a module refers to hardware specifically configured to recognize and / or execute code to be stored on a non-transitory medium. Furthermore, in another implementation, the use of "module" refers to a non-transitory medium comprising code specifically suitable for execution by a microcontroller to perform a predetermined operation. And, as can be inferred, in yet another implementation, the term "module" (in this example) could refer to a combination of a microcontroller and a non-transitory medium. Typically, the boundaries of modules shown as separate entities often vary and potentially overlap. For example, first and second modules may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware. In one implementation, the use of the term "logic" includes hardware (e.g., transistors, registers) or other hardware (e.g., programmable logic devices).

[0058] In one implementation, the phrase "configured to" refers to arranging, assembling, manufacturing, offering for sale, importing, and / or designing a device, hardware, logic, or element to perform a specified or defined task. In this example, if a non-operating device or its element is designed, coupled, and / or interconnected to perform a specified task, it is still "configured to" perform said specified task. Simply as an illustrative example, a logic gate can provide 0 or 1 during operation. However, a logic gate "configured to" provide an enable signal to the clock does not include every potential logic gate that can provide 1 or 0. Instead, a logic gate is one that is coupled in some way to output 1 or 0 during operation to enable the clock. Again, note that the use of the term "configured to" does not require operation but focuses on the potential state of a device, hardware, and / or element, in which the device, hardware, and / or element is designed to perform a specific task while the device, hardware, and / or element is operational.

[0059] Furthermore, in one implementation, the use of the phrases "for," "capable of / for," and / or "operable for" refers to a device, logic, hardware, and / or element designed in such a manner that the device, logic, hardware, and / or element is used in the specified manner. As mentioned above, in one implementation, the use of "for," "capable of," or "operable for" refers to a potential state of a device, logic, hardware, and / or element where the device, logic, hardware, and / or element is not currently operational but is designed to use the device in the specified manner.

[0060] The values ​​used in this document include any known representation of numbers, states, logical states, or binary logical states. Generally, the use of logic levels, logic values, or logical values ​​is also referred to as 1 and 0, which simply represent binary logical states. For example, 1 refers to a high logic level, and 0 refers to a low logic level. In one implementation, a storage unit such as a transistor or flash memory cell is capable of holding a single logic value or multiple logic values. However, other representations of values ​​have been used in computer systems. For example, the decimal digit ten can also be represented as the binary value 1010 and the hexadecimal letter A. Therefore, values ​​include any representation of information that can be stored in a computer system.

[0061] Some specific implementations of algorithms and symbolic representations for manipulating data bits within computer memory are presented. These algorithmic descriptions and representations are means used by those skilled in the art of data processing to most effectively communicate the essence of their work to others skilled in the art. An algorithm herein, and generally, is considered a self-consistent sequence of steps that produces the desired result. A step is a physical manipulation of physical quantities. Typically, though not always, these quantities take the form of electrical or magnetic signals that can be stored, transmitted, combined, compared, and otherwise manipulated. Primarily for general reasons, it has proven convenient to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, etc.

[0062] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise explicitly stated, as is evident from the above discussion, it should be understood that throughout the description, the use of terms such as “receive”, “adjust”, etc., refers to the actions and processes of a computing system or similar electronic computing device that manipulate and convert data, represented as physical (e.g., electronic) quantities within the registers and memories of the computing system, into other data (which are similarly represented as physical quantities within the memory or registers of the computing system or other such information storage, transmission, or display devices).

[0063] The terms “example” or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example” or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the use of the terms “example” or “exemplary” is intended to present the concept in a specific manner. As used herein, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise stated or clear from the context, “X comprises A or B” is intended to mean any of the natural inclusive permutations and combinations. That is, if X comprises A; X comprises B; or X comprises both A and B, then “X comprises A or B” is satisfied under any of the foregoing examples. Additionally, the articles “a” and “an” as used herein and in the appended claims should generally be construed as meaning “one or more” unless otherwise stated or clearly pointed to in the singular form from the context. Furthermore, unless described as such, the use of the terms “embodiment” or “an embodiment” or “implementation” or “an implementation” throughout the document is not intended to mean the same embodiment or implementation.

[0064] The embodiments described herein may also relate to means for performing the operations described herein. This means may be specifically constructed for the desired purpose, or it may include general-purpose hardware selectively activated or reconfigured by firmware stored therein. Such firmware may be stored in a non-transitory computer-readable storage medium, such as, but not limited to, NVM, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, flash memory, or any type of medium suitable for storing electronic instructions. The term "computer-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "computer-readable medium" should also be considered to include any medium capable of storing, encoding, or carrying a set of instructions for execution by hardware, and causing the hardware to perform any one or more methods of this embodiment. Therefore, the term "computer-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, electromagnetic media, and any medium capable of storing a set of instructions for execution by hardware, and causing the hardware to perform any one or more methods of this embodiment.

[0065] The foregoing description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., to provide a good understanding of several embodiments of the present disclosure. However, it will be apparent to those skilled in the art that at least some embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known components or methods have not been described in detail, or have been presented in a simple block diagram format to avoid unnecessarily obscuring the present disclosure. Therefore, the specific details set forth above are merely exemplary. Specific embodiments may differ from these exemplary details and are still considered to be within the scope of this disclosure.

[0066] It should be understood that the above description is intended to be illustrative rather than restrictive. Many other embodiments will become apparent to those skilled in the art upon reading and understanding the above description. Therefore, the scope of this disclosure should be determined by reference to the appended claims, together with the full scope of their equivalents.

[0067] In the foregoing description, numerous specific details have been set forth for purposes of explanation in order to provide a thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail but rather illustrated by block diagrams in order to avoid unnecessarily obscuring the understanding of this specification.

[0068] References to "an embodiment" or "an embodiment" in this specification indicate that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. The phrase "in an embodiment" in various locations throughout this specification does not necessarily refer to the same embodiment.

Claims

1. An apparatus comprising: Non-volatile memory used to store forensic keys and data received from the host computing system; as well as A processing device coupled to the non-volatile memory, wherein the processing device is used for: Allows the host computing system to write the data to at least a first region or a second region of the non-volatile memory; Detect events in the non-volatile memory; In response to the event: Detect a lock signal received from the host computing system, the lock signal including information embedded in the opcode of a Serial Peripheral Interface (SPI) command, the information specifying a restriction on access to the first or second region of the non-volatile memory; Retrieve the information from the opcode of the SPI command; and In the event that the detected event is a crash event, in response to the information, an assertion lock is made on the first region of the non-volatile memory and the writing of data is transferred to the second region, the lock being used to restrict access to the first region of the non-volatile memory by an external device; In the event that the detected event is a power outage, in response to the information, a lock is asserted on the first and second regions of the non-volatile memory, the lock being used to restrict access to both the first and second regions of the non-volatile memory by an external device; and In response to verification of the forensic key received from the external device, unrestricted access by the external device to the first and second regions of the non-volatile memory is provided.

2. The apparatus according to claim 1, wherein, The restrictions on access include read-only access to the regions of the non-volatile memory.

3. The apparatus according to claim 1, wherein, The restrictions on access include: only writing to erased sectors of the region of the non-volatile memory.

4. The apparatus according to claim 1, wherein, The restrictions on access include: not allowing the erasure of one or more sectors of the region of the non-volatile memory.

5. The apparatus according to claim 1, wherein, The restrictions on access include: full access to some sectors of the region of the non-volatile memory, and prohibition of access to other sectors of the region of the non-volatile memory.

6. The apparatus according to claim 1, wherein, The restrictions on access include: limited access to some sectors of the region of the non-volatile memory, and prohibition of access to other sectors of the region of the non-volatile memory.

7. The apparatus according to claim 1, wherein, The non-volatile memory includes one of ferroelectric random access memory (FRAM) or magnetoresistive random access memory (MRAM).

8. The apparatus of claim 1, further comprising a locking pin coupled to the processing device, wherein, The locking pin is asserted by the locking signal to assert the locking.

9. The apparatus according to claim 1, wherein, The locking includes the memory location in the region of the non-volatile memory to which the locking command within the locking signal is written.

10. A method comprising: In response to powering on a non-volatile memory device, a processing device of the non-volatile memory device restricts access to a memory region of the non-volatile memory device, wherein the non-volatile memory device stores a cryptographic key, and wherein the memory region includes a first memory region and a second memory region; The processing device uses the cryptographic key to authenticate secure interactions with the host computing system, wherein the host computing system also stores the cryptographic key; In response to successful authentication, the processing device does not restrict access to the memory regions of the non-volatile memory device; The processing device records the data received from the host computing system within the first memory area of ​​the non-volatile memory device; The processing device detects events in the non-volatile memory device; In response to the event, a lock signal is received from the host computing system, the lock signal including information embedded in the opcode of a Serial Peripheral Interface (SPI) command, the information specifying restrictions on access to the memory region of the non-volatile memory; and In the event that the detected event is a crash event, the processing device restricts access to the first memory region of the non-volatile memory device with restrictions corresponding to the information, and transfers the recorded data to the second memory region; and In the event that is detected as a power outage, the processing device restricts access to the first memory region and the second memory region of the non-volatile memory device by means of restrictions corresponding to the information.

11. The method of claim 10, further comprising: In response to powering on the non-volatile memory device after the power outage, the processing device uses one of the cryptographic key or the forensic key to authenticate secure interaction with external devices. In response to successful authentication with the external device, the processing device does not restrict access by the external device to the memory region of the non-volatile memory device; as well as The external device is allowed to read the data recorded in the memory area of ​​the non-volatile memory device.

12. The method according to claim 10, wherein, Restricting access to the memory regions of the non-volatile memory device includes allowing read-only access.

13. The method according to claim 10, wherein, Restricting access to the memory region of the non-volatile memory device includes allowing only writes to erased sectors of the memory region.

14. The method of claim 10, wherein, Restricting access to the memory region of the non-volatile memory device includes disallowing the erasure of one or more sectors of the memory region.

15. The method according to claim 10, wherein, Restricting access to the memory regions of the non-volatile memory device includes allowing full access to some sectors of the memory regions while disallowing access to other sectors of the memory regions.

16. The method of claim 10, wherein, Restricting access to the memory region of the non-volatile memory device includes allowing limited access to some sectors of the memory region, while disallowing access to other sectors of the memory region.

17. A system comprising: A non-volatile memory (NVM) device, wherein the NVM device includes a processing device and a non-volatile memory (NVM), wherein the NVM is used to store forensic keys and data; A host computing system coupled to the NVM device, the host computing system including a processor configured to write the data to the NVM until a lock is detected on the NVM device; and The processing device is used for: Detect events in the non-volatile memory; In response to the event, a lock signal received from the host computing system is detected, the lock signal including information embedded in the opcode of a Serial Peripheral Interface (SPI) command, the information specifying a restriction on access to a first region or a second region of the non-volatile memory; In the event that the detected event is a crash event, in response to the information retrieved from the opcode of the SPI command, an assertion lock is made on a first region of the non-volatile memory and the write of data is transferred to a second region, wherein the lock includes the restriction on access; In the event that the detected event is a power failure event, in response to the information, a lock is asserted on the first and second regions of the non-volatile memory, the lock being used to restrict access to both the first and second regions of the non-volatile memory by an external device; Verify the forensic key received from either an external computing device coupled to the NVM device or the host computing system; and In response to verification of the forensic key, unrestricted access is provided by one of the host computing systems or the external computing devices to the NVM of the non-volatile memory device.

18. The system according to claim 17, wherein, The processor is configured to transmit the lock signal to the NVM device in response to either a power outage event or a crash event detected by the processor.

19. The system according to claim 17, wherein, The processing device is further configured to: before receiving the locking signal, Using cryptographic keys to authenticate secure interactions with the host computing system; and The data is allowed to be logged in the NVM in response to successful authentication.

20. The system according to claim 17, wherein, The non-volatile memory device includes one of ferroelectric random access memory (FRAM) or magnetoresistive random access memory (MRAM).

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