Display module and electronic device

Abstract

The present disclosure relates to a display module and an electronic device. The display module includes a display panel, a plurality of sensors, a plurality of multiplexers, a plurality of spider lines, a plurality of flexible printed circuit boards, a circuit board, and a plurality of input detection driving circuits. The plurality of sensors and the plurality of input detection driving circuits detect a touch of a user by using a self-point method. The circuit board electrically connects the plurality of sensors and the plurality of input detection driving circuits to each other. The circuit board includes a plurality of connection lines, and a portion and another portion of at least one of the plurality of connection lines are disposed in different layers of the circuit board.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to and all benefits derived therefrom of Korean Patent Application No. 10-2024-0200514, filed on December 30, 2024, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to electronic components, display modules, and electronic devices including display modules, and more specifically, to electronic components and display modules for providing input detection circuitry with a large area, and electronic devices including display modules. Background Technology

[0004] Various display devices are being developed for use in multimedia devices such as televisions, cellular phones, tablet computers, navigation devices, or game consoles. In such display devices, for example, a keyboard or mouse may be provided as an input device.

[0005] In addition, such a display device may include an input detection circuit configured to detect a user's touch or pressure applied by the user as an input device for the display device.

[0006] The display device can be configured to detect touch by a human finger on the screen of the display device via an input detection circuit. The input detection circuit can use various touch detection methods, such as resistive film methods, optical methods, capacitive methods, or ultrasonic methods. Among these methods, the capacitive method uses the change in capacitance when a touch generating device is touched on the screen of the display device to detect whether a touch has occurred.

[0007] Large-sized displays are being used in various recent electronic devices installed in vehicles. However, when such large displays detect touch input, the performance of touch detection may be reduced. Summary of the Invention

[0008] Embodiments of this disclosure will provide a display module and electronic device including input detection circuitry with improved touch sensitivity.

[0009] Furthermore, another embodiment of this disclosure provides electronic components configured to improve the touch sensitivity of the input detection circuit.

[0010] A display module according to an embodiment of the present disclosure includes a display panel, a plurality of sensors, a first multiplexer, a second multiplexer, a first spider wire, a second spider wire, a plurality of flexible printed circuit boards, a circuit board, a first input detection driving circuit, and a second input detection driving circuit. In such an embodiment, the display panel includes a display area and a non-display area surrounding the display area. In such an embodiment, a plurality of sensors may be provided on the display area and include a first sensor and a second sensor disposed adjacent to the first sensor. In such an embodiment, the first multiplexer is electrically connected to the first sensor, and the second multiplexer is electrically connected to the second sensor and spaced apart from the first multiplexer. In such an embodiment, the first spider wire is electrically connected to the first multiplexer and provided on the non-display area, and has a first length. In such an embodiment, the second spider wire is electrically connected to the second multiplexer and provided on the non-display area, and has a second length shorter than the first length. At least one of the plurality of flexible printed circuit boards may be electrically connected to at least one corresponding to the first spider wire and the second spider wire. In such an embodiment, the circuit board includes a first connecting line having a third length and a second connecting line having a fourth length longer than the third length, and the first connecting line and the second connecting line can be electrically connected to the first spider line and the second spider line respectively through at least any one of a plurality of flexible printed circuit boards.

[0011] In one embodiment, a first input detection drive circuit is electrically connected to a first connection line and mounted on a circuit board. In another embodiment, a second input detection drive circuit is electrically connected to a second connection line and mounted on a circuit board.

[0012] In embodiments of this disclosure, the circuit board may further include: a first substrate layer; a second substrate layer; and a first substrate insulating layer disposed between the first substrate layer and the second substrate layer. In such embodiments, a first connecting line may be provided on the first substrate layer. In such embodiments, a portion of a second connecting line may be disposed on the first substrate layer, and another portion of the second connecting line may be disposed between the first substrate insulating layer and the second substrate layer.

[0013] In embodiments of this disclosure, the circuit board may further include: a first substrate layer; a second substrate layer; and a first substrate insulating layer disposed between the first substrate layer and the second substrate layer. In such embodiments, the first connecting line may include: a first upper connecting line disposed on the first substrate layer; and a first lower connecting line disposed between the first substrate insulating layer and the second substrate layer. In such embodiments, the second connecting line may include: a second upper connecting line disposed on the first substrate layer; and a second lower connecting line disposed between the first substrate insulating layer and the second substrate layer.

[0014] In embodiments of this disclosure, the circuit board may further include: a first substrate layer; a second substrate layer; a third substrate layer; a first substrate insulating layer disposed between the first substrate layer and the second substrate layer; and a second substrate insulating layer disposed between the second substrate layer and the third substrate layer. In such embodiments, the first connecting line may include: a first upper connecting line disposed on the first substrate layer; and a first lower connecting line disposed between the first substrate insulating layer and the second substrate layer. In such embodiments, the second connecting line may include: a second upper connecting line disposed on the first substrate layer; an intermediate connecting line disposed between the first substrate insulating layer and the second substrate layer; and a second lower connecting line disposed between the second substrate insulating layer and the third substrate layer.

[0015] In embodiments of this disclosure, the capacitance formed by the first connecting line and other components can be 0.9 times or greater and 1.1 times or less than the capacitance formed by the second connecting line and other components.

[0016] In embodiments of this disclosure, no sensor may be positioned between the first and second sensors. In such embodiments, the second sensor may be spaced apart from the first sensor in a first direction, and the second multiplexer may be spaced apart from the first multiplexer in the first direction.

[0017] In embodiments of this disclosure, the first input detection driving circuit can detect changes in the capacitance formed by the first sensor and other components. In such embodiments, the second input detection driving circuit can detect changes in the capacitance formed by the second sensor and other components.

[0018] In embodiments of this disclosure, the plurality of flexible printed circuit boards may be bendable to overlap the circuit boards with the display panel.

[0019] An electronic device according to an embodiment of the present disclosure includes a plurality of sensors, a first multiplexer, a second multiplexer, a first spider wire, a second spider wire, a circuit board, a first input detection driving circuit, and a second input detection driving circuit. In such an embodiment, the plurality of sensors includes a first sensor and a second sensor disposed adjacent to the first sensor, and each of the first and second sensors forms a capacitance with an object approaching from the outside. In such an embodiment, the first multiplexer is electrically connected to the first sensor, and the second multiplexer is electrically connected to the second sensor and spaced apart from the first multiplexer. In such an embodiment, the first spider wire is electrically connected to the first multiplexer and has a first length. In such an embodiment, the second spider wire is electrically connected to the second multiplexer and has a second length shorter than the first length. In such an embodiment, the circuit board includes a first connecting line having a third length and a second connecting line having a fourth length longer than the third length. In such an embodiment, the first connecting line is electrically connected to the first spider wire, and the second connecting line is electrically connected to the second spider wire. In such an embodiment, the first input detection driving circuit is electrically connected to the first connecting line, and the first input detection driving circuit detects changes in the capacitance of the first sensor. In such an embodiment, the second input detection driving circuit is electrically connected to the second connection line, and the second input detection driving circuit detects changes in the capacitance of the second sensor.

[0020] In embodiments of this disclosure, the circuit board may further include: a first base layer; a first base insulating layer disposed below the first base layer; and a second base layer disposed below the first base insulating layer. In such embodiments, a portion of the second connecting line may be disposed on the first base layer, and another portion of the second connecting line may be disposed between the first base insulating layer and the second base layer.

[0021] In embodiments of this disclosure, none of the multiple sensors may be positioned between the first sensor and the second sensor.

[0022] In embodiments of this disclosure, the first sensor may be electrically insulated from the second sensor.

[0023] In embodiments of this disclosure, multiple sensors may each allow at least some of the incident light to penetrate or pass through.

[0024] The electronic device according to embodiments of the present disclosure may further include a display panel configured to overlap with a plurality of sensors.

[0025] The electronic device according to embodiments of the present disclosure may further include a plurality of flexible printed circuit boards. At least one of the plurality of flexible printed circuit boards may be electrically connected to at least one corresponding to the first spider wire and the second spider wire.

[0026] In embodiments of this disclosure, the capacitance formed by the first connecting line and other components can be 0.9 times or greater and 1.1 times or less than the capacitance formed by the second connecting line and other components.

[0027] An electronic component according to an embodiment of the present disclosure includes a first substrate layer, a first substrate insulating layer disposed below the first substrate layer, a second substrate layer disposed below the first substrate insulating layer, and a plurality of connecting lines, each of the plurality of connecting lines having at least a portion disposed on the first substrate layer. In such an embodiment, among the plurality of connecting lines, the length of a first connecting line electrically connected to a first external component is different from the length of a second connecting line electrically connected to a second external component.

[0028] In embodiments of this disclosure, a portion of the second connecting line may be disposed on the first substrate layer, and another portion of the second connecting line may be disposed between the first substrate insulating layer and the second substrate layer.

[0029] In embodiments of this disclosure, the first external component may be a first multiplexer, and the second external component may be a second multiplexer spaced apart from the first multiplexer.

[0030] The electronic component according to embodiments of the present disclosure may further include a first input detection drive circuit electrically connected to a first multiplexer and a second input detection drive circuit electrically connected to a second multiplexer.

[0031] According to embodiments of this disclosure, a display module and electronic device including an input detection circuit with improved touch sensitivity can be provided.

[0032] According to embodiments of this disclosure, electronic components configured to enhance the touch sensitivity of input detection circuitry can be provided. Attached Figure Description

[0033] These and / or other features of the embodiments of this disclosure will become apparent and more readily understood from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

[0034] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0035] Figure 2A , Figure 2B , Figure 2C and Figure 2D Each of them is Figure 1 A schematic cross-sectional view of the electronic device shown;

[0036] Figure 3 This is a schematic plan view of a display module according to an embodiment of the present disclosure;

[0037] Figure 4 This is an equivalent circuit diagram of a pixel according to an embodiment of the present disclosure;

[0038] Figure 5 Is applied to Figure 4 The timing diagram of the light emission control signal and the scanning signal of the pixel in the diagram;

[0039] Figure 6 This is a schematic cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0040] Figure 7 This is a schematic diagram illustrating an operation method of an input detection circuit according to an embodiment of the present disclosure;

[0041] Figure 8A and Figure 8B Each of these is a schematic diagram of a portion of a cross-section of a circuit board according to an embodiment of the present disclosure;

[0042] Figure 9A and Figure 9B Each of these is a schematic diagram of a portion of a cross-section of a circuit board according to an embodiment of the present disclosure;

[0043] Figure 10A and Figure 10B Each of these is a schematic diagram of a portion of a cross-section of a circuit board according to an embodiment of the present disclosure;

[0044] Figure 11 This is a schematic diagram of the shape of a portion of a circuit board as viewed in a plane according to an embodiment of the present disclosure;

[0045] Figure 12 This is a block diagram of an electronic device according to an embodiment; and

[0046] Figure 13 These are schematic diagrams of electronic devices according to various embodiments. Detailed Implementation

[0047] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals throughout refer to the same elements.

[0048] It will be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or an intermediary element may exist between the element and the other element. In contrast, when an element is referred to as being "directly on" another element, no intermediary element exists.

[0049] It will be understood that although the terms “first,” “second,” “third,” etc., may be used in this document to describe various elements, components, areas, layers, and / or segments, these elements, components, areas, layers, and / or segments should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or segment from another element, component, area, layer, or segment. Therefore, without departing from the teachings herein, “first element,” “first component,” “first area,” “first layer,” or “first segment” discussed below may be referred to as “second element,” “second component,” “second area,” “second layer,” or “second segment.”

[0050] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both the singular and the plural. Thus, a reference to “the” element following a reference to “a” element in the claims includes one element and multiple elements. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as limiting “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that, when used in this specification, the terms “comprises and / or comprising” or “includes and / or including” indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0051] Furthermore, relative terms such as “below” or “bottom” and “above” or “top” may be used herein to describe the relationship between one element and another, as shown in the accompanying drawings. It will be understood that, in addition to the orientation depicted in the drawings, the relative terms are also intended to cover different orientations of the device. For example, if the device is flipped in a drawing, an element described as being “below” the other elements will subsequently be oriented to be “above” the other elements. Thus, depending on the specific orientation of the drawing, the term “below” can cover both “below” and “above” orientations. Similarly, if the device is flipped in a drawing, an element described as being “below” or “under” the other elements will subsequently be oriented to be “above” the other elements. Thus, the terms “below” or “under” can cover both “above” and “below” orientations.

[0052] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that, unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their context in the relevant field and their meaning in this disclosure, and shall not be interpreted in an idealized or overly formal sense.

[0053] Embodiments are described herein with reference to cross-sectional views as schematic representations of idealized embodiments. Thus, variations in the shapes illustrated will be expected due to factors such as manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape due to factors such as manufacturing. For example, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0054] The display device according to the embodiments can be applied to various electronic devices. The electronic device according to the embodiments may include the described display device, and may also include modules or devices with additional functions in addition to the display device.

[0055] Figure 1 This is a schematic diagram of an electronic device ED according to an embodiment of the present disclosure.

[0056] Figure 1 An embodiment of an electronic device ED installed in a vehicle is shown. However, devices that include an electronic device ED are not limited thereto.

[0057] An electronic device ED may have a display area DA and a non-display area NDA defined within the electronic device ED. The display area DA may be configured to display an image and detect user input.

[0058] Figure 1 The shape of the display area DA shown is merely an example, and the shape of the display area DA can be modified as needed without limitation.

[0059] The non-display area NDA can be an area adjacent to the display area DA and an area where no image is displayed. The border area of ​​the electronic device ED can be defined by the non-display area NDA. The non-display area NDA can surround the display area DA. However, the shape of the non-display area NDA is not limited to this. The shape of the display area DA and the shape of the non-display area NDA can be modified in various ways.

[0060] Figure 2A , Figure 2B , Figure 2C and Figure 2D Each of them is Figure 1 A schematic cross-sectional view of the electronic device ED shown.

[0061] For ease of explanation, the functional panels and / or the stacked structure of functional panels included in the electronic device ED, Figures 2A to 2D It has been simplified.

[0062] In an embodiment, at least a portion of the display area DA may be parallel to the plane defined by the first direction axis DR1 and the second direction axis DR2. The normal direction of the display area DA (i.e., the thickness direction of the electronic device ED) may be the third direction axis DR3. The front (or upper) and rear (or lower) surfaces of each component may be distinguished by the third direction axis DR3. However, the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3 are merely relative concepts and may be converted to other directions. In the following, the first direction DR1, the second direction DR2, and the third direction DR3 are the directions indicated by the first direction axis DR1, the second direction axis DR2, and the third direction axis DR3, respectively, and are described using the same reference numerals.

[0063] Reference Figure 2A In an embodiment, the electronic device ED may include a display module DM, a reflective protection (or anti-reflective) component RPP, a window component WP, and multiple adhesive components OCA.

[0064] The display module DM may include a display panel DP and an input (or touch) detection circuit ISC. The display module DM may emit light and detect input (or touch on the display module DM). In an embodiment, a substrate member may be further disposed below the display module DM.

[0065] The display panel DP can emit light. According to an embodiment, the display panel DP can be a light-emitting display panel. In an embodiment, for example, the display panel DP can be an organic light-emitting display panel, a quantum dot light-emitting display panel, or a micro light-emitting display panel.

[0066] An input detection circuit (ISC) can be provided on the display panel (DP). The input detection circuit (ISC) can obtain coordinate information from external inputs. In embodiments, for example, at least one selected from capacitive input sensors, resistive input sensors, optical sensors, electromagnetic resonant input sensors, ultrasonic input sensors, and infrared input sensors can be used as the input detection circuit (ISC).

[0067] A reflective protective element (RPP) can be provided on the display module DM. The RPP can reduce the light reflectivity of external light incident from the upper side of the window element WP. According to embodiments of this disclosure, the RPP may include a retarder, a polarizer, and multiple color filters.

[0068] The window component WP can be mounted on the reflective protection component RPP. The window component WP may include a light-transmitting component WTA and a light-blocking component WBM.

[0069] The light-transmitting element WTA may comprise glass and / or synthetic resin. The light-transmitting element WTA may be defined by a single layer, but is not limited thereto. The light-transmitting element WTA may comprise two or more films coupled to each other by adhesive members. At least a portion of the light-transmitting element WTA may overlap with the display area DA of the electronic device ED.

[0070] The light-blocking component WBM can partially overlap with the light-transmitting component WTA. The light-blocking component WBM can be positioned below the light-transmitting component WTA to overlap with the non-display area NDA of the electronic device ED.

[0071] Multiple adhesive components (OCAs) can be optically transparent adhesive components. Multiple adhesive components (OCAs) can each be disposed between a lower component and an upper component to attach the lower component and the upper component to each other.

[0072] One portion of the multiple adhesive components OCA can be positioned between the display module DM and the reflective protective member RPP. Another portion of the multiple adhesive components OCA can be positioned between the reflective protective member RPP and the window member WP.

[0073] The location of multiple adhesive component OCAs is not limited to this. Multiple adhesive component OCAs can also be located between the display panel DP and the input detection circuit ISC. Furthermore, at least some of the multiple adhesive component OCAs can be omitted.

[0074] Reference Figure 2B In another embodiment, the electronic device ED may include a display panel DP, a reflection protection component RPP, an input detection circuit ISC, and a window component WP.

[0075] In such an embodiment, a portion of the plurality of adhesive components OCA can be disposed between the display panel DP and the reflective protective member RPP. Another portion of the plurality of adhesive components OCA can be disposed between the reflective protective member RPP and the input detection circuit ISC. Yet another portion of the plurality of adhesive components OCA can be disposed between the input detection circuit ISC and the window member WP.

[0076] Reference Figure 2C In another embodiment, in Figure 2B In the stacked structure shown, the positions of the reflection protection component RPP and the input detection circuit ISC can be interchanged.

[0077] Reference Figure 2D In another embodiment, multiple adhesive components OCA can be omitted, and the display panel DP, input detection circuit ISC, reflection protection component RPP, and window component WP can be sequentially stacked in the electronic device ED. In another embodiment, the stacking order of the input detection circuit ISC and reflection protection component RPP can be modified in various ways.

[0078] Figure 3 This is a schematic plan view of a display module DM according to an embodiment of the present disclosure.

[0079] Reference Figure 3 In this embodiment, the display panel DP (reference) Figure 2A This can include the display area DA and the non-display area NDA defined within the display panel DP. The non-display area NDA may be defined along the periphery of the display area DA. The display area DA may be... Figure 1 The electronic device ED shown corresponds to the display area DA. The non-display area NDA can be associated with... Figure 1 The non-display area NDA of the electronic device ED shown corresponds to this.

[0080] The display module DM may include: multiple pixels PX, multiple sensor groups SG1, SG2 and SG3, multiple multiplexers MX1, MX2 and MX3, multiple flexible printed circuit boards FPCB, circuit board PCB, multiple input detection drive circuits TIC1, TIC2 and TIC3, and control drive circuit (not shown).

[0081] Multiple pixels (PX) can be set on the display area (DA) of the display panel (DP). Each pixel (PX) can emit light independently.

[0082] Multiple sensor groups SG1, SG2, and SG3 can be arranged on the display area DA of the display panel DP. Each of the multiple sensor groups SG1, SG2, and SG3 can include multiple sensors SN. The first sensor group SG1, the second sensor group SG2, and the third sensor group SG3 can be arranged sequentially in the first direction DR1.

[0083] According to embodiments of this disclosure, the plurality of sensor SNs can be sensors configured to detect touch using a self-dot method. Therefore, the plurality of sensor SNs can be arranged in a matrix shape in a plan view or when viewed on a third-direction DR3. Furthermore, the plurality of sensor SNs can each be electrically connected to a signal line SGL to be electrically connected to a corresponding multiplexer among a plurality of multiplexers MX1, MX2, and MX3.

[0084] Multiple sensors (SNs) can be electrically insulated from each other. Each sensor (SN) can also be transparent, allowing at least some of the incident light to pass through.

[0085] Multiple multiplexers MX1, MX2 and MX3 can be set on the non-display area NDA of the display panel DP.

[0086] Multiple multiplexers MX1, MX2, and MX3 may include a first multiplexer MX1, a second multiplexer MX2, and a third multiplexer MX3. The first multiplexer MX1, the second multiplexer MX2, and the third multiplexer MX3 may be arranged sequentially on the first direction DR1.

[0087] The first multiplexer MX1 ​​can be electrically connected to multiple sensors SN of the first sensor group SG1. The first multiplexer MX1 ​​can transmit electrical signals received from the sensor SN of the first sensor group SG1 to the first input detection drive circuit TIC1, or transmit electrical signals received from the first input detection drive circuit TIC1 to the sensor SN of the first sensor group SG1.

[0088] The second multiplexer MX2 can be electrically connected to multiple sensor SNs of the second sensor group SG2. The second multiplexer MX2 can transmit electrical signals received from the sensor SNs of the second sensor group SG2 to the second input detection drive circuit TIC2, or transmit electrical signals received from the second input detection drive circuit TIC2 to the sensor SNs of the second sensor group SG2.

[0089] The third multiplexer MX3 can be electrically connected to multiple sensor SNs of the third sensor group SG3. The third multiplexer MX3 can transmit electrical signals received from the sensor SNs of the third sensor group SG3 to the third input detection drive circuit TIC3, or transmit electrical signals received from the third input detection drive circuit TIC3 to the sensor SNs of the third sensor group SG3.

[0090] Multiple flexible printed circuit boards (FPCBs) can be electrically connected to the display panel (DP) and the circuit board (PCB). The multiple FPCBs can be bendable. Therefore, the circuit board (PCB) can be positioned below the display panel (DP), and the circuit board (PCB) and the display panel (DP) can be configured to overlap each other on a third-direction DR3.

[0091] The circuit board (PCB) may have multiple input detection drive circuits TIC1, TIC2, and TIC3 mounted on the circuit board (PCB). In the embodiment, although in Figure 3Not shown, but in addition to the multiple input detection drive circuits TIC1, TIC2, and TIC3, the circuit board PCB may also include a control drive circuit (not shown) further mounted in the circuit board PCB. The control drive circuit (not shown) may be an element configured to control various electronic components including the multiple input detection drive circuits TIC1, TIC2, and TIC3.

[0092] The circuit board (PCB) may include multiple connection lines CL1 and CL2. These connection lines CL1 and CL2 can be electrically connected to flexible printed circuit boards (FPCBs) corresponding to multiple input detection drive circuits TIC1, TIC2, and TIC3 mounted on the PCB. For ease of explanation, Figure 3 Only the first connecting line CL1 and the second connecting line CL2 are shown among the multiple connecting lines.

[0093] Multiple input detection drive circuits TIC1, TIC2, and TIC3 can be mounted on a circuit board (PCB). Through multiple sensor groups SG1, SG2, and SG3, the multiple input detection drive circuits TIC1, TIC2, and TIC3 can be configured to process signals corresponding to changes in current caused by a user's touch applied to the display area DA, or signals corresponding to pressure applied from an external source. In this specification, the circuit board (PCB) and the multiple input detection drive circuits TIC1, TIC2, and TIC3 can be referred to as electronic components.

[0094] When configured to detect touch using a self-pointing method, each sensor SN is typically connected to a signal line SGL. Therefore, to include multiple sensor SNs positioned on a large display panel DP and to detect touch using a self-pointing method, the number of signal lines SGL increases. This leads to issues with increased resistance and capacitance, as well as space constraints due to the increased number of pads connected to the display panel DP. To address these issues, multiple multiplexers MX1, MX2, and MX3 can be used.

[0095] Because multiple multiplexers MX1, MX2, and MX3 are used to connect the sensor SN to different input detection drive circuits TIC1, TIC2, and TIC3, problems may arise in the touch detection of the sensor SN due to differences in resistance or capacitance caused by wires of varying lengths. Methods to overcome these problems will be described below using the first sensor SN1 and the second sensor SN2.

[0096] Reference Figure 3The first sensor SN1 of the first sensor group SG1 and the second sensor SN2 of the second sensor group SG2 are arranged adjacent to each other, and no other sensor is arranged between the first sensor SN1 and the second sensor SN2.

[0097] The first sensor SN1 can be electrically connected to the first multiplexer MX1 ​​via a corresponding signal line SGL. The first multiplexer MX1 ​​can be configured to electrically connect the first sensor SN1 to a corresponding flexible printed circuit board FPCB via a first spiderline (or spider web) SPL1. The flexible printed circuit board FPCB can be configured to electrically connect the first spiderline SPL1 and the first connecting line CL1. Since the first connecting line CL1 is electrically connected to the first input detection drive circuit TIC1, the first sensor SN1 and the first input detection drive circuit TIC1 can be electrically connected to each other.

[0098] The second sensor SN2 can be electrically connected to the second multiplexer MX2 via a corresponding signal line SGL. The second multiplexer MX2 can be configured to electrically connect the second sensor SN2 to a corresponding flexible printed circuit board FPCB via a second spider line SPL2. The flexible printed circuit board FPCB can be configured to electrically connect the second spider line SPL2 and the second connection line CL2. Since the second connection line CL2 is electrically connected to the second input detection drive circuit TIC2, the second sensor SN2 and the second input detection drive circuit TIC2 can be electrically connected to each other.

[0099] Here, because the first length of the first spider wire SPL1 is longer than the second length of the second spider wire SPL2, the first spider wire SPL1 and the second spider wire SPL2 can each have different resistances or capacitances formed with other components. Due to the above, problems may exist in the touch detection of the first sensor SN1 and the touch detection of the second sensor SN2. Therefore, by making the third length of the first connecting line CL1 shorter than the fourth length of the second connecting line CL2, problems in the touch detection of the first sensor SN1 and the second sensor SN2 due to differences in resistance or capacitance can be effectively prevented. Therefore, the first capacitance formed by the first connecting line CL1 with other components can be 0.9 times or greater and 1.1 times or less than the second capacitance formed by the second connecting line CL2 with other components. When the first capacitance is less than 0.9 times or greater than 1.1 times the second capacitance, problems may exist in the touch detection of the first sensor SN1 and the second sensor SN2 due to the difference in capacitance.

[0100] Reference Figures 8A to 10B The method for controlling the length of the first connecting line CL1 and the length of the second connecting line CL2 is described in detail.

[0101] In another embodiment, although the first sensor SN1 and the second sensor SN2 are arranged adjacent to each other, the first sensor SN1 and the second sensor SN2 are controlled by different input detection drive circuits TIC1 and TIC2. Therefore, length control as described in this disclosure would be desirable, but even without separate control of the line length, there may be no problem when two adjacent sensors SN are controlled by the same input detection drive circuit.

[0102] Figure 4 It is the equivalent circuit of pixel PX according to an embodiment of the present disclosure. Figure 5 Is applied to Figure 4 The timing diagram of the light emission control signal Ei and the scanning signals Si-1, Si and Si+1 of pixel PX in the diagram. Figure 4 An embodiment of a pixel PX connected to the i-th scan line SLi and the i-th emission control line ECLi is shown.

[0103] In one embodiment, a pixel PX may include a light-emitting diode (LED) LD and a pixel circuit CC. The pixel circuit CC may include a plurality of transistors T1 to T7 and a capacitor CP. The pixel circuit CC may be configured to control the amount of current flowing through the LED LD in response to a data signal.

[0104] The light-emitting diode (LD) can be configured to emit light with a brightness corresponding to the amount of current supplied from the pixel circuit CC. In an embodiment, the level of the first power voltage ELVDD can be set to be higher than the level of the second power voltage ELVSS.

[0105] Each of the transistors T1 to T7 may include an input electrode (or source electrode), an output electrode (or drain electrode), and a control electrode (or gate electrode). In this specification, for ease of description, one of the input electrode and the output electrode may be referred to as the first connection electrode, and the other of the input electrode and the output electrode may be referred to as the second connection electrode.

[0106] The first connection electrode of the first transistor T1 can be connected to the first power voltage ELVDD via the fifth transistor T5, and the second connection electrode can be connected to the first driving electrode of the light-emitting diode LD via the sixth transistor T6. In this specification, the first transistor T1 may be referred to as the driving transistor.

[0107] The first transistor T1 can control the amount of current flowing through the light-emitting diode LD in response to the voltage applied to the control electrode of the first transistor T1.

[0108] The second transistor T2 can be connected between the data line DL and the first connection electrode of the first transistor T1. Furthermore, the control electrode of the second transistor T2 can be connected to the i-th scan line SLi. When the i-th scan signal Si is provided to the i-th scan line SLi, the second transistor T2 can be turned on to electrically connect the data line DL and the first connection electrode of the first transistor T1 to each other.

[0109] The third transistor T3 can be connected between the second connection electrode and the control electrode of the first transistor T1. The control electrode of the third transistor T3 can be connected to the i-th scan line SLi. When the i-th scan signal Si is provided to the i-th scan line SLi, the third transistor T3 can be turned on to electrically connect the second connection electrode and the control electrode of the first transistor T1 to each other. Therefore, when the third transistor T3 is turned on, the first transistor T1 can be connected in the form of a diode.

[0110] The fourth transistor T4 can be connected between node ND and the initialization power generation unit (not shown). Furthermore, the control electrode of the fourth transistor T4 is connected to the (i-1)th scan line SLi-1. When the (i-1)th scan signal Si-1 is provided to the (i-1)th scan line SLi-1, the fourth transistor T4 can be turned on to provide the initialization voltage Vint to node ND.

[0111] The fifth transistor T5 can be connected between the power line PL and the first connection electrode of the first transistor T1. Here, the power line PL can deliver the first power voltage ELVDD. The control electrode of the fifth transistor T5 can be connected to the i-th light-emitting control line ECLi.

[0112] The sixth transistor T6 can be connected between the second connection electrode of the first transistor T1 and the first driving electrode of the light-emitting diode LD. Furthermore, the control electrode of the sixth transistor T6 can be connected to the i-th light-emitting control line ECLi.

[0113] The seventh transistor T7 can be connected between the initialization power generation unit (not shown) and the first driving electrode of the light-emitting diode LD. Furthermore, the control electrode of the seventh transistor T7 can be connected to the (i+1)th scan line SLi+1. When the (i+1)th scan signal Si+1 is provided to the (i+1)th scan line SLi+1, the seventh transistor T7 can be turned on to provide the initialization voltage Vint to the first driving electrode of the light-emitting diode LD.

[0114] The seventh transistor T7 can improve the black level performance of pixel PX. In an embodiment, for example, when the seventh transistor T7 is turned on, the parasitic capacitor (not shown) of the light-emitting diode LD can be discharged. Then, when black brightness is achieved, the light-emitting diode LD does not emit light due to the leakage current from the first transistor T1. In this way, the black level performance of the pixel can be improved.

[0115] Figure 4 An embodiment is shown in which the control electrode of the seventh transistor T7 is connected to the (i+1)th scan line SLi+1, but this disclosure is not limited thereto. In another embodiment of this disclosure, the control electrode of the seventh transistor T7 may be connected to the i-th scan line SLi or the (i-1)th scan line SLi-1.

[0116] Figure 4 An embodiment is shown in which each transistor of the pixel circuit CC is a P-type metal-oxide-semiconductor (PMOS) transistor, but this disclosure is not limited thereto. In another embodiment of this disclosure, each transistor of the pixel circuit CC is an N-type metal-oxide-semiconductor (NMOS) transistor. In yet another embodiment of this disclosure, the pixel PX may include a combination of NMOS transistors and PMOS transistors.

[0117] The capacitor CP can be located between the power line PL and the node ND. The capacitor CP can be configured to store the voltage corresponding to the data signal. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 can be determined based on the voltage stored in the capacitor CP.

[0118] In this disclosure, the structure of the pixel PX is not limited to Figure 4 The structure shown is illustrated. In another embodiment of this disclosure, the pixel PX can be provided in various forms for emitting light in a light-emitting diode (LD).

[0119] Reference Figure 5 The light emission control signal Ei can be either high (E-HIGH) or low (E-LOW). The scan signals Si-1, Si, and Si+1 can each be either high (S-HIGH) or low (S-LOW).

[0120] In an embodiment, for example, when the light emission control signal Ei has a high level E-HIGH, the fifth transistor T5 and the sixth transistor T6 are turned off. When the fifth transistor T5 is turned off, the power line PL and the first connection electrode of the first transistor T1 can be electrically disconnected. When the sixth transistor T6 is turned off, the second connection electrode of the first transistor T1 and the first driving electrode of the light-emitting diode LD can be electrically disconnected. Therefore, when the light emission control signal Ei with a high level E-HIGH is provided to the i-th light emission control line ECLi, the light-emitting diode LD may not emit light. In other words, the period when the light emission control signal Ei has a high level E-HIGH can correspond to a non-light emission period.

[0121] Subsequently, when the (i-1)th scan signal Si-1 provided to the (i-1)th scan line SLi-1 has a low level S-LOW, the fourth transistor T4 can be turned on. When the fourth transistor T4 is turned on, the initialization voltage Vint can be provided to node ND.

[0122] When the i-th scan signal Si supplied to the i-th scan line SLi has a low level S-LOW, the second transistor T2 and the third transistor T3 can be turned on. When the second transistor T2 is turned on, the data signal can be supplied to the first connection electrode of the first transistor T1. Here, since node ND is initialized to the initialization voltage Vint, the first transistor T1 can be turned on. When the first transistor T1 is turned on, the voltage corresponding to the data signal can be supplied to node ND. Here, the capacitor CP can store the voltage corresponding to the data signal.

[0123] When the (i+1)th scan signal Si+1 provided to the (i+1)th scan line SLi+1 has a low level S-LOW, the seventh transistor T7 can be turned on.

[0124] When the seventh transistor T7 is turned on, the initialization voltage Vint can be provided to the first driving electrode of the light-emitting diode LD, thereby discharging the parasitic capacitor of the light-emitting diode LD.

[0125] When the light emission control signal Ei supplied to the light emission control line ECLi is at a low level (E-LOW), the fifth transistor T5 and the sixth transistor T6 can be turned on. When the fifth transistor T5 is turned on, the first power voltage ELVDD can be supplied to the first connection electrode of the first transistor T1. When the sixth transistor T6 is turned on, the second connection electrode of the first transistor T1 and the first driving electrode of the light emission diode LD can be electrically connected to each other. Then, the light emission diode LD generates light with a brightness corresponding to the amount of current supplied. In other words, the period when the light emission control signal Ei is at a low level (E-LOW) corresponds to the light emission period.

[0126] Figure 6 This is a schematic cross-sectional view of a display panel DP according to an embodiment of the present disclosure.

[0127] In this embodiment, the display panel DP (reference) Figure 2A It may include a substrate component BL, a circuit layer CCL, a light-emitting diode layer ELL, and a packaging layer TFE. Light can be emitted from the display panel DP.

[0128] The substrate component BL can be the substrate of the display panel DP. That is, other components of the display panel DP can be stacked on the substrate component BL. The substrate component BL can include organic layers and / or inorganic layers. The organic layers can include organic materials. In an embodiment, for example, the organic layer can include polyimide. The inorganic layers can include inorganic materials.

[0129] The circuit layer CLL may include a barrier layer BR, a buffer layer BF, a gate insulating layer GI, an interlayer insulating layer ILD, a circuit insulating layer VIA, a first transistor T1, and a second transistor T2.

[0130] The first transistor T1 and the second transistor T2 can be configured to transmit electrical signals. Furthermore, the first transistor T1 and the second transistor T2 may include multiple active components ACL, multiple first connection electrodes CE1, multiple control electrodes GE, and multiple second connection electrodes CE2.

[0131] A barrier layer BR can be provided on the substrate component BL. The barrier layer BR can be configured to prevent the penetration of moisture, for example, introduced from the outside. The barrier layer BR may include inorganic insulating materials such as silicon oxide and silicon nitride.

[0132] A buffer layer (BF) can be provided on the barrier layer (BR). The buffer layer (BF) can prevent impurities introduced from below from being transported upwards. Therefore, components disposed on the buffer layer (BF) can be protected. The buffer layer (BF) can include inorganic insulating materials such as silicon oxide and silicon nitride.

[0133] Multiple active component ACLs can be provided on the buffer layer BF. The multiple active component ACLs can include polycrystalline silicon or amorphous silicon. Other active component ACLs can include metal-oxide-semiconductor (MOS) semiconductors. Each of the multiple active component ACLs can include a channel region and a first ion-doped region and a second ion-doped region, the channel region serving as a passage for electrons or holes to move through, the channel region being disposed between the first ion-doped region and the second ion-doped region.

[0134] The gate insulating layer GI covers the buffer layer BF and multiple active components ACL. The gate insulating layer GI may include organic films and / or inorganic films. The gate insulating layer GI may include multiple inorganic thin films or be defined by multiple inorganic thin films. The multiple inorganic thin films may include a silicon nitride layer and a silicon oxide layer.

[0135] Multiple control electrodes GE can be provided on the buffer layer BF. Multiple control electrodes GE can overlap with multiple active components ACL on the third-direction DR3. Furthermore, the multiple control electrodes GE may include molybdenum (Mo).

[0136] An interlayer insulating layer (ILD) can be provided on and covering multiple control electrodes (GE) on the gate insulating layer (GI). The ILD can include organic and / or inorganic films. The ILD can include multiple inorganic or organic thin films. The multiple inorganic thin films can include a silicon nitride film (silicon nitride layer) and a silicon oxide film (silicon oxide layer).

[0137] Multiple first connection electrodes CE1 and multiple second connection electrodes CE2 may be provided on the interlayer insulating layer (ILD). The multiple first connection electrodes CE1 and multiple second connection electrodes CE2 may be electrically connected to multiple active components (ACLs) through contact holes defined in the interlayer insulating layer (ILD). Furthermore, the multiple first connection electrodes CE1 and multiple second connection electrodes CE2 may include metal.

[0138] The circuit insulating layer VIA may cover the interlayer insulating layer ILD, the plurality of first connecting electrodes CE1, and the plurality of second connecting electrodes CE2. The circuit insulating layer VIA may include an organic film and / or an inorganic film. The circuit insulating layer VIA may provide a flat surface or include a flat upper surface. In another embodiment, more circuit insulating layers VIA may be provided as needed.

[0139] The light-emitting diode layer ELL can include a pixel-defining film (PDL) and a light-emitting diode (LD). Light can be emitted from the light-emitting diode layer ELL.

[0140] The pixel defining film (PDL) can be disposed on a portion of the circuit insulating layer (VIA). The PDL can define an opening portion (OP). Furthermore, the opening portion (OP) can expose the light-emitting diode (LD).

[0141] A light-emitting diode (LD) can be configured to emit light. Furthermore, a LD may include a first driving electrode DE1, a light-emitting unit LEP, and a second driving electrode DE2.

[0142] A first driving electrode DE1 may be provided on a portion of the circuit insulating layer VIA. An opening OP may expose the first driving electrode DE1. Furthermore, the first driving electrode DE1 may be electrically connected to a corresponding one of a plurality of second connection electrodes CE2 via a contact hole defined in the circuit insulating layer VIA. Therefore, the first driving electrode DE1 may be configured to receive electrical signals from the first transistor T1 and the second transistor T2.

[0143] Figure 6 An embodiment of the pixel circuit CC of a pixel is shown, comprising a first transistor T1 and a second transistor T2; however, the structure of the first transistor T1 and the second transistor T2 is not limited thereto. Figure 6 In the diagram, the first transistor T1 is shown as being in direct contact with the first driving electrode DE1 via one of a plurality of second connection electrodes CE2; however, this is merely a cross-sectional shape and is therefore shown. In an embodiment, the first transistor T1 may be connected to the first driving electrode DE1 via another transistor. However, this disclosure is not limited thereto, and in another embodiment of this disclosure, the first transistor T1 may be in direct contact with the first driving electrode DE1 via a corresponding one of the plurality of second connection electrodes CE2.

[0144] The first driving electrode DE1 can be the anode electrode of a light-emitting diode (LD). Holes can be provided through the first driving electrode DE1. However, the configuration of the first driving electrode DE1 is not limited thereto. In another embodiment of this disclosure, the first driving electrode DE1 can be the cathode electrode of the light-emitting diode (LD) and provide electrons, and the configuration and effect of the first functional layer FL1 and the second functional layer FL2 can be interchanged.

[0145] The light-emitting unit (LEP) may include a first functional layer FL1, a light-emitting layer EML, and a second functional layer FL2. Light can be emitted from the light-emitting unit (LEP).

[0146] A first functional layer FL1 may be provided on the first driving electrode DE1. The first functional layer FL1 may be configured to support the transport of holes generated from the first driving electrode DE1. In an embodiment, for example, the first functional layer FL1 may be configured to more easily receive holes injected from the first driving electrode DE1 and facilitate hole transport. The first functional layer FL1 may have a multilayer structure. In an embodiment, for example, the first functional layer FL1 may have a structure further including, for example, a first injection layer (not shown) and a first transport layer (not shown).

[0147] An emissive layer (EML) can be provided on the first functional layer (FL1). Light can be emitted from the emissive layer (EML). For example, the emissive layer (EML) may include organic light-emitting materials or quantum dots. Therefore, the light-emitting diode (LD) may be an organic light-emitting diode or a quantum dot light-emitting diode.

[0148] A second functional layer FL2 may be provided on the light-emitting layer EML. The second functional layer FL2 may be configured to support the transport of electrons generated from the second driving electrode DE2. In embodiments, for example, the second functional layer FL2 may be configured to more easily receive electrons injected from the second driving electrode DE2 and facilitate electron transport. The second functional layer FL2 may have a multilayer structure. In embodiments, for example, the second functional layer may have a structure further including, for example, a second injection layer (not shown) and a second transport layer (not shown).

[0149] A second driving electrode DE2 can be provided on the light-emitting unit (LEP). The second driving electrode DE2 can have a low surface resistance to allow current to flow easily through it.

[0150] The second driving electrode DE2 can be the cathode electrode of a light-emitting diode (LD). Electrons can be supplied through the second driving electrode DE2. However, the configuration of the second driving electrode DE2 is not limited thereto. In another embodiment of this disclosure, the second driving electrode DE2 can be the anode electrode of the light-emitting diode (LD) and supply holes, and the configuration and effect of the first functional layer FL1 and the second functional layer FL2 can be interchanged.

[0151] The second driving electrode DE2 allows incident light to pass through via a selectable light transmittance. Light passing through the second driving electrode DE2 can be emitted to... Figure 1 The electronic device ED is external and visible to the user.

[0152] The second driving electrode DE2 can reflect incident light through a selectable reflectivity. Light reflected by the second driving electrode DE2 can be reflected by the first driving electrode DE1, which can induce resonance in the light-emitting diode (LD). Due to the resonance phenomenon in the LD, the luminous efficiency of the LD can be increased.

[0153] The encapsulation layer TFE can be configured to seal the light-emitting diode (LD) to protect it from external oxygen or moisture. The encapsulation layer TFE may include a first inorganic encapsulation layer CVD1, an organic encapsulation layer MN, and a second inorganic encapsulation layer CVD2.

[0154] In an embodiment, such as Figure 6 As shown, the encapsulation layer TFE may include two inorganic encapsulation layers CVD1 and CVD2 and one organic encapsulation layer MN, but this disclosure is not limited to this example. In another embodiment, for example, the encapsulation layer TFE may include three inorganic encapsulation layers and two organic encapsulation layers. In such an embodiment, the inorganic and organic encapsulation layers may be stacked alternately.

[0155] Figure 7This is a schematic diagram illustrating the operation method of the input detection circuit ISC according to an embodiment of the present disclosure.

[0156] Reference Figure 7 Also refer to Figure 2A and Figure 3 Touch operation may include the process of an input detection driving unit IDR providing a free charge voltage Vpre and a drive signal Vdrv to a sensor SN, and the process of an input detection unit IDT detecting a touch. The touch detection process can refer to the process of detecting a touch from an external source and determining the coordinates of the touch. In an embodiment, input detection driving circuits TIC1, TIC2, and TIC3 may each include an input detection driving unit IDR and an input detection unit IDT. The input detection driving unit IDR may be configured to provide the free charge voltage Vpre and the drive signal Vdrv to the sensor SN and receive a detection signal corresponding to the drive signal from the sensor SN to determine the coordinates of the touch.

[0157] In embodiments, for example, the free-charge transistor TRP of the input detection driving unit IDR can be controlled by the gate voltage Vg to apply a free-charge voltage Vpre to the sensor SN. The input detection circuit ISC according to embodiments of this disclosure may include a drive signal generation unit (not shown) in the input detection driving unit IDR for enhancing touch sensitivity. When a touch is detected, the drive signal generation unit may apply a drive signal Vdrv to a drive capacitor Cdrv. In embodiments of this disclosure, the drive capacitor Cdrv may be a capacitor formed between the sensor SN to be sensed and other elements adjacent to the sensor SN (e.g., another sensor or signal line). In embodiments of this disclosure, the drive signal Vdrv may be a pulse-type signal with a variable voltage level.

[0158] When finger FG touches the portion adjacent to sensor SN, a contact capacitive capacitance Ct can be generated. For example, when finger FG touches window member WP that overlaps with sensor SN in the thickness direction or third direction DR3, a contact capacitive capacitance Ct can be generated.

[0159] In embodiments of this disclosure, at the second driving electrode DE2 (reference) Figure 6 The capacitive capacitance value Cgnd formed between the sensor SN and the sensor SN, or the voltage of the sensing node NS, can be changed based on the touch-ground voltage Vgnd applied to the second driving electrode DE2.

[0160] With the driving signal Vdrv applied to the driving capacitor Cdrv, the input detection unit IDT can be configured to determine whether the finger FG touches the sensor SN or the coordinates of the touch based on the voltage difference between when the contact capacitive capacitor Ct is generated and when the contact capacitive capacitor Ct is not generated.

[0161] For example, when a user's finger FG contacts at least one of the sensors SN, a contact capacitance Ct can be generated between the finger FG and the sensor SN, and the capacitance value Cgnd or the voltage of the sensing node NS can be changed by the contact capacitance Ct. The changed capacitance value Cgnd or the changed voltage of the sensing node NS can be transmitted to the input detection unit IDT via a signal line SGL connected to the sensor SN contacted by the finger FG. The input detection unit IDT can determine the signal line SGL and the coordinates of the touch, with the signal line SGL receiving the changed capacitance value Cgnd or the changed voltage of the sensing node NS. That is, the input detection unit IDT can be configured to detect the change in self-capacitance formed by the sensor SN and determine the coordinates of the touch.

[0162] Figure 8A and Figure 8B Each of these is a schematic diagram of a portion of a cross-section of a circuit board (PCB) according to an embodiment of this disclosure.

[0163] The circuit board (PCB) according to embodiments of this disclosure may include multiple layers, and Figure 8A and Figure 8B This shows only a portion of the multiple layers of a circuit board (PCB).

[0164] Reference Figure 8A and Figure 8B In an embodiment, the circuit board PCB may include multiple base layers SB1, SB2 and SB3, multiple base insulating layers SBI1, SBI2 and SBI3, and connecting lines CL1 and CL2.

[0165] At least a portion of the connecting wires CL1 and CL2 may be disposed on the first substrate layer SB1. The first substrate insulating layer SBI1 may be disposed below the first substrate layer SB1. The second substrate layer SB2 may be disposed below the first substrate insulating layer SBI1. The second substrate insulating layer SBI2 may be disposed below the second substrate layer SB2. The third substrate insulating layer SB3 may be disposed below the second substrate insulating layer SBI2. The third substrate insulating layer SBI3 may be disposed below the third substrate layer SB3.

[0166] Figure 8A This is a schematic diagram of a section corresponding to a portion of the first connection line CL1 on the PCB. (Refer to...) Figure 8AThe first connecting line CL1 can be set on the first base layer SB1.

[0167] Figure 8B This is a schematic diagram of a cross-section corresponding to another part of the second connection line CL2 on the PCB. (Refer to...) Figure 8B The second connecting line CL2 may include an upper connecting line CLT and a lower connecting line CLB. The upper connecting line CLT may be a portion of the second connecting line CL2 disposed on the first substrate layer SB1. The lower connecting line CLB may be a portion of the second connecting line CL2 disposed between the first substrate insulating layer SBI1 and the second substrate layer SB2. The upper connecting line CLT and the lower connecting line CLB may be electrically connected to each other through a first through-hole TH1 defined in the first substrate layer SB1 and the first substrate insulating layer SBI1. Figure 8B As shown, the upper connecting line CLT and the lower connecting line CLB of the second connecting line CL2 are set in different layers (or directly on different layers) so that the length of the second connecting line CL2 is longer than the length of the first connecting line CL1.

[0168] Figure 9A and Figure 9B Each of these is a schematic diagram of a portion of a cross-section of a circuit board PCB-1 according to an embodiment of the present disclosure.

[0169] Figure 9A This is a schematic diagram of a section corresponding to a portion of the first connection line CL1-1 on circuit board PCB-1. (Refer to...) Figure 9A The first connecting line CL1-1 may include a first upper connecting line CLT1 and a first lower connecting line CLB1. The first upper connecting line CLT1 may be a portion of the first connecting line CL1-1 disposed on the first substrate layer SB1. The first lower connecting line CLB1 may be a portion of the first connecting line CL1-1 disposed between the first substrate insulating layer SBI1 and the second substrate layer SB2. The first upper connecting line CLT1 and the first lower connecting line CLB1 may be electrically connected to each other through a first through-hole TH1 defined in the first substrate layer SB1 and the first substrate insulating layer SBI1.

[0170] Figure 9B This is a schematic diagram of a section corresponding to a portion of the second connection line CL2-1 on circuit board PCB-1. (Refer to...) Figure 9BThe second connecting line CL2-1 may include a second upper connecting line CLT2, an intermediate connecting line CLM2, and a second lower connecting line CLB2. The second upper connecting line CLT2 may be a portion of the second connecting line CL2-1 disposed on the first substrate layer SB1. The intermediate connecting line CLM2 may be another portion of the second connecting line CL2-1 disposed between the first substrate insulating layer SBI1 and the second substrate layer SB2. The second lower connecting line CLB2 may be yet another portion of the second connecting line CL2-1 disposed between the second substrate insulating layer SBI2 and the third substrate layer SB3.

[0171] The second upper connecting line CLT2, the middle connecting line CLM2, and the second lower connecting line CLB2 can be electrically connected to each other through a first through-hole TH1 defined in the first base layer SB1 and the first base insulating layer SBI1, and a second through-hole TH2 defined in the second base layer SB2 and the second base insulating layer SBI2. For example... Figure 9B As shown, the second connecting line CL2-1 can be set in three different layers, and the length of the second connecting line CL2-1 can be longer than the length of the first connecting line CL1-1 set on two different layers.

[0172] Figure 10A and Figure 10B Each of these is a schematic diagram of a portion of a cross-section of a circuit board PCB-2 according to an embodiment of the present disclosure.

[0173] Figure 10A This is a schematic diagram of a section corresponding to a portion of the first connection line CL1-1 on circuit board PCB-2. (For...) Figure 10A Description and targeting Figure 9A The descriptions are essentially the same, and therefore... Figure 10A Any repeated detailed descriptions will be omitted.

[0174] Figure 10B This is a schematic diagram of a cross-section corresponding to another part of the second connection line CL2-2 on circuit board PCB-2. (Refer to...) Figure 10B The second connecting line CL2-2 may include a second upper connecting line CLT2-1, a middle connecting line CLM2-1, and a second lower connecting line CLB2-1. Because... Figure 10B The structure of the second upper connecting line CLT2-1, the middle connecting line CLM2-1, and the second lower connecting line CLB2-1 shown in the figure are similar to those of the second upper connecting line CLT2-1, the middle connecting line CLM2-1, and the second lower connecting line CLB2-1. Figure 9B The structures of the second upper connecting line CLT2, the middle connecting line CLM2, and the second lower connecting line CLB2 shown are only partially different, therefore their substantial descriptions are essentially the same, and thus... Figure 10B Any repeated detailed descriptions will be omitted.

[0175] Figure 11 This is a schematic diagram showing the shape of a portion of a circuit board (PCB) according to an embodiment of the present disclosure, viewed in a planar manner. Specifically, Figure 11 This is shown when viewed on a plane or when viewed on a third-direction DR3. Figure 8B A plan view of the shape of the lower connector CLB. (Refer to...) Figure 11 The lower connecting line CLB can be configured to have a zigzag or sawtooth shape in the plane to increase the total length of the second connecting line CL2. However, this disclosure is not limited thereto, and the lower connecting line CLB2 can also be configured to have a straight shape in the plane.

[0176] Figure 12 This is a block diagram of an electronic device ED according to an embodiment.

[0177] Reference Figure 12 According to an embodiment, the electronic device ED may include a display module DM, a processor PCS, a memory MMR, and a power module PM.

[0178] The processor PCS may include at least one selected from a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0179] The memory MMR can be configured to store data information for the operation of the processor PCS or the display module DM. In applications where the processor PCS operates on data stored in the memory MMR, the display module DM can be configured to receive image data signals and / or input control signals and process the received signals to provide image information output through the display screen.

[0180] The power module PM may include a power supply module such as a power adapter or battery device, and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device ED.

[0181] At least one of the elements of the described electronic device ED may be included in the display device according to the embodiments described above. Furthermore, some of the individual modules functionally included in a single module may be included in the display device, and others of the individual modules may be provided separately from the display device. In embodiments, for example, the display module DM may be included in the display device, and the processor PCS, memory MMR, and power module PM may be provided as another device within the electronic device ED besides the display device.

[0182] Figure 13 These are schematic diagrams of electronic devices according to various embodiments.

[0183] Reference Figure 13 The various electronic devices including the display device according to the embodiments can include not only image display electronic devices such as smartphones ED-1a, tablet computers ED-1b, laptop computers ED-1c, televisions (TVs) ED1-d and desktop monitors ED-1e, but also wearable electronic devices including display modules such as smart glasses ED-2a, head-mounted displays ED-2b and smartwatches ED-2c, as well as vehicle electronic devices including display modules such as dashboards, center consoles and central information displays (CIDs) and rearview mirror displays in automobiles ED-3.

[0184] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0185] Although the invention has been specifically shown and described with reference to embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the appended claims.

Claims

1. A display module, wherein, The display module includes: A display panel includes a display area and a non-display area surrounding the display area; Multiple sensors are provided on the display area and include a first sensor and a second sensor disposed adjacent to the first sensor; A first multiplexer is electrically connected to the first sensor; A second multiplexer is electrically connected to the second sensor and spaced apart from the first multiplexer; A first spider line, electrically connected to the first multiplexer, is provided on the non-display area and has a first length; A second spider wire, electrically connected to the second multiplexer, is provided on the non-display area and has a second length shorter than the first length; Multiple flexible printed circuit boards, at least one of which is electrically connected to at least one corresponding one of the first spider wire and the second spider wire; The circuit board includes a first connecting line having a third length and a second connecting line having a fourth length longer than the third length, wherein the first connecting line and the second connecting line are electrically connected to the first spider line and the second spider line respectively via at least one of the plurality of flexible printed circuit boards; A first input detection driving circuit is electrically connected to the first connection line and mounted on the circuit board; and The second input detection drive circuit is electrically connected to the second connection line and is mounted on the circuit board.

2. The display module according to claim 1, wherein: The circuit board further includes: a first base layer; a second base layer; and a first base insulating layer disposed between the first base layer and the second base layer; The first connection line is provided on the first substrate layer; and A portion of the second connecting line is disposed on the first substrate layer, and another portion of the second connecting line is disposed between the first substrate insulating layer and the second substrate layer.

3. The display module according to claim 1, wherein: The circuit board further includes: a first base layer; a second base layer; and a first base insulating layer disposed between the first base layer and the second base layer; The first connecting line includes: a first upper connecting line disposed on the first substrate layer; and a first lower connecting line disposed between the first substrate insulating layer and the second substrate layer; and The second connecting line includes: a second upper connecting line disposed on the first substrate layer; and a second lower connecting line disposed between the first substrate insulating layer and the second substrate layer.

4. The display module according to claim 1, wherein: The circuit board further includes: a first base layer; a second base layer; a third base layer; a first base insulating layer disposed between the first base layer and the second base layer; and a second base insulating layer disposed between the second base layer and the third base layer. The first connecting line includes: a first upper connecting line disposed on the first substrate layer; and a first lower connecting line disposed between the first substrate insulating layer and the second substrate layer; and The second connecting line includes: a second upper connecting line disposed on the first substrate layer; an intermediate connecting line disposed between the first substrate insulating layer and the second substrate layer; and a second lower connecting line disposed between the second substrate insulating layer and the third substrate layer.

5. The display module according to claim 1, wherein, The capacitance formed by the first connecting line and other components is 0.9 times or greater and 1.1 times or less than the capacitance formed by the second connecting line and other components.

6. The display module according to claim 1, wherein, None of the multiple sensors are positioned between the first sensor and the second sensor. The second sensor is spaced apart from the first sensor in a first direction, and The second multiplexer is spaced apart from the first multiplexer in the first direction.

7. The display module according to claim 6, wherein, The first input detection drive circuit detects the change in capacitance formed by the first sensor and other components, and The second input detection drive circuit detects changes in the capacitance formed by the second sensor and other components.

8. The display module according to claim 7, wherein, The plurality of flexible printed circuit boards are bendable so that they overlap with the display panel.

9. An electronic device, wherein, The electronic device includes: Multiple sensors, including a first sensor and a second sensor disposed adjacent to the first sensor, wherein each of the first sensor and the second sensor forms a capacitance with an object approaching from the outside; A first multiplexer is electrically connected to the first sensor; A second multiplexer is electrically connected to the second sensor and spaced apart from the first multiplexer; A first spider wire is electrically connected to the first multiplexer and has a first length; The second spider wire is electrically connected to the second multiplexer and has a second length that is shorter than the first length; A circuit board includes a first connecting line having a third length and a second connecting line having a fourth length longer than the third length, wherein the first connecting line is electrically connected to the first spider line and the second connecting line is electrically connected to the second spider line; A first input detection driving circuit is electrically connected to the first connection line, wherein the first input detection driving circuit detects changes in the capacitance of the first sensor; and A second input detection driving circuit is electrically connected to the second connection line, wherein the second input detection driving circuit detects the change in capacitance of the second sensor.

10. The electronic device according to claim 9, wherein: The circuit board also includes: First basal layer; A first substrate insulating layer is disposed beneath the first substrate layer; and The second substrate layer is disposed below the first substrate insulating layer, and A portion of the second connecting line is disposed on the first substrate layer, and another portion of the second connecting line is disposed between the first substrate insulating layer and the second substrate layer.

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