A driver, a display device including the same, and an electronic device including the same

Abstract

The present application relates to a driver, a display device including the same, and an electronic device including the same. The driver includes a stage. The stage includes an input portion that transmits a forward carry signal to a first control node in response to a first clock signal and a second clock signal having a different phase from the first clock signal, a carry output portion that generates a current carry signal based on a first high power voltage and a low power voltage in response to a signal of the first control node, a level shifter that generates a signal of a second control node and a signal of a third control node based on a second high power voltage greater than the first high power voltage and the low power voltage in response to the current carry signal, and an output portion that generates an output signal based on the second high power voltage and the low power voltage in response to the signal of the second control node or the signal of the third control node.

Description

Technical Field

[0001] This invention relates to a driver, a display device including the same, and an electronic device including the same, specifically a CMOS type driver used as a gate driver or an emitter driver, a display device including the same, and an electronic device including the same. Background Technology

[0002] Typically, a display device includes a display panel and a display panel driving unit. The display panel includes a plurality of gate lines, a plurality of data lines, a plurality of emitter lines, and a plurality of pixels. The display panel driving unit includes a gate driving unit that provides gate signals to the plurality of gate lines, a data driving unit that provides data voltages to the data lines, an emitter driving unit that provides emitter signals to the emitter lines, and a drive control unit that controls the gate driving unit, the data driving unit, and the emitter driving unit.

[0003] The driver of the display device (e.g., a gate driver and / or a transmitter driver) can sequentially provide signals (e.g., gate signals and / or transmitter signals) to the pixels of the display panel row by row. The driver can be implemented in the form of a shift register including multiple stages to provide the signals sequentially row by row.

[0004] In the aforementioned driver, when the clock signal, carry signal, and output signal are generated based on the same power supply voltage, the power consumption of the display device is a significant problem. Summary of the Invention

[0005] The purpose of this invention is to provide a driver that includes a level shifter, thereby allowing the swing range of the clock signal and the carry signal to be set to be smaller than the swing range of the output signal, thereby reducing power consumption.

[0006] Another object of the present invention is to provide a display device including the driver.

[0007] Another object of the present invention is to provide an electronic device including the driver.

[0008] A driver according to an embodiment of the present invention for achieving the above-described object of the present invention includes a stage. The stage includes: an input section that transmits a carry signal to a first control node in response to a first clock signal and a second clock signal having a different phase from the first clock signal; a carry output section that generates a current carry signal based on a first high power supply voltage and a low power supply voltage in response to a signal from the first control node; a level shifter that generates a signal from a second control node and a signal from a third control node based on a second high power supply voltage greater than the first high power supply voltage and the low power supply voltage in response to the current carry signal; and an output section that generates an output signal based on the second high power supply voltage and the low power supply voltage in response to the signal from the second control node or the signal from the third control node.

[0009] In one embodiment of the present invention, when the stage is an odd-numbered stage, the output unit generates the output signal in response to the signal of the second control node. Alternatively, when the stage is an even-numbered stage, the output unit generates the output signal in response to the signal of the third control node.

[0010] In one embodiment of the present invention, when the level is an odd-numbered level, the phase of the current carry signal is opposite to the phase of the output signal. Alternatively, when the level is an even-numbered level, the phase of the current carry signal is the same as the phase of the output signal.

[0011] In one embodiment of the present invention, when the level is an odd-numbered level, the phase of the signal of the first control node is the same as the phase of the output signal. Alternatively, when the level is an even-numbered level, the phase of the signal of the first control node is opposite to the phase of the output signal.

[0012] In one embodiment of the present invention, the high level of the carry signal, the current carry signal, the first clock signal, and the second clock signal may be the first high power supply voltage. Alternatively, the low level of the carry signal, the current carry signal, the first clock signal, and the second clock signal may be the low power supply voltage. Alternatively, the high level of the output signal may be the second high power supply voltage. Alternatively, the low level of the output signal may be the low power supply voltage.

[0013] In one embodiment of the present invention, the high level of the signal of the first control node may be the first high power supply voltage. Alternatively, the low level of the signal of the first control node may be the low power supply voltage.

[0014] In one embodiment of the present invention, the high level of the signal of the second control node and the high level of the signal of the third control node may be the second high power supply voltage. Alternatively, the low level of the signal of the second control node and the low level of the signal of the third control node may be the low power supply voltage.

[0015] In one embodiment of the present invention, the input section may include: a first transistor including a control electrode to which the first clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node; and a second transistor including a control electrode to which the second clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node.

[0016] In one embodiment of the present invention, the carry output section may include: a third transistor, including a control electrode connected to the first control node, a first electrode to which the first high power supply voltage is applied, and a second electrode connected to the carry output node; and a fourth transistor, including a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the carry output node.

[0017] In one embodiment of the present invention, the carry output section may further include: a capacitor, including a first electrode to which the first high power supply voltage is applied and a second electrode connected to the first control node.

[0018] In one embodiment of the present invention, the carry output section may further include: a capacitor, including a first electrode to which the second high power supply voltage is applied and a second electrode connected to the first control node.

[0019] In one embodiment of the present invention, the carry output section may further include: a capacitor, including a first electrode to which the low power supply voltage is applied and a second electrode connected to the first control node.

[0020] In one embodiment of the present invention, the level converter may include: a fifth transistor, including a control electrode connected to the second control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the first intermediate node; a sixth transistor, including a control electrode connected to the carry output node, a first electrode connected to the first intermediate node, and a second electrode connected to the third control node; a seventh transistor, including a control electrode connected to the carry output node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the third control node; an eighth transistor, including a control electrode connected to the third control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the second intermediate node; a ninth transistor, including a control electrode connected to the first control node, a first electrode connected to the second intermediate node, and a second electrode connected to the second control node; and a tenth transistor, including a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the second control node.

[0021] In one embodiment of the present invention, the output section may include: an eleventh transistor, including a control electrode connected to the second control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the output node; and a twelfth transistor, including a control electrode connected to the second control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the output node.

[0022] In one embodiment of the present invention, the output section may include: an eleventh transistor, including a control electrode connected to the third control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the output node; and a twelfth transistor, including a control electrode connected to the third control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the output node.

[0023] In one embodiment of the present invention, when the stage is an odd-numbered stage, the odd-numbered stage includes: a first transistor, including a control electrode to which the first clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node; a second transistor, including a control electrode to which the second clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node; a third transistor, including a control electrode connected to the first control node, a first electrode to which the first high power supply voltage is applied, and a second electrode connected to the carry output node; a fourth transistor, including a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the carry output node; a fifth transistor, including a control electrode connected to the second control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the first intermediate node; and a sixth transistor, including a control electrode connected to the carry output node and a first electrode connected to the first intermediate node. The transistor includes a second electrode connected to the third control node; a seventh transistor, including a control electrode connected to the carry output node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the third control node; an eighth transistor, including a control electrode connected to the third control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the second intermediate node; a ninth transistor, including a control electrode connected to the first control node, a first electrode connected to the second intermediate node, and a second electrode connected to the second control node; a tenth transistor, including a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the second control node; an eleventh transistor, including a control electrode connected to the second control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the output node; and a twelfth transistor, including a control electrode connected to the second control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the output node. It is possible that the first, third, fifth, sixth, eighth, ninth, and eleventh transistors of the odd-numbered stages are P-type transistors. It is possible that the second transistor, the fourth transistor, the seventh transistor, the tenth transistor, and the twelfth transistor of the odd-numbered stage are N-type transistors.

[0024] In one embodiment of the present invention, when the stage is an even-numbered stage, the even-numbered stage includes: a first transistor, including a control electrode to which the second clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node; a second transistor, including a control electrode to which the first clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node; a third transistor, including a control electrode connected to the first control node, a first electrode to which the first high power supply voltage is applied, and a second electrode connected to the carry output node; a fourth transistor, including a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the carry output node; a fifth transistor, including a control electrode connected to the second control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the first intermediate node; and a sixth transistor, including a control electrode connected to the carry output node and a first electrode connected to the first intermediate node. The transistor includes a second electrode connected to the third control node; a seventh transistor, including a control electrode connected to the carry output node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the third control node; an eighth transistor, including a control electrode connected to the third control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the second intermediate node; a ninth transistor, including a control electrode connected to the first control node, a first electrode connected to the second intermediate node, and a second electrode connected to the second control node; a tenth transistor, including a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the second control node; an eleventh transistor, including a control electrode connected to the third control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the output node; and a twelfth transistor, including a control electrode connected to the third control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the output node. It is possible that the first, third, fifth, sixth, eighth, ninth, and eleventh transistors of the even-numbered stages are P-type transistors. It is possible that the second transistor, the fourth transistor, the seventh transistor, the tenth transistor, and the twelfth transistor of the even-numbered stage are N-type transistors.

[0025] A display device according to an embodiment of the present invention for achieving the above-described object of the present invention includes a display panel, a gate driving unit, a data driving unit, and a transmission driving unit. The display panel includes pixels. The gate driving unit outputs a gate signal to the pixels. The data driving unit outputs a data voltage to the pixels. The transmission driving unit outputs a transmission signal to the pixels. The gate driving unit includes at least one stage. The stage of the gate driving unit includes: an input unit that, in response to a first clock signal and a second clock signal having a different phase from the first clock signal, transmits a carry signal to a first control node; a carry output unit that, in response to a signal from the first control node, generates a current carry signal based on a first high power supply voltage and a low power supply voltage; a level shifter that, in response to the current carry signal, generates a signal from a second control node and a signal from a third control node based on a second high power supply voltage greater than the first high power supply voltage and the low power supply voltage; and an output unit that, in response to the signal from the second control node or the signal from the third control node, generates an output signal based on the second high power supply voltage and the low power supply voltage.

[0026] A display device according to an embodiment of the present invention for achieving the above-described object of the present invention includes a display panel, a gate driving unit, a data driving unit, and a transmission driving unit. The display panel includes pixels. The gate driving unit outputs a gate signal to the pixels. The data driving unit outputs a data voltage to the pixels. The transmission driving unit outputs a transmission signal to the pixels. The transmission driving unit includes at least one stage. The stage of the transmission driving unit includes: an input unit that, in response to a first clock signal and a second clock signal having a different phase from the first clock signal, transmits a carry signal to a first control node; a carry output unit that, in response to a signal from the first control node, generates a current carry signal based on a first high power supply voltage and a low power supply voltage; a level converter that, in response to the current carry signal, generates a signal from a second control node and a signal from a third control node based on a second high power supply voltage greater than the first high power supply voltage and the low power supply voltage; and an output unit that, in response to the signal from the second control node or the signal from the third control node, generates an output signal based on the second high power supply voltage and the low power supply voltage.

[0027] An electronic device according to an embodiment of the present invention for achieving the above-described objectives includes a display panel, a gate driving unit, a data driving unit, a transmission driving unit, a drive control unit, and a processor. The display panel includes pixels. The gate driving unit outputs gate signals to the pixels. The data driving unit outputs data voltages to the pixels. The transmission driving unit outputs transmission signals to the pixels. The drive control unit controls the gate driving unit, the data driving unit, and the transmission driving unit. The processor outputs input image data and input control signals to the drive control unit. The gate driving unit and the transmission driving unit include at least one stage. The stage includes: an input unit that transmits a carry signal to a first control node in response to a first clock signal and a second clock signal having a different phase from the first clock signal; a carry output unit that generates a current carry signal based on a first high power supply voltage and a low power supply voltage in response to a signal from the first control node; a level converter that generates a signal from a second control node and a signal from a third control node based on a second high power supply voltage greater than the first high power supply voltage and the low power supply voltage in response to the current carry signal; and an output unit that generates an output signal based on the second high power supply voltage and the low power supply voltage in response to the signal from the second control node or the signal from the third control node.

[0028] It is possible that, according to such a driver, a display device including the driver, and an electronic device including the driver, the driver includes the level shifter, so that the clock signal and the carry signal oscillate between a first high power supply voltage and a low power supply voltage, and the output signal oscillates between a second high power supply voltage greater than the first high power supply voltage and the low power supply voltage.

[0029] The swing amplitude of the clock signal and the carry signal of the driver can be reduced, thereby reducing the power consumption of the display device. Attached Figure Description

[0030] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0031] Figure 2a It is shown Figure 1 Block diagram of the gate driving section.

[0032] Figure 2b It is shown Figure 1 Block diagram of the launch drive unit.

[0033] Figure 3 It is used for explanation Figure 2a as well as Figure 2b A timing diagram of an example of how the driver works.

[0034] Figure 4 It is shown Figure 2a as well as Figure 2b The circuit diagram of the odd-numbered stage of the driver.

[0035] Figure 5 It is shown Figure 2a as well as Figure 2b The circuit diagram of the even-numbered stage of the driver.

[0036] Figure 6 It is used for explanation Figure 4 as well as Figure 5 A timing diagram of an example of a task at the higher level.

[0037] Figure 7 It is used for explanation Figure 6 In the second period Figure 4 A circuit diagram of an example of the operation of the level.

[0038] Figure 8 It is used for explanation Figure 6 In the second period Figure 4 A timing diagram of an example of a task at the higher level.

[0039] Figure 9 It is used for explanation Figure 6 In the eighth period Figure 4 A circuit diagram of an example of the operation of the level.

[0040] Figure 10 It is used for explanation Figure 6 In the eighth period Figure 4 A timing diagram of an example of a task at the higher level.

[0041] Figure 11 It is used for explanation Figure 6 In the third period Figure 5 A circuit diagram of an example of the operation of the level.

[0042] Figure 12 It is used for explanation Figure 6 In the third period Figure 5 A timing diagram of an example of a task at the higher level.

[0043] Figure 13 It is used for explanation Figure 6 In the ninth period Figure 5 A circuit diagram of an example of the operation of the level.

[0044] Figure 14 It is used for explanation Figure 6 In the ninth period Figure 5 A timing diagram of an example of a task at the higher level.

[0045] Figure 15It is shown Figure 1 A circuit diagram of an example of the pixels of a display panel.

[0046] Figure 16 It is shown Figure 15 A timing diagram of an example of the input signal of a pixel.

[0047] Figure 17 This is a circuit diagram illustrating the odd-numbered stage of a driver for a display device according to an embodiment of the present invention.

[0048] Figure 18 This is a circuit diagram illustrating the odd-numbered stage of a driver for a display device according to an embodiment of the present invention.

[0049] Figure 19 This is a circuit diagram illustrating the odd-numbered stage of a driver for a display device according to an embodiment of the present invention.

[0050] Figure 20 This is a block diagram illustrating an electronic device according to an embodiment of the present invention.

[0051] Figure 21 It is shown Figure 20 The diagram shows an example of an electronic device implemented as a smartphone.

[0052] Figure 22 This is a block diagram illustrating an electronic device according to an embodiment of the present invention.

[0053] Figure 23 yes Figure 22 A schematic diagram of the electronic device.

[0054] (Explanation of reference numerals in the attached diagram)

[0055] 100: Display panel; 200: Drive control unit

[0056] 300: Gate driving section; 400: Gamma reference voltage generation section

[0057] 500: Data drive unit; 600: Transmission drive unit Detailed Implementation

[0058] The invention will now be described in more detail with reference to the accompanying drawings.

[0059] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0060] Reference Figure 1The display device includes a display panel 100 and a display panel driving unit. The display panel driving unit includes a driving control unit 200, a gate driving unit 300, a gamma reference voltage generating unit 400, a data driving unit 500, and a transmission driving unit 600.

[0061] The display panel 100 includes a display section for displaying images and a peripheral section disposed adjacent to the display section.

[0062] The display panel 100 includes a plurality of gate lines GWL, GCL, GIL, GBL, a plurality of data lines DL, a plurality of emitter lines EL, and a plurality of pixels electrically connected to each of the gate lines GWL, GCL, GIL, GBL, the data lines DL, and the emitter lines EL. The gate lines GWL, GCL, GIL, and GBL extend in a first direction D1, the data lines DL extend in a second direction D2 intersecting the first direction D1, and the emitter lines EL extend in the first direction D1.

[0063] The drive control unit 200 receives input image data IMG and input control signals CONT from external devices (e.g., processors, application processors, host computers, setup units). For example, the input image data IMG may include red image data, green image data, and blue image data. The input image data IMG may include white image data. The input image data IMG may include magenta image data, yellow image data, and cyan image data. The input control signal CONT may include a master clock signal and a data enable signal. The input control signal CONT may also include a vertical synchronization signal and a horizontal synchronization signal.

[0064] The drive control unit 200 generates a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, a fourth control signal CONT4, and a data signal DATA based on the input image data IMG and the input control signal CONT.

[0065] The drive control unit 200 generates a first control signal CONT1 for controlling the operation of the gate drive unit 300 based on the input control signal CONT, and outputs it to the gate drive unit 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0066] The drive control unit 200 generates a second control signal CONT2 to control the operation of the data drive unit 500 based on the input control signal CONT, and outputs it to the data drive unit 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0067] The drive control unit 200 generates the data signal DATA based on the input image data IMG. The drive control unit 200 outputs the data signal DATA to the data drive unit 500.

[0068] The drive control unit 200 generates a third control signal CONT3 to control the operation of the gamma reference voltage generation unit 400 based on the input control signal CONT, and outputs it to the gamma reference voltage generation unit 400.

[0069] The drive control unit 200 generates a fourth control signal CONT4 for controlling the operation of the transmitter drive unit 600 based on the input control signal CONT and outputs it to the transmitter drive unit 600.

[0070] The gate driving unit 300 generates gate signals for driving the gate lines GWL, GCL, GIL, and GBL in response to the first control signal CONT1 received from the driving control unit 200. The gate driving unit 300 can output the gate signals to the gate lines GWL, GCL, GIL, and GBL.

[0071] The gamma reference voltage generation unit 400 generates a gamma reference voltage VGREF in response to the third control signal CONT3 received from the drive control unit 200. The gamma reference voltage generation unit 400 provides the gamma reference voltage VGREF to the data drive unit 500. The gamma reference voltage VGREF has a value corresponding to each data signal DATA.

[0072] For example, the gamma reference voltage generation unit 400 may be configured within the drive control unit 200 or within the data drive unit 500.

[0073] The data driving unit 500 receives the second control signal CONT2 and the data signal DATA from the driving control unit 200, and receives the gamma reference voltage VGREF from the gamma reference voltage generation unit 400. The data driving unit 500 converts the data signal DATA into an analog data voltage using the gamma reference voltage VGREF. The data driving unit 500 outputs the data voltage to the data line DL.

[0074] The transmit drive unit 600 generates a transmit signal for driving the transmit line EL in response to the fourth control signal CONT4 received from the drive control unit 200. The transmit drive unit 600 can output the transmit signal to the transmit line EL.

[0075] For ease of explanation, Figure 1 The diagram shows the gate driving portion 300 disposed on a first side of the display panel 100 and the emission driving portion 600 disposed on a second side of the display panel 100, but the present invention is not limited thereto. For example, both the gate driving portion 300 and the emission driving portion 600 may be disposed on the first side of the display panel 100. For example, both the gate driving portion 300 and the emission driving portion 600 may be disposed on both sides of the display panel 100. For example, the gate driving portion 300 and the emission driving portion 600 may be integrally formed.

[0076] Figure 2a It is shown Figure 1 Block diagram of the gate driving section 300. Figure 2b It is shown Figure 1 Block diagram of the launch drive unit 600. Figure 3 It is used for explanation Figure 2a as well as Figure 2b A timing diagram of an example of how the driver works.

[0077] exist Figure 2a The example illustrates the case where the driver is a gate drive unit 300 that outputs the gate signal. Figure 2b The example shown illustrates a case where the driver is a transmit drive unit 600 that outputs the transmit signal. Thus, the driver circuit of the present invention can be used in either the gate drive unit 300 or the transmit drive unit 600.

[0078] Reference Figures 2a to 3 According to embodiments of the present invention, the driver may include multiple stages STG1, STG2, STG3, STG4, ... The driver may be implemented as a shift register that sequentially outputs carry signals CR1, CR2, CR3, STG4, ... and output signals OUT1, OUT2, OUT3, OUT4, ... through multiple stages STG1, STG2, STG3, STG4, ... . Furthermore, the driver is a driver included in a display device and may be formed on the display panel 100 of the display device (see reference 100). Figure 1 For example, the driver may be integrated or formed on the substrate of the display panel 100.

[0079] Multiple stages STG1, STG2, STG3, STG4, ... can sequentially output output signals OUT1, OUT2, OUT3, OUT4, ... based on a start signal FLM, a first clock signal CLK1, and a second clock signal CLK2 having a different phase from the first clock signal CLK1. Alternatively, the first stage STG1 can receive the start signal FLM as its input signal, and each subsequent stage STG2, STG3, STG4, ... can receive the carry signals CR1, CR2, CR3, ... of the previous stage as its input signal. For example, the second stage STG2 can receive the first carry signal CR1 of the first stage STG1 as its input signal, the third stage STG3 can receive the second carry signal CR2 of the second stage STG2 as its input signal, and the fourth stage STG4 can receive the third carry signal CR3 of the third stage STG3 as its input signal.

[0080] For example, the phase of the second clock signal CLK2 can be opposite to the phase of the first clock signal CLK1. Specifically, in the first time period P1, the third time period P3, the fifth time period P5, the seventh time period P7, the ninth time period P9, the eleventh time period P11, the thirteenth time period P13, the fifteenth time period P15, and the seventeenth time period P17, the first clock signal CLK1 is at a high level and the second clock signal CLK2 is at a low level. Alternatively, in the second time period P2, the fourth time period P4, the sixth time period P6, the eighth time period P8, the tenth time period P10, the twelfth time period P12, the fourteenth time period P14, the sixteenth time period P16, and the eighteenth time period P18, the second clock signal CLK2 is at a high level and the first clock signal CLK1 is at a low level.

[0081] In another embodiment, each odd-numbered STG1, STG3, ... may start outputting signals OUT1, OUT3, ... when the first clock signal CLK1 is low and the second clock signal CLK2 is high, and each even-numbered STG2, STG4, ... may start outputting signals OUT2, OUT4, ... when the second clock signal CLK2 is low and the first clock signal CLK1 is high.

[0082] For example, such as Figures 2a to 3 As shown, if the first clock signal CLK1 goes low after the start signal FLM goes high, then the first stage STG1 can start outputting a first output signal OUT1 with a high level. Conversely, if the first clock signal CLK1 goes low after the start signal FLM goes low, then the first stage STG1 can start outputting the first output signal OUT1 with a low level.

[0083] If the second clock signal CLK2 goes low after the first output signal OUT1 goes high (after the first carry signal CR1 goes low), then the second stage STG2 can start outputting a second output signal OUT2 with a high level. Alternatively, if the second clock signal CLK2 goes low after the first output signal OUT1 goes low (after the first carry signal CR1 goes high), then the second stage STG2 can start outputting a second output signal OUT2 with a low level.

[0084] If the first clock signal CLK1 becomes low after the second output signal OUT2 becomes high (after the second carry signal CR2 becomes high), then the third-stage STG3 can begin outputting the third output signal OUT3 with a high level. Conversely, if the first clock signal CLK1 becomes low after the second output signal OUT2 becomes low (after the second carry signal CR2 becomes low), then the third-stage STG3 can begin outputting the third output signal OUT3 with a low level.

[0085] In this way, multiple STG1, STG2, STG3, STG4, ... can sequentially output the output signals OUT1, OUT2, OUT3, OUT4, ... while delaying or shifting the output signals OUT1, OUT2, OUT3, OUT4, ... by half the period of the first clock signal CLK1.

[0086] In this embodiment, the first clock signal CLK1 and the second clock signal CLK2 can be applied to each of the aforementioned stages.

[0087] In this embodiment, when the level is the odd-numbered level STG1, STG3, ..., the phase of the current carry signal CR1, CR3, ... can be opposite to the phase of the output signal OUT1, OUT3, ... Conversely, when the level is the even-numbered level STG2, STG4, ..., the phase of the current carry signal CR2, CR4, ... can be the same as the phase of the output signal OUT2, OUT4, ...

[0088] Figure 4 It is shown Figure 2a as well as Figure 2b The circuit diagram of the odd-numbered stage of the driver. Figure 5 It is shown Figure 2a as well as Figure 2b The circuit diagram of the even-numbered stage of the driver. Figure 6 It is used for explanation Figure 4as well as Figure 5 A timing diagram of an example of a task at the higher level.

[0089] Reference Figure 4 The odd-numbered stage includes: an input unit that, in response to the first clock signal CLK1 and a second clock signal CLK2 having a different phase from the first clock signal CLK1, transmits a carry signal (e.g., CR[N-1]) or the start signal FLM to the first control node AO; a carry output unit that, in response to the signal from the first control node AO, generates a current carry signal (e.g., CR[N]) based on a first high power supply voltage SVGH and a low power supply voltage VGL; a level shifter that, in response to the current carry signal CR[N], generates a signal from the second control node QO and a signal from the third control node QBO based on a second high power supply voltage VGH greater than the first high power supply voltage SVGH and the low power supply voltage VGL; and an output unit that, in response to the signal from the second control node QO, generates an output signal (e.g., OUT[N]) based on the second high power supply voltage VGH and the low power supply voltage VGL.

[0090] Reference Figure 5 The even-numbered stage includes: an input section that, in response to the first clock signal CLK1 and the second clock signal CLK2, transmits a carry signal (e.g., CR[N]) to the first control node AE; a carry output section that, in response to the signal from the first control node AE, generates a current carry signal (e.g., CR[N+1]) based on the first high power supply voltage SVGH and the low power supply voltage VGL; a level shifter that, in response to the current carry signal CR[N+1], generates a signal from the second control node QE and a signal from the third control node QBE based on the second high power supply voltage VGH and the low power supply voltage VGL; and an output section that, in response to the signal from the third control node QBE, generates an output signal (e.g., OUT[N+1]) based on the second high power supply voltage VGH and the low power supply voltage VGL.

[0091] When the odd-numbered stage is the first stage, the input unit can receive the start signal FLM. When the odd-numbered stage is not the first stage (when it is the Nth stage), the input unit can receive the carry signal CR[N-1].

[0092] In this embodiment, the carry signal CR[N-1] is not limited to the carry signal of the previous stage of the current stage, but can refer to any carry signal in the previous stage of the current stage.

[0093] The input section of the even-numbered stage (when it is the N+1th stage) can receive the carry signal CR[N].

[0094] The following is a detailed description Figure 4 The configuration of the input section, the carry output section, the level converter, and the output section of the odd-numbered stage.

[0095] The input section of the odd-numbered stage may include: a first transistor TO1, including a control electrode to which the first clock signal CLK1 is applied, a first electrode to which the carry signal CR[N-1] is applied, and a second electrode connected to the first control node AO; and a second transistor TO2, including a control electrode to which the second clock signal CLK2 is applied, a first electrode to which the carry signal CR[N-1] is applied, and a second electrode connected to the first control node AO.

[0096] The carry output section of the odd-numbered stage may include: a third transistor TO3, including a control electrode connected to the first control node AO, a first electrode to which the first high power supply voltage SVGH is applied, and a second electrode connected to the carry output node; and a fourth transistor TO4, including a control electrode connected to the first control node AO, a first electrode to which the low power supply voltage VGL is applied, and a second electrode connected to the carry output node.

[0097] The carry output section of the odd-numbered stage may further include: a capacitor CHO, including a first electrode to which the first high power supply voltage SVGH is applied and a second electrode connected to the first control node AO.

[0098] When the first clock signal CLK1 and the second clock signal CLK2 are continuously oscillating, the carry signal (e.g., CR[N-1]) or the start signal FLM can be periodically applied to the first control node AO. When the display device operates in a power-saving mode, such as driving at a low frequency to reduce power consumption, the oscillation of the first clock signal CLK1 and the second clock signal CLK2 may be temporarily interrupted.

[0099] When the swing of the first clock signal CLK1 and the second clock signal CLK2 is temporarily interrupted, the signal of the first control node AO may be in a floating state, causing the high level of the signal of the first control node AO to change to a low level or the low level to a high level. If the high level of the signal of the first control node AO changes to a low level or the low level changes to a high level, the level of the output signal OUT[N] may change, and the reliability of the driver may be compromised.

[0100] The stage includes the capacitor CHO connected to the first control node AO, so that even if the swing of the first clock signal CLK1 and the second clock signal CLK2 is temporarily interrupted, the signal of the first control node AO can be stably maintained, thereby improving the reliability of the driver.

[0101] The level shifter of the odd-numbered stage may include: a fifth transistor TO5, including a control electrode connected to the second control node QO, a first electrode to which the second high power supply voltage VGH is applied, and a second electrode connected to the first intermediate node; a sixth transistor TO6, including a control electrode connected to the carry output node, a first electrode connected to the first intermediate node, and a second electrode connected to the third control node QBO; a seventh transistor TO7, including a control electrode connected to the carry output node, a first electrode to which the low power supply voltage VGL is applied, and a second electrode connected to the third control node QBO; an eighth transistor TO8, including a control electrode connected to the third control node QBO, a first electrode to which the second high power supply voltage VGH is applied, and a second electrode connected to the second intermediate node; a ninth transistor TO9, including a control electrode connected to the first control node AO, a first electrode connected to the second intermediate node, and a second electrode connected to the second control node QO; and a tenth transistor TO10, including a control electrode connected to the first control node AO, a first electrode to which the low power supply voltage VGL is applied, and a second electrode connected to the second control node QO.

[0102] The output section of the odd-numbered stage may include: an eleventh transistor TO11, including a control electrode connected to the second control node QO, a first electrode to which the second high power supply voltage VGH is applied, and a second electrode connected to the output node; and a twelfth transistor TO12, including a control electrode connected to the second control node QO, a first electrode to which the low power supply voltage VGL is applied, and a second electrode connected to the output node.

[0103] The first transistor TO1, the third transistor TO3, the fifth transistor TO5, the sixth transistor TO6, the eighth transistor TO8, the ninth transistor TO9, and the eleventh transistor TO11 in the odd-numbered stages can be P-type transistors. The second transistor TO2, the fourth transistor TO4, the seventh transistor TO7, the tenth transistor TO10, and the twelfth transistor TO12 in the odd-numbered stages can be N-type transistors.

[0104] In this embodiment, the odd-numbered stage and the even-numbered stage of the driver can have different structures.

[0105] For example, the first clock signal CLK1 may be applied to the control electrode of the first transistor TO1 in the odd-numbered stage, and the second clock signal CLK2 may be applied to the control electrode of the second transistor TO2 in the odd-numbered stage. Conversely, the second clock signal CLK2 may be applied to the control electrode of the first transistor TE1 in the even-numbered stage, and the first clock signal CLK1 may be applied to the control electrode of the second transistor TE2 in the even-numbered stage.

[0106] For example, the control electrodes of the eleventh transistor TO11 and the twelfth transistor TO12 in the odd-numbered stage can be connected to the second control node QO in the odd-numbered stage. Conversely, the control electrodes of the eleventh transistor TE11 and the twelfth transistor TE12 in the even-numbered stage can be connected to the third control node QBE in the even-numbered stage.

[0107] That is, the output section of the even-numbered stage may include: the eleventh transistor TE11, which includes a control electrode connected to the third control node QBE, a first electrode to which the second high power supply voltage VGH is applied, and a second electrode connected to the output node; and the twelfth transistor TE12, which includes a control electrode connected to the third control node QBE, a first electrode to which the low power supply voltage VGL is applied, and a second electrode connected to the output node.

[0108] The transistors TE3, TE4 and capacitor CHE of the carry output section of the even-numbered stages, as well as the transistors TE5, TE6, TE7, TE8, TE9, and TE10 of the level converter, may have substantially the same structure as the transistors TO3, TO4 and capacitor CHO of the carry output section of the odd-numbered stages, as well as the transistors TO5, TO6, TO7, TO8, TO9, and TO10 of the level converter.

[0109] The first transistor TE1, the third transistor TE3, the fifth transistor TE5, the sixth transistor TE6, the eighth transistor TE8, the ninth transistor TE9, and the eleventh transistor TE11 in the even-numbered stages can be P-type transistors. The second transistor TE2, the fourth transistor TE4, the seventh transistor TE7, the tenth transistor TE10, and the twelfth transistor TE12 in the even-numbered stages can be N-type transistors.

[0110] Reference Figures 1 to 6When the level is the odd-numbered level, the phase of the current carry signal CR[N] can be opposite to the phase of the output signal OUT[N]. When the level is the even-numbered level, the phase of the current carry signal CR[N+1] can be the same as the phase of the output signal OUT[N+1].

[0111] Furthermore, when the stage is an odd-numbered stage, the phase of the signal of the first control node AO can be the same as the phase of the output signal OUT[N]. When the stage is an even-numbered stage, the phase of the signal of the first control node AE ​​can be opposite to the phase of the output signal OUT[N+1].

[0112] Additionally, the high level of the start signal FLM, the carry signal (e.g., CR[N], CR[N+1]), the first clock signal CLK1, and the second clock signal CLK2 can be the first high power supply voltage SVGH. The low level of the start signal FLM, the carry signal (e.g., CR[N], CR[N+1]), the first clock signal CLK1, and the second clock signal CLK2 can be the low power supply voltage VGL. The high level of the output signals OUT[N] and OUT[N+1] can be the second high power supply voltage VGH. The low level of the output signals OUT[N] and OUT[N+1] can be the low power supply voltage VGL.

[0113] Additionally, the high level of the signals of the first control nodes AO and AE can be the first high power supply voltage SVGH. The low level of the signals of the first control nodes AO and AE can be the low power supply voltage VGL.

[0114] In one embodiment of the present invention, the high level of the signals of the second control nodes QO and QE and the signals of the third control nodes QBO and QBE can be the second high power supply voltage VGH. The low level of the signals of the second control nodes QO and QE and the signals of the third control nodes QBO and QBE can be the low power supply voltage VGL.

[0115] Figure 7 It is used for explanation Figure 6 In the second period P2 Figure 4 A circuit diagram of an example of the operation of the level. Figure 8 It is used for explanation Figure 6 In the second period P2 Figure 4 A timing diagram of an example of a task at the higher level. Figure 9 It is used for explanation Figure 6 The eighth period, P8 Figure 4 A circuit diagram of an example of the operation of the level. Figure 10 It is used for explanation Figure 6 The eighth period, P8 Figure 4 A timing diagram of an example of a task at the higher level.

[0116] Reference Figures 1 to 10 During the second time period P2, in response to the first clock signal CLK1 and the second clock signal CLK2, the first transistor TO1 and the second transistor TO2 are turned on, and the input signal (e.g., FLM or CR[N-1]) is transmitted to the first control node AO.

[0117] During the second time period P2, in response to the first high power supply voltage SVGH of the first control node AO, the fourth transistor TO4 is turned on to generate the current carry signal CR[N] with the low power supply voltage VGL.

[0118] Additionally, during the second time period P2, in response to the first high power supply voltage SVGH of the first control node AO, the tenth transistor TO10 is turned on, and the signal of the second control node QO has the low power supply voltage VGL.

[0119] During the second time period P2, the fifth transistor TO5 and the sixth transistor TO6 are turned on in response to the current carry signal CR[N] having the low power supply voltage VGL and the signal of the second control node QO having the low power supply voltage VGL, and the signal of the third control node QBO has the second high power supply voltage VGH.

[0120] During the second time period P2, in response to the signal of the second control node QO having the low power supply voltage VGL, the eleventh transistor TO11 is turned on, and the output signal OUT[N] having the second high power supply voltage VGH is output.

[0121] In the eighth time period P8, in response to the first clock signal CLK1 and the second clock signal CLK2, the first transistor TO1 and the second transistor TO2 are turned on, and the input signal (e.g., FLM or CR[N-1]) is transmitted to the first control node AO.

[0122] In the eighth time period P8, in response to the low power supply voltage VGL of the first control node AO, the third transistor TO3 is turned on to generate the current carry signal CR[N] having the first high power supply voltage SVGH.

[0123] Additionally, during the eighth time period P8, in response to the current carry signal CR[N] having the first high power supply voltage SVGH, the seventh transistor TO7 is turned on, and the signal of the third control node QBO has the low power supply voltage VGL.

[0124] In the eighth time period P8, the eighth transistor TO8 and the ninth transistor TO9 are turned on in response to the signal of the third control node QBO having the low power supply voltage VGL and the signal of the first control node AO having the low power supply voltage VGL, and the signal of the second control node QO has the second high power supply voltage VGH.

[0125] During the eighth time period P8, the twelfth transistor TO12 is turned on in response to the signal of the second control node QO having the second high power supply voltage VGH, and the output signal OUT[N] having the low power supply voltage VGL is output.

[0126] Figure 11 It is used for explanation Figure 6 In the third time period P3 Figure 5 A circuit diagram of an example of the operation of the level. Figure 12 It is used for explanation Figure 6 In the third time period P3 Figure 5 A timing diagram of an example of a task at the higher level. Figure 13 It is used for explanation Figure 6 In the ninth period P9 Figure 5 A circuit diagram of an example of the operation of the level. Figure 14 It is used for explanation Figure 6 In the ninth period P9 Figure 5 A timing diagram of an example of a task at the higher level.

[0127] Reference Figures 1 to 14 In the third time period P3, in response to the first clock signal CLK1 and the second clock signal CLK2, the first transistor TE1 and the second transistor TE2 are turned on, and the input signal (e.g., CR[N]) is transmitted to the first control node AE.

[0128] During the third time period P3, in response to the low power supply voltage VGL of the first control node AE, the third transistor TE3 is turned on to generate the current carry signal CR[N+1] having the first high power supply voltage SVGH.

[0129] Additionally, during the third time period P3, in response to the current carry signal CR[N+1] having the first high power supply voltage SVGH, the seventh transistor TE7 is turned on, and the third control node QBE has the low power supply voltage VGL.

[0130] During the third time period P3, the eighth transistor TE8 and the ninth transistor TE9 are turned on in response to the signal of the third control node QBE having the low power supply voltage VGL and the signal of the first control node AE ​​having the low power supply voltage VGL, and the signal of the second control node QE has the second high power supply voltage VGH.

[0131] During the third time period P3, the eleventh transistor TE11 is turned on in response to the signal of the third control node QBE having the low power supply voltage VGL, and the output signal OUT[N+1] having the second high power supply voltage VGH is output.

[0132] In the ninth time period P9, in response to the first clock signal CLK1 and the second clock signal CLK2, the first transistor TE1 and the second transistor TE2 are turned on, and the input signal (e.g., CR[N]) is transmitted to the first control node AE.

[0133] In the ninth period P9, in response to the first high power supply voltage SVGH of the first control node AE, the fourth transistor TE4 is turned on to generate the current carry signal CR[N+1] with the low power supply voltage VGL.

[0134] Additionally, during the ninth period P9, in response to the first high power supply voltage SVGH of the first control node AE, the tenth transistor TE10 is turned on, and the second control node QE has the low power supply voltage VGL.

[0135] In the ninth period P9, the fifth transistor TE5 and the sixth transistor TE6 are turned on in response to the current carry signal CR[N+1] having the low power supply voltage VGL and the signal of the second control node QE having the low power supply voltage VGL, and the third control node QBE has the second high power supply voltage VGH.

[0136] During the ninth period P9, the twelfth transistor TE12 is turned on in response to the signal of the third control node QBE having the second high power supply voltage VGH, and outputs the output signal OUT[N+1] having the low power supply voltage VGL.

[0137] Figure 15 It is shown Figure 1 A circuit diagram of an example of a display panel with 100 pixels. Figure 16 It is shown Figure 15 A timing diagram of an example of the input signal of a pixel.

[0138] Reference Figures 1 to 16 The display panel 100 includes a plurality of pixels, and each pixel includes a light-emitting element EE.

[0139] The pixel receives a write gate signal GW, a compensation gate signal GC, a data initialization gate signal GI, a light-emitting element initialization gate signal GB, a data voltage VDATA, and a transmit signal EM. The light-emitting element EE is made to emit light according to the level of the data voltage VDATA to display the image.

[0140] In this embodiment, the pixel may include a first type of switching element and a second type of switching element different from the first type. For example, the first type of switching element may be a P-type transistor, and the second type of switching element may be an N-type transistor.

[0141] For example, the switching element of the first type can be a polycrystalline silicon thin-film transistor. For example, the switching element of the first type can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor. For example, the switching element of the second type can be an oxide semiconductor thin-film transistor.

[0142] In contrast, the pixel may also include only P-type transistors or only N-type transistors.

[0143] At least one of the pixels may include first to seventh pixel switching elements PT1 to PT7, storage capacitor CST, and light-emitting element EE.

[0144] The first pixel switching element PT1 includes a control electrode connected to the first pixel node PN1, a first electrode connected to the second pixel node PN2, and a second electrode connected to the third pixel node PN3.

[0145] The second pixel switching element PT2 includes a control electrode to which the write gate signal GW is applied, a first electrode to which the data voltage VDATA is applied, and a second electrode connected to the second pixel node PN2.

[0146] The third pixel switching element PT3 includes a control electrode to which the compensation gate signal GC is applied, a first electrode connected to the first pixel node PN1, and a second electrode connected to the third pixel node PN3.

[0147] The fourth pixel switching element PT4 includes a control electrode to which the data initialization gate signal GI is applied, a first electrode to which the initialization voltage VINT is applied, and a second electrode connected to the first pixel node PN1.

[0148] The fifth pixel switching element PT5 includes a control electrode to which the emission signal EM is applied, a first electrode to which the pixel high power supply voltage ELVDD is applied, and a second electrode connected to the second pixel node PN2.

[0149] The sixth pixel switching element PT6 includes a control electrode to which the emission signal EM is applied, a first electrode connected to the third pixel node PN3, and a second electrode connected to the anode electrode of the light-emitting element EE.

[0150] The seventh pixel switching element PT7 includes a control electrode to which the light-emitting element initialization gate signal GB is applied, a first electrode to which the initialization voltage VINT is applied, and a second electrode connected to the anode electrode of the light-emitting element EE.

[0151] The storage capacitor CST includes a first electrode to which the pixel high power supply voltage ELVDD is applied and a second electrode connected to the first pixel node PN1.

[0152] The light-emitting element EE includes the anode electrode and the cathode electrode to which a pixel low power supply voltage ELVSS is applied.

[0153] In this embodiment, the third pixel switching element PT3 and the fourth pixel switching element PT4 can be N-type transistors. The first pixel switching element PT1, the second pixel switching element PT2, the fifth pixel switching element PT5, the sixth pixel switching element PT6, and the seventh pixel switching element PT7 can be P-type transistors.

[0154] observe Figure 16 During the first pixel driving period DU1, the first pixel node PN1 and the storage capacitor CST are initialized by the data initialization gate signal GI. During the second pixel driving period DU2, the threshold voltage (|VTH|) of the first pixel switching element PT1 is compensated by the write gate signal GW and the compensation gate signal GC, and the data voltage VDATA compensated by the threshold voltage (|VTH|) is written to the first pixel node PN1. During the third pixel driving period DU3, the anode electrode of the light-emitting element EE is initialized by the light-emitting element initialization gate signal GB. During the fourth pixel driving period DU4, the light-emitting element EE emits light by the emission signal EM, thereby displaying an image on the display panel 100.

[0155] In this embodiment, the cutoff period of the transmitted signal EM is illustrated as the first to third pixel driving periods DU1, DU2, and DU3, but the present invention is not limited thereto. As long as the cutoff period of the transmitted signal EM includes the data writing pixel driving period, i.e., the second pixel driving period DU2, the cutoff period of the transmitted signal EM can be longer than the first to third pixel driving periods DU1, DU2, and DU3.

[0156] During the first pixel driving period DU1, the data initialization gate signal GI may have an active level. For example, the active level of the data initialization gate signal GI may be a high level. When the data initialization gate signal GI has the active level, the fourth pixel switching element PT4 is turned on, and the initialization voltage VINT may be applied to the first pixel node PN1.

[0157] During the second pixel driving period DU2, the write gate signal GW and the compensation gate signal GC may have an activation level. For example, the activation level of the write gate signal GW may be low, and the activation level of the compensation gate signal GC may be high. When the write gate signal GW and the compensation gate signal GC have the activation level, the second pixel switching element PT2 and the third pixel switching element PT3 are turned on. In addition, the first pixel switching element PT1 is also turned on by the initialization voltage VINT.

[0158] Based on the path formed by the first to third pixel switching elements PT1, PT2, and PT3, a voltage is set at the first pixel node PN1 by subtracting the absolute value (|VTH|) of the threshold voltage of the first pixel switching element PT1 from the data voltage VDATA.

[0159] During the third pixel driving period DU3, the light-emitting element initialization gate signal GB may have an active level. For example, the active level of the light-emitting element initialization gate signal GB may be a low level. When the light-emitting element initialization gate signal GB has the active level, the seventh pixel switching element PT7 is turned on, and the initialization voltage VINT may be applied to the anode electrode of the light-emitting element EE.

[0160] In this embodiment, the initialization voltage applied to the fourth pixel switching element PT4 and the initialization voltage applied to the seventh pixel switching element PT7 are illustrated, but the invention is not limited thereto. According to the embodiment, the initialization voltage applied to the fourth pixel switching element PT4 and the initialization voltage applied to the seventh pixel switching element PT7 may be different from each other.

[0161] During the fourth pixel driving period DU4, the transmit signal EM may have an activation level. For example, the activation level of the transmit signal EM may be a low level. When the transmit signal EM has the activation level, the fifth pixel switching element PT5 and the sixth pixel switching element PT6 are turned on. In addition, the first pixel switching element PT1 is also turned on by the data voltage VDATA.

[0162] The driving current can flow in the order of the fifth pixel switching element PT5, the first pixel switching element PT1, and the sixth pixel switching element PT6 to drive the light-emitting element EE. The intensity of the driving current can be determined by the level of the data voltage VDATA. The brightness of the light-emitting element EE can be determined by the intensity of the driving current.

[0163] exist Figure 16 [N] refers to the signal of the current stage. Figure 15 as well as Figure 16 The signals from the preceding or following stages are not applied to the pixels, so omitting [N] is acceptable.

[0164] For example, Figure 4 as well as Figure 5 The output signals OUT[N] and OUT[N+1] of the stage circuit can be the compensation gate signal GC applied to the third pixel switching element PT3.

[0165] For example, Figure 4 as well as Figure 5 The output signals OUT[N] and OUT[N+1] of the stage circuit can be the data initialization gate signal GI applied to the fourth pixel switching element PT4.

[0166] For example, Figure 4 as well as Figure 5 The output signals OUT[N] and OUT[N+1] of the stage circuit can be the light-emitting element initialization gate signal GB applied to the seventh pixel switching element PT7.

[0167] For example, Figure 4 as well as Figure 5 The output signals OUT[N] and OUT[N+1] of the stage circuit can be the transmission signals EM applied to the fifth pixel switching element PT5 and the sixth pixel switching element PT6.

[0168] According to this embodiment, the driver includes the level converter. Therefore, the clock signals CLK1, CLK2 and the carry signals CR[N-1], CR[N], CR[N+1] may oscillate between the first high power supply voltage SVGH and the low power supply voltage VGL, and the output signals OUT[N], OUT[N+1] may oscillate between the second high power supply voltage VGH, which is greater than the first high power supply voltage SVGH, and the low power supply voltage VGL.

[0169] The swing amplitude of the clock signals CLK1, CLK2 and the carry signals CR[N-1], CR[N], CR[N+1] of the driver can be reduced, thereby reducing the power consumption of the display device.

[0170] Figure 17 This is a circuit diagram illustrating the odd-numbered stage of a driver for a display device according to an embodiment of the present invention.

[0171] Figure 17 If, in addition to applying a second high power supply voltage VGH to the first electrode of the capacitor CHO in the carry output section, the stage circuit is connected to... Figure 4 The stage circuits are the same, so repeated descriptions are omitted.

[0172] Reference Figures 1 to 3 , Figure 6 as well as Figure 17 The carry output section of the odd-numbered stage may include: a third transistor TO3, including a control electrode connected to the first control node AO, a first electrode to which the first high power supply voltage SVGH is applied, and a second electrode connected to the carry output node; and a fourth transistor TO4, including a control electrode connected to the first control node AO, a first electrode to which the low power supply voltage VGL is applied, and a second electrode connected to the carry output node.

[0173] In this embodiment, the carry output section of the odd-numbered stage may further include: a capacitor CHO, including a first electrode to which the second high power supply voltage VGH is applied and a second electrode connected to the first control node AO.

[0174] Although not shown, the carry output of the even-numbered stage may have the same structure as the carry output of the odd-numbered stage.

[0175] According to this embodiment, the driver includes the level converter. Therefore, the clock signals CLK1, CLK2 and the carry signals CR[N-1], CR[N], CR[N+1] may oscillate between the first high power supply voltage SVGH and the low power supply voltage VGL, and the output signals OUT[N], OUT[N+1] may oscillate between the second high power supply voltage VGH, which is greater than the first high power supply voltage SVGH, and the low power supply voltage VGL.

[0176] The swing amplitude of the clock signals CLK1, CLK2 and the carry signals CR[N-1], CR[N], CR[N+1] of the driver can be reduced, thereby reducing the power consumption of the display device.

[0177] Figure 18 This is a circuit diagram illustrating the odd-numbered stage of a driver for a display device according to an embodiment of the present invention.

[0178] Figure 18 If, in addition to applying a low power supply voltage VGL to the first electrode of the capacitor CHO in the carry output section, the stage circuit is connected to... Figure 4 The stage circuits are the same, so repeated descriptions are omitted.

[0179] Reference Figures 1 to 3 , Figure 6 as well as Figure 18 The carry output section of the odd-numbered stage may include: a third transistor TO3, including a control electrode connected to the first control node AO, a first electrode to which the first high power supply voltage SVGH is applied, and a second electrode connected to the carry output node; and a fourth transistor TO4, including a control electrode connected to the first control node AO, a first electrode to which the low power supply voltage VGL is applied, and a second electrode connected to the carry output node.

[0180] In this embodiment, the carry output section of the odd-numbered stage may further include: a capacitor CHO, including a first electrode to which the low power supply voltage VGL is applied and a second electrode connected to the first control node AO.

[0181] Although not shown, the carry output of the even-numbered stage may have the same structure as the carry output of the odd-numbered stage.

[0182] According to this embodiment, the driver includes the level converter. Therefore, the clock signals CLK1, CLK2 and the carry signals CR[N-1], CR[N], CR[N+1] may oscillate between the first high power supply voltage SVGH and the low power supply voltage VGL, and the output signals OUT[N], OUT[N+1] may oscillate between the second high power supply voltage VGH, which is greater than the first high power supply voltage SVGH, and the low power supply voltage VGL.

[0183] The swing amplitude of the clock signals CLK1, CLK2 and the carry signals CR[N-1], CR[N], CR[N+1] of the driver can be reduced, thereby reducing the power consumption of the display device.

[0184] Figure 19 This is a circuit diagram illustrating the odd-numbered stage of a driver for a display device according to an embodiment of the present invention.

[0185] Figure 19 If the stage circuit does not include the capacitor CHO (refer to the carry output section) Figure 4 In addition to, Figure 4 The stage circuits are the same, so repeated descriptions are omitted.

[0186] Reference Figures 1 to 3 , Figure 6 as well as Figure 19 The carry output section of the odd-numbered stage may include: a third transistor TO3, including a control electrode connected to the first control node AO, a first electrode to which the first high power supply voltage SVGH is applied, and a second electrode connected to the carry output node; and a fourth transistor TO4, including a control electrode connected to the first control node AO, a first electrode to which the low power supply voltage VGL is applied, and a second electrode connected to the carry output node.

[0187] In this embodiment, the carry output section of the odd-numbered stage may not include the capacitor connected to the first control node AO.

[0188] Although not shown, the carry output of the even-numbered stage may have the same structure as the carry output of the odd-numbered stage.

[0189] According to this embodiment, the driver includes the level converter. Therefore, the clock signals CLK1, CLK2 and the carry signals CR[N-1], CR[N], CR[N+1] may oscillate between the first high power supply voltage SVGH and the low power supply voltage VGL, and the output signals OUT[N], OUT[N+1] may oscillate between the second high power supply voltage VGH, which is greater than the first high power supply voltage SVGH, and the low power supply voltage VGL.

[0190] The swing amplitude of the clock signals CLK1, CLK2 and the carry signals CR[N-1], CR[N], CR[N+1] of the driver can be reduced, thereby reducing the power consumption of the display device.

[0191] Figure 20 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the present invention. Figure 21 It is shown Figure 20 The diagram shows an example of an electronic device 1000 implemented as a smartphone.

[0192] Reference Figures 1 to 21 The electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be... Figure 1 The display device. Additionally, the electronic device 1000 may also include various ports that can communicate with video cards, sound cards, memory cards, USB devices, etc., or with other systems.

[0193] According to one embodiment, such as Figure 21 As shown, the electronic device 1000 can be implemented as a smartphone. However, it is exemplary, and the electronic device 1000 is not limited thereto. For example, the electronic device 1000 can be implemented as a mobile phone, video phone, smart tablet, smartwatch, tablet PC, vehicle navigation system, computer monitor, laptop computer, head-mounted display device, etc.

[0194] Processor 1010 can perform specific calculations or tasks. According to embodiments, processor 1010 can be a microprocessor, a central processing unit, an application processor, etc. Processor 1010 can be connected to other components via an address bus, a control bus, and a data bus. According to embodiments, processor 1010 can also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus.

[0195] The processor 1010 can send to Figure 1 The drive control unit 200 outputs the input image data IMG and the input control signal CONT.

[0196] The memory device 1020 can store the data required for the operation of the electronic device 1000. For example, memory device 1020 may include non-volatile memory devices such as erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory device, phase-change random access memory (PRAM), resistive random access memory (RRAM), nano-floating gate memory (NFGM), polymer random access memory (PoRAM), magnetic random access memory (MRAM), and ferroelectric random access memory (FRAM), and / or dynamic random access memory (DRAM) devices, static random access memory (SRAM), etc. Volatile memory devices such as Access Memory (SRAM) devices and mobile DRAM devices.

[0197] Storage device 1030 may include a solid-state drive (SSD), a hard disk drive (HDD), a read-only optical disc drive (CD-ROM), etc. Input / output device 1040 may include input components such as a keyboard, numeric keypad, touchpad, touch screen, and mouse, and output components such as a speaker and printer. According to an embodiment, display device 1060 may also be included in input / output device 1040. Power supply 1050 can supply the power required for the operation of electronic device 1000. Display device 1060 can be connected to other components via the bus or other communication links.

[0198] Figure 22 This is a block diagram illustrating an electronic device according to an embodiment of the present invention. Figure 23 yes Figure 22 A schematic diagram of the electronic device.

[0199] Reference Figure 22 According to one embodiment, the electronic device 10 may include a display module 11, a processor 12, a memory 13, and a power module 14.

[0200] The display device according to an embodiment of the present invention can be applied to various electronic devices 10.

[0201] In one embodiment, the electronic device 10 may include Figure 1 The display device. That is, the operation of the display device included in the electronic device 10 can be compared with the reference. Figures 1 to 19 The operation of the display device described herein is the same. In addition to the display device, the electronic device 10 may also include modules or devices with other additional functions.

[0202] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0203] In one embodiment, the processor 12 may direct input to components including... Figure 1 The drive control unit 200 in the display device provides Figure 1 The input control signal CONT and Figure 1 The input image data IMG.

[0204] In one embodiment, the processor 12 may be provided in two or more parts, either functionally or structurally. For example, the processor 12 may include a main processor in the form of a first driver chip containing a central processing unit and an auxiliary processor in the form of a second driver chip containing a controller that receives image signals from the main processor and processes the image signals in a manner matching the interface specifications of the display module 11. For example, the auxiliary processor may include components containing... Figure 1 The drive control unit 200 in the display device. Therefore, the main processor can provide the auxiliary processor with... Figure 1 The input control signal CONT and Figure 1 The input image data IMG. The auxiliary processor can process the image signal based on the input control signal CONT and the input image data IMG.

[0205] The memory 13 may include at least one of non-volatile memory and volatile memory. The memory 13 may store data information required for the operation of the processor 12 or the display module 11. For example, if the processor 12 runs an application program stored in the memory 13, the input control signal CONT and / or the input image data IMG are transmitted to the display module 11, and the display module 11 processes the received input control signal CONT and / or the input image data IMG to output image information through the display screen.

[0206] The power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 10.

[0207] At least one of the components of the electronic device 10 may be included within the display device according to an embodiment of the present invention. Alternatively, a portion of a separate module functionally included in one module may be included within the display device, while another portion may be provided separately from the display device. For example, the display device may include the display module 11, while the processor 12, the memory 13, and the power module 14 may be provided as other devices within the electronic device 10, rather than the display device.

[0208] Reference Figure 23 The various electronic devices applicable to the display device according to this embodiment may include not only image display electronic devices such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, TVs 10_1d, and desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b, and smartwatches 10_2c; and vehicle electronic devices 10_3 including display modules, such as car dashboards, central dashboards, CIDs (Center Information Displays) configured in instrument panels, and room mirror displays. Electronic device 10 is not limited to image display electronic devices, wearable electronic devices, and vehicle electronic devices 10_3.

[0209] According to the driver, display device, and electronic device described above based on the invention, the power consumption of the display device can be reduced.

[0210] While the invention has been described above with reference to embodiments, those skilled in the art will understand that the invention can be modified and altered in various ways without departing from the concept and scope of the invention as set forth in the appended claims.

Claims

1. A driver, characterized in that, Including levels, The level includes: The input unit, in response to a first clock signal and a second clock signal having a different phase from the first clock signal, transmits a carry signal to the first control node; The carry output unit, in response to the signal from the first control node, generates the current carry signal based on the first high power supply voltage and the low power supply voltage; A level shifter, in response to the current carry signal, generates signals for a second control node and a third control node based on a second high power supply voltage greater than the first high power supply voltage and the low power supply voltage; and The output unit generates an output signal based on the second high power supply voltage and the low power supply voltage in response to the signal from the second control node or the signal from the third control node.

2. The driver according to claim 1, characterized in that, When the stage is an odd-numbered stage, the output unit generates the output signal in response to the signal from the second control node. When the stage is an even-numbered stage, the output unit generates the output signal in response to the signal from the third control node.

3. The driver according to claim 2, characterized in that, When the level is the odd-numbered level, the phase of the current carry signal is opposite to the phase of the output signal. When the level is the even-numbered level, the phase of the current carry signal is the same as the phase of the output signal.

4. The driver according to claim 2, characterized in that, When the level is an odd-numbered level, the phase of the signal of the first control node is the same as the phase of the output signal. When the level is the even-numbered level, the phase of the signal of the first control node is opposite to the phase of the output signal.

5. The driver according to claim 1, characterized in that, The high level of the carry signal, the current carry signal, the first clock signal, and the second clock signal is the first high power supply voltage, and the low level of the carry signal, the current carry signal, the first clock signal, and the second clock signal is the low power supply voltage. The high level of the output signal is the second high power supply voltage, and the low level of the output signal is the low power supply voltage.

6. The driver according to claim 5, characterized in that, The high level of the signal of the first control node is the first high power supply voltage, and the low level of the signal of the first control node is the low power supply voltage.

7. The driver according to claim 5, characterized in that, The high level of the signal of the second control node and the high level of the signal of the third control node are the second high power supply voltage, and the low level of the signal of the second control node and the low level of the signal of the third control node are the low power supply voltage.

8. The driver according to claim 1, characterized in that, The input section includes: The first transistor includes a control electrode to which the first clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node; and The second transistor includes a control electrode to which the second clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node.

9. The driver according to claim 1, characterized in that, The carry-out unit includes: The third transistor includes a control electrode connected to the first control node, a first electrode to which the first high power supply voltage is applied, and a second electrode connected to the carry output node; and The fourth transistor includes a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the carry output node.

10. The driver according to claim 9, characterized in that, The carry-out output unit also includes: The capacitor includes a first electrode to which the first high power supply voltage is applied and a second electrode connected to the first control node.

11. The driver according to claim 9, characterized in that, The carry-out output unit also includes: The capacitor includes a first electrode to which the second high power supply voltage is applied and a second electrode connected to the first control node.

12. The driver according to claim 9, characterized in that, The carry-out output unit also includes: The capacitor includes a first electrode to which the low power supply voltage is applied and a second electrode connected to the first control node.

13. The driver according to claim 1, characterized in that, The level converter includes: The fifth transistor includes a control electrode connected to the second control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the first intermediate node; The sixth transistor includes a control electrode connected to the carry output node, a first electrode connected to the first intermediate node, and a second electrode connected to the third control node; The seventh transistor includes a control electrode connected to the carry output node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the third control node; The eighth transistor includes a control electrode connected to the third control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the second intermediate node; The ninth transistor includes a control electrode connected to the first control node, a first electrode connected to the second intermediate node, and a second electrode connected to the second control node; and The tenth transistor includes a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the second control node.

14. The driver according to claim 13, characterized in that, The output section includes: The eleventh transistor includes a control electrode connected to the second control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the output node; and The twelfth transistor includes a control electrode connected to the second control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the output node.

15. The driver according to claim 13, characterized in that, The output section includes: The eleventh transistor includes a control electrode connected to the third control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the output node; and The twelfth transistor includes a control electrode connected to the third control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the output node.

16. The driver according to claim 1, characterized in that, When the level is the odd-numbered level The odd-numbered level includes: The first transistor includes a control electrode to which the first clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node; The second transistor includes a control electrode to which the second clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node; The third transistor includes a control electrode connected to the first control node, a first electrode to which the first high power supply voltage is applied, and a second electrode connected to the carry output node. The fourth transistor includes a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the carry output node; The fifth transistor includes a control electrode connected to the second control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the first intermediate node; The sixth transistor includes a control electrode connected to the carry output node, a first electrode connected to the first intermediate node, and a second electrode connected to the third control node; The seventh transistor includes a control electrode connected to the carry output node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the third control node; The eighth transistor includes a control electrode connected to the third control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the second intermediate node; The ninth transistor includes a control electrode connected to the first control node, a first electrode connected to the second intermediate node, and a second electrode connected to the second control node; The tenth transistor includes a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the second control node; The eleventh transistor includes a control electrode connected to the second control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the output node; and The twelfth transistor includes a control electrode connected to the second control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the output node. The first, third, fifth, sixth, eighth, ninth, and eleventh transistors of the odd-numbered stages are P-type transistors. The second transistor, the fourth transistor, the seventh transistor, the tenth transistor, and the twelfth transistor of the odd-numbered stage are N-type transistors.

17. The driver according to claim 16, characterized in that, When the level is the even-numbered level The even-numbered level includes: The first transistor includes a control electrode to which the second clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node; The second transistor includes a control electrode to which the first clock signal is applied, a first electrode to which the carry signal is applied, and a second electrode connected to the first control node; The third transistor includes a control electrode connected to the first control node, a first electrode to which the first high power supply voltage is applied, and a second electrode connected to the carry output node. The fourth transistor includes a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the carry output node; The fifth transistor includes a control electrode connected to the second control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the first intermediate node; The sixth transistor includes a control electrode connected to the carry output node, a first electrode connected to the first intermediate node, and a second electrode connected to the third control node; The seventh transistor includes a control electrode connected to the carry output node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the third control node; The eighth transistor includes a control electrode connected to the third control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the second intermediate node; The ninth transistor includes a control electrode connected to the first control node, a first electrode connected to the second intermediate node, and a second electrode connected to the second control node; The tenth transistor includes a control electrode connected to the first control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the second control node; The eleventh transistor includes a control electrode connected to the third control node, a first electrode to which the second high power supply voltage is applied, and a second electrode connected to the output node; and The twelfth transistor includes a control electrode connected to the third control node, a first electrode to which the low power supply voltage is applied, and a second electrode connected to the output node. The first, third, fifth, sixth, eighth, ninth, and eleventh transistors of the even-numbered stages are P-type transistors. The second transistor, the fourth transistor, the seventh transistor, the tenth transistor, and the twelfth transistor of the even-numbered stage are N-type transistors.

18. A display device, characterized in that, include: Display panel, including pixels; The gate driving section outputs a gate signal to the pixel; The data driving unit outputs data voltage to the pixel; as well as The transmitting drive unit outputs a transmitting signal to the pixel. The gate driving section and the emitter driving section include at least one stage. The stage of the gate driving section or the stage of the emitter driving section includes: The input unit, in response to a first clock signal and a second clock signal having a different phase from the first clock signal, transmits a carry signal to the first control node; The carry output unit, in response to the signal from the first control node, generates the current carry signal based on the first high power supply voltage and the low power supply voltage; A level shifter, in response to the current carry signal, generates signals for a second control node and a third control node based on a second high power supply voltage greater than the first high power supply voltage and the low power supply voltage; and The output unit generates an output signal based on the second high power supply voltage and the low power supply voltage in response to the signal from the second control node or the signal from the third control node.

19. An electronic device, characterized in that, include: Display panel, including pixels; The gate driving section outputs a gate signal to the pixel; The data driving unit outputs data voltage to the pixel; The transmitting drive unit outputs a transmitting signal to the pixel; A drive control unit controls the gate drive unit, the data drive unit, and the transmit drive unit; as well as The processor outputs input image data and input control signals to the drive control unit. The gate driving section and the emitter driving section include at least one stage. The level includes: The input unit, in response to a first clock signal and a second clock signal having a different phase from the first clock signal, transmits a carry signal to the first control node; The carry output unit, in response to the signal from the first control node, generates the current carry signal based on the first high power supply voltage and the low power supply voltage; A level shifter, in response to the current carry signal, generates signals for a second control node and a third control node based on a second high power supply voltage greater than the first high power supply voltage and the low power supply voltage; and The output unit generates an output signal based on the second high power supply voltage and the low power supply voltage in response to the signal from the second control node or the signal from the third control node.

Images