A wake-up system pre-charge circuit and a method of operation thereof

Abstract

This invention discloses a pre-charging circuit and its operating method for a wake-up system, relating to the field of backup power wake-up for low-power electronic devices. The output of a wake-up trigger module is electrically connected to the enable pin of a boost converter chip to control the start and stop of the boost converter chip. The output of the boost converter chip is connected to the source of a PMOS transistor. The drain of the PMOS transistor is connected to the positive terminal of a capacitive load and the system power supply terminal of the system to be powered, respectively, and the negative terminal of the capacitive load is grounded. A current-limiting pre-charging module is connected in parallel between the source and drain of the PMOS transistor to pre-charge the capacitive load with current limiting before the PMOS transistor is turned on. A passive voltage divider drive module is also connected to the source of the PMOS transistor. The other end of the passive voltage divider drive module is grounded, and the voltage divider output of the passive voltage divider drive module is connected to the gate of the PMOS transistor to drive the PMOS transistor to self-adaptively turn on through changes in the output voltage of the boost converter chip. This design offers the advantage of high wake-up stability.

Description

Technical Field

[0001] This invention relates to the field of backup power wake-up for low-power electronic devices, specifically a pre-charging circuit for a wake-up system and its operating method. Background Technology

[0002] In existing wake-up systems, after a button press triggers the backup boost chip, the complex gate control logic of the PMOS transistor often causes a short circuit in the downstream capacitive load during the moment of conduction, generating a large instantaneous current that triggers the overcurrent protection of the boost chip. To address this, some solutions (such as CN100527576C) use two MOS transistors. First, the MOSFET with higher on-resistance (Q1) is turned on, and after a specified time, the MOSFET with lower on-resistance (Q2) is turned on, thus suppressing the inrush current when power is switched on and ensuring the stability of the system wake-up. Other solutions use an additional control chip to adjust the PMOS turn-on timing, increasing circuit complexity and cost. Summary of the Invention

[0003] This invention provides a pre-charging circuit for a wake-up system that balances wake-up efficiency and stability, and is adapted to the battery life requirements of low-power devices.

[0004] The present invention provides the following technical solution: a pre-charging circuit for a wake-up system, wherein the output terminal of the wake-up trigger module is electrically connected to the enable pin of the boost chip, for controlling the start and stop of the boost chip;

[0005] The output terminal of the boost chip is connected to the source of the PMOS transistor;

[0006] The drain of the PMOS transistor is connected to the positive terminal of the capacitive load and the system power supply terminal of the system to be powered, respectively, and the negative terminal of the capacitive load is grounded.

[0007] A current-limiting pre-charge module is connected in parallel between the source and drain of the PMOS transistor to limit the current of the capacitive load before the PMOS transistor is turned on, thereby suppressing the instantaneous inrush current during startup.

[0008] The source of the PMOS transistor is also connected to a passive voltage divider drive module. The other end of the passive voltage divider drive module is grounded, and the voltage divider output terminal of the passive voltage divider drive module is connected to the gate of the PMOS transistor. This module is used to drive the PMOS transistor to self-adaptively turn on by changing the output voltage of the boost chip.

[0009] As a further improvement of the present invention, the passive voltage divider drive module is composed of a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series. The first end of the first voltage divider resistor R1 is electrically connected to the source of the PMOS transistor, the second end of the first voltage divider resistor R1 is electrically connected to the first end of the second voltage divider resistor R2 and the gate of the PMOS transistor, respectively, and the second end of the second voltage divider resistor R2 is grounded.

[0010] As a further improvement of the present invention, the first end of the wake-up trigger module is electrically connected to the positive terminal of the backup power supply, and the second end of the wake-up trigger module is electrically connected to the enable pin of the boost chip; the input pin of the boost chip is electrically connected to the positive terminal of the backup power supply, and the ground pin is grounded with the system ground.

[0011] As a further improvement of the present invention, a diode D is connected between the output terminal of the boost chip and the source of the PMOS transistor. The positive terminal of the diode D is connected to the output terminal of the boost chip, and the negative terminal of the diode D is connected to the source of the PMOS transistor.

[0012] As a further improvement of the present invention, the capacitive load is one or both of electrolytic capacitors and ceramic capacitors, with a total capacitance range of 100μF to 2000μF.

[0013] As a further improvement of the present invention, the current limiting pre-charge module is a pre-charge resistor R3. When the PMOS transistor is saturated and turned on, the current shunting ratio of the pre-charge resistor R3 is less than 0.2%.

[0014] A method for operating a wake-up system pre-charge circuit, applicable to the aforementioned wake-up system pre-charge circuit, includes the following steps:

[0015] When the wake-up trigger module is triggered, it outputs a high-level enable signal to the enable terminal of the boost chip, and the boost chip starts to work, with its output voltage rising steadily from 0V.

[0016] When the output voltage of the boost chip rises to 80% of the set output value, the instantaneous inrush current is suppressed by the current limiting pre-charge module connected in parallel between the source and drain of the PMOS transistor until the voltage difference between the voltage across the capacitive load and the output voltage of the boost chip is reduced to within the preset threshold.

[0017] As the output voltage of the boost chip increases, the absolute value of the gate-source voltage of the PMOS transistor reaches and exceeds its conduction threshold, and the PMOS transistor enters the saturation conduction state.

[0018] The supply current mainly flows to the system power supply terminal through the low on-resistance PMOS transistor to provide stable power to the system to be powered.

[0019] As a further improvement of the present invention, a power-off sleep step is also included:

[0020] The wake-up trigger module triggers a shutdown command, the enable pin of the boost chip returns to a low level, and the voltage output stops;

[0021] The PMOS transistor then turns off, and the capacitive load discharges through the internal discharge circuit of the system to be powered, returning the circuit to standby mode and waiting for the next wake-up.

[0022] As a further improvement of the present invention, the standby state is as follows: the wake-up trigger module is not triggered, the boost chip is in a sleep-off state, and there is no voltage output; the gate-source voltage V of the PMOS transistor is... GS The voltage is 0, indicating that the conduction threshold has not been reached and the circuit is in the off state; the voltage across the capacitive load is 0, and the circuit is in low-power standby mode.

[0023] As a further improvement of the present invention, the preset turn-on threshold of the PMOS transistor is 0.3V.

[0024] The present invention has the following beneficial effects:

[0025] In this invention, a current-limiting pre-charge module suppresses the startup inrush current, and a gate voltage divider is used to drive the PMOS transistor to turn on automatically with the source voltage. No additional control chip is required, resulting in a very simple structure and low cost. This solves the timing matching problem between the startup of the boost chip and the turn-on of the PMOS transistor in existing technologies, avoiding boost protection or wake-up failures caused by momentary short circuits. Furthermore, during normal operation, the current flows through the low-impedance path of the PMOS transistor, and the pre-charge resistor consumes no additional power, making it suitable for the extended battery life requirements of low-power devices. Attached Figure Description

[0026] Figure 1 This is a block diagram of the pre-charging circuit of the wake-up system in this invention.

[0027] Figure 2 This is a circuit diagram of the pre-charging circuit of the wake-up system in this invention.

[0028] Figure 3 This is a flowchart illustrating the operation of the pre-charging circuit of the wake-up system in this invention. Detailed Implementation

[0029] The technical solutions of the embodiments of this specification will be explained and described below with reference to the accompanying drawings. However, the following embodiments are only preferred embodiments of this specification and not all of them. Other embodiments obtained by those skilled in the art based on the embodiments in the implementation methods without creative effort are all within the protection scope of this specification.

[0030] The terms "first," "second," "third," etc., in the description, claims, and accompanying drawings are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such processes, methods, products, or apparatus.

[0031] All data involved in this application are information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of the relevant data comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0032] Example 1

[0033] Please see Figure 1 , 2 As shown, a pre-charge circuit for a wake-up system includes: a wake-up trigger module, a boost converter chip, a PMOS transistor, a capacitive load, a current-limiting pre-charge module, and a passive voltage divider drive module. Among them,

[0034] The output of the wake-up trigger module is electrically connected to the enable pin of the boost chip to control the start and stop of the boost chip.

[0035] For example, the wake-up trigger module is a button wake-up module, which uses a mechanical button (model KFC-A01). One end of the button is connected to the positive terminal of the backup power supply (lithium battery / dry cell battery), and the other end is connected to the enable pin (EN pin) of the boost chip. The VIN pin of the boost chip is connected to the positive terminal of the backup power supply, and the GND pin is connected to the negative terminal of the backup power supply and the system ground. The VOUT pin of the boost chip serves as the output terminal and is directly soldered to the source (S pin) of the PMOS transistor, with an output voltage V. DCDC It can be set to 3.3V or 5V according to system requirements.

[0036] The output terminal of the boost chip is connected to the source of the PMOS transistor.

[0037] For example, a low-power boost converter chip (such as TPS61021) is selected, with an input voltage of 3.7V (lithium battery) and an output voltage of V. DCDC =3.3V or 5V.

[0038] The drain of the PMOS transistor is connected to the positive terminal of the capacitive load and the system power supply terminal of the system to be powered, respectively, and the negative terminal of the capacitive load is grounded.

[0039] The capacitive load is one or both of electrolytic capacitors and ceramic capacitors, with a total capacitance range of 100μF to 2000μF. The capacitive load uses a combination of electrolytic and ceramic capacitors (1000μF electrolytic capacitor + 10μF ceramic capacitor in parallel). The positive terminal of the capacitive load is connected to the D pin and V_SYS terminal of the PMOS transistor, and the negative terminal of the capacitive load is directly connected to the system ground. The V_SYS terminal extends through copper foil lines to the power input pins of the system main control chip, sensors, and other power-consuming units, forming a complete power supply loop.

[0040] For example, a P-channel MOSFET with an on-resistance of <50mΩ (such as AO3401) is selected, with a threshold voltage V.TH =-1V, meeting the high current power supply requirements. The source (S pin) of the PMOS transistor is connected to the VOUT pin of the boost chip through a copper foil circuit, and the drain (D pin) is connected to both the positive terminal of the capacitive load and the system power supply terminal V_SYS through a copper foil circuit. The two ends of the 10Ω current-limiting precharge resistor R3 (model 0805 package, power 1W) are fixed to the S pin and D pin solder joints of the PMOS transistor respectively to ensure that the resistor and the PMOS transistor form a parallel path. The solder joints at both ends of the resistor need to be treated with anti-oxidation treatment.

[0041] A current-limiting pre-charge module is connected in parallel between the source and drain of the PMOS transistor to limit the current of the capacitive load before the PMOS transistor is turned on, thereby suppressing the instantaneous inrush current during startup.

[0042] The current-limiting pre-charge module is a pre-charge resistor R3. When the PMOS transistor is saturated and turned on, the current shunting ratio of the pre-charge resistor R3 is less than 0.2%.

[0043] The source of the PMOS transistor is also connected to a passive voltage divider drive module. The other end of the passive voltage divider drive module is grounded, and the voltage divider output terminal of the passive voltage divider drive module is connected to the gate of the PMOS transistor. This module is used to drive the PMOS transistor to self-adaptively turn on by changing the output voltage of the boost chip.

[0044] like Figure 1 As shown, the passive voltage divider drive module is composed of a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series. The first end of the first voltage divider resistor R1 is electrically connected to the source of the PMOS transistor, and the second end of the first voltage divider resistor R1 is electrically connected to the first end of the second voltage divider resistor R2 and the gate of the PMOS transistor, respectively. The second end of the second voltage divider resistor R2 is grounded.

[0045] For example, one end of the first voltage divider resistor R1 (100kΩ, 0805 package) is soldered to the S pin of the PMOS transistor, and the other end is soldered to the gate (G pin) of the PMOS transistor; one end of the second voltage divider resistor R2 (10kΩ, 0805 package) is soldered to the G pin of the PMOS transistor, and the other end is soldered to system ground; the connection node of the first voltage divider resistor R1 and the second voltage divider resistor R2 must accurately correspond to the G pin of the PMOS transistor to ensure that the gate voltage changes synchronously with the source voltage, without any cold solder joints or poor contact.

[0046] like Figure 1 As shown, the first terminal of the wake-up trigger module is electrically connected to the positive terminal of the backup power supply, and the second terminal of the wake-up trigger module is electrically connected to the enable pin of the boost chip; the input pin of the boost chip is electrically connected to the positive terminal of the backup power supply, and the ground pin is grounded with the system ground.

[0047] To prevent current from flowing back to the boost chip, a diode D is connected between the output terminal of the boost chip and the source of the PMOS transistor. The positive terminal of the diode D is connected to the output terminal of the boost chip, and the negative terminal of the diode D is connected to the source of the PMOS transistor.

[0048] The circuit described above employs "dual protection and self-adaptive turn-on," namely, a 10Ω pre-charge resistor R3 suppresses the startup inrush current, and the gate voltage divider drive enables the PMOS transistor to turn on automatically with the source voltage, eliminating the need for an additional control chip, resulting in a very simple structure and low cost. It solves the timing matching problem between the startup of the boost chip and the turn-on of the PMOS transistor in existing technologies, avoiding boost protection or wake-up failures caused by momentary short circuits. Furthermore, during normal operation, the current flows through the low-impedance path of the PMOS transistor, and the pre-charge resistor consumes no additional power, making it suitable for the extended battery life requirements of low-power devices.

[0049] Example 2

[0050] The key points for debugging the above circuit during operation include the following three points:

[0051] First, measuring V during the pre-charge phase. SYS Voltage rise rate, ensuring that V before PMOS turns on. SYS With V DCDC Pressure difference < 0.5V.

[0052] Second, test the peak output current of the boost chip. It must be lower than its overcurrent protection threshold (e.g., set to 2A, the actual peak value should be controlled within 1.5A).

[0053] Third, verify the wake-up success rate under different load capacitances to ensure stable startup within the range of 100μF~2000μF.

[0054] The detailed test and verification data for the above circuit are recorded below:

[0055] 1. Basic performance test (3.3V system, capacitive load 1000μF)

[0056] Test Project Test data Compared with existing technology (CN100527576C) Advantages Peak pre-charge current 310mA 450mA DC-DC protection risks are lower. PMOS conduction time 5.2ms 8.7ms Faster wake-up speed and better user experience Circuit impedance under normal power supply 25mΩ 40mΩ Higher power efficiency and lower power loss Number of consecutive wake-up faults 500 times 300 times Significantly improved stability PCB footprint 4.8mm² 12.3mm² Higher integration, adaptable to miniaturized devices

[0057] 2. Compatibility test with different load capacitors (3.3V system)

[0058] Capacitive load specifications Precharge time Peak current Wake-up success rate 100μF 1.1ms 95mA 100% 500μF 3.5ms 180mA 100% 1000μF 5.2ms 310mA 100% 2000μF 8.7ms 390mA 100%

[0059] 3. High and low temperature environment stability test (1000μF load, 3.3V system)

[0060] Test ambient temperature Peak pre-charge current On-time Wake-up success rate Number of tests -20℃ 330mA 6.5ms 100% 100 times 25℃(normal temperature) 310mA 5.2ms 100% 100 times 60℃ 295mA 4.8ms 100% 100 times

[0061] Example 3

[0062] Please see Figure 3As shown, a method for operating a wake-up system pre-charging circuit, applicable to the aforementioned wake-up system pre-charging circuit, includes the following steps:

[0063] When the wake-up trigger module is triggered, it outputs a high-level enable signal to the enable terminal of the boost chip, and the boost chip starts to work, with its output voltage rising steadily from 0V.

[0064] When the output voltage of the boost chip rises to 80% of the set output value, the instantaneous inrush current is suppressed by the current limiting pre-charge module connected in parallel between the source and drain of the PMOS transistor until the voltage difference between the voltage across the capacitive load and the output voltage of the boost chip is reduced to within the preset threshold.

[0065] As the output voltage of the boost chip increases, the absolute value of the gate-source voltage of the PMOS transistor reaches and exceeds its conduction threshold, and the PMOS transistor enters the saturation conduction state.

[0066] The supply current mainly flows to the system power supply terminal through the low on-resistance PMOS transistor to provide stable power to the system to be powered.

[0067] The power-off sleep procedure of this circuit is as follows:

[0068] The wake-up trigger module triggers a shutdown command, the enable pin of the boost chip returns to a low level, and the voltage output stops;

[0069] The PMOS transistor then turns off, and the capacitive load discharges through the internal discharge circuit of the system to be powered, returning the circuit to standby mode and waiting for the next wake-up.

[0070] In the above, the standby state is as follows: the wake-up trigger module is not triggered, the boost chip is in a sleep-off state, and there is no voltage output; the gate-source voltage V of the PMOS transistor is... GS The voltage is 0, indicating that the conduction threshold has not been reached and the circuit is in the off state; the voltage across the capacitive load is 0, and the circuit is in low-power standby mode.

[0071] In the above, the preset turn-on threshold of the PMOS transistor is 0.3V.

[0072] The working process of each stage of the above circuit is described in detail below:

[0073] 1. Standby state (t0-t1 time period)

[0074] When the button is not pressed, the EN pin of the boost chip is at a low level, the chip is in sleep mode, and the VOUT pin has no voltage output (V DCDC =0V); at this time, the S pin of the PMOS transistor is not powered, the gate (G) is grounded through R2, and the gate-source voltage V GS =0V, not reaching the PMOS transistor's turn-on threshold (V). TH=-1V), the PMOS transistor is in the off state; there is no voltage difference across the pre-charge resistor R3, no current flows through it, and the voltage across the capacitive load C is V. SYS =0V, the standby power consumption of the entire circuit is determined only by the leakage current of the button wake-up module (measured <1μA), which meets the battery life requirements of low-power devices.

[0075] 2. Wake-up and startup phase (t1-t2 period)

[0076] When the user presses the mechanical button (at time t1), the button wake-up module transmits the backup power supply voltage to the EN pin of the boost chip, making the enable signal high and starting the boost chip. The voltage VOUT pin of the boost chip... DCDC The voltage gradually increases from 0V, following the inherent startup characteristics of the chip (e.g., the startup time of TPS61021 is approximately 2ms). DCDC During the t1-t2 period, the voltage rises steadily to the set value (3.3V or 5V); during this stage, the voltage at the source pin of the PMOS transistor increases with V. DCDC Synchronous rise, but gate voltage V G Determined by the voltage division relationship between R1 and R2 (V G =V S ×R2 / (R1+R2)), because V S Sufficient voltage has not yet been reached, V GS =V G -V S =-V S The absolute value of ×R1 / (R1+R2) is less than the conduction threshold V. TH The PMOS transistor remains off, and the main power supply path is still not open.

[0077] 3. Pre-charging phase (t2-t3 period)

[0078] When V DCDC When the voltage rises to 80% of the set value (e.g., approximately 2.64V in a 3.3V system) (at time t2), an effective voltage difference is formed across the pre-charge resistor R3, and the boost chip output voltage begins pre-charging the capacitive load C through R3; due to the current limiting effect of R3, the charging current I... R3 =(V DCDC -V SYS ) / R3, initial stage V SYS =0V, maximum pre-charge current is approximately 330mA (3.3V system), this current value is lower than the overcurrent protection threshold of the boost chip (set to 500mA), avoiding triggering the boost chip's protection; during the t2-t3 period, V SYS As the charging process progresses slowly, the measured voltage rise rate during this stage is approximately 0.6V / ms, reaching V at time t3. SYS With V DCDCThe voltage difference is reduced to less than 0.3V, and the "short circuit effect" of capacitive load is completely eliminated.

[0079] 4. Normal power supply phase (after time t3)

[0080] V at time t3 SYS Rise to V DCDC When the voltage difference is <0.3V, the gate-source voltage V of the PMOS transistor is GS =V G -V S =-V S The absolute value of ×R1 / (R1+R2) reaches and exceeds the conduction threshold V. TH (e.g. V) S When V = 3.3V, V GS =-3.3V×100k / (100k+10k)≈-3V>-1V), the PMOS transistor begins to conduct and gradually enters the saturation conduction state; due to the on-resistance R of the PMOS transistor DS (on) = 20mΩ, which is much smaller than the pre-charge resistor R3 (10Ω). According to the current shunting principle of parallel circuits, the current mainly flows to the V_SYS terminal through the PMOS transistor. The current shunting ratio of the pre-charge resistor is <0.2%, with almost no additional power consumption. At this time, the voltage of the system power supply terminal V_SYS is close to the voltage of the boost chip output terminal (measured voltage difference <0.1V), which meets the working voltage requirements of the main control chip, sensors and other power-consuming units, and the system enters normal operation.

[0081] 5. Power outage sleep phase

[0082] When the system finishes its work or a sleep command is triggered by a key, the EN pin of the boost chip returns to a low level, the boost chip stops outputting, and V DCDC The voltage drops to 0V; the voltage at the source pin of the PMOS transistor disappears, and the gate is grounded through R2. GS The voltage returns to 0V, the PMOS transistor is cut off; the capacitive load discharges through the system's internal discharge circuit, V SYS The voltage gradually drops to 0V, and the circuit returns to standby mode, waiting to be woken up by the next button press.

[0083] The embodiments described above are merely preferred embodiments of this specification and are not intended to limit the scope of this specification. Any modifications and improvements made by those skilled in the art to the technical solutions of this specification without departing from the spirit of this specification should fall within the protection scope defined by the claims of this specification.

Claims

1. A pre-charging circuit for a wake-up system, characterized in that, The output of the wake-up trigger module is electrically connected to the enable pin of the boost chip to control the start and stop of the boost chip; The output terminal of the boost chip is connected to the source of the PMOS transistor; The drain of the PMOS transistor is connected to the positive terminal of the capacitive load and the system power supply terminal of the system to be powered, respectively, and the negative terminal of the capacitive load is grounded. A current-limiting pre-charge module is connected in parallel between the source and drain of the PMOS transistor to limit the current of the capacitive load before the PMOS transistor is turned on, thereby suppressing the instantaneous inrush current during startup. The source of the PMOS transistor is also connected to a passive voltage divider drive module. The other end of the passive voltage divider drive module is grounded, and the voltage divider output terminal of the passive voltage divider drive module is connected to the gate of the PMOS transistor. This module is used to drive the PMOS transistor to self-adaptively turn on by changing the output voltage of the boost chip.

2. The wake-up system pre-charging circuit according to claim 1, characterized in that, The passive voltage divider drive module is composed of a first voltage divider resistor R1 and a second voltage divider resistor R2 connected in series. The first end of the first voltage divider resistor R1 is electrically connected to the source of the PMOS transistor, and the second end of the first voltage divider resistor R1 is electrically connected to the first end of the second voltage divider resistor R2 and the gate of the PMOS transistor, respectively. The second end of the second voltage divider resistor R2 is grounded.

3. The wake-up system pre-charging circuit according to claim 1, characterized in that, The first terminal of the wake-up trigger module is electrically connected to the positive terminal of the backup power supply, and the second terminal of the wake-up trigger module is electrically connected to the enable pin of the boost chip; the input pin of the boost chip is electrically connected to the positive terminal of the backup power supply, and the ground pin is grounded with the system ground.

4. The wake-up system pre-charging circuit according to claim 1, characterized in that, A diode D is also connected between the output terminal of the boost chip and the source of the PMOS transistor. The positive terminal of the diode D is connected to the output terminal of the boost chip, and the negative terminal of the diode D is connected to the source of the PMOS transistor.

5. The wake-up system pre-charging circuit according to claim 1, characterized in that, The capacitive load is one or both of electrolytic capacitors and ceramic capacitors, with a total capacitance range of 100μF to 2000μF.

6. The wake-up system pre-charging circuit according to claim 1, characterized in that, The current-limiting pre-charge module is a pre-charge resistor R3. When the PMOS transistor is saturated and turned on, the current shunting ratio of the pre-charge resistor R3 is less than 0.2%.

7. A method for operating a pre-charging circuit of a wake-up system, the method being applicable to the pre-charging circuit of a wake-up system according to any one of claims 1-6, characterized in that, Includes the following steps: When the wake-up trigger module is triggered, it outputs a high-level enable signal to the enable terminal of the boost chip, and the boost chip starts to work, with its output voltage rising steadily from 0V. When the output voltage of the boost chip rises to 80% of the set output value, the instantaneous inrush current is suppressed by the current limiting pre-charge module connected in parallel between the source and drain of the PMOS transistor until the voltage difference between the voltage across the capacitive load and the output voltage of the boost chip is reduced to within the preset threshold. As the output voltage of the boost chip increases, the absolute value of the gate-source voltage of the PMOS transistor reaches and exceeds its conduction threshold, and the PMOS transistor enters the saturation conduction state. The supply current mainly flows to the system power supply terminal through the low on-resistance PMOS transistor to provide stable power to the system to be powered.

8. The method for operating the pre-charging circuit of the wake-up system according to claim 7, characterized in that, It also includes a power-off sleep mode: The wake-up trigger module triggers a shutdown command, the enable pin of the boost chip returns to a low level, and the voltage output stops; The PMOS transistor then turns off, and the capacitive load discharges through the internal discharge circuit of the system to be powered, returning the circuit to standby mode and waiting for the next wake-up.

9. The method of operating the pre-charging circuit of the wake-up system according to claim 8, characterized in that, The standby state is as follows: the wake-up trigger module is not triggered, the boost chip is in a sleep-off state, and there is no voltage output; the gate-source voltage V of the PMOS transistor is... GS The voltage is 0, indicating that the conduction threshold has not been reached and the circuit is in the off state; the voltage across the capacitive load is 0, and the circuit is in low-power standby mode.

10. The method of operating the pre-charging circuit of the wake-up system according to claim 7, characterized in that, The voltage difference between the capacitive load and the boost chip output voltage is ≤0.3V.

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