High amplitude and phase consistency adaptive adjusting circuit of array power amplifier

Abstract

This invention discloses a high amplitude and phase consistency adaptive adjustment circuit for arrayed power amplifiers, belonging to the field of microwave wireless communication. The circuit includes at least two power amplifiers, a current detection circuit corresponding to each power amplifier, and a programmable gate voltage regulator circuit. A microcontroller forms a closed-loop adjustment circuit. Based on the drain static current fed back from the current detection circuit, the microcontroller adjusts the gate voltage bias output by the programmable gate voltage regulator circuit, stabilizing the drain static current of each power amplifier to a pre-calibrated target value. This circuit supports fixed-step gate voltage adjustment, and the microcontroller can remember control signals after power-down and perform temperature drift dynamic compensation through a pre-stored temperature mapping table. This effectively improves the amplitude and phase consistency and debugging efficiency of the arrayed power amplifier, is compatible with various RF and microwave power amplifiers, and is suitable for arrayed transmission systems.

Description

Technical Field

[0001] This invention relates to the field of microwave wireless communication technology, and more specifically to a high amplitude phase consistency adaptive adjustment circuit for an arrayed power amplifier. Background Technology

[0002] With the rapid development of electronic equipment system technology, arrayed equipment has become the mainstream technical solution in fields such as microwave wireless communication and radar detection. For arrayed transmission systems, the gain and phase consistency of their internal multi-channel power amplifiers directly determine the efficiency of spatial power combining, placing extremely high demands on the gain and phase consistency of the power amplifiers.

[0003] To achieve good gain and phase consistency among multiple power amplifiers, the key is to ensure that the gate voltage bias Vg of each power amplifier is at the appropriate value, thereby maintaining the drain quiescent current within the target range. Otherwise, the gain and phase consistency of the power amplifier cannot be effectively guaranteed.

[0004] In existing technologies, to obtain the gate bias Vg required by a power amplifier, a suitable gate voltage value is typically obtained by adjusting the DC power supply first, and then a voltage regulator circuit with a fixed feedback resistor is used to output this gate voltage value in the actual application circuit. This approach has the following significant drawbacks: First, due to the limitation of resistor accuracy, the gate voltage regulator circuit usually requires multiple resistor replacements to obtain the target regulated voltage value, resulting in extremely low debugging efficiency and a huge workload. Second, due to the discreteness of semiconductor processes, different power amplifiers require different gate bias Vg to achieve the same drain quiescent current. Existing voltage regulator circuits with fixed parameters cannot achieve personalized and precise control of arrayed multi-channel power amplifiers. In addition, the performance of the power amplifier and the resistance characteristics are closely related to the ambient temperature, resulting in a serious temperature "drift" problem. Existing voltage regulator circuits with fixed parameters cannot achieve dynamic adjustment, leading to rapid degradation of the amplitude and phase consistency of the power amplifier under wide operating temperature conditions, which seriously affects the spatial synthesis efficiency of the array system.

[0005] Therefore, how to achieve efficient, dynamic, and adaptive control of amplitude and phase uniformity in arrayed power amplifiers has become a technical problem that urgently needs to be solved in this field. Summary of the Invention

[0006] In view of the above problems, the present invention provides a high amplitude and phase consistency adaptive adjustment circuit for arrayed power amplifiers. Through an integrated circuit design that combines charge and discharge control, bypass output, adjustable secondary voltage output, and operating status detection, and in conjunction with a differentiated threshold discharge control strategy with high open and low close voltage, the charging and discharging process of the energy storage device can be accurately and reliably controlled.

[0007] In a first aspect, embodiments of the present invention provide a high-amplitude phase consistency adaptive adjustment circuit for an arrayed power amplifier, comprising: At least two power amplifiers, a current detection circuit and a programmable gate voltage regulator circuit corresponding to each of the power amplifiers, and a microcontroller; The output terminal of the programmable gate voltage regulator circuit is electrically connected to the gate of the corresponding power amplifier, and is used to provide an adjustable gate voltage bias for the power amplifier. The current detection circuit is connected in series in the drain power supply circuit of the corresponding power amplifier to detect the drain static current of the power amplifier in real time. The microcontroller is communicatively connected to the signal output terminal of each current detection circuit and the control terminal of each programmable gate voltage regulator circuit. The microcontroller has a pre-stored target static drain current. The microcontroller is used to output a control signal to the programmable gate voltage regulator circuit based on the drain static current fed back by the current detection circuit, and adjust the gate voltage bias of the output circuit so that the drain static current of the corresponding power amplifier is stabilized at the target static drain current.

[0008] In some embodiments, the programmable gate voltage regulator circuit is provided with multiple digital control terminals. The microcontroller outputs parallel digital signals to the digital control terminals to adjust the gate voltage bias output by the programmable gate voltage regulator circuit, so that the gate voltage bias is continuously adjustable in fixed steps.

[0009] In some embodiments, the gate voltage bias output range of the programmable gate voltage regulator circuit is V. gmin ~V gmin +2 n-1 Δu, where V gmin Δu represents the lower limit of the voltage output, n represents the number of bits in the digital control terminal, and Δu represents the single-step voltage adjustment step. The number of bits in the digital control terminal can be configured according to the sensitivity of the power amplifier's drain current to the gate voltage.

[0010] In some embodiments, the programmable gate voltage regulator circuit is powered by a negative voltage, its digital control terminal is a 5-bit parallel control terminal, the single-step voltage adjustment step Δu is 0.1V, and the output range of the gate voltage bias is -3.5V to -0.4V; the input level of the digital control terminal is TTL level or LVTTL level.

[0011] In some embodiments, the microcontroller has a built-in non-volatile memory unit for storing control signals for the gate voltage bias of each power amplifier, so that when the circuit is powered off and then powered on again, the programmable gate voltage regulator circuit can be restored to the gate voltage output state before the power failure, maintaining the target static drain current of the power amplifier.

[0012] In some embodiments, the microcontroller pre-stores a mapping table showing the correspondence between the gate voltage bias, drain quiescent current, gain, and phase of the power amplifier under different ambient temperatures. The microcontroller can call the corresponding mapping table to adjust the gate voltage bias according to the real-time ambient temperature, so as to dynamically compensate for the temperature drift of the power amplifier gain and phase.

[0013] In some embodiments, the target static drain current is a pre-calibrated optimal value, which is determined by traversing the gate voltage bias range of the power amplifier, simultaneously testing the linear gain curve of the power amplifier under each gate voltage bias, and selecting the drain static current corresponding to the gain curve with the best linearity.

[0014] In some embodiments, the current detection circuit is a high-precision DC current detection circuit, used to acquire the static drain current of the power amplifier in real time during the gate voltage bias adjustment process, and feed the acquisition result back to the microcontroller to form a closed-loop adjustment circuit.

[0015] In some embodiments, the power amplifier is a radio frequency power amplifier or a microwave power amplifier, and its semiconductor material includes GaN material.

[0016] In some embodiments, the microcontroller is any one of a microcontroller, FPGA, or CPLD, and its control terminal is initially preset to a state of all zeros, so that the programmable gate voltage regulator circuit outputs the lower limit value of the gate voltage bias upon power-up.

[0017] The high amplitude and phase consistency adaptive adjustment circuit for an arrayed power amplifier provided in this invention has the following significant technical advantages compared with the prior art: This invention achieves adaptive and precise control of the drain static current of arrayed multi-channel power amplifiers through an architecture of current detection, microcontroller, and programmable gate voltage regulator circuit. This ensures that all power amplifiers operate at a consistent DC bias point, thereby guaranteeing a high degree of consistency in gain and phase from the source and significantly improving the spatial power combining efficiency of the arrayed system.

[0018] By replacing the traditional fixed feedback resistor with a programmable gate voltage regulator circuit, there is no need to repeatedly replace and adjust the resistor. The gate voltage can be quickly and precisely adjusted in steps through digital signals, which completely solves the problems of low debugging efficiency and poor accuracy of traditional solutions. It is especially suitable for batch debugging and control of large-scale array power amplifier systems.

[0019] This invention achieves power-off memory of power amplifier operating parameters through the non-volatile storage design of the microcontroller processor. After system restart, it can quickly restore to the optimal operating state, avoiding repeated debugging and ensuring long-term consistency of operating state. Furthermore, temperature drift dynamic compensation of gain and phase can be achieved through a pre-stored temperature mapping table, solving the problem of consistency degradation in wide-temperature environments of traditional solutions and improving the environmental adaptability and operating stability of arrayed power amplifier systems.

[0020] The circuit architecture in this invention is highly versatile, with flexible configuration of control bit depth, adjustment step size, and output voltage range. It is compatible with different types and frequency bands of RF and microwave power amplifiers, and is suitable for various arrayed transmission systems, thus possessing good application value.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0022] The invention will now be described in more detail with reference to embodiments and the accompanying drawings.

[0023] Figure 1 A schematic diagram of an exemplary prior art multi-element array power amplifier system architecture is shown in one embodiment of the present invention. Figure 2 The diagram illustrates an exemplary power amplifier unit circuit using a fixed feedback resistor voltage regulator circuit in the prior art, as presented in an embodiment of the present invention. Figure 3 This diagram illustrates an exemplary power amplifier unit circuit with adaptive gate voltage bias adjustment according to one embodiment of the present invention. Figure 4 The diagram shows a schematic of an exemplary high-amplitude phase consistency adaptive adjustment circuit for an arrayed power amplifier according to an embodiment of the present invention. Detailed Implementation

[0024] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and are not intended to limit the present invention.

[0025] For arrayed transmission systems, the gain of their internal multi-element power amplifiers must maintain good consistency to achieve better spatial power combining. (See [reference needed]). Figure 1 As shown, to maintain good gain and phase consistency among multiple power amplifiers, each power amplifier needs to have a suitable gate voltage bias V.g To maintain the drain quiescent current within a certain range, it is difficult to guarantee the gain and phase consistency of the power amplifier.

[0026] To obtain the required gate voltage bias V g The main approach currently is to first adjust the gate voltage bias V of the power amplifier using a DC power supply. g To achieve optimal gain linearity. In practical application circuits, the gate V of the power amplifier... g A voltage regulator circuit is used to obtain the same gate voltage V as the DC power supply by adjusting the feedback resistor ratio. g .

[0027] See Figure 2 As shown, due to resistor accuracy issues, gate voltage regulator circuits typically require multiple resistor replacements to obtain the required regulated voltage V. g The efficiency is relatively low, especially in arrayed systems, because inconsistencies in power amplifier manufacturing processes mean that different power amplifiers typically require different gate bias voltages V. g To obtain the same drain quiescent current I dopt This is to ensure consistency in gain and phase. In addition, the performance of the power amplifier and its resistance characteristics are closely related to temperature, and there is a temperature "drift" problem.

[0028] Therefore, based on the research of the above-mentioned existing technologies, it is necessary to design a high amplitude and phase consistency adaptive adjustment circuit for arrayed power amplifiers to improve the gain and phase consistency index of multi-element arrayed power amplifiers and solve the problem of consistency index "drift" at different temperatures.

[0029] To address the problems of existing technologies, this application proposes a high-amplitude and phase consistency adaptive adjustment circuit for arrayed power amplifiers, enabling arrayed multi-element power amplifiers to have the same static drain current I. dopt This achieves superior gain and phase consistency. The method utilizes a current detection circuit, a programmable gate voltage regulator circuit, and a microcontroller to dynamically adjust the gain and phase consistency of the power amplifier. See details... Figure 3 As shown.

[0030] The programmable gate voltage regulator circuit 2 uses a microcontroller 3 to control D1~D2 via parallel port. n To achieve a gate voltage V with a fixed step Δu variation g Output, output range is V gmin ~V gmin +2 n-1 Δu(V) gmin (This is the lower limit of the voltage output). The microcontroller 3 changes V... gTo adjust the DC bias point of the power amplifier, thereby adjusting its gain and phase, the drain bias current I is detected by current detection circuit 1. d And record the feedback to the microcontroller processor 3.

[0031] The gain linearity of the power amplifier was tested using a signal source and an RF power meter. Within the linear region of the power amplifier, the power P at the RF input port... in The power P at the RF output port is provided by a signal source and gradually increased. out By using a power meter to record synchronously, the gain of the power amplifier in the linear region, Gain=P, can be calculated. out -P in By iterating through the gate voltage V of the power amplifier g Simultaneously test the corresponding linear gain curve Gain and static drain current I. d By comparing the tested gain curves, the gain curve with the best linearity can be selected, and the corresponding static drain current I... d This will be used as the gate voltage V for subsequent multi-element power amplifiers. g Reference Standard I dopt . use Figure 3 The power amplifier unit circuit shown replaces Figure 2 Traditional power amplifier unit circuits can be quickly adjusted. Figure 1 Gate voltage V of medium power amplifier 1~N g To obtain the best I dopt At this point, power amplifiers 1 through N will have good gain and phase consistency. Microcontroller 3 synchronously stores the gate voltage control signal for the corresponding power amplifier unit, ensuring that the subsequent multi-element power amplifiers maintain the same static drain current I after power loss and power-on. dopt Based on the above principle, the power amplifier grid V at different temperatures can also be... g The gain and phase relationships are recorded and saved to compensate for temperature drift.

[0032] See Figure 4 As shown, this embodiment provides a high-amplitude and phase consistency adaptive adjustment circuit for an arrayed power amplifier, including N power amplifiers arranged in an array (N≥2, where N is the number of power amplifier channels in the arrayed system), a current detection circuit and a 5-bit programmable gate voltage regulator circuit corresponding to each power amplifier, and a microcontroller. The microcontroller has multiple parallel I / O interfaces and an ADC acquisition channel, which can simultaneously perform parallel control of the circuits of all power amplifier channels, realizing unified management and control of the arrayed system.

[0033] In this embodiment, the power amplifier is a microwave power amplifier made of GaN material, and its operating frequency band covers the mainstream frequency band of microwave wireless communication; in other embodiments, radio frequency power amplifiers or microwave power amplifiers made of other materials may also be used, and the present invention does not limit this.

[0034] The programmable gate voltage regulator circuit is powered by a -5V DC power supply and features 5 parallel digital control terminals D4~D0. The control level is compatible with both TTL and LVTTL levels. The single-step voltage adjustment step Δu is set to 0.1V, and the output range of the gate voltage bias is -3.5V to -0.4V. When the input signal at control terminals D4~D0 is 00000, the programmable gate voltage regulator circuit outputs a gate voltage bias of -3.5V (lower limit of voltage output); when the input signal is 11111, it outputs a gate voltage bias of -0.4V (upper limit of voltage output). In other embodiments, the number of bits in the digital control terminals can be increased or decreased according to the sensitivity of the power amplifier's drain current to the gate voltage to adjust the adjustment accuracy and output range, adapting to different models of power amplifiers.

[0035] The current detection circuit adopts a high-precision DC current detection circuit, which is connected in series in the drain power supply circuit of the corresponding power amplifier. It can collect the static drain current Id of the power amplifier in real time and convert the collected current signal into an analog voltage signal of 0~3.3V, which is fed back to the ADC acquisition terminal of the microcontroller to provide real-time feedback data for closed-loop regulation.

[0036] The microcontroller can be an industrial-grade microcontroller, or in other embodiments, a programmable logic device such as an FPGA or CPLD. The microcontroller has a built-in Flash non-volatile memory unit, enabling long-term storage of control parameters. The parallel I / O ports of the microcontroller are electrically connected one-to-one with the digital control terminals D4~D0 of each programmable gate voltage regulator circuit, and the ADC acquisition channels are electrically connected one-to-one with the signal output terminals of each current detection circuit.

[0037] The circuit operation process in this embodiment specifically includes three core steps: target static drain current pre-calibration, adaptive closed-loop adjustment, and power-down memory and temperature compensation, as detailed below: Target static drain current I dopt Pre-calibration: Target static drain current I doptThe linearity of the power amplifier is the core benchmark for ensuring the consistency of the array amplitude and phase. This embodiment completes the pre-calibration in the following way: A calibration test system is built using a power amplifier of the same model as the array system. An RF signal source provides progressively increasing input power (Pin) to the RF input port of the power amplifier. Simultaneously, an RF power meter collects the output power (Pout) at the RF output port of the power amplifier, and the gain of the power amplifier in the linear operating region is calculated as Gain = Pout - Pin. The entire adjustment range of the power amplifier's gate voltage bias (-3.5V to -0.4V) is traversed, with the gate voltage bias adjusted in -0.1V steps. Simultaneously, the linear gain curve of the power amplifier and the corresponding static drain current (I) are tested under each gate voltage bias. d By comparing all the linear gain curves obtained from the tests, the gain curve with the best linearity is selected. The static drain current corresponding to this curve is the target static drain current I. dopt , the I dopt The value is pre-stored in the storage unit of the microcontroller processor as a unified control reference for all power amplifier channels in the array.

[0038] Adaptive closed-loop adjustment process: Upon system power-up, the microcontroller initializes all digital control terminals of the programmable gate voltage regulator circuits to all zeros, ensuring that all programmable gate voltage regulator circuits initially output a gate voltage lower limit of -3.5V. This prevents overcurrent damage to the power amplifiers due to excessively high gate voltages during power-up, thus guaranteeing system power-up safety. After power-up, the microcontroller, through the current detection circuits of each channel, continuously monitors the static drain current I of the corresponding power amplifier. d The I collected from each channel d Value and pre-stored target static drain current I dopt Perform real-time comparison. If the I signal collected by a certain channel... d Less than I dopt The microcontroller adjusts the parallel digital signal of the programmable gate voltage regulator circuit for this channel, increasing the output gate voltage in fixed steps of -0.1V (adjusting towards -0.4V), thus gradually increasing the drain quiescent current of the power amplifier; if the acquired Id is greater than I... dopt Then, the parallel digital signal is adjusted in reverse to reduce the output gate voltage in fixed steps of -0.1V (adjusting towards -3.5V), causing the drain quiescent current to gradually decrease. Through the above closed-loop feedback regulation, the quiescent drain current of all power amplifiers in the array is finally stabilized at the target quiescent drain current I. dopt This ensures that all power amplifiers operate at a completely consistent DC bias point, thereby achieving a high degree of consistency in gain and phase of the arrayed multi-channel power amplifiers and guaranteeing spatial power combining efficiency.

[0039] Power-off memory and temperature compensation: The microcontroller performs closed-loop regulation of each channel, ensuring the power amplifier operates stably at I0. dopt Then, the digital control signal corresponding to the channel is stored in the built-in Flash non-volatile memory. When the system is powered on again after a power outage, the microcontroller directly calls the stored control signals of each channel. Without repeated closed-loop debugging, it can control the output of each programmable gate voltage regulator circuit to be exactly the same as the gate voltage bias before the power outage, so that all power amplifiers can quickly recover to the target static drain current I. dopt This ensures the stability of amplitude and phase consistency after the system restarts.

[0040] Meanwhile, this embodiment allows for pre-calibration of the power amplifier gate voltage bias V under different ambient temperatures within the operating temperature range. g With drain quiescent current I d The correspondence between gain and phase is established to generate multiple sets of temperature-gate voltage mapping tables, which are pre-stored in the microcontroller. During system operation, the real-time ambient temperature of the array can be acquired via an external temperature sensor. The microcontroller dynamically adjusts the gate voltage bias V of each channel by calling the corresponding mapping table based on the real-time temperature. g This compensates for gain and phase drift caused by temperature changes, further improving the amplitude and phase consistency of the array power amplifier under wide operating temperature conditions.

[0041] In practical applications, a high-amplitude and phase-coherence adaptive adjustment circuit for an arrayed power amplifier includes a power amplifier, a current detection circuit, a 5-bit programmable gate voltage regulator circuit, and a microcontroller required for programming control, such as... Figure 4 As shown. The current detection circuit is used to detect the power amplifier at different gate voltages V. g The quiescent current of the drain under varying conditions.

[0042] The programmable gate voltage regulator circuit operates on a -5V power supply, with a regulated output voltage range of -3.5V to -0.4V. It utilizes parallel ports D4-D0 to achieve -0.1V increments, with control levels that can be TTL or LVTTL. When D4-D0 is 00000, the programmable regulator outputs -3.5V. When D4-D0 is 11111, the programmable regulator outputs -0.4V. For higher voltage precision, the number of control bits can be increased, depending on the sensitivity of the power amplifier's drain current to the gate voltage Vg.

[0043] The microcontroller controls the parallel port control terminal of the programmable gate voltage regulator circuit. The control lines Dn~D0 are initially preset to all zeros to ensure the output voltage of the gate voltage regulator circuit is -3.5V. The microcontroller calculates the voltage based on the current detection value and the preset drain current I. doptBy comparison, D4~D0 are controlled to adaptively adjust the output voltage of the programmable gate voltage regulator circuit. Simultaneously, the microcontroller must have a program persistence function to ensure that after a power outage and power-on, the programmable gate voltage regulator circuit maintains the same gate voltage output as before the power outage. This can be implemented using a microcontroller, FPGA, or CPLD. The current detection circuit detects the static drain current of the power amplifier and feeds it back to the microcontroller for adaptive adjustment of the programmable gate voltage regulator circuit's output voltage.

[0044] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-amplitude phase consistency adaptive adjustment circuit for an arrayed power amplifier, characterized in that, It includes at least two power amplifiers, a current detection circuit and a programmable gate voltage regulator circuit that are configured one-to-one with each of the power amplifiers, and a microcontroller. The output terminal of the programmable gate voltage regulator circuit is electrically connected to the gate of the corresponding power amplifier, and is used to provide an adjustable gate voltage bias for the power amplifier. The current detection circuit is connected in series in the drain power supply circuit of the corresponding power amplifier to detect the drain static current of the power amplifier in real time. The microcontroller is communicatively connected to the signal output terminal of each current detection circuit and the control terminal of each programmable gate voltage regulator circuit. The microcontroller has a pre-stored target static drain current. The microcontroller is used to output a control signal to the programmable gate voltage regulator circuit based on the drain static current fed back by the current detection circuit, and adjust the gate voltage bias of the output circuit so that the drain static current of the corresponding power amplifier is stabilized at the target static drain current.

2. The high amplitude and phase consistency adaptive adjustment circuit for an arrayed power amplifier according to claim 1, characterized in that, The programmable gate voltage regulator circuit is provided with multiple digital control terminals. The microcontroller outputs parallel digital signals to the digital control terminals to adjust the gate voltage bias output by the programmable gate voltage regulator circuit, so that the gate voltage bias is continuously adjustable in fixed steps.

3. The high amplitude and phase consistency adaptive adjustment circuit for an arrayed power amplifier according to claim 2, characterized in that, The gate voltage bias output range of the programmable gate voltage regulator circuit is V. gmin ~V gmin +2 n-1 Δu, where V gmin Δu represents the lower limit of the voltage output, n represents the number of bits in the digital control terminal, and Δu represents the single-step voltage adjustment step. The number of bits in the digital control terminal can be configured according to the sensitivity of the power amplifier's drain current to the gate voltage.

4. The high amplitude and phase consistency adaptive adjustment circuit for an arrayed power amplifier according to claim 3, characterized in that, The programmable gate voltage regulator circuit is powered by a negative voltage. Its digital control terminal is a 5-bit parallel control terminal, the single-step voltage adjustment step Δu is 0.1V, and the output range of the gate voltage bias is -3.5V to -0.4V. The input level of the digital control terminal is TTL level or LVTTL level.

5. The high amplitude and phase consistency adaptive adjustment circuit for an arrayed power amplifier according to claim 1, characterized in that, The microcontroller has a built-in non-volatile memory unit for storing the control signals for the gate voltage bias of each power amplifier. This allows the programmable gate voltage regulator circuit to restore the gate voltage output state before the power failure when the circuit is powered on again, thus maintaining the target static drain current of the power amplifier.

6. The high amplitude and phase consistency adaptive adjustment circuit for an arrayed power amplifier according to claim 1, characterized in that, The microcontroller pre-stores a mapping table showing the correspondence between the gate voltage bias, drain quiescent current, gain, and phase of the power amplifier under different ambient temperatures. The microcontroller can call the corresponding mapping table to adjust the gate voltage bias according to the real-time ambient temperature, so as to dynamically compensate for the temperature drift of the power amplifier gain and phase.

7. The high amplitude and phase consistency adaptive adjustment circuit for an arrayed power amplifier according to claim 1, characterized in that, The target static drain current is a pre-calibrated optimal value. This optimal value is determined by traversing the gate voltage bias range of the power amplifier, simultaneously testing the linear gain curve of the power amplifier under each gate voltage bias, and selecting the drain static current corresponding to the gain curve with the best linearity.

8. The high amplitude and phase consistency adaptive adjustment circuit for an arrayed power amplifier according to claim 1, characterized in that, The current detection circuit is a high-precision DC current detection circuit, used to collect the static drain current of the power amplifier in real time during the gate voltage bias adjustment process, and feed the collection results back to the microcontroller to form a closed-loop adjustment circuit.

9. The high amplitude and phase consistency adaptive adjustment circuit for an arrayed power amplifier according to claim 1, characterized in that, The power amplifier is a radio frequency power amplifier or a microwave power amplifier, and its semiconductor material includes GaN material.

10. The high amplitude and phase consistency adaptive adjustment circuit for an arrayed power amplifier according to claim 1, characterized in that, The microcontroller can be any one of a single-chip microcomputer, FPGA, or CPLD. Its control terminal is initially preset to all zeros, so that the programmable gate voltage regulator circuit outputs the lower limit of the gate voltage bias value upon power-up.

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