A low-complexity high-precision delay method based on polyphase filter interpolation

Abstract

This invention relates to the field of digital signal processing technology and discloses a low-complexity, high-precision delay method based on polyphase filter interpolation, comprising: S1 designing a prototype low-pass filter; S2 performing polyphase decomposition on the interpolated filter, decomposing it into I-phase; S3 decomposing the fractional delay requirement of the input signal, with the integer part implemented through sampling period delay and the fractional part implemented through a fractional delay filter; S4 storing the coefficients of the I-phase filter as a coefficient array, and determining the delay interval of the virtual branch according to the input fractional delay parameters; S5 using polynomial interpolation to fit the filter coefficients of the virtual branch from the coefficient array, configuring them into an FIR filter to form a fractional delay filter; S6 designing the fractional delay filter as a high-speed parallel filter structure, converting serial computation into L-way parallel computation. This invention achieves high-precision variable fractional delay control with a low-complexity, low-computational-load configurable filter structure.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing technology, specifically to a low-complexity, high-precision delay method based on polyphase filter interpolation. Background Technology

[0002] In the field of digital signal processing, high-precision delay control is one of the core technologies for systems such as array signal processing, radar signal simulation, and satellite navigation and communication. With the continuous increase in the operating frequency of modern electronic systems, the requirements for delay accuracy have risen from the nanosecond level to the picosecond level. Simultaneously, the significant increase in system data throughput has made high-speed multi-channel parallel processing the norm. In hardware implementation platforms such as FPGAs, how to reduce implementation complexity, minimize resource consumption, and adapt to high-speed data stream processing while ensuring delay accuracy has become a key challenge for high-precision delay technology.

[0003] Currently, the mainstream high-precision delay implementation methods mainly include the following three categories. However, these technologies have each exposed obvious defects when dealing with high-speed multi-path parallel scenarios.

[0004] Existing technology 1: Variable delay method based on FARROW filter The FARROW filter is a classic variable fractional delay implementation structure that uses polynomial fitting to update the filter coefficients in real time based on the delay parameters. However, the FARROW filter was originally designed for sampling rate conversion, requiring all multiphase branches to participate in the calculation simultaneously, resulting in a complex structure and high computational load. Especially in high-speed applications, the operation of updating the filter coefficients in real time further exacerbates the implementation difficulty, consuming a large amount of FPGA multipliers and logic resources, making it difficult to meet the requirements of high-speed multi-channel parallel processing.

[0005] Existing technology 2: A method based on interpolation using multiple fixed filters This method designs multiple sets of fixed-delay filters and then uses interpolation algorithms such as Lagrange to fit the multiple outputs to obtain filter coefficients with arbitrary fractional delays. Although this method can achieve high delay accuracy, it is essentially still a parallel structure of "multiple fixed filters + interpolation filters," requiring multiple fixed-delay branches to exist and operate simultaneously, resulting in high structural complexity and computational load. More importantly, existing technologies of this kind are all single-channel processing architectures. When faced with high-speed, multi-channel parallel inputs, the structure becomes even more complex, consumes more resources, and cannot be directly applied.

[0006] Existing technology 3: A method for branch gating based on polyphase filters This method decomposes the prototype filter into multiple phases and controls the delay by selecting the output of one of the phases. While this reduces computational complexity compared to a full-structure implementation, its delay accuracy is directly limited by the number of phases decomposed—for an N-phase decomposition, the minimum delay step is only T / N, resulting in limited accuracy. Increasing the number of phases to improve accuracy increases the filter order, thus increasing design complexity.

[0007] In summary, existing high-precision delay technologies have the following common drawbacks: First, the FARROW structure itself has a large computational load and consumes a lot of resources; second, the multi-set fixed filter interpolation method has a complex structure and requires multiple filter branches to run in parallel; third, the accuracy of the multi-phase branch gating method is limited; fourth, the FARROW filter and the multi-set fixed filter interpolation method do not consider the implementation problem in multi-path parallel scenarios, making it difficult to implement efficiently in high-speed environments. Summary of the Invention

[0008] The present invention aims to provide a low-complexity, high-precision delay method based on polyphase filter interpolation, in order to solve the technical problems of existing high-precision delay filters being complex in structure, large in computation, high in resource consumption, and difficult to implement in high-speed multi-channel parallel processing.

[0009] To solve the above problems, the present invention adopts the following technical solution: A low-complexity, high-precision delay method based on polyphase filter interpolation includes the following steps: Step S1: Design a prototype low-pass filter and perform I-fold interpolation on the prototype low-pass filter to increase the sampling rate of the output signal to I times the input sampling rate; Step S2: Perform polyphase decomposition on the interpolated filter, decompose it into I phases, the sampling period of each phase output is the same as the input signal, and the relative delay of each phase filter output is 0, 1 / I, 2 / I, ..., (I-1) / I sampling periods respectively; Step S3: Decompose the fractional delay requirement of the input signal into an integer part and a fractional part. The integer part is achieved by delaying the sampling period, and the fractional part is achieved by using a fractional delay filter. Step S4: Store the coefficients of the I-phase filter as a coefficient array, determine the delay interval of the virtual branch according to the input fractional delay parameter, and calculate the relative normalized offset x. Step S5: Use polynomial interpolation to fit the filter coefficients of the virtual branch from the coefficient array, and configure the fitted coefficients into the configurable coefficient FIR filter to form a fractional delay filter. Step S6: Design the fractional delay filter as a high-speed parallel filter structure, converting serial computation into L-way parallel computation to meet the needs of high-speed multi-channel input data processing.

[0010] Beneficial effects: By combining polyphase decomposition and polynomial interpolation, a single-path configurable filter replaces the multi-path parallel structure, reducing the computational load to approximately 1 / (M+1) of the traditional FARROW structure, where M is the order of the polynomial fitted to the FARROW filter. At the same time, it breaks through the accuracy limitations of the polyphase gating method, achieving a balance between low complexity and high accuracy. Through parallel design, the single-path structure is adapted to high-speed multi-path scenarios, solving the problem of excessive resource consumption in high-speed environments in existing technologies.

[0011] This invention enables high-precision variable decimal delay control in high-speed multi-channel parallel scenarios using a single-channel configurable filter structure with low complexity and low computational load.

[0012] Preferably, I in I-times interpolation is 4, that is, 4-times interpolation is performed, and the relative delays of each phase after multiphase decomposition are 0, 0.25, 0.5, and 0.75 sampling periods, respectively.

[0013] Beneficial effects: 4x interpolation is the optimal balance between computational load and accuracy. Under these parameters, the computational load of this scheme is about 25% of that of the traditional FARROW structure, while ensuring sufficient base point density to obtain high-precision interpolation results.

[0014] Preferably, the polynomial interpolation method uses the third-order Newton interpolation method, given 4 points. Its third-order Newton interpolation polynomial is:

[0015] in The representative difference quotient, with the x-coordinates of the four base points evenly spaced and normalized to 1, is set as follows: ,when The range is At that time, there are two base point constraints on each side of the estimation point, resulting in high estimation accuracy.

[0016] Beneficial effects: Newton interpolation has the characteristics that the difference quotient can be calculated recursively and that no coefficients need to be recalculated when adding a new base point, which is convenient for hardware implementation; the dynamic base point selection (-1,0,1,2) makes the interpolation interval [0,1] located in the middle position, with sufficient base points on both sides, which has better numerical stability than fixed base points, and is particularly suitable for FPGA fixed-point operation environment.

[0017] Preferably, the calculation process for the difference quotient is as follows: The result of the first-order difference quotient calculation is as follows:

[0018]

[0019]

[0020] The result of the second-order difference quotient calculation is:

[0021]

[0022] The result of the third-order difference quotient calculation is as follows:

[0023] Final fitting result: .

[0024] Beneficial effects: By pre-deriving the explicit expression of the difference quotient, the division operation is transformed into a division with constants (2, 6). In FPGA implementation, it can be further optimized into shift and addition operations, which greatly reduces the complexity of real-time calculation and enables coefficient updates to be completed within a single clock cycle.

[0025] Preferably, decomposing the input delay into an integer part and a fractional part includes: After multiplying the relative period of the decimal delay by I, the integer part is 0. (I-1) corresponds to the base point position, that is, to determine which phase the virtual branch is located in in the multiphase decomposition; its fractional part is used as the offset x required for polynomial calculation, and N3(x) is calculated after determining the coefficients of group I and the offset x.

[0026] Beneficial effects: The time delay decomposition naturally corresponds to the multiphase structure, the integer part is directly mapped to the multiphase position, and the fractional part is finely adjusted through interpolation. The decomposition method is highly compatible with the filter structure, simplifying the control logic.

[0027] Preferably, converting serial computation into L-way parallel computation includes: The coefficients and input data of the single-channel FIR filter are rearranged according to the L-channel parallel architecture. Using polyphase decomposition or fast parallel FIR algorithm, the L-channel input data are multiplied and added with the corresponding filter coefficient groups in the same clock cycle, and the L-channel delay results are output in parallel.

[0028] Beneficial effects: Without changing the single-channel filter coefficient generation logic, the parallel reorganization of data flow and coefficients enables the originally serially processed single-channel filter to adapt to the data throughput requirements of L times speed, avoiding the waste of resources in traditional solutions.

[0029] Preferably, the single-channel configurable coefficient FIR filter has an asymmetric structure, and its coefficients are updated in real time according to the polynomial interpolation results. The filter order is equal to the number of coefficients K of each phase after the polyphase decomposition of the prototype filter.

[0030] Beneficial effects: The filter order is only 1 / I of the prototype filter, which further reduces the single-channel computation. The simple structure facilitates pipeline design and can improve the maximum operating frequency.

[0031] Preferably, the sampling period delay is implemented through a register chain or RAM / FIFO.

[0032] Beneficial effects: The implementation method can be flexibly selected according to the size of the integer delay value. For small delays, register chains can be used to obtain the lowest latency and the simplest control, while for large delays, RAM / FIFO can significantly save register resources, thus maximizing the resource efficiency of the integer delay module.

[0033] Preferably, the method further includes: the virtual filter coefficients are processed using fixed-point methods, and the bit width of the fixed-point coefficients is determined according to the bit width of the FPGA's DSP unit and the system accuracy requirements.

[0034] Beneficial effects: By employing a targeted coefficient quantization strategy, the fitted coefficients are directly adapted to the FPGA fixed-point arithmetic architecture, avoiding the resource consumption and timing pressure caused by floating-point operations; at the same time, a balance is achieved between accuracy and resources through reasonable bit width design, ensuring that the quantization error is controlled within the system's allowable range.

[0035] Preferably, the array signal delay system, broadband radar signal simulation system, or satellite navigation and communication system implemented in FPGA are used, and the input signal is a multi-channel parallel digital signal after analog-to-digital conversion, with the processing clock frequency of each signal being 1 / L of the total sampling rate of the system.

[0036] Beneficial effects: The design is optimized for FPGA hardware characteristics and high-speed multi-channel signal processing scenarios. It makes full use of the parallel computing capabilities, reconfigurability and abundant DSP resources of FPGA to achieve high-performance delay control with picosecond-level delay accuracy and gigahertz-level data throughput on resource-constrained embedded platforms, which has important engineering application value.

[0037] (a) Advantages of the present invention This invention achieves a unified approach to low complexity, high precision, and high speed by deeply integrating polyphase filter decomposition and polynomial interpolation fitting, and by innovatively extending the single-path structure to high-speed parallel scenarios. Specific advantages include: First, the computational load is significantly reduced. For a 4-phase decomposition structure, this scheme only requires implementing one configurable filter. Under the same 3rd-order fitting polynomial conditions, the computational load is approximately 25% of that of the traditional FARROW structure. Compared to interpolation methods with multiple fixed filters, this avoids the waste of resources caused by multiple fixed branches running simultaneously.

[0038] Second, the delay accuracy is not limited by the number of phases. The accuracy of traditional multiphase gating methods is locked at T / I, while this invention uses polynomial interpolation to virtually create arbitrary decimal positions between adjacent phases. Under the same prototype filter design, the accuracy depends only on the interpolation order and the number of quantization bits of the coefficients, and can easily reach T / (100×I) or even higher.

[0039] Third, high-speed multi-channel adaptation. High-speed multi-channel filters consume twice the resources compared to basic filters. FARROW filters and multi-channel fixed-gated interpolation filters have complex structures, making their high-speed design more complex and resource-intensive. In contrast, this invention uses only a single-channel virtual filter, reducing the "cardinality" and thus offering greater resource advantages in high-speed multi-channel applications.

[0040] (ii) Compared with the prior art, the present invention solves the technical problem in an unexpected way. Current technologies generally consider high-precision delay and low complexity to be an irreconcilable contradiction—achieving high precision requires more filter branches or higher polynomial orders, inevitably leading to increased complexity; reducing complexity requires reducing the number of branches, inevitably sacrificing precision. Meanwhile, high-speed multi-channel parallel processing is often seen as a modified copy of a single-channel structure, and the exponential increase in resource consumption is taken for granted.

[0041] This invention overcomes the aforementioned technical biases: by extracting an equally divided uniform delay coefficient array through polyphase decomposition as interpolation base points, and then using polynomial interpolation to "virtually" generate filter coefficients at arbitrary positions, arbitrary fractional delays can be achieved by configuring only a single-channel filter. This "polyphase extraction + single-channel reconstruction" approach unifies high precision and low complexity. Its simple data processing flow facilitates pipeline optimization and is better suited for high clock frequency processing. Furthermore, due to the simplified structure, single-channel filter resources are reduced, resulting in a more significant resource advantage in high-speed multi-channel applications.

[0042] (III) The unexpected nature of the technical means of this invention This invention features two unconventional design elements that produce unexpected results: First, the Newton interpolation with dynamic base point selection. Traditional interpolation uses four fixed base points, with an x-offset range equivalent to [-1, 3] in this scheme. When the fitted point falls outside the [0, 1] interval, the fitting accuracy decreases, especially in the [2, 3] interval where there are no base points on the right, resulting in a greater decrease in accuracy. This invention deliberately selects dynamic base points (-1, 0, 1, 2), always using the "previous phase" of the current delay interval as base point 0 and the "next phase" as base point 1. This design places the interpolation interval [0, 1] at the center of the base points, providing stronger extrapolation constraints on the left (-1, 0) and right (1, 2), resulting in more stable interpolation characteristics within the [0, 1] interval. Experiments show that this dynamic base point selection significantly improves numerical stability in FPGA fixed-point computing environments compared to the fixed baseband scheme, effectively suppressing coefficient fitting errors.

[0043] Second, the parallelization strategy of decomposition followed by merging. Traditional parallelization approaches involve replicating multiple paths and processing them separately. This invention, however, first performs multi-phase decomposition to extract coefficients, then performs single-path interpolation fitting, and finally expands the parallelization. This three-stage strategy of decomposition, reconstruction, and expansion postpones parallelization to the simplest single-path structure stage, avoiding the resource explosion problem of parallel expansion in complex multi-path stages, and minimizing the cost of high-speed adaptation. Attached Figure Description

[0044] Figure 1 This is a diagram showing the amplitude-frequency response characteristics of the prototype filter of this invention.

[0045] Figure 2 This is a block diagram of the delay processing structure of the present invention.

[0046] Figure 3 This is a schematic diagram of the prototype filter polyphase decomposition and virtual filter generation of the present invention.

[0047] Figure 4 This is a schematic diagram of the dynamic base point method for fitting filter coefficients according to the present invention.

[0048] Figure 5 This is a schematic diagram of the implementation structure of the two-input high-speed filter of the present invention.

[0049] Figure 6 This is a schematic diagram of the four-input high-speed filter implementation structure of the present invention. Detailed Implementation

[0050] The following detailed description illustrates the specific implementation method: This invention provides a low-complexity, high-precision delay method based on polyphase filter interpolation. Taking FPGA high-speed signal processing as a typical application scenario, this method achieves low-complexity, high-precision, and high-speed fractional delay control through a complete process of "prototype filter design → polyphase decomposition → coefficient array storage → delay decomposition → polynomial interpolation fitting → coefficient configuration → single-path filtering or high-speed parallel filtering".

[0051] Specifically, firstly, based on the system bandwidth and delay accuracy requirements, a prototype low-pass filter with 4x interpolation is designed. This prototype filter increases the sampling rate of the output signal to four times the input sampling rate, ensuring no aliasing in the signal spectrum after interpolation. Subsequently, the interpolation filter is decomposed into four phases, with the sampling period of each phase output consistent with the input signal, and the relative delays of each phase filter output being 0, 0.25, 0.5, and 0.75 sampling periods, respectively. Each of these four phase filters corresponds to a set of filter coefficients, collectively forming a coefficient array of four sets of coefficients, which is stored in memory for later retrieval.

[0052] When delay control is required, the system converts the input delay requirement into a multiple of the input signal sampling period and decomposes it into an integer part and a fractional part. The integer part is implemented through a sampling period delay, which can be implemented using a register chain or RAM / FIFO in an FPGA; the fractional part needs to be finely implemented using a fractional delay filter. For the fractional part, the system first multiplies it by 4, and its integer part is 0. 3. The multiphase position of the virtual branch is determined (i.e., which set in the coefficient array is selected as the interpolation base point), and its fractional part is used as the normalized offset x required for polynomial interpolation.

[0053] During the coefficient fitting stage, the system employs third-order Newton interpolation, selecting the four sets of coefficients closest to the virtual branch position from the coefficient array as interpolation base points. The x-coordinates of these four base points are equally spaced and normalized to 1, set as (x0=-1, x1=0, x2=1, x3=2), ensuring that when the offset x is within 0... Within a range of 1, there are two base point constraints on each side of the estimation point, resulting in high interpolation accuracy. By using the pre-derived explicit formulas for the first, second, and third order difference quotients, the coefficients of each term in the Newton interpolation polynomial are calculated, and then the filter coefficients of the virtual branch are fitted.

[0054] The fitted coefficients are configured in real time into a single-path configurable asymmetric FIR filter, forming a fractional delay filter. The input signal enters this fractional delay filter after an integer delay, and the output yields the accurate fractional delay result. Because this filter has only one branch and the coefficients can be dynamically updated, its structure is extremely simple, and the computational load is far lower than that of traditional FARROW structures or multiple fixed filter structures.

[0055] To meet the demands of high-speed, multi-channel parallel processing, this single-channel fractional delay filter is further parallelized through a high-speed parallel conversion module. Specifically, the coefficients and input data of the single-channel FIR filter are rearranged according to an L-channel parallel architecture. Using polyphase decomposition or a fast parallel FIR algorithm, the L input data are multiplied and added with their corresponding filter coefficient groups within the same clock cycle, resulting in the parallel output of L delay results. This conversion process only involves the reorganization of the data stream and coefficients, without altering the core operational logic of the filter. Therefore, it can maintain the advantage of low complexity in a single channel while meeting the requirements of high-speed data throughput.

[0056] Differences and advantages compared to prior art documents and conventional techniques in the field: Comparison document 1: CN118316420B (A high-precision variable time delay control method) Differences: First, the structures are fundamentally different. Comparative document 1 employs a three-stage cascade structure: "integer delay FIFO + multiple parallel fixed delay filters + multiple parallel Lagrange interpolation filters." The fractional-sampling-point delay filter bank contains multiple parallel fixed delay filters, and the fractional-sampling-point variable delay filter bank contains multiple parallel Lagrange interpolation filters; essentially, it is still a multi-path parallel operation structure. This invention, however, adopts a "single-path configurable coefficient FIR filter" structure. Coefficients are generated in real-time through polynomial interpolation and configured to this single-path filter, eliminating the need for parallel operation of multiple branch filters.

[0057] Second, the methods for obtaining the interpolation base points are different. The Lagrange interpolation in Comparison Document 1 interpolates the "output results of four fixed-delay filters with adjacent steps", that is, the interpolation object is the output signal of multiple filters; the Newton interpolation of this invention interpolates the "coefficient array after polyphase decomposition", that is, the interpolation object is the filter coefficients rather than the signal, and the interpolation result directly generates new filter coefficients.

[0058] Third, the high-speed multi-path adaptation methods differ. Comparative document 1 does not address multi-path parallel processing; methods based on FARROW filters and interpolation using multiple fixed filters cannot be easily extended, making high-speed multi-path designs more complex and resource-intensive. Furthermore, the implementation method for multiphase filter branch gating is not mentioned in the context of high-speed multi-path processing. This invention explicitly designs a high-speed parallel conversion module, further expanding its resource-saving advantages.

[0059] Advantages: The computational complexity of this invention is significantly lower than that of Comparative Document 1. Comparative Document 1 requires running multiple fixed-delay filters (seven 8th-order filters in this example) during the fractional-number fixed-delay stage, and four Lagrange interpolation filters during the fractional-number variable-delay stage, resulting in a massive overall computational load. This invention only requires running one K-order configurable filter (K ​​being one-quarter of the order of the prototype filter), with a computational load approximately one-quarter to one-seventh that of Comparative Document 1. In high-speed, multi-channel scenarios, the resource-saving advantage is further amplified.

[0060] Comparison document 2: CN111367196A (W-band broadband variable fractional delay method and system) Differences: First, the core structures are different. Comparison document 2 is based on the FARROW structure, optimizing the resource consumption of the multi-path parallel FARROW structure through "split matrix weighting" and the "fast parallel FIR algorithm." Its essence remains a FARROW structure, requiring all multiphase branches to participate in the computation. This invention fundamentally abandons the FARROW structure, adopting a new paradigm of multiphase decomposition coefficient extraction + single-path interpolation fitting, eliminating the need for multiple branches to run simultaneously.

[0061] Second, the optimization objectives are different. The optimization in Comparison Document 2 is to "reduce the number of multipliers while retaining the FARROW structure," which is a local optimization at the structural level; this invention reconstructs the delay implementation principle at the algorithm level, transforming "multi-path parallel computing" into "single-path coefficient configuration," resulting in a more thorough optimization.

[0062] Third, the interpolation methods are different. Comparison document 2 uses Lagrange interpolation to solve for the FARROW coefficients, while this invention uses Newton interpolation to fit virtual coefficients from a multiphase coefficient array. The mathematical foundations and application scenarios are different.

[0063] Advantages: Compared to prior art document 2, this invention offers a simpler structure and clearer control logic while maintaining the same level of precision. Prior art document 2's "three-dimensional FARROW structure" and "splitting matrix weighting" involve complex matrix operations and coefficient mapping, making implementation difficult. In contrast, the configurable filter structure of this invention is intuitive and straightforward; coefficient updates require only simple polynomial calculations, making timing convergence easier to achieve on FPGAs. Furthermore, this invention avoids the inherent "all branches participate in the calculation" characteristic of the FARROW structure, resulting in a lower lower limit to computational complexity.

[0064] Comparison document 3: CN108768343A (High-precision delay method based on polyphase filter) Differences: First, the delay accuracy mechanisms differ. Comparative document 3 achieves delay through a single output of a multiphase filter using a "switch gating" mechanism, with accuracy strictly limited to T / I (where I is the number of phases), which is a "discrete gating" mechanism. This invention, however, uses polynomial interpolation to fit virtual coefficients between adjacent phases, achieving accuracy far exceeding T / I, which is a "continuous fitting" mechanism.

[0065] Second, the filter operation methods are different. Pj(k) in comparison document 3 is a fixed-coefficient filter, which does not change after selection; the filter coefficients of this invention are updated in real time according to the delay requirements, and have continuous variable capability.

[0066] Third, their high-speed adaptation capabilities differ. Comparison document 3 does not cover multi-path parallel processing.

[0067] Advantages: This invention overcomes the accuracy bottleneck of prior art document 3. To achieve the accuracy of this invention, prior art document 3 requires increasing the phase number I by a factor of 100, resulting in a simultaneous increase in filter order and complexity. This invention, while maintaining a low phase number (e.g., I=4), improves accuracy by more than two orders of magnitude through interpolation, achieving a balance between "low phase number and high accuracy." Furthermore, the continuously variable capability of this invention makes it suitable for scenarios with dynamically changing delays, while prior art document 3 is only applicable to fixed-delay applications.

[0068] Conventional techniques in this field When faced with high-speed, multi-channel, high-precision delay requirements, those skilled in the art typically employ the following approach: select a FARROW structure or multiple fixed filter structures as a base, optimize the single-channel structure using a fast parallel FIR algorithm, and then replicate it. This linear expansion approach of "designing a single channel first, then replicating multiple channels" results in resource consumption being directly proportional to the number of parallel channels.

[0069] The specific implementation process of this invention is as follows: like Figure 1 As shown, a prototype filter is designed based on the bandwidth. For real signals, the classic bandwidth is 0.4 times the sampling rate, which means the normalized cutoff frequency is 0.8 (in filter design, half of the sampling rate is generally normalized to 1). The passband normalized cutoff frequency of the 4x interpolation filter is designed to be 0.8 / 4 = 0.2. To ensure image suppression during interpolation, the stopband normalized cutoff frequency needs to be designed to be 0.5 - 0.2 = 0.3 (0.5 being the zero-point position). Furthermore, since the sampling rate is restored after 4x decimation, the interpolated image signal and the original signal will be aliased. To reduce aliasing, the stopband rejection should be designed to be >60dB. Based on these parameters, tools can be used for filter design. like Figure 3As shown, the prototype filter coefficients are fixed-point quantized and stored in 4 groups; 18 bits are sufficient for quantization; The coefficients are decomposed into 4 groups according to the polyphase structure. If the original signal coefficients are not integer multiples of 4, they are padded with zeros to make them integer multiples of 4. like Figure 2 As shown, after receiving the delay, the FPGA converts it into the number of sampling periods, then decomposes it into an integer part and a fractional part. The integer part is sent directly to the integer delay unit.

[0070] The relative periodic delay of the fractional part is 0. 1. Multiplying it by 4 results in an integer part of 0. 3 corresponds to the base point position (which phase of the multiphase it is located in); while the fractional part is the offset x required for polynomial calculation. The four sets of coefficients are extracted through the structure shown in the figure, and the set of coefficients after offset x is calculated in sequence according to Newton's interpolation method. The set of coefficients is then sent to the fractional delay unit. like Figure 1-4 As shown, the integer delay timer delays based on the sampling period. When implemented using an FPGA, it can be implemented using a register or RAM. When implemented in software, it can be padded with zeros at the beginning. The fractional delay is a set of conventional FIR filters with asymmetric coefficients. Since the filter coefficients after polyphase decomposition have an asymmetric structure, the fitted result is also asymmetric.

[0071] Figure 4 This diagram illustrates the fitting of filter coefficients using a dynamic base-point method. The diagram clearly shows how Newton interpolation, calculated using four adjacent points, fits and ultimately forms the four sets of coefficients for the polyphase filter.

[0072] Figure 5 This is a schematic diagram of the implementation structure of the two-input high-speed filter of the present invention. This structure is equivalent to twice the speed of the original filter (although there are a total of 4 paths, the coefficients of each path are reduced by half).

[0073] Figure 6 This is a schematic diagram of the implementation structure of the four-input high-speed filter of the present invention. This structure is equivalent to 4 times the processing speed of the original filter (although there are 16 channels in total, the coefficient of each channel is reduced by 3 / 4).

[0074] Effects and advantages of the embodiments Example 1: Single-path implementation of 4-phase decomposition + 3rd-order Newton interpolation With a 4-phase decomposition and 3rd-order Newton interpolation configuration, this scheme only requires the implementation of one configurable coefficient FIR filter, with a computational load of approximately 25% of that of the traditional FARROW structure. The delay accuracy can reach less than 1 / 1000 of the sampling period, which is more than two orders of magnitude higher than the 1 / 4 sampling period accuracy of the multiphase gating method.

[0075] Example 2: Multi-path parallel high-speed adaptation The single-channel structure of Embodiment 1 is expanded into a 4-channel parallel structure using a high-speed parallel conversion module, capable of processing a 1.0 Gsps data stream at a 250 MHz clock. Compared to the traditional approach of "copying four complete structures," the multiplier resource consumption of this invention is significantly reduced compared to FARROW filters and multiple fixed filters plus interpolation resources, and the control logic is simpler, with easier timing convergence. In other embodiments, higher sampling rates such as 8 or 16 channels can be supported, but the filter structure will be adapted accordingly for different numbers of channels.

[0076] The above are merely embodiments of the present invention. Commonly known technical solutions and / or characteristics are not described in detail here. It should be noted that those skilled in the art can make various modifications and improvements without departing from the technical solution of the present invention, and these should also be considered within the scope of protection of the present invention. These modifications and improvements will not affect the effectiveness of the implementation of the present invention or the practicality of the patent. The scope of protection claimed in this application should be determined by the content of its claims, and the specific embodiments described in the specification can be used to interpret the content of the claims.

Claims

1. A low-complexity, high-precision delay method based on polyphase filter interpolation, characterized in that, Includes the following steps: Step S1: Design a prototype low-pass filter and perform I-fold interpolation on the prototype low-pass filter to increase the sampling rate of the output signal to I times the input sampling rate; Step S2: Perform polyphase decomposition on the interpolated filter, decompose it into I phases, the sampling period of each phase output is the same as the input signal, and the relative delay of each phase filter output is 0, 1 / I, 2 / I, ..., (I-1) / I sampling periods respectively; Step S3: Decompose the fractional delay requirement of the input signal into an integer part and a fractional part. The integer part is achieved by delaying the sampling period, and the fractional part is achieved by using a fractional delay filter. Step S4: Store the coefficients of the I-phase filter as a coefficient array, determine the delay interval of the virtual branch according to the input fractional delay parameter, and calculate the relative normalized offset x. Step S5: Use polynomial interpolation to fit the filter coefficients of the virtual branch from the coefficient array, and configure the fitted coefficients into the configurable coefficient FIR filter to form a fractional delay filter. Step S6: Design the fractional delay filter as a high-speed parallel filter structure, converting serial computation into L-way parallel computation to meet the needs of high-speed multi-channel input data processing.

2. The method according to claim 1, characterized in that, In I-times interpolation, I is 4, meaning a 4-times interpolation is performed. After multiphase decomposition, the relative delays of each phase are 0, 0.25, 0.5, and 0.75 sampling periods, respectively.

3. The method according to claim 1 or 2, characterized in that, The polynomial interpolation method uses the third-order Newton interpolation method, given 4 points. Its third-order Newton interpolation polynomial is: in The representative difference quotient, with the x-coordinates of the four base points evenly spaced and normalized to 1, is set as follows: ,when The range is At that time, there are two base point constraints on each side of the estimation point, resulting in high estimation accuracy.

4. The method according to claim 3, characterized in that, The calculation process for the difference quotient is as follows: The result of the first-order difference quotient calculation is as follows: The result of the second-order difference quotient calculation is: The result of the third-order difference quotient calculation is as follows: Final fitting result: .

5. The method according to claim 1, characterized in that, Decomposing the input delay into integer and fractional parts includes: After multiplying the relative period of the fractional delay by I, the integer part is 0. (I-1) corresponds to the base point position, that is, to determine which phase the virtual branch is located in in the multiphase decomposition; its fractional part is used as the offset x required for polynomial calculation, and N3(x) is calculated after determining the coefficients of group I and the offset x.

6. The method according to claim 1, characterized in that, Converting serial computation to L-way parallel computation includes: The coefficients and input data of the single-channel FIR filter are rearranged according to the L-channel parallel architecture. Using polyphase decomposition or fast parallel FIR algorithm, the L-channel input data are multiplied and added with the corresponding filter coefficient groups in the same clock cycle, and the L-channel delay results are output in parallel.

7. The method according to claim 1, characterized in that, A single-channel configurable coefficient FIR filter has an asymmetric structure. Its coefficients are updated in real time based on the polynomial interpolation results. The filter order is equal to the number of coefficients K of each phase after the polyphase decomposition of the prototype filter.

8. The method according to claim 1, characterized in that, The sampling period delay is implemented through register chains or RAM / FIFO.

9. The method according to claim 1, characterized in that, Also includes: The virtual filter coefficients are processed using fixed-point methods, and the bit width of the fixed-point coefficients is determined based on the bit width of the FPGA's DSP unit and the system accuracy requirements.

10. The method according to claim 1, characterized in that, It is used in array signal delay systems, broadband radar signal simulation systems or satellite navigation and communication systems implemented in FPGA. The input signal is a multi-channel parallel digital signal after analog-to-digital conversion. The processing clock frequency of each signal is 1 / L of the total sampling rate of the system.

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