A CMOS analog switch on control method

Abstract

The application discloses a CMOS analog switch opening control method, and relates to the technical field of CMOS analog switch circuit control. The method performs pre-opening static bias calibration on paired NMOS and PMOS switch tubes, collects real-time parameters, and establishes a reference mapping relationship of device static working points; a multi-step gate opening pulse timing is generated, which is divided into three continuous timing stages of pre-charging, linear rising and steady-state locking; the gate voltages of the two tubes are synchronously controlled in each stage to start a gate voltage dynamic clamping mechanism; the opening process is corrected by closed-loop feedback of timing and voltage parameters; and after the opening is completed, the gate voltage dynamic fine adjustment of the steady-state conduction stage is performed. The application controls the channel charge injection through the multi-step timing, improves the opening control precision through the closed-loop feedback, guarantees the steady-state working stability through the two-stage clamping mechanism, and improves the switch conduction linearity and opening consistency through the parameter adaptation of the whole process, so that the application can be adapted to complex working conditions of wide temperature range and wide power voltage.

Description

Technical Field

[0001] This invention relates to the field of CMOS analog switch circuit control technology, and in particular to a CMOS analog switch turn-on control method. Background Technology

[0002] CMOS analog switches, as core devices for switching analog signal paths, are widely used in integrated circuit systems such as high-precision data acquisition, analog front-end signal processing, RF communication, and industrial measurement and control. Their dynamic performance during the turn-on process directly determines the signal transmission accuracy, linearity, and anti-interference capability of the entire system. With the continuous advancement of integrated circuit manufacturing processes and the shrinking feature sizes, the channel length and gate oxide thickness of CMOS switches are decreasing. This leads to increasingly prominent issues during the turn-on process, such as channel charge injection, clock feedthrough, and nonlinear fluctuations in on-resistance, becoming core bottlenecks restricting the performance improvement of CMOS analog switches. In high-precision and high-stability applications, charge injection during the turn-on process causes a level shift at the switch port, directly resulting in signal distortion. Nonlinear changes in on-resistance introduce harmonic interference, compromising signal integrity. Existing turn-on control schemes struggle to simultaneously meet the multiple requirements of turn-on speed, charge injection suppression, and on-resistance linearity.

[0003] In existing technologies, the turn-on control of CMOS analog switches mostly adopts a single-stage gate voltage transition control method, directly switching the gate voltage of the switch to the steady-state turn-on value. This method has simple control logic and convenient circuit implementation, but it generates severe channel charge injection and clock feedthrough effects at the turn-on moment, which cannot meet the application requirements of high-precision systems. Some improved solutions adopt a simple step-by-step turn-on control method, dividing the gate turn-on voltage into two stages of output, which alleviates the charge injection problem to some extent. However, the timing parameters and voltage amplitudes of these solutions are mostly fixed, which cannot adapt to changes in device characteristics under different ambient temperatures, system power supply voltages, and port load capacitances. In wide temperature range and wide power supply voltage application scenarios, the turn-on control effect will deteriorate significantly. At the same time, existing solutions do not finely control the nonlinear changes in conduction resistance during the turn-on process. The sudden change in conduction resistance during the turn-on process will cause signal distortion, especially in high-frequency signal switching scenarios, which will seriously affect the dynamic performance of the system. Furthermore, most existing turn-on control schemes adopt open-loop control logic, which can only complete the turn-on action according to the preset timing sequence. They cannot dynamically correct the control parameters according to the real-time operating status of the device. They lack effective compensation mechanisms for process deviations caused by chip manufacturing and characteristic aging caused by long-term operation of the device. This results in poor turn-on consistency of devices in the same batch and the performance stability of the device throughout its entire life cycle cannot be guaranteed. The corresponding gate voltage protection mechanism also mostly adopts a single threshold design, which cannot take into account the response speed of voltage correction and control stability. It is prone to problems such as untimely overshoot correction or noise false triggering, which further limits the application of CMOS analog switches in complex operating conditions. Summary of the Invention

[0004] This invention proposes a CMOS analog switch turn-on control method to solve the problems mentioned in the prior art.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a CMOS analog switch turn-on control method, comprising the following steps: Pre-enable static bias calibration is performed on the paired NMOS and PMOS switches in the CMOS analog switch. Real-time parameters such as ambient temperature, power supply voltage, load capacitance, and substrate bias voltage are collected. A reference mapping relationship between the static operating point and the relevant parameters is established by fitting and completing the correction of the resulting operating point offset. Based on the real-time parameter and reference mapping relationship, a multi-step gate turn-on pulse timing sequence is generated, which is divided into three continuous timing stages: pre-charge, linear rise, and steady-state lockout. The duration and voltage amplitude of each stage are matched to the current device and operating conditions. During the pre-charge step stage, a pre-charge bias voltage is applied synchronously to the gates of both transistors to form a uniform weak inversion layer and pre-charge the gate parasitic capacitance. In the linear rise step stage, the NMOS gate voltage is linearly increased and the PMOS gate voltage is decreased according to a preset slope, and the gate-source voltage difference is adjusted synchronously to suppress nonlinear fluctuations in on-resistance and distortion of transmission signals. In the steady-state lockout step stage, after the two transistors enter the stable strong inversion region, they lock the gate voltage to the steady-state turn-on value and start the gate voltage dynamic clamping mechanism to suppress voltage overshoot and undershoot caused by power supply fluctuations and load changes. Throughout the entire startup process, parameters are collected at a fixed frequency, and the timing parameters and voltage amplitude of each step are corrected in real time through closed-loop feedback. After startup, the on-resistance and channel charge distribution are continuously monitored, and the gate voltage is dynamically fine-tuned to maintain low on-resistance and high linearity steady-state operation, compensating for the impact of device characteristic aging on conduction performance.

[0006] Furthermore, before generating the multi-step gate turn-on pulse timing sequence, the duration of the pre-charge step is adaptively matched. Based on the device's gate-source parasitic capacitance, switching load capacitance, and current ambient temperature parameters, an adaptive matching model for the timing duration is constructed. The optimal duration of the pre-charge step is calculated through the model, and segmented calibration of the pre-charge duration is performed simultaneously. Differentiated reference duration parameters are set for CMOS devices at different process nodes. During the pre-charge process, the gate charge accumulation and the formation state of the channel weak inversion layer are monitored in real time, and the pre-charge duration is dynamically fine-tuned. At the same time, a high-temperature gate leakage current compensation mechanism is introduced, adjusting the temperature compensation weight of the pre-charge duration according to the ambient temperature. The calculation expression for the timing duration is as follows: ; This is the reference duration for the pre-charge tiers. The capacitance weighting coefficient is... For the gate-source parasitic capacitance of the switching transistor, For the load capacitor of the switch port, As a reference capacitor, Temperature weighting coefficient, The current ambient temperature. This is the reference temperature.

[0007] Furthermore, during the execution of the gate voltage dynamic clamping mechanism, a two-stage linkage clamping threshold is set. The first stage is the soft clamping threshold. When the deviation between the gate voltage and the steady-state turn-on voltage exceeds 5%, the gate leakage current micro-adjustment circuit is activated, and the soft clamping adaptive adjustment circuit is set simultaneously. The gain coefficient of the micro-adjustment circuit is adjusted according to the power supply voltage fluctuation amplitude. The second stage is the hard clamping threshold. When the deviation between the gate voltage and the steady-state turn-on voltage exceeds 10%, the gate voltage clamping circuit is directly triggered. At the same time, the anti-interference and anti-jitter mechanism of hard clamping is added. The hard clamping action is triggered only when the voltage deviation exceeds the threshold for 3 sampling cycles. The current voltage deviation data is latched simultaneously and incorporated into the parameter correction system of the subsequent closed-loop feedback. At the same time, the seamless connection logic of the two clamping stages is set. When the soft clamping action cannot correct the deviation, the hard clamping is automatically triggered to complete the voltage jump and secondary charge injection suppression during the clamping process.

[0008] Furthermore, this also includes constructing a quantitative evaluation system for on-resistance nonlinearity during the closed-loop feedback correction of timing parameters and voltage amplitude. The quantified value of on-resistance nonlinearity is obtained through multi-dimensional parameter fusion calculation. Based on the deviation between the quantized value and a preset threshold, the slope of the voltage change in the linearly rising step is dynamically corrected. Simultaneously, an adaptive distribution strategy for sampling points is set, with increased sampling points at the beginning and end of the linear rising phase, and the sampling density adjusted according to device characteristics in the intermediate phase. A correlation mapping relationship between nonlinearity and channel charge injection is established synchronously. The calculation expression for on-resistance nonlinearity is as follows: ; This refers to the on-resistance nonlinearity during the turn-on process of a CMOS analog switch. This represents the average value of the on-resistance during the linear rise phase. This represents the number of parameter sampling points during the linear ascent phase. For the first The real-time on-resistance value collected at each sampling point.

[0009] Furthermore, the static bias calibration step also includes real-time acquisition and calibration of the threshold voltages of NMOS and PMOS switches. By applying a millivolt-level test bias voltage to the drain and source of the device, the corresponding microampere-level drain and source current is acquired. The actual threshold voltage of the device under the current operating condition is obtained by fitting the device current-voltage characteristic curve. At the same time, the differential measurement method is used to eliminate the influence of substrate bias effect. The amplitude of the test bias voltage is adaptively adjusted for switches with different aspect ratios. The deviation between the actual threshold voltage and the reference threshold voltage is incorporated into the voltage amplitude calculation system of the multi-step gate turn-on pulse timing. In addition, a fast threshold voltage calibration is performed before each switch is turned on, rather than a single calibration is performed only during the power-on stage. The temperature drift coefficient of the device threshold voltage is pre-stored synchronously.

[0010] Furthermore, in the pre-charge step stage, differential synchronous control is also included for the pre-charge bias voltages of the NMOS and PMOS switches. The timing of the application of the pre-charge voltages of the two switches is synchronously controlled to keep the timing deviation within 500ps. At the same time, the drain-source current of the weak inversion layer in the channel is collected in real time during the pre-charge process, and the pre-charge bias voltage is finely adjusted in a closed loop to complete the formation control of the uniform weak inversion layer in the channel of the two switches. The device substrate bias voltage is adjusted synchronously with the pre-charge bias voltage to complete the threshold voltage offset compensation caused by the substrate bulk effect. At the same time, the level status of the switch port is monitored in real time, and the bias voltage is adjusted immediately when the port level offset exceeds the preset range.

[0011] Furthermore, in the linear rise-step stage, the system also includes synchronous matching control of the gate voltage change slopes of the NMOS and PMOS switches, ensuring that the absolute values ​​of the rising slope of the NMOS switch gate voltage and the falling slope of the PMOS switch gate voltage are completely consistent. This allows the total on-resistance of the CMOS analog switch to decrease smoothly during the turn-on process. Simultaneously, the gate voltage values ​​of the two transistors are sampled every 1 ns to calculate the slope deviation. In addition, the slope is nonlinearly fine-tuned to address the change in channel characteristics from weak inversion to strong inversion. The slope is reduced at the beginning and end of the turn-on process, while maintaining a constant slope in the middle stage. This adapts to the changes in the conduction characteristics of the adapter channel and adaptively adjusts the absolute value of the slope based on the load capacitance at the switch port.

[0012] Furthermore, the quantitative evaluation of on-resistance nonlinearity also includes setting a three-level linkage nonlinearity control threshold. When the nonlinearity quantification value is below 1%, the voltage change slope of the current linear rise step remains unchanged. When the nonlinearity quantification value is within the range of 1% to 3%, the voltage change slope is reduced by a fixed step size. When the nonlinearity quantification value is above 3%, the linear rise process is immediately paused, the device's static operating point is recalibrated, and the process is resumed. At the same time, the range of the three-level threshold is adaptively adjusted for different ambient temperatures. The threshold range is tightened under high temperature conditions and appropriately relaxed under low temperature conditions. The temperature drift change of the adapter device characteristics is also considered. After the nonlinearity exceeds the threshold, multi-dimensional parameters such as gate voltage, drain-source current, and threshold voltage are collected simultaneously to complete fault tracing and locate the core cause of the nonlinearity exceeding the standard. At the same time, a fast recovery mechanism is set after the pause. After recalibration, a smoother slope is used to gradually restore the linear rise process, and historical data of nonlinearity are statistically analyzed.

[0013] Furthermore, the closed-loop feedback step in the startup process also includes an adaptive adjustment mechanism for the sampling frequency. During the dynamic change phases of the pre-charging ladder and the linear ascending ladder, the parameter sampling frequency is set to 1GHz. During the stable phase of the steady-state locking ladder, the parameter sampling frequency is reduced to 100MHz. This reduces the dynamic power consumption and switching noise of the control circuit while ensuring monitoring accuracy. At the same time, a multi-sampling channel parallel operation mode is adopted. In the high-frequency sampling phase, a moving average digital filtering process is added to suppress parameter miscorrection caused by sampling noise. In the low-frequency sampling phase, a parameter abnormal jump monitoring mechanism is set up. When a parameter change is detected, the mode is immediately switched back to high-frequency sampling mode. In addition, for low-power scenarios powered by batteries, the sampling frequency in the steady-state phase is further reduced to balance monitoring accuracy and system power consumption.

[0014] Furthermore, in the steady-state turn-on dynamic fine-tuning step after turn-on, the device's real-time on-resistance, channel charge distribution, and drain-source voltage parameters are collected every 100μs. When the change in on-resistance exceeds 2%, the gate steady-state turn-on voltage is finely adjusted within a range of ±50mV. Simultaneously, a single-step fine-tuning step size of no more than 10mV is set. The entire operating temperature range of -40℃ to 125℃ is divided into five consecutive temperature segments, each with independent fine-tuning reference parameters. These parameters are also based on the device's cumulative turn-on time and historical turn-on voltage. By using resistance variation data, a device aging compensation model is established, and the threshold and step size of fine-tuning are dynamically adjusted to offset the performance degradation caused by the characteristic aging of the device during long-term operation. For multi-channel CMOS analog switch arrays, synchronous steady-state fine-tuning is performed to control the consistency of conduction resistance between channels. At the same time, the integrity of the switch transmission signal is monitored in real time during the fine-tuning process. When signal distortion is detected, the fine-tuning is immediately paused and restored to the reference gate voltage, thus completing the continuous maintenance of low conduction resistance and high linearity conduction state of CMOS analog switches across the entire temperature range and the entire power supply voltage fluctuation range.

[0015] Compared with existing technologies, the beneficial effects of this invention are: This invention, through the design of a multi-step gate turn-on pulse timing sequence, divides the turn-on process of a CMOS analog switch into three consecutive timing stages. This timing-based approach effectively suppresses channel charge injection and clock feedthrough effects, reduces the level offset at the switch port during turn-on, and minimizes signal transmission distortion. By employing a static bias calibration step before pre-turn-on, a baseline mapping relationship is established between the device's static operating point and environmental and electrical parameters. This corrects for operating point offsets caused by process deviations, temperature drift, and substrate bulk effects, improving the adaptability of turn-on control under different operating conditions and ensuring consistency in the turn-on process for different devices and operating environments.

[0016] This invention utilizes differential synchronization control during the pre-charge staircase stage to ensure that paired NMOS and PMOS switches synchronously form a uniform weak inversion layer. Simultaneously, it pre-charges the gate parasitic capacitance, shortening the device's turn-on response delay and avoiding signal crosstalk issues caused by premature turn-on of a single transistor. During the linear rise staircase stage, synchronous matching control of the gate voltage change slope ensures uniform widening of the device's conduction channel, effectively reducing nonlinear fluctuations in on-resistance during turn-on, minimizing harmonic interference caused by sudden changes in on-resistance, and improving the integrity of signal transmission during turn-on.

[0017] This invention effectively suppresses gate voltage overshoot and undershoot through a two-stage linked dynamic gate voltage clamping mechanism, avoiding the risk of gate oxide breakdown. Simultaneously, its anti-interference and anti-jitter design prevents false triggering caused by noise, improving operational stability during the turn-on steady-state lock-in phase. Through a closed-loop feedback chain throughout the entire turn-on process, timing and voltage parameters can be dynamically corrected based on real-time device operating parameters, effectively adapting to real-time changes in device characteristics. Furthermore, combined with a quantitative evaluation system for on-resistance nonlinearity, stable control of on-resistance linearity is achieved during the turn-on process.

[0018] This invention, through dynamic fine-tuning of the gate voltage during the steady-state conduction phase and combined with a device aging compensation model, offsets the performance degradation caused by the aging of the device's long-term operating characteristics. It achieves continuous maintenance of low on-resistance and high linearity conduction state throughout the entire life cycle of the device. The accompanying real-time threshold voltage calibration mechanism further improves the accuracy of turn-on control, enabling the CMOS analog switch to maintain stable operating performance under complex operating conditions with a wide temperature range and wide power supply voltage. Attached Figure Description

[0019] Figure 1 This is a schematic block diagram of a CMOS analog switch turn-on control method proposed in this invention; Figure 2 Flowchart of adaptive timing control sub-control for the pre-charging phase; Figure 3 The flowchart for the closed-loop feedback and slope correction in the linear ascent phase is shown below. Figure 4 The flowchart for the dynamic clamping protection sub-process during the steady-state locking phase is shown below. Figure 5 The flowchart for the dynamic fine-tuning of steady-state conduction after startup is shown. Detailed Implementation

[0020] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0022] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they may refer to a fixed connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances. The invention will now be described in further detail with reference to the accompanying drawings.

[0023] Reference Figures 1 to 5 A CMOS analog switch turn-on control method includes the following steps: Static bias calibration is performed on the paired NMOS and PMOS switches in the CMOS analog switch before pre-turn-on. Real-time parameters such as ambient temperature, system power supply voltage, switch port load capacitance, and device substrate bias voltage are collected. A reference mapping relationship between the device static operating point and environmental and electrical parameters is established by fitting, and the static operating point offset caused by process deviation, temperature drift effect, and substrate bulk effect is corrected. Based on the real-time parameters and the reference mapping relationship, a multi-step gate turn-on pulse timing sequence is generated. The output process of the gate turn-on voltage is divided into three continuous and time-free timing stages: pre-charge step, linear rise step, and steady-state lock-in step. The duration and voltage amplitude of each stage are matched to the current device parameters, load characteristics and operating conditions. From the timing dimension, the channel charge injection effect and clock feedthrough effect at the moment of turn-on are suppressed. During the pre-charge step stage, a pre-charge bias voltage is applied synchronously to the gates of the NMOS and PMOS switches to pre-form a uniform weak inversion layer in the semiconductor channels of the two switches. At the same time, the pre-charge operation of the gate parasitic capacitance is completed, eliminating the influence of the gate capacitance charging and discharging delay on the turn-on speed and shortening the device response delay in the subsequent linear rise stage. In the linear rise step stage, the gate voltage of the NMOS switch is linearly increased and the gate voltage of the PMOS switch is linearly decreased according to the preset change slope. The gate-source voltage difference between the two transistors is adjusted synchronously to make the device conduction channel uniformly widened, reduce the nonlinear fluctuation of the conduction resistance during the turn-on process, and complete the suppression of transmission signal distortion and harmonic interference caused by the sudden change of conduction resistance. During the steady-state lock-in stage, after both the NMOS and PMOS switches enter the stable strong inversion region, the gate voltages of the two switches are locked to the preset steady-state turn-on voltage. At the same time, the gate voltage dynamic clamping mechanism is activated to suppress gate voltage overshoot and undershoot caused by power supply voltage fluctuations and load changes, thereby avoiding the risk of device gate oxide breakdown and turn-on instability. Throughout the entire turn-on process, the drain-source current, real-time on-resistance, channel charge change, and gate-source voltage difference of the NMOS and PMOS switches are collected in real time at a fixed sampling frequency. The timing parameters and voltage amplitude of each step are corrected in real time through a closed-loop feedback link to achieve consistency and stability control of the turn-on process under different operating conditions. After the power-on process is completed, the on-resistance and channel charge distribution of the device are continuously monitored. Dynamic fine-tuning of the gate voltage is performed during the steady-state conduction phase to maintain the low on-resistance and high linearity steady-state operation of the CMOS analog switch. At the same time, the impact of long-term aging of the device characteristics on the conduction performance is compensated.

[0024] This invention also includes adaptive matching of the duration of the pre-charge step before generating the multi-step gate turn-on pulse timing. Based on the device's gate-source parasitic capacitance, switching load capacitance, and current ambient temperature parameters, an adaptive matching model for the timing duration is constructed. The optimal duration of the pre-charge step is calculated through the model, and segmented calibration of the pre-charge duration is performed simultaneously. Differentiated reference timing parameters are set for CMOS devices at different process nodes. During the pre-charge process, the gate charge accumulation and the formation state of the channel weak inversion layer are monitored in real time, and the pre-charge duration is dynamically fine-tuned. Simultaneously, a high-temperature gate leakage current compensation mechanism is introduced, adjusting the temperature compensation weight of the pre-charge duration according to the ambient temperature to achieve precise control of the channel weak inversion layer formation and charge accumulation during the pre-charge stage. The calculation expression for the timing duration is as follows: ; The pre-charge step reference duration is set to 20 ns. This is the capacitor weighting coefficient, with a value of 0.8. For the gate-source parasitic capacitance of the switching transistor, For the load capacitor of the switch port, The reference capacitor has a value of 1pF. This is the temperature weighting coefficient, with a value of 0.0035 / ℃. The current ambient temperature. The reference temperature is set to 25℃. This expression adapts to the pre-charge time under different device parasitic parameters, load conditions and ambient temperatures, achieving a precise match between the pre-charge time and device characteristics and operating conditions.

[0025] This invention also includes setting two-stage linkage clamping thresholds during the execution of the gate voltage dynamic clamping mechanism. The first stage is a soft clamping threshold. When the deviation between the gate voltage and the steady-state turn-on voltage exceeds 5%, the gate leakage current micro-adjustment circuit is activated to slowly correct the gate voltage deviation. Simultaneously, an adaptive adjustment circuit for soft clamping is set to adjust the gain coefficient of the micro-adjustment circuit according to the power supply voltage fluctuation amplitude. The second stage is a hard clamping threshold. When the deviation between the gate voltage and the steady-state turn-on voltage exceeds 10%, the gate voltage clamping circuit is directly triggered to quickly pull the gate voltage back to the steady-state turn-on voltage range. At the same time, an anti-interference and anti-jitter mechanism for hard clamping is added. Hard clamping action is triggered only when the voltage deviation exceeds the threshold for 3 sampling cycles. The current voltage deviation data is latched simultaneously and incorporated into the parameter correction system of the subsequent closed-loop feedback. At the same time, a seamless connection logic between the two clamping stages is set. When the soft clamping action cannot correct the deviation, hard clamping is automatically triggered to complete the voltage jump and secondary charge injection suppression during the clamping process.

[0026] This invention also includes constructing a quantitative evaluation system for on-resistance nonlinearity during the closed-loop feedback correction of timing parameters and voltage amplitude. The quantified value of on-resistance nonlinearity is obtained through multi-dimensional parameter fusion calculation. Based on the deviation between the quantized value and a preset threshold, the slope of the voltage change in the linearly rising step is dynamically corrected. Simultaneously, an adaptive distribution strategy for sampling points is set, with increased sampling points at the beginning and end of the linear rising phase, and the sampling density adjusted according to device characteristics in the intermediate phase to improve the accuracy of nonlinearity quantification. A correlation mapping relationship between nonlinearity and channel charge injection is established simultaneously, co-optimizing nonlinearity correction and charge injection suppression. Differentiated slope correction step sizes are set for different deviation amplitudes to achieve a smooth transition of the corrected slope and avoid device oscillations caused by sudden slope changes. The calculation expression for on-resistance nonlinearity is as follows: ; This refers to the on-resistance nonlinearity during the turn-on process of a CMOS analog switch. This represents the average value of the on-resistance during the linear rise phase. This represents the number of parameter sampling points during the linear ascent phase. For the first The real-time on-resistance value collected at each sampling point is used to accurately quantify the fluctuation of the on-resistance during the turn-on process. This provides a quantitative basis for the slope correction of the linear ascending step, thereby achieving stable control of the linearity of the on-resistance during the turn-on process.

[0027] In this invention, the static bias calibration step further includes real-time acquisition and calibration of the threshold voltages of NMOS and PMOS switches. By applying a millivolt-level test bias voltage to the drain and source of the device, the corresponding microampere-level drain and source current is acquired. The actual threshold voltage of the device under the current operating condition is obtained by fitting the device current-voltage characteristic curve. Simultaneously, the differential measurement method is used to eliminate the influence of substrate bias effect. The amplitude of the test bias voltage is adaptively adjusted for switches with different aspect ratios to ensure that the test signals of both large-size and small-size switches have sufficient signal-to-noise ratio. The deviation between the actual threshold voltage and the reference threshold voltage is incorporated into the voltage amplitude calculation system of the multi-step gate turn-on pulse timing. At the same time, a fast threshold voltage calibration is performed before each switch is turned on, rather than a single calibration is performed only during the power-on stage. The temperature drift coefficient of the device threshold voltage is pre-stored synchronously. Combined with the real-time measurement value, a dual calibration is completed to compensate for the impact of threshold voltage temperature drift and process deviation on the turn-on control accuracy.

[0028] In this invention, during the pre-charge step stage, differential synchronous control is also included for the pre-charge bias voltages of the NMOS and PMOS switches. The pre-charge bias voltage of the NMOS switch is set to be 0.1V to 0.2V higher than its actual threshold voltage, and the pre-charge bias voltage of the PMOS switch is set to be -0.1V to -0.2V lower than its actual threshold voltage. The timing of the application of the pre-charge voltages of the two switches is synchronously controlled to keep the timing deviation within 500ps. At the same time, the drain-source current of the weak inversion layer in the channel is collected in real time during the pre-charge process, and the pre-charge bias voltage is finely adjusted in a closed loop to achieve uniform and consistent weak inversion layer formation control in the two channels. The device substrate bias voltage is adjusted synchronously with the pre-charge bias voltage to complete the threshold voltage offset compensation caused by the substrate bulk effect. At the same time, the level status of the switch port is monitored in real time. When the port level offset exceeds the preset range, the bias voltage is adjusted immediately to achieve the suppression of switch channel level offset and signal crosstalk caused by premature conduction of a single switch.

[0029] In this invention, during the linear rise-step stage, the slope of the gate voltage change of the NMOS and PMOS switches is synchronously matched and controlled to ensure that the absolute values ​​of the rising slope of the NMOS gate voltage and the falling slope of the PMOS gate voltage are completely consistent. This achieves synchronous improvement of the conduction level of the two channels, allowing the total on-resistance of the CMOS analog switch to decrease smoothly during the turn-on process. Simultaneously, the gate voltage values ​​of the two switches are sampled every 1 ns, and the slope deviation is calculated. If the deviation exceeds 2%, the output step size of the digital-to-analog converter is immediately fine-tuned to control the slope synchronization accuracy. Furthermore, the slope is nonlinearly fine-tuned to accommodate the channel's characteristic change from weak inversion to strong inversion, reducing the slope at the beginning and end of the turn-on process and maintaining a constant slope in the intermediate stage. This adapts to the change in the conduction characteristics of the adapter channel. The absolute value of the slope is also adaptively adjusted based on the load capacitance of the switch port; the larger the load capacitance, the lower the slope. A digital-to-analog converter with 12 bits or more is used for step-by-step voltage output, achieving a stepless continuous output of voltage changes and suppressing transmission signal distortion and harmonic interference caused by sudden changes in on-resistance.

[0030] In this invention, the quantitative evaluation process of on-resistance nonlinearity also includes setting a three-level linkage nonlinearity control threshold. When the nonlinearity quantification value is below 1%, the voltage change slope of the current linear rise step remains unchanged. When the nonlinearity quantification value is within the range of 1% to 3%, the voltage change slope is reduced by a fixed step size. When the nonlinearity quantification value is above 3%, the linear rise process is immediately paused, the device's static operating point is recalibrated, and the process is resumed. At the same time, the range of the three-level threshold is adaptively adjusted for different ambient temperatures. The threshold range is tightened under high temperature conditions and appropriately widened under low temperature conditions to accommodate the temperature drift of the adapter device characteristics. Simultaneously, after the nonlinearity exceeds the threshold, multi-dimensional parameters such as gate voltage, drain-source current, and threshold voltage are collected to complete fault tracing and locate the core cause of the nonlinearity exceeding the standard. At the same time, a fast recovery mechanism is set after the pause. After recalibration, a smoother slope is used to gradually restore the linear rise process, avoiding sudden changes in on-resistance during the recovery process. At the same time, historical data of nonlinearity is statistically analyzed, and the preset threshold is optimized based on the device aging trend to maintain the on-control accuracy throughout the device's entire life cycle.

[0031] In this invention, the closed-loop feedback step of the start-up process also includes an adaptive adjustment mechanism for setting the sampling frequency. During the dynamic change phases of the pre-charging ladder and the linear ascending ladder, the parameter sampling frequency is set to 1GHz to achieve high-frequency and accurate monitoring of changes in the device's electrical parameters. During the stable phase of the steady-state locking ladder, the parameter sampling frequency is reduced to 100MHz to reduce the dynamic power consumption and switching noise of the control circuit while ensuring monitoring accuracy. At the same time, a multi-sampling channel parallel operation mode is adopted to achieve seamless transition of sampling frequency switching and avoid data loss during the switching process. In the high-frequency sampling phase, a moving average digital filtering process is added to suppress parameter miscorrection caused by sampling noise. In the low-frequency sampling phase, a parameter abnormal jump monitoring mechanism is set up to immediately switch back to the high-frequency sampling mode when a parameter mutation is detected. In addition, for the low-power scenario of battery power supply, the sampling frequency in the steady-state phase is further reduced to balance monitoring accuracy and system power consumption. The data of the most recent 100 sampling points are cached synchronously for predicting the parameter change trend of the closed-loop feedback and improving the response speed of the feedback control.

[0032] In this invention, the steady-state turn-on dynamic fine-tuning step after turn-on includes acquiring the device's real-time on-resistance, channel charge distribution, and drain-source voltage parameters every 100μs. When the on-resistance change exceeds 2%, the gate steady-state turn-on voltage is finely adjusted within a range of ±50mV. Simultaneously, a single-step fine-tuning step size of no more than 10mV is set to avoid sudden changes in on-resistance and signal distortion caused by the fine-tuning process. The entire operating temperature range from -40℃ to 125℃ is divided into five consecutive temperature segments, each with independent fine-tuning reference parameters to adapt to changes in device characteristics at different temperatures. Simultaneously, based on the cumulative conduction time and historical on-resistance variation data of the device, a device aging compensation model is established to dynamically adjust the fine-tuning threshold and step size to offset the performance degradation caused by the characteristic aging of the device during long-term operation. For multi-channel CMOS analog switch arrays, synchronous steady-state fine-tuning operation is performed to control the consistency of on-resistance between channels. At the same time, the integrity of the switch transmission signal is monitored in real time during the fine-tuning process. When signal distortion is detected, the fine-tuning is immediately paused and restored to the reference gate voltage, so as to continuously maintain the low on-resistance and high linearity conduction state of the CMOS analog switch in the full temperature range and the full power supply voltage fluctuation range.

[0033] The following two examples further illustrate the specific implementation of this system: Example 1: Application of CMOS Analog Switch On / Off Control in a High-Precision 16-Bit Data Acquisition System This embodiment applies to a 16-bit high-precision data acquisition system in the field of industrial measurement and control. The system includes 8 differential analog input channels, each channel is equipped with a CMOS transmission gate analog switch composed of paired NMOS and PMOS transistors. The switching transistors are manufactured using 0.18μm CMOS technology. The system power supply voltage is 3.3V, the operating temperature range is -40℃ to 85℃, and the channel load capacitance is 10pF. It needs to achieve low charge injection, high linearity, and high consistency switch-on control, fully covering all the technical solutions of this invention. The specific implementation process is as follows.

[0034] Before the switch is turned on, a pre-turn-on static bias calibration is first performed. Real-time parameters such as the current ambient temperature, system power supply voltage, switch port load capacitance, and device substrate bias voltage are collected. A reference mapping relationship between the device's static operating point and environmental and electrical parameters is established by fitting, and the static operating point offset caused by process deviations, temperature drift effects, and substrate bulk effects is corrected. Simultaneously, the threshold voltages of NMOS and PMOS switches are collected and calibrated in real time. A millivolt-level test bias voltage is applied to the drain and source of the device, and the corresponding microampere-level drain and source current is collected. The actual threshold voltage of the device under the current operating condition is obtained by fitting the device current-voltage characteristic curve. The influence of substrate bias effect is eliminated by differential measurement method. The amplitude of the test bias voltage is adaptively adjusted for switches with different aspect ratios to ensure that the test signal has a sufficient signal-to-noise ratio. Before each switch is turned on, a fast threshold voltage calibration is performed, and the temperature drift coefficient of the device threshold voltage is pre-stored simultaneously. The dual calibration is completed by combining the real-time measurement value and incorporating the deviation between the actual threshold voltage and the reference threshold voltage into the voltage amplitude calculation system of the multi-step gate turn-on pulse timing.

[0035] Based on the real-time parameters and the reference mapping relationship, a multi-step gate-on pulse timing sequence is generated. The output process of the gate-on voltage is divided into three continuous and time-free timing stages: a pre-charge step, a linear rising step, and a steady-state lock-in step. The duration and voltage amplitude of each stage are matched to the current device parameters, load characteristics, and operating conditions. Before timing sequence generation, the duration of the pre-charge step is adaptively matched. Based on the device's gate-source parasitic capacitance, switching load capacitance, and current ambient temperature parameters, an adaptive matching model for the timing duration is constructed to calculate the optimal duration of the pre-charge step. Segmented calibration of the pre-charge duration is performed simultaneously. Differentiated reference duration parameters are set for CMOS devices at different process nodes. During the pre-charge process, the gate charge accumulation and the formation state of the weak inversion layer in the channel are monitored in real time, and the pre-charge duration is dynamically fine-tuned. At the same time, a high-temperature gate leakage current compensation mechanism is introduced to adjust the temperature compensation weight of the pre-charge duration according to the ambient temperature.

[0036] During the pre-charge staircase phase, pre-charge bias voltages are synchronously applied to the gates of both the NMOS and PMOS switches. The pre-charge bias voltage for the NMOS switch is set to be 0.15V higher than its actual threshold voltage, and the pre-charge bias voltage for the PMOS switch is set to be -0.15V lower than its actual threshold voltage. The timing of the application of the pre-charge voltages for both switches is synchronously controlled to keep the timing deviation within 500ps. During the pre-charge process, the drain-source current of the weak inversion layer in the channel is acquired in real time, and the pre-charge bias voltage is finely adjusted in a closed loop to achieve uniform and consistent weak inversion layer formation control in both channels. The device substrate bias voltage is adjusted synchronously in conjunction with the pre-charge bias voltage to compensate for the threshold voltage offset caused by the substrate bulk effect. At the same time, the level status of the switch port is monitored in real time, and the bias voltage is adjusted immediately when the port level offset exceeds the preset range.

[0037] In the linear rise-step stage, the gate voltage of the NMOS switch is linearly increased and the gate voltage of the PMOS switch is linearly decreased according to a preset slope. Synchronous matching control is applied to the slope changes of the gate voltages of the two transistors, ensuring that the absolute values ​​of the rising and falling slopes of the NMOS and PMOS gate voltages are completely consistent. This achieves synchronized improvement in the conduction level of the two channels, allowing the total on-resistance of the CMOS analog switch to decrease smoothly during the turn-on process. The gate voltage values ​​of the two transistors are sampled every 1 ns, and the slope deviation is calculated. If the deviation exceeds 2%, the output step size of the digital-to-analog converter is immediately fine-tuned to control the slope synchronization accuracy. Simultaneously, nonlinear fine-tuning is applied to the slope as the channel characteristics change from weak inversion to strong inversion. The slope is reduced at the beginning and end of the turn-on process, while maintaining a constant slope in the intermediate stage. The absolute value of the slope is adaptively adjusted based on the load capacitance at the switch port to adapt to changes in the conduction characteristics of the adapter channel. A 12-bit digital-to-analog converter is used for step-by-step voltage output, achieving a stepless continuous output of voltage changes. A quantitative evaluation system for on-resistance nonlinearity is constructed simultaneously. The quantitative value of on-resistance nonlinearity is obtained by multi-dimensional parameter fusion calculation. Based on the deviation between the quantitative value and the preset threshold, the slope of voltage change in the linear rising step is dynamically corrected. An adaptive distribution strategy for sampling points is set, and the sampling points are densified at the beginning and end of the linear rising stage. The sampling density is adjusted according to the characteristics of the adapter device in the middle stage. The correlation mapping relationship between nonlinearity and channel charge injection is established. The correction of nonlinearity and the suppression of charge injection are synergistically optimized. Different slope correction step sizes are set for different deviation amplitudes.

[0038] In the steady-state lockout stage, once both the NMOS and PMOS switches enter the stable strong inversion region, their gate voltages are locked to the preset steady-state turn-on voltage, and a dynamic gate voltage clamping mechanism is activated. A two-stage linkage clamping threshold is set. The first stage is a soft clamping threshold; when the deviation between the gate voltage and the steady-state turn-on voltage exceeds 5%, a gate leakage current fine-tuning circuit is activated to slowly correct the gate voltage deviation. Simultaneously, an adaptive adjustment circuit for the soft clamping is set, adjusting the gain coefficient of the fine-tuning circuit according to the power supply voltage fluctuation. The second stage is a hard clamping threshold; when the deviation between the gate voltage and the steady-state turn-on voltage exceeds 10%, the gate voltage clamping circuit is directly triggered, quickly pulling the gate voltage back to the steady-state turn-on voltage range. An anti-interference and anti-jitter mechanism for the hard clamping is also added; the hard clamping action is triggered only when the voltage deviation continuously exceeds the threshold for three sampling cycles. The current voltage deviation data is simultaneously latched and incorporated into the subsequent closed-loop feedback parameter correction system. Seamless connection logic between the two clamping stages is set; the hard clamping is automatically triggered when the soft clamping action cannot correct the deviation.

[0039] Throughout the startup process, an adaptive adjustment mechanism for the sampling frequency is implemented. During the dynamic changes of the pre-charge and linear ascending steps, the parameter sampling frequency is set to 1GHz to achieve high-frequency and accurate monitoring of changes in device electrical parameters. During the stable phase of the steady-state locking step, the parameter sampling frequency is reduced to 100MHz. A multi-channel parallel operation is employed to achieve seamless transitions in sampling frequency switching. A moving average digital filter is added during the high-frequency sampling phase, and a parameter anomaly monitoring mechanism is implemented during the low-frequency sampling phase. Upon detecting a sudden parameter change, the system immediately switches back to high-frequency sampling mode, synchronously buffering data from the most recent 100 sampling points for predicting parameter change trends in the closed-loop feedback. The drain-source current, real-time on-resistance, channel charge change, and gate-source voltage difference of the NMOS and PMOS switches are acquired in real time at a fixed sampling frequency. The timing parameters and voltage amplitudes of each step are corrected in real time through the closed-loop feedback link.

[0040] After the startup process is completed, the on-resistance and channel charge distribution of the device are continuously monitored, and dynamic fine-tuning of the gate voltage is performed during the steady-state turn-on phase. Real-time on-resistance, channel charge distribution, and drain-source voltage parameters of the device are collected every 100μs. When the change in on-resistance exceeds 2%, the steady-state gate voltage is finely adjusted within a range of ±50mV, with a single-step fine-tuning step size not exceeding 10mV. The operating temperature range of -40℃ to 85℃ is divided into 5 consecutive temperature segments, each with independent fine-tuning reference parameters. Based on the device's cumulative turn-on time and historical on-resistance change data, a device aging compensation model is established to dynamically adjust the fine-tuning threshold and step size. Synchronous steady-state fine-tuning is performed on the 8-channel analog switch array to control the consistency of on-resistance between channels. Simultaneously, the integrity of the switch transmission signal is monitored in real time during fine-tuning. If signal distortion is detected, fine-tuning is immediately paused and restored to the reference gate voltage.

[0041] Table 1. Performance comparison between this method and traditional start-up control methods in high-precision data acquisition scenarios. Table 1 shows the data from the actual test results of 1000 consecutive opening cycles of the 8-channel analog switches in this embodiment, covering the entire operating temperature range from -40℃ to 85℃. Traditional single-stage opening methods offer fast opening speeds, but suffer from severe charge injection and level shift issues, failing to meet the accuracy requirements of 16-bit data acquisition systems. Traditional two-step opening methods alleviate the charge injection problem to some extent, but fixed timing parameters result in poor consistency across the entire temperature range and high on-resistance nonlinearity. The method of this invention, through multi-stage timing control, closed-loop feedback, and full-process parameter adaptation, significantly reduces charge injection and on-resistance nonlinearity while maintaining opening speed. Port level shift is significantly reduced, and the opening consistency between channels is greatly improved, fully meeting the performance requirements of high-precision data acquisition systems.

[0042] Example 2: Application of CMOS Analog Switch Enable Control for Broadband RF Front-End Signal Switching This embodiment is applied to the front-end signal switching link of a broadband radio frequency communication system. The link is configured with 4 single-ended radio frequency signal switching channels. Each channel uses an RFCMOS analog switch composed of paired NMOS and PMOS transistors. The switching transistors are manufactured using 0.13μm RFCMOS technology. The system power supply voltage is 1.8V, the operating temperature range is -40℃ to 125℃, the operating frequency covers DC-3GHz, and the channel load capacitance is 5pF. It needs to achieve low crosstalk, low harmonic distortion, and fast and stable switch-on control, fully covering all the technical solutions of this invention. The specific implementation process is as follows.

[0043] Before the switch is turned on, a pre-turn-on static bias calibration is first performed. Real-time parameters such as the current ambient temperature, system power supply voltage, switch port load capacitance, and device substrate bias voltage are collected. A reference mapping relationship between the device's static operating point and environmental and electrical parameters is established by fitting, and the static operating point offset caused by process deviations, temperature drift effects, and substrate bulk effects is corrected. Simultaneously, the threshold voltages of NMOS and PMOS switches are collected and calibrated in real time. A millivolt-level test bias voltage is applied to the drain and source of the device, and the corresponding microampere-level drain and source current is collected. The actual threshold voltage of the device under the current operating condition is obtained by fitting the device current-voltage characteristic curve. The influence of substrate bias effect is eliminated by differential measurement method. The amplitude of the test bias voltage is adaptively adjusted for the large aspect ratio device characteristics of the RF switch to ensure that the test signal has a sufficient signal-to-noise ratio. Before each switch is turned on, a fast threshold voltage calibration is performed, and the temperature drift coefficient of the device threshold voltage is pre-stored simultaneously. The dual calibration is completed by combining the real-time measurement value and incorporating the deviation between the actual threshold voltage and the reference threshold voltage into the voltage amplitude calculation system of the multi-step gate turn-on pulse timing.

[0044] Based on the real-time parameters and the reference mapping relationship, a multi-step gate-on pulse timing sequence is generated. The output process of the gate-on voltage is divided into three continuous and time-free timing stages: a pre-charge step, a linear rising step, and a steady-state lock-in step. The duration and voltage amplitude of each stage are matched to the current device parameters, load characteristics, and operating conditions. Before timing sequence generation, the duration of the pre-charge step is adaptively matched. Based on the device's gate-source parasitic capacitance, switch load capacitance, and current ambient temperature parameters, an adaptive matching model for the timing duration is constructed to calculate the optimal duration of the pre-charge step. Segmented calibration of the pre-charge duration is performed simultaneously. Differentiated reference duration parameters are set for the device characteristics of the RF switch. During the pre-charge process, the gate charge accumulation and the formation state of the weak inversion layer in the channel are monitored in real time, and the pre-charge duration is dynamically fine-tuned. At the same time, a high-temperature gate leakage current compensation mechanism is introduced to adjust the temperature compensation weight of the pre-charge duration according to the ambient temperature.

[0045] During the precharge staircase phase, precharge bias voltages are synchronously applied to the gates of both the NMOS and PMOS switches. The precharge bias voltage for the NMOS switch is set to be 0.12V higher than its actual threshold voltage, and the precharge bias voltage for the PMOS switch is set to be -0.12V lower than its actual threshold voltage. The timing of the application of the precharge voltages for both switches is synchronously controlled to keep the timing deviation within 500ps. During the precharge process, the drain-source current of the weak inversion layer in the channel is acquired in real time, and the precharge bias voltage is finely adjusted in a closed loop to achieve uniform and consistent weak inversion layer formation control in both channels. The device substrate bias voltage is adjusted synchronously in conjunction with the precharge bias voltage to compensate for the threshold voltage offset caused by the substrate bulk effect. At the same time, the RF signal level of the switch port is monitored in real time. If the port level offset exceeds the preset range, the bias voltage is adjusted immediately to suppress signal crosstalk during the turn-on process.

[0046] In the linear rise-step stage, the gate voltage of the NMOS switch is linearly increased and the gate voltage of the PMOS switch is linearly decreased according to a preset slope. Synchronous matching control is applied to the slope changes of the gate voltages of the two transistors, ensuring that the absolute values ​​of the rising and falling slopes of the NMOS and PMOS gate voltages are completely consistent. This achieves synchronized improvement in the conduction level of the two channels, allowing the total on-resistance of the CMOS analog switch to decrease smoothly during the turn-on process. The gate voltage values ​​of the two transistors are sampled every 1 ns, and the slope deviation is calculated. If the deviation exceeds 2%, the output step size of the digital-to-analog converter is immediately fine-tuned to control the slope synchronization accuracy. Simultaneously, the slope is non-linearly fine-tuned to address the change in RF switch channel characteristics from weak inversion to strong inversion. The slope is reduced at the beginning and end of the turn-on process, while maintaining a constant slope in the intermediate stage. The absolute value of the slope is adaptively adjusted based on the load capacitance of the RF channel to adapt to changes in the conduction characteristics of the adapter channel. A 12-bit digital-to-analog converter is used for step-by-step voltage output, achieving a stepless continuous output of voltage changes and suppressing harmonic distortion during the turn-on process. A quantitative evaluation system for on-resistance nonlinearity is constructed simultaneously. The quantitative value of on-resistance nonlinearity is obtained by multi-dimensional parameter fusion calculation. Based on the deviation between the quantitative value and the preset threshold, the slope of the voltage change of the linear rising step is dynamically corrected. A three-level linkage nonlinearity control threshold is set, and the range of the three-level threshold is adaptively adjusted for different ambient temperatures. The threshold range is tightened under high temperature conditions and appropriately relaxed under low temperature conditions. Simultaneously, after the nonlinearity exceeds the threshold, multi-dimensional parameters such as gate voltage, drain-source current, and threshold voltage are collected to complete fault tracing. A fast recovery mechanism after pause is set, historical data of nonlinearity are statistically analyzed, and the preset threshold is optimized based on the device aging trend.

[0047] In the steady-state lockout stage, after both the NMOS and PMOS switches enter the stable strong inversion region, the gate voltages of the two switches are locked to the preset steady-state turn-on voltage, and the gate voltage dynamic clamping mechanism is activated at the same time. A two-stage linkage clamping threshold is set. The first stage is the soft clamping threshold. When the deviation between the gate voltage and the steady-state turn-on voltage exceeds 5%, the gate leakage current fine-tuning circuit is activated to slowly correct the gate voltage deviation. At the same time, the soft clamping adaptive adjustment circuit is set to adjust the gain coefficient of the fine-tuning circuit according to the power supply voltage fluctuation amplitude. The second stage is the hard clamping threshold. When the deviation between the gate voltage and the steady-state turn-on voltage exceeds 10%, the gate voltage clamping circuit is directly triggered to quickly pull the gate voltage back to the steady-state turn-on voltage range. At the same time, the anti-interference and anti-jitter mechanism of hard clamping is added. The hard clamping action is triggered only when the voltage deviation exceeds the threshold for 3 sampling cycles. The current voltage deviation data is latched and incorporated into the subsequent closed-loop feedback parameter correction system. The seamless connection logic of the two clamping stages is set. When the soft clamping action cannot correct the deviation, the hard clamping is automatically triggered to suppress the amplitude distortion of the RF signal.

[0048] Throughout the startup process, an adaptive adjustment mechanism for the sampling frequency is implemented. During the dynamic changes of the pre-charge and linear ascending steps, the parameter sampling frequency is set to 1GHz to achieve high-frequency and accurate monitoring of changes in device electrical parameters. During the stable phase of the steady-state locking step, the parameter sampling frequency is reduced to 100MHz. A multi-channel parallel operation is employed to achieve seamless transitions in sampling frequency switching. A moving average digital filter is added during the high-frequency sampling phase, and a parameter anomaly monitoring mechanism is implemented during the low-frequency sampling phase. Upon detecting a sudden parameter change, the system immediately switches back to high-frequency sampling mode, synchronously buffering data from the most recent 100 sampling points for predicting parameter change trends in the closed-loop feedback. The drain-source current, real-time on-resistance, channel charge change, and gate-source voltage difference of the NMOS and PMOS switches are acquired in real time at a fixed sampling frequency. The timing parameters and voltage amplitudes of each step are corrected in real time through the closed-loop feedback link.

[0049] After the startup process is completed, the on-resistance and channel charge distribution of the device are continuously monitored, and dynamic fine-tuning of the gate voltage is performed during the steady-state turn-on phase. Real-time on-resistance, channel charge distribution, and drain-source voltage parameters are acquired every 100μs. When the change in on-resistance exceeds 2%, the steady-state gate voltage is finely adjusted within a range of ±50mV, with a single-step adjustment step size not exceeding 10mV. The full operating temperature range from -40℃ to 125℃ is divided into 5 consecutive temperature segments, each with independent fine-tuning reference parameters. Based on the device's cumulative turn-on time and historical on-resistance change data, a device aging compensation model is established to dynamically adjust the fine-tuning threshold and step size. Synchronous steady-state fine-tuning is performed on the 4 RF switch channels to control the consistency of on-resistance and insertion loss between channels. Simultaneously, the integrity of the RF transmission signal is monitored in real time during fine-tuning. If signal distortion is detected, fine-tuning is immediately paused and restored to the reference gate voltage.

[0050] Table 2 Performance Comparison of This Method and Traditional Power-On Control Method in Broadband RF Front-End Scenarios Table 2 data comes from continuous field measurements of the four RF switches in this embodiment at a 3GHz operating frequency, covering the entire operating temperature range from -40℃ to 125℃. Traditional single-stage turn-on methods offer fast turn-on speeds but suffer from severe gate overshoot, poor crosstalk and harmonic distortion, and cannot meet the linearity requirements of broadband RF systems. Traditional two-step turn-on methods reduce overshoot to some extent, but fixed timing parameters result in large performance fluctuations across the entire temperature range and high signal distortion during the turn-on process. The method of this invention, through multi-step timing control, slope synchronization matching, and a two-stage clamping mechanism, significantly improves the crosstalk rejection ratio, reduces harmonic distortion and signal distortion, effectively suppresses gate overshoot, and significantly narrows performance fluctuations across the entire temperature range, fully meeting the high linearity and high stability application requirements of broadband RF front-ends. refer to Figure 1 This figure illustrates the complete process of the CMOS analog switch turn-on control method. First, before pre-turn-on, the system performs static bias calibration on the paired NMOS and PMOS transistors to correct process and temperature drift deviations. Next, based on real-time acquired environmental and electrical parameters, a multi-step gate pulse timing sequence is generated, comprising three seamlessly connected stages: pre-charge, linear rise, and steady-state lockout. Subsequently, these three stages are executed sequentially to complete channel pre-forming, on-resistance linearization and equalization, and steady-state lockout and voltage clamping, respectively. The entire turn-on process is continuously corrected in real-time by high-frequency sampling closed-loop feedback. After the turn-on process is completed, the gate voltage is continuously monitored and dynamically fine-tuned to maintain a low on-resistance and high linearity operating state.

[0051] Reference Figure 2This diagram details the control logic for the pre-charge stepped phase. Before the process begins, the system first acquires the threshold voltage in real time to ensure the accuracy of subsequent biasing. Using an adaptive matching model, combined with capacitance, temperature, and process node parameters, the optimal duration of the pre-charge phase is calculated. During pre-charge execution, the system applies pre-charge bias voltages to the NMOS and PMOS transistors, based on differential synchronous control of their respective actual threshold voltages. Simultaneously, the system monitors the gate charge and weak inversion layer drain-source current in real time, fine-tuning the pre-charge duration and voltage amplitude in a closed-loop manner to ensure a uniform weak inversion layer is formed in both transistor channels, thus shortening the response delay.

[0052] Reference Figure 3 This diagram illustrates the closed-loop control core logic of the linear rise-step stage. During this stage, the system synchronously and linearly adjusts the gate voltages of the NMOS and PMOS according to a preset slope. During the rise process, the system collects parameters such as on-resistance at a high sampling frequency of 1 GHz and calculates its nonlinearity score. Nonlinearity is determined based on a three-level linkage control threshold: below 1%, the slope is maintained; between 1% and 3%, the slope is reduced by a fixed step size; above 3%, the system immediately pauses and recalibrates the operating point. The corrected slope transitions smoothly, ensuring that the on-resistance decreases steadily during the turn-on process and suppressing signal distortion and harmonic interference.

[0053] Reference Figure 4 This diagram details the voltage stabilization and protection mechanism during the steady-state lockout step phase. Once the switching transistor enters the stable strong inversion region, the system locks the gate voltage to a preset steady-state value. The sampling frequency is then adaptively reduced to 100MHz to lower power consumption. At this point, a dynamic gate voltage clamping mechanism is activated: when a voltage deviation exceeds the soft clamping threshold (5%), a micro-adjustment loop is initiated for slow correction; if the deviation continues to exceed the hard clamping threshold (10%) for three sampling cycles, the clamping circuit is directly triggered to quickly pull back the voltage, and the deviation data is latched for closed-loop feedback. The seamless integration of soft and hard clamping effectively suppresses voltage fluctuations caused by sudden power supply and load changes, mitigating the risk of device instability.

[0054] refer to Figure 5 This figure illustrates the lifecycle characteristic maintenance mechanism of a CMOS analog switch after the turn-on process is completed. The system periodically collects parameters such as on-resistance and channel charge distribution under steady-state conduction every 100μs. Using an aging compensation model, the fine-tuning threshold and step size are dynamically adjusted based on the cumulative conduction time. When the on-resistance change exceeds the threshold (e.g., 2%), a fine-tuning adjustment of no more than 10mV is performed on the gate steady-state turn-on voltage in a single step. Simultaneously, the integrity of the switch transmission signal is monitored in real time; if distortion is detected, fine-tuning is immediately paused and the reference voltage is restored, ensuring low on-resistance and high linearity conduction across the entire temperature range and during long-term operation.

[0055] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A CMOS analog switch activation control method, characterized in that, Includes the following steps: Pre-enable static bias calibration is performed on the paired NMOS and PMOS switches in the CMOS analog switch. Real-time parameters such as ambient temperature, power supply voltage, load capacitance, and substrate bias voltage are collected. A reference mapping relationship between the static operating point and the relevant parameters is established by fitting and completing the correction of the resulting operating point offset. Based on the real-time parameter and reference mapping relationship, a multi-step gate turn-on pulse timing sequence is generated, which is divided into three continuous timing stages: pre-charge, linear rise, and steady-state lockout. The duration and voltage amplitude of each stage are matched to the current device and operating conditions. During the pre-charge step stage, a pre-charge bias voltage is applied synchronously to the gates of both transistors to form a uniform weak inversion layer and pre-charge the gate parasitic capacitance. In the linear rise step stage, the NMOS gate voltage is linearly increased and the PMOS gate voltage is decreased according to a preset slope, and the gate-source voltage difference is adjusted synchronously to suppress nonlinear fluctuations in on-resistance and distortion of transmission signals. In the steady-state lockout step stage, after the two transistors enter the stable strong inversion region, they lock the gate voltage to the steady-state turn-on value and start the gate voltage dynamic clamping mechanism to suppress voltage overshoot and undershoot caused by power supply fluctuations and load changes. Throughout the entire startup process, parameters are collected at a fixed frequency, and the timing parameters and voltage amplitude of each step are corrected in real time through closed-loop feedback. After startup, the on-resistance and channel charge distribution are continuously monitored, and the gate voltage is dynamically fine-tuned to maintain low on-resistance and high linearity steady-state operation, compensating for the impact of device characteristic aging on conduction performance.

2. The CMOS analog switch activation control method according to claim 1, characterized in that, This also includes adaptive matching of the duration of the precharge step before generating the multi-step gate-on pulse timing sequence. Based on the device's gate-source parasitic capacitance, switching load capacitance, and current ambient temperature parameters, an adaptive matching model for the timing duration is constructed. The optimal duration of the precharge step is calculated through the model, and segmented calibration of the precharge duration is performed simultaneously. Differentiated reference timing parameters are set for CMOS devices at different process nodes. During the precharge process, the gate charge accumulation and the formation state of the channel weak inversion layer are monitored in real time, and the precharge duration is dynamically fine-tuned. A high-temperature gate leakage current compensation mechanism is also introduced, adjusting the temperature compensation weight of the precharge duration according to the ambient temperature. The calculation expression for the timing duration is as follows: ; This is the reference duration for the pre-charge tiers. The capacitance weighting coefficient is... For the gate-source parasitic capacitance of the switching transistor, For the load capacitor of the switch port, As a reference capacitor, Temperature weighting coefficient, The current ambient temperature. This is the reference temperature.

3. The CMOS analog switch activation control method according to claim 1, characterized in that, It also includes setting two-stage linkage clamping thresholds during the execution of the gate voltage dynamic clamping mechanism. The first stage is the soft clamping threshold. When the deviation between the gate voltage and the steady-state turn-on voltage exceeds 5%, the gate leakage current micro-adjustment circuit is activated, and the soft clamping adaptive adjustment circuit is set simultaneously. The gain coefficient of the micro-adjustment circuit is adjusted according to the power supply voltage fluctuation amplitude. The second stage is the hard clamping threshold. When the deviation between the gate voltage and the steady-state turn-on voltage exceeds 10%, the gate voltage clamping circuit is directly triggered. At the same time, the anti-interference and anti-jitter mechanism of hard clamping is added. The hard clamping action is triggered only when the voltage deviation exceeds the threshold for 3 sampling cycles. The current voltage deviation data is latched simultaneously and incorporated into the parameter correction system of the subsequent closed-loop feedback. At the same time, the seamless connection logic of the two-stage clamping is set. When the soft clamping action cannot correct the deviation, the hard clamping is automatically triggered to complete the voltage jump and secondary charge injection suppression during the clamping process.

4. The CMOS analog switch activation control method according to claim 1, characterized in that, This also includes constructing a quantitative evaluation system for on-resistance nonlinearity during the closed-loop feedback correction of timing parameters and voltage amplitude. The quantified value of on-resistance nonlinearity is obtained through multi-dimensional parameter fusion calculation. Based on the deviation between the quantified value and a preset threshold, the slope of the voltage change in the linearly rising step is dynamically corrected. Simultaneously, an adaptive distribution strategy for sampling points is set, with increased sampling points at the beginning and end of the linear rising phase, and the sampling density adjusted according to device characteristics in the intermediate phase. A correlation mapping relationship between nonlinearity and channel charge injection is established synchronously. The calculation expression for on-resistance nonlinearity is as follows: ; This refers to the on-resistance nonlinearity during the turn-on process of a CMOS analog switch. This represents the average value of the on-resistance during the linear rise phase. This represents the number of parameter sampling points during the linear ascent phase. For the first The real-time on-resistance value collected at each sampling point.

5. The CMOS analog switch activation control method according to claim 1, characterized in that, The static bias calibration step also includes real-time acquisition and calibration of the threshold voltages of NMOS and PMOS switches. By applying a millivolt-level test bias voltage to the drain and source of the device, the corresponding microampere-level drain and source current is acquired. The actual threshold voltage of the device under the current operating condition is obtained by fitting the device current-voltage characteristic curve. At the same time, the differential measurement method is used to eliminate the influence of substrate bias effect. The amplitude of the test bias voltage is adaptively adjusted for switches with different aspect ratios. The deviation between the actual threshold voltage and the reference threshold voltage is incorporated into the voltage amplitude calculation system of the multi-step gate turn-on pulse timing. In addition, a fast threshold voltage calibration is performed before each switch is turned on, rather than a single calibration is performed only during the power-on stage. The temperature drift coefficient of the device threshold voltage is pre-stored synchronously.

6. The CMOS analog switch activation control method according to claim 2, characterized in that, The pre-charge step stage also includes differential synchronous control of the pre-charge bias voltage of NMOS and PMOS switches, synchronously controlling the application timing of the pre-charge voltage of the two switches to keep the timing deviation within 500ps. At the same time, the drain-source current of the weak inversion layer in the channel is collected in real time during the pre-charge process, and the pre-charge bias voltage is finely adjusted in a closed loop to complete the formation control of the uniform weak inversion layer in the two channels. The device substrate bias voltage is adjusted in sync with the pre-charge bias voltage to complete the threshold voltage offset compensation caused by the substrate bulk effect. At the same time, the level status of the switch port is monitored in real time, and the bias voltage is adjusted immediately when the port level offset exceeds the preset range.

7. The CMOS analog switch activation control method according to claim 1, characterized in that, In the linear rise-step stage, synchronous matching control is also included for the gate voltage change slope of the NMOS and PMOS switches. This ensures that the absolute values ​​of the rising slope of the NMOS switch gate voltage and the falling slope of the PMOS switch gate voltage are completely consistent, so that the total on-resistance of the CMOS analog switch decreases smoothly during the turn-on process. At the same time, the gate voltage values ​​of the two transistors are collected every 1ns to calculate the slope deviation. In addition, the slope is nonlinearly fine-tuned according to the characteristic change of the channel from weak inversion to strong inversion. The slope is reduced at the beginning and end of the turn-on process and maintained at a constant slope in the middle stage. The absolute value of the slope is adaptively adjusted according to the change of the conduction characteristics of the adapter channel and the load capacitance of the switch port.

8. The CMOS analog switch activation control method according to claim 4, characterized in that, The quantitative evaluation of on-resistance nonlinearity also includes setting a three-level linkage nonlinearity control threshold. When the nonlinearity quantification value is below 1%, the voltage change slope of the current linear rise step remains unchanged. When the nonlinearity quantification value is between 1% and 3%, the voltage change slope is reduced by a fixed step size. When the nonlinearity quantification value is above 3%, the linear rise process is immediately paused, the device's static operating point is recalibrated, and the process is resumed. At the same time, the range of the three-level threshold is adaptively adjusted for different ambient temperatures. The threshold range is tightened under high temperature conditions and appropriately relaxed under low temperature conditions. The temperature drift change of the adapter device characteristics is also considered. After the nonlinearity exceeds the threshold, multi-dimensional parameters such as gate voltage, drain-source current, and threshold voltage are collected simultaneously to complete fault tracing and locate the core cause of the nonlinearity exceeding the standard. At the same time, a fast recovery mechanism is set after the pause. After recalibration, a smoother slope is used to gradually restore the linear rise process, and historical data of nonlinearity are statistically analyzed.

9. The CMOS analog switch activation control method according to claim 1, characterized in that, The closed-loop feedback step in the startup process also includes an adaptive adjustment mechanism for setting the sampling frequency. During the dynamic change phases of the pre-charging ladder and the linear ascending ladder, the parameter sampling frequency is set to 1GHz. During the stable phase of the steady-state locking ladder, the parameter sampling frequency is reduced to 100MHz. This reduces the dynamic power consumption and switching noise of the control circuit while ensuring monitoring accuracy. At the same time, a multi-sampling channel parallel operation mode is adopted. In the high-frequency sampling phase, a moving average digital filtering process is added to suppress parameter miscorrection caused by sampling noise. In the low-frequency sampling phase, a parameter abnormal jump monitoring mechanism is set up. When a parameter change is detected, the mode is immediately switched back to high-frequency sampling mode. In addition, for low-power scenarios powered by batteries, the sampling frequency in the steady-state phase is further reduced to balance monitoring accuracy and system power consumption.

10. The CMOS analog switch activation control method according to claim 1, characterized in that, The steady-state turn-on dynamic fine-tuning step after turn-on includes acquiring the device's real-time on-resistance, channel charge distribution, and drain-source voltage parameters every 100μs. When the on-resistance change exceeds 2%, the gate steady-state turn-on voltage is finely adjusted within a range of ±50mV. Simultaneously, a single-step fine-tuning step size of no more than 10mV is set. The entire operating temperature range of -40℃ to 125℃ is divided into 5 consecutive temperature segments, each with independent fine-tuning reference parameters. Based on the device's cumulative turn-on time and historical on-resistance change data, a device aging compensation model is established to dynamically adjust the fine-tuning threshold and step size to offset the performance degradation caused by the characteristic aging of the device during long-term operation. For multi-channel CMOS analog switch arrays, synchronous steady-state fine-tuning operations are performed to control the consistency of on-resistance between channels. At the same time, the integrity of the switch transmission signal is monitored in real time during fine-tuning. When signal distortion is detected, fine-tuning is immediately paused and restored to the reference gate voltage, thus completing the continuous maintenance of low on-resistance and high linearity conduction state of the CMOS analog switch across the entire temperature range and the entire power supply voltage fluctuation range.

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