CMOS transmission gate sampling switch circuit, charge injection compensation method, electronic device and storage medium

Abstract

This invention discloses a CMOS transmission gate sampling switch circuit, a charge injection compensation method, an electronic device, and a storage medium. The CMOS transmission gate sampling switch circuit includes: a CMOS transmission gate, an output compensation circuit, and an input compensation circuit. The CMOS transmission gate includes a first NMOS transistor MN1 and a first PMOS transistor MP1. The gate of MP1 is connected to a second logic signal, and the gate of MN1 is connected to a first logic signal. The output compensation circuit includes MP2 for compensating for charge injection in the MP1 channel and MN2 for compensating for charge injection in the MN1 channel. The input compensation circuit includes MP3 for compensating for charge injection in the MP1 channel and MN3 for compensating for charge injection in the MN1 channel. The CMOS transmission gate sampling switch circuit, charge injection compensation method, electronic device, and storage medium proposed in this invention can effectively suppress injection errors while maintaining a miniaturized structure, overcoming the performance limitations caused by charge injection in existing designs.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and relates to a sampling switch circuit, and more particularly to a CMOS transmission gate sampling switch circuit, a charge injection compensation method, an electronic device, and a storage medium. Background Technology

[0002] CMOS transmission gate sampling switches are controllable sampling switch circuits that can transmit full-swing analog signals without distortion. Due to their relatively constant on-resistance, they are widely used in integrated circuits such as data converters and sensors that require high linearity analog sampling. They are especially suitable for scenarios that require a certain degree of linearity but do not pursue extreme speed and accuracy.

[0003] As a key module in analog integrated circuits, the performance of sampling switches directly determines the overall accuracy and linearity of the system. With the rapid development of emerging fields such as wearable devices, the Internet of Things, artificial intelligence, and autonomous driving, the demand for high-performance sampling switches continues to rise, driving related technologies towards higher precision, lower power consumption, and smaller area. CMOS transmission gate sampling switches, due to their simple structure and good performance, have become one of the mainstream choices for such applications.

[0004] The basic structure of a CMOS transmission gate consists of an NMOS and a PMOS transistor connected in parallel, with their source and drain connected, serving as the input and output terminals respectively. The gates are controlled by a pair of complementary clock signals to ensure that both devices are turned on or off simultaneously. Due to the symmetry of the structure, the input and output terminals can be used interchangeably, exhibiting excellent bidirectional transmission characteristics. Compared to a single MOS switch, a CMOS transmission gate can achieve lossless transmission of analog signals across the entire power supply voltage swing, thanks to its complementary circuit structure. A single MOS switch is limited by threshold voltage loss and cannot fully transmit high or low level signals; however, a CMOS transmission gate, composed of an NMOS and a PMOS transistor connected in parallel, exhibits opposite on-resistance trends with the input voltage—the NMOS has low on-resistance and the PMOS has high on-resistance when the input voltage VIN is low, and vice versa when VIN is high. This complementary characteristic results in minimal variation in the equivalent on-resistance of the transmission gate over a wide input range, effectively improving the linearity of signal transmission.

[0005] In actual operation, when a MOSFET is turned on, conductive charge is stored in its channel. The charge stored in the NMOS channel can be represented as Q. n =-W n L n C ox (V dd -V in -V thn The charge stored in the PMOS channel can represent Q.p =W p L p C ox (V in -|V thp |), where W and L are the transistor dimensions (width and length, respectively), C ox It is the gate oxide capacitance per unit area, V dd V is the power supply voltage. th Threshold voltage (V) thn V is the threshold voltage of MN1. thp (This is the threshold voltage of MP1). When the switch is turned off, these charges are released through the source and drain terminals and injected into the sampling capacitor, causing a jump in the sampling signal. This phenomenon is called the charge injection effect. To suppress this effect, the size ratio of the NMOS to the PMOS can be adjusted so that Q is lower than the threshold voltage of MP1 at a specific input voltage. n +Q p =0, the charges released from the channels of the two exactly cancel each other out, thus reducing the jump amplitude at the output. However, when the input voltage deviates from this specific value, due to the mismatch in the changes in charge between the NMOS and PMOS channels, the charge injection cannot be completely canceled out, thus introducing residual error.

[0006] In sensor chip circuits, chopping technology is typically used to eliminate offset: the input signal is chopped and modulated by a transmission gate before being output to the subsequent circuit. When the differential amplitude of the input signal is large, a mismatched charge injection effect occurs when the positive and negative terminals of the signal pass through the transmission gate, causing a jump in the sampling output. After subsequent filtering, this ultimately manifests as a ripple at the output that is positively correlated with the magnitude of the input differential signal. This phenomenon is undesirable in practical applications.

[0007] In view of this, there is an urgent need to design a new CMOS transmission gate sampling switch circuit in order to overcome at least some of the above-mentioned defects of existing CMOS transmission gate sampling switch circuits. Summary of the Invention

[0008] This invention provides a CMOS transmission gate sampling switch circuit and its charge injection compensation method, which can effectively suppress injection error while maintaining a miniaturized structure and overcome the performance limitations caused by charge injection in existing designs.

[0009] To solve the above-mentioned technical problems, according to one aspect of the present invention, the following technical solution is adopted: A CMOS transmission gate sampling switch circuit, the CMOS transmission gate sampling switch circuit comprising: The CMOS transmission gate includes a first NMOS transistor MN1 and a first PMOS transistor MP1. The source of MN1 and the drain of MP1 are connected to the input terminal, and the drain of MN1 and the source of MP1 are connected to the output terminal. The gate of MP1 is connected to a second logic signal, and the gate of MN1 is connected to a first logic signal. When the first logic signal is the power supply voltage VDD, both the first NMOS transistor MN1 and the first PMOS transistor MP1 are turned on, and when the first logic signal is 0, both transistors are turned off. The first logic signal and the second logic signal are inverted logic signals. The output compensation circuit is connected to the first NMOS transistor MN1 and the first PMOS transistor MP1, respectively, and includes a second PMOS transistor MP2 for compensating for channel charge injection of MP1 and a second NMOS transistor MN2 for compensating for channel charge injection of MN1; wherein, the source and drain of the second PMOS transistor MP2 are shorted and connected to the output terminal, and the gate of the second PMOS transistor MP2 is connected to the first logic signal; the source and drain of the second NMOS transistor MN2 are shorted and connected to the output terminal, and the gate of the second NMOS transistor MN2 is connected to the second logic signal; The input compensation circuit is connected to the first NMOS transistor MN1 and the first PMOS transistor MP1, and includes a third PMOS transistor MP3 for compensating for channel charge injection of MP1 and a third NMOS transistor MN3 for compensating for channel charge injection of MN1. The source and drain of the third PMOS transistor MP3 are shorted and connected to the input terminal, and the gate of the third PMOS transistor MP3 is connected to the first logic signal. The source and drain of the third NMOS transistor MN3 are shorted and connected to the input terminal, and the gate of the third NMOS transistor MN3 is connected to the second logic signal.

[0010] In one embodiment of the present invention, the size relationship between the first NMOS transistor MN1 and the first PMOS transistor MP1 satisfies a set condition to ensure that when the input voltage VIN changes within a set range, the parallel value of the on-resistance of the first NMOS transistor MN1 and the first PMOS transistor MP1 changes within the set range.

[0011] As one embodiment of the present invention, the width-to-length ratio of the second PMOS transistor MP2 and the third PMOS transistor MP3 used to compensate for the charge injection at the output and input terminals of the first PMOS transistor MP1 meets the set conditions, so that the second PMOS transistor MP2 or / and the third PMOS transistor MP3 conducts after the switch is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal. The width-to-length ratio of the second NMOS transistors MN2 and MN3, used to compensate for the charge injection at the output and input terminals of the first NMOS transistor MN1, meets the set conditions, so that the second NMOS transistor MN2 or / and the third NMOS transistor MN3 conducts after the switch is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal.

[0012] In one embodiment of the present invention, the dimensional relationship between the first NMOS transistor MN1 and the first PMOS transistor MP1 satisfies This is used to ensure that the parallel change in the on-resistance of the first PMOS transistor MP1 and the first NMOS transistor MN1 is minimized when the input voltage VIN varies across the full swing range, thereby optimizing the linearity of signal transmission; where W n1 L is the width of the first NMOS transistor MN1. n1 W is the length of the first NMOS transistor MN1. p1 L is the width of the first PMOS transistor MP1. p1 The length of the first PMOS transistor MP1.

[0013] In one embodiment of the present invention, a second PMOS transistor MP2 and a third PMOS transistor MP3 are provided to compensate for charge injection at the output and input terminals of the first PMOS transistor MP1, and their width-to-length ratio is [missing information]. Among them, W p2 L is the width of the second PMOS transistor MP2. p2 W is the length of the second PMOS transistor MP2. p3 L is the width of the third PMOS transistor MP3. p3 The length of the third PMOS transistor MP3; A second NMOS transistor MN2 and a third NMOS transistor MN3 are configured to compensate for charge injection at the output and input terminals of the first NMOS transistor MN1, with a width-to-length ratio of [missing value]. Among them, W n2 L is the width of the second NMOS transistor MN2. n2 W is the length of the second NMOS transistor MN2. n3 L is the width of the third NMOS transistor MN3. n3 The length of the third NMOS transistor MN3.

[0014] According to another aspect of the present invention, the following technical solution is adopted: a charge injection compensation method for the above-mentioned CMOS transmission gate sampling switch circuit, the charge injection compensation method comprising: When the first logic signal is the power supply voltage VDD, both the first NMOS transistor MN1 and the first PMOS transistor MP1 are turned on; when the first logic signal is 0, both the first NMOS transistor MN1 and the first PMOS transistor MP1 are turned off. The second PMOS transistor MP2 compensates for the channel charge injection of the first PMOS transistor MP1 at the output terminal, and the second NMOS transistor MN2 compensates for the channel charge injection of the first NMOS transistor MN1 at the output terminal. The third PMOS transistor MP3 compensates for the channel charge injection of the first PMOS transistor MP1 at its input terminal, and the third NMOS transistor MN3 compensates for the channel charge injection of the first NMOS transistor MN1 at its input terminal.

[0015] As one embodiment of the present invention, the size relationship between the first NMOS transistor MN1 and the first PMOS transistor MP1 is set to meet the set conditions, so as to ensure that when the input voltage VIN changes within the set range, the parallel value of the on-resistance of the first NMOS transistor MN1 and the first PMOS transistor MP1 changes within the set range. The width-to-length ratio of the second PMOS transistor MP2 and the third PMOS transistor MP3, which are used to compensate for the charge injection at the output and input terminals of the first PMOS transistor MP1, is set to meet the set conditions so that the second PMOS transistor MP2 or / and the third PMOS transistor MP3 conducts after the switch is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal. The width-to-length ratio of the second NMOS transistor MN2 and the third NMOS transistor MN3, used to compensate for charge injection at the output and input terminals of MN1, is set to meet the set conditions so that the second NMOS transistor MN2 or / and the third NMOS transistor MN3 conducts after the switch is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal.

[0016] In one embodiment of the present invention, the dimensional relationship between the first PMOS transistor MP1 and the first NMOS transistor MN1 is set to satisfy... This proportional relationship is used to ensure that when the input voltage VIN varies across the full swing range, the parallel change in the on-resistance of the first PMOS transistor MP1 and the first NMOS transistor MN1 is minimized, thereby optimizing the linearity of signal transmission; where W n1 L is the width of the first NMOS transistor MN1. n1 W is the length of the first NMOS transistor MN1. p1 L is the width of the first PMOS transistor MP1. p1 The length of the first PMOS transistor MP1; A second PMOS transistor MP2 and a third PMOS transistor MP3 are configured to compensate for charge injection at the output and input terminals of the first PMOS transistor MP1, with their width-to-length ratio being [value missing]. Among them, W p2 L is the width of the second PMOS transistor MP2. p2 W is the length of the second PMOS transistor MP2. p3 L is the width of the third PMOS transistor MP3. p3 The length of the third PMOS transistor MP3; the second PMOS transistor MP2 and the third PMOS transistor MP3 are turned on after the first PMOS transistor MP1 is turned off, absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal; A second NMOS transistor MN2 and a third NMOS transistor MN3 are configured to compensate for charge injection at the output and input terminals of the first NMOS transistor MN1, with their width-to-length ratio being [value missing]. Among them, W n2 L is the width of the second NMOS transistor MN2. n2 W is the length of the second NMOS transistor MN2. n3 L is the width of the third NMOS transistor MN3. n3 The length of the third NMOS transistor MN3 is given. The second NMOS transistor MN2 and the third NMOS transistor MN3 are turned on after the first NMOS transistor MN1 is turned off, absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection on the sampling signal.

[0017] According to another aspect of the present invention, the following technical solution is adopted: an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the above method.

[0018] According to another aspect of the present invention, the following technical solution is adopted: a storage medium storing computer program instructions thereon, which, when executed by a processor, implement the steps of the above-described method.

[0019] The beneficial effects of this invention are as follows: the CMOS transmission gate sampling switch circuit, charge injection compensation method, electronic device and storage medium proposed in this invention make the charge injection effect as independent of the input voltage as possible, which can effectively suppress injection error while maintaining miniaturized structure and overcome the performance limitations caused by charge injection in existing designs.

[0020] In one application scenario of the present invention, in order to suppress the charge injection effect introduced therefrom, compensation transistors MN2, MN3, MP2, and MP3 are added to the circuit. These compensation transistors are turned on after the switching transistor is turned off, and their size is set to half that of the corresponding switching transistor, so as to accurately absorb the charge released in the channel, thereby effectively eliminating the interference of charge injection on the sampling signal.

[0021] In this structure, NMOS and PMOS compensation transistors, which are opposite to the switching timing of the transmission gate transistor, are used to absorb the charge in the channel after the transmission gate transistor is turned off. Even if the input voltage is different, there will be no mismatched charge injection effect, thus avoiding sampling signal jumps and output ripple caused by different input voltages. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a traditional CMOS transmission gate sampling switch structure.

[0023] Figure 2 This is a schematic diagram of a CMOS transmission gate sampling switch circuit in one embodiment of the present invention. Detailed Implementation

[0024] The preferred embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0025] To further understand the present invention, preferred embodiments of the present invention are described below in conjunction with examples. However, it should be understood that these descriptions are only for further illustrating the features and advantages of the present invention, and not for limiting the scope of the claims of the present invention.

[0026] The description in this section pertains to only a few typical embodiments, and the present invention is not limited to the scope of the embodiments described. Substitution of identical or similar prior art methods with some technical features in the embodiments is also within the scope of the description and protection of this invention.

[0027] The steps described in the various embodiments in the specification are for illustrative purposes only, and the implementation of this application is not limited by the order of the steps.

[0028] The term "coupled" or "connected" in the specification includes both direct and indirect connections, such as connections made through active devices, passive devices, or electrical conduction media; it may also include connections made by other active or passive devices that are known to those skilled in the art and can achieve the same or similar functional purpose, such as connections made through circuits or components such as switches or follower circuits.

[0029] This invention discloses a CMOS transmission gate sampling switch circuit. Figure 2 This is a schematic diagram of a CMOS transmission gate sampling switch circuit structure in one embodiment of the present invention; please refer to [link / reference]. Figure 2The CMOS transmission gate sampling switch circuit includes: a CMOS transmission gate, an output compensation circuit, and an input compensation circuit.

[0030] The CMOS transmission gate includes a first NMOS transistor MN1 and a first PMOS transistor MP1. The source of MN1 and the drain of MP1 are connected to the input terminal, and the drain of the first NMOS transistor MN1 and the source of MP1 are connected to the output terminal; the gate of MP1 is connected to... The gate of the first NMOS transistor MN1 is connected to the CLK signal (the first logic signal). When CLK = power supply voltage VDD, both the first NMOS transistor MN1 and the first PMOS transistor MP1 are turned on, and both transistors are turned off when CLK = 0. The first logic signal and the second logic signal are logic signals that are inverses of each other.

[0031] The output compensation circuit is connected to the first NMOS transistor MN1 and the first PMOS transistor MP1, respectively. It includes a second PMOS transistor MP2 for compensating for channel charge injection in MP1 and a second NMOS transistor MN2 for compensating for channel charge injection in the first NMOS transistor MN1. The source and drain of the second NMOS transistor MP2 are shorted and connected to the output terminal, and the gate of the second PMOS transistor MP2 is connected to the CLK signal. The source and drain of the second NMOS transistor MN2 are shorted and connected to the output terminal, and the gate of the second NMOS transistor MN2 is connected to... Signal.

[0032] The input compensation circuit is connected to the first NMOS transistor MN1 and the first PMOS transistor MP1, respectively, and includes a third PMOS transistor MP3 for compensating for channel charge injection in MP1 and a third NMOS transistor MN3 for compensating for channel charge injection in MN1. The source and drain of the third PMOS transistor MP3 are short-circuited and connected to the input terminal, and its gate is connected to the CLK signal. The source and drain of the third NMOS transistor MN3 are short-circuited and connected to the input terminal, and its gate is connected to... Signal.

[0033] In one embodiment of the present invention, the size relationship between the transmission gate switching transistors (first PMOS transistor MP1 and first NMOS transistor MN1) satisfies a set condition to ensure that when the input voltage VIN changes within a set range, the parallel value of the on-resistance of the first PMOS transistor MP1 and the first NMOS transistor MN1 changes within the set range.

[0034] The width-to-length ratio of the second PMOS transistors MP2 and MP3, used to compensate for the charge injection at the output and input terminals of the first PMOS transistor MP1, meets the set conditions, so that the second PMOS transistor MP2 or / and the third PMOS transistor MP3 conducts after the switch is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal.

[0035] The width-to-length ratio of the second NMOS transistors MN2 and MN3, used to compensate for the charge injection at the output and input terminals of the first NMOS transistor MN1, meets the set conditions, so that the second NMOS transistor MN2 or / and the third NMOS transistor MN3 conducts after the switch is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal.

[0036] In one embodiment of the present invention, the size relationship between the transmission gate switching transistors (the first PMOS transistor MP1 and the first NMOS transistor MN1) satisfies This is used to ensure that the parallel change in the on-resistance of MP1 and MN1 is minimized when the input voltage VIN varies across its full swing range (e.g., 0 to VDD), thereby optimizing the linearity of signal transmission; where W n1 L is the width of the first NMOS transistor MN1. n1 W is the length of the first NMOS transistor MN1. p1 L is the width of the first PMOS transistor MP1. p1 The length of the first PMOS transistor MP1.

[0037] A second PMOS transistor MP2 and a third PMOS transistor MP3 are configured to compensate for charge injection at the output and input terminals of MP1, with a width-to-length ratio of [missing information]. Among them, W p2 L is the width of the second PMOS transistor MP2. p2 W is the length of the second PMOS transistor MP2. p3 L is the width of the third PMOS transistor MP3. p3 The length of the third PMOS transistor MP3.

[0038] A second NMOS transistor MN2 and a third NMOS transistor MN3 are configured to compensate for charge injection at the output and input terminals of MN1, with a width-to-length ratio of [missing information]. Among them, W n2 L is the width of the second NMOS transistor MN2. n2 W is the length of the second NMOS transistor MN2. n3 L is the width of the third NMOS transistor MN3. n3 The length of the third NMOS transistor MN3.

[0039] This invention also explains a charge injection compensation method for the above-mentioned CMOS transmission gate sampling switch circuit, the charge injection compensation method comprising: When the first logic signal is the power supply voltage VDD, both the first PMOS transistor MP1 and the first NMOS transistor MN1 are turned on; when the first logic signal is 0, both the first PMOS transistor MP1 and the first NMOS transistor MN1 are turned off. The second PMOS transistor MP2 compensates for the channel charge injection of the first PMOS transistor MP1 at the output terminal, and the second NMOS transistor MN2 compensates for the channel charge injection of the first NMOS transistor MN1 at the output terminal. The third PMOS transistor MP3 compensates for the channel charge injection of the first PMOS transistor MP1 at its input terminal, and the third NMOS transistor MN3 compensates for the channel charge injection of the first NMOS transistor MN1 at its input terminal.

[0040] In one embodiment of the present invention, the size relationship between transmission gate switch transistors MP1 and MN1 is set to meet the set conditions, so as to ensure that when the input voltage VIN changes within the set range, the parallel value of the on-resistance of MP1 and MN1 changes within the set range. The width-to-length ratio of MP2 and MP3 is set to compensate for the charge injection at the output and input ends of MP1, so that it meets the set conditions, so that MP2 or / and MP3 conducts after the switching transistor is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference of charge injection on the sampling signal. The width-to-length ratio of MN2 and MN3, used to compensate for the charge injection at the output and input terminals of MN1, is set to meet the set conditions so that MN2 or / and MN3 conducts after the switch is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal.

[0041] In one embodiment of the present invention, the dimensional relationship between transmission gate switching transistors MP1 and MN1 is set to satisfy... This proportional relationship is used to ensure that when the input voltage VIN varies across its full swing range (e.g., from 0 to VDD), the parallel change in the on-resistance of MP1 and MN1 is minimized, thereby optimizing the linearity of signal transmission; where W n1 L is the width of MN1. n1 Let W be the length of MN1. p1 L is the width of MP1 p1 The length of MP1; MP2 and MP3 are configured to compensate for charge injection at the output and input terminals of MP1, and their aspect ratios are... Among them, W p2 L is the width of MP2 p2 W is the length of MP2 p3 L is the width of the MP3 file.p3 The length of MP3; MP2 and MP3 are turned on after MP1 is turned off, absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal; MN2 and MN3 are configured to compensate for charge injection at the output and input terminals of MN1, with a width-to-length ratio of [missing value]. Among them, W n2 L is the width of MN2. n2 Let W be the length of MN2. n3 L is the width of MN3. n3 MN2 and MN3 are the lengths of MN3. MN2 and MN3 are turned on after MN1 is turned off, absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal.

[0042] When the transmission gate switch is turned on, the amount of charge stored in the MN1 and MP1 channels can be expressed as Q, respectively. n =-W n L n C ox (V dd -V in -V thn ) and Q p =W p L p C ox (V in -|V thp |); where Vthn is the threshold voltage of MN1 and Vthp is the threshold voltage of MP1.

[0043] At the instant the transmission gate turns off, the charge stored in its channel is released to the source and drain ends, and it can usually be assumed that the charge is evenly distributed to both sides. To suppress the charge injection effect introduced by this, compensation transistors MN2, MN3, MP2, and MP3 are added to the circuit. These compensation transistors conduct after the switching transistor is turned off, and their size is set to half that of the corresponding switching transistor to accurately absorb the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal. In addition, the opposite signal at the gate can also effectively suppress clock feedthrough caused by clock transitions.

[0044] In summary, the CMOS transmission gate sampling switch circuit, charge injection compensation method, electronic device, and storage medium proposed in this invention make the charge injection effect as independent of the input voltage as possible. This can effectively suppress injection errors while maintaining a miniaturized structure and overcome the performance limitations caused by charge injection in existing designs.

[0045] In one application scenario of the present invention, in order to suppress the charge injection effect introduced therefrom, compensation transistors MN2, MN3, MP2, and MP3 are added to the circuit. These compensation transistors are turned on after the switching transistor is turned off, and their size is set to half that of the corresponding switching transistor, so as to accurately absorb the charge released in the channel, thereby effectively eliminating the interference of charge injection on the sampling signal.

[0046] In this structure, NMOS and PMOS compensation transistors, which are opposite to the switching timing of the transmission gate transistor, are used to absorb the charge in the channel after the transmission gate transistor is turned off. Even if the input voltage is different, there will be no mismatched charge injection effect, thus avoiding sampling signal jumps and output ripple caused by different input voltages.

[0047] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0048] The description and application of the present invention herein are illustrative and not intended to limit the scope of the invention to the embodiments described above. Effects or advantages involved in the embodiments may not be apparent due to various factors, and the description of effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and various substitutions and equivalents of the components in the embodiments are well known to those skilled in the art. It should be apparent to those skilled in the art that the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts without departing from the spirit or essential characteristics of the invention. Other variations and modifications can be made to the embodiments disclosed herein without departing from the scope and spirit of the invention.

Claims

1. A CMOS transmission gate sampling switch circuit, characterized in that, The CMOS transmission gate sampling switch circuit includes: The CMOS transmission gate includes a first NMOS transistor MN1 and a first PMOS transistor MP1. The source of MN1 and the drain of MP1 are connected to the input terminal, and the drain of MN1 and the source of MP1 are connected to the output terminal. The gate of MP1 is connected to a second logic signal, and the gate of MN1 is connected to a first logic signal. When the first logic signal is the power supply voltage VDD, both the first NMOS transistor MN1 and the first PMOS transistor MP1 are turned on, and when the first logic signal is 0, both transistors are turned off. The first logic signal and the second logic signal are inverted logic signals. The output compensation circuit is connected to the first NMOS transistor MN1 and the first PMOS transistor MP1, respectively, and includes a second PMOS transistor MP2 for compensating for channel charge injection of MP1 and a second NMOS transistor MN2 for compensating for channel charge injection of MN1; wherein, the source and drain of the second PMOS transistor MP2 are shorted and connected to the output terminal, and the gate of the second PMOS transistor MP2 is connected to the first logic signal; the source and drain of the second NMOS transistor MN2 are shorted and connected to the output terminal, and the gate of the second NMOS transistor MN2 is connected to the second logic signal; The input compensation circuit is connected to the first NMOS transistor MN1 and the first PMOS transistor MP1, and includes a third PMOS transistor MP3 for compensating for channel charge injection of MP1 and a third NMOS transistor MN3 for compensating for channel charge injection of MN1. The source and drain of the third PMOS transistor MP3 are shorted and connected to the input terminal, and the gate of the third PMOS transistor MP3 is connected to the first logic signal. The source and drain of the third NMOS transistor MN3 are shorted and connected to the input terminal, and the gate of the third NMOS transistor MN3 is connected to the second logic signal.

2. The CMOS transmission gate sampling switch circuit according to claim 1, characterized in that: The size relationship between the first NMOS transistor MN1 and the first PMOS transistor MP1 meets the set conditions to ensure that when the input voltage VIN changes within the set range, the parallel change in the on-resistance of the first NMOS transistor MN1 and the first PMOS transistor MP1 is minimized.

3. The CMOS transmission gate sampling switch circuit according to claim 2, characterized in that: The width-to-length ratio of the second PMOS transistor MP2 and the third PMOS transistor MP3 used to compensate for the charge injection at the output and input terminals of the first PMOS transistor MP1 meets the set conditions, so that the second PMOS transistor MP2 or / and the third PMOS transistor MP3 conducts after the first PMOS transistor MP1 is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal. The width-to-length ratio of the second NMOS transistors MN2 and MN3, used to compensate for the charge injection at the output and input terminals of the first NMOS transistor MN1, meets the set conditions, so that the second NMOS transistor MN2 or / and the third NMOS transistor MN3 conducts after the first NMOS transistor MN1 is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal.

4. The CMOS transmission gate sampling switch circuit according to claim 1, characterized in that: The dimensional relationship between the first NMOS transistor MN1 and the first PMOS transistor MP1 satisfies This is used to ensure that the parallel change in the on-resistance of the first PMOS transistor MP1 and the first NMOS transistor MN1 is minimized when the input voltage VIN varies across the full swing range, thereby optimizing the linearity of signal transmission; where W n1 L is the width of the first NMOS transistor MN1. n1 W is the length of the first NMOS transistor MN1. p1 L is the width of the first PMOS transistor MP1. p1 The length of the first PMOS transistor MP1.

5. The CMOS transmission gate sampling switch circuit according to claim 4, characterized in that: A second PMOS transistor MP2 and a third PMOS transistor MP3 are configured to compensate for charge injection at the output and input terminals of the first PMOS transistor MP1, with a width-to-length ratio of [missing information]. Among them, W p2 L is the width of the second PMOS transistor MP2. p2 W is the length of the second PMOS transistor MP2. p3 L is the width of the third PMOS transistor MP3. p3 The length of the third PMOS transistor MP3; A second NMOS transistor MN2 and a third NMOS transistor MN3 are configured to compensate for charge injection at the output and input terminals of the first NMOS transistor MN1, with a width-to-length ratio of [missing value]. Among them, W n2 L is the width of the second NMOS transistor MN2. n2 W is the length of the second NMOS transistor MN2. n3 L is the width of the third NMOS transistor MN3. n3 The length of the third NMOS transistor MN3.

6. A charge injection compensation method for the CMOS transmission gate sampling switch circuit according to any one of claims 1 to 5, characterized in that, The charge injection compensation method includes: When the first logic signal is the power supply voltage VDD, both the first NMOS transistor MN1 and the first PMOS transistor MP1 are turned on; when the first logic signal is 0, both the first NMOS transistor MN1 and the first PMOS transistor MP1 are turned off. The second PMOS transistor MP2 compensates for the channel charge injection of the first PMOS transistor MP1 at the output terminal, and the second NMOS transistor MN2 compensates for the channel charge injection of the first NMOS transistor MN1 at the output terminal. The third PMOS transistor MP3 compensates for the channel charge injection of the first PMOS transistor MP1 at its input terminal, and the third NMOS transistor MN3 compensates for the channel charge injection of the first NMOS transistor MN1 at its input terminal.

7. The charge injection compensation method according to claim 6, characterized in that: The size relationship between the first NMOS transistor MN1 and the first PMOS transistor MP1 is set to meet the set conditions to ensure that when the input voltage VIN changes within the set range, the parallel value of the on-resistance of the first NMOS transistor MN1 and the first PMOS transistor MP1 changes within the set range. The width-to-length ratio of the second PMOS transistor MP2 and the third PMOS transistor MP3, which are used to compensate for the charge injection at the output and input terminals of the first PMOS transistor MP1, is set to meet the set conditions so that the second PMOS transistor MP2 or / and the third PMOS transistor MP3 conducts after the switch is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal. The width-to-length ratio of the second NMOS transistor MN2 and the third NMOS transistor MN3, used to compensate for charge injection at the output and input terminals of MN1, is set to meet the set conditions so that the second NMOS transistor MN2 or / and the third NMOS transistor MN3 conducts after the switch is turned off, accurately absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal.

8. The charge injection compensation method according to claim 6, characterized in that: Set the dimensional relationship between the first PMOS transistor MP1 and the first NMOS transistor MN1 to satisfy... This proportional relationship is used to ensure that when the input voltage VIN varies across the full swing range, the parallel change in the on-resistance of the first PMOS transistor MP1 and the first NMOS transistor MN1 is minimized, thereby optimizing the linearity of signal transmission; where W n1 L is the width of the first NMOS transistor MN1. n1 W is the length of the first NMOS transistor MN1. p1 L is the width of the first PMOS transistor MP1. p1 The length of the first PMOS transistor MP1; A second PMOS transistor MP2 and a third PMOS transistor MP3 are configured to compensate for charge injection at the output and input terminals of the first PMOS transistor MP1, with their width-to-length ratio being [value missing]. Among them, W p2 L is the width of the second PMOS transistor MP2. p2 W is the length of the second PMOS transistor MP2. p3 L is the width of the third PMOS transistor MP3. p3 The length of the third PMOS transistor MP3; the second PMOS transistor MP2 and the third PMOS transistor MP3 are turned on after the first PMOS transistor MP1 is turned off, absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection to the sampling signal; A second NMOS transistor MN2 and a third NMOS transistor MN3 are configured to compensate for charge injection at the output and input terminals of the first NMOS transistor MN1, with their width-to-length ratio being [value missing]. Among them, W n2 L is the width of the second NMOS transistor MN2. n2 W is the length of the second NMOS transistor MN2. n3 L is the width of the third NMOS transistor MN3. n3 The length of the third NMOS transistor MN3 is given. The second NMOS transistor MN2 and the third NMOS transistor MN3 are turned on after the first NMOS transistor MN1 is turned off, absorbing the charge released in the channel, thereby effectively eliminating the interference caused by charge injection on the sampling signal.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 6 to 8.

10. A storage medium storing computer program instructions thereon, characterized in that, When executed by a processor, the computer program instructions implement the steps of the method according to any one of claims 6 to 8.

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