Metal oxide semiconductor gate cell and inverter

Abstract

A high voltage (e.g., 3.3V) tolerant MOS gate cell implemented with low voltage (e.g., 1.8V) MOS transistors. The MOS gate cell includes a source terminal, a drain terminal, and a gate terminal, and a first transistor, a second transistor, and a third transistor, each configured to operate at low voltage. The source of the first transistor is coupled to the source terminal, and the drain of the first transistor is coupled to the source of the second transistor. The source (or drain) of the third transistor is coupled to the gate of the first transistor, the drain (or source) of the third transistor is coupled to the gate terminal, and the gate of the third transistor is coupled to the gate of the second transistor. The drain of the second transistor is coupled to the drain terminal. The MOS gate cell functions exactly the same as a MOS transistor configured to operate at high voltage when a limit voltage (e.g., 1.65V) significantly lower than the high voltage is applied to the gate of the third transistor.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and particularly relates to a metal oxide semiconductor (MOS) gate cell and inverter. Background Technology

[0002] As process nodes continue to shrink and advance, the external supply voltage of chips is gradually migrating from higher to lower voltages, such as from 3.3V to 1.8V. Typically, if a 3.3V external power supply is used, a 3.3V device will be used in the design. If a 1.8V external power supply is used, a 1.8V device will generally be used. Some foundries offer processes that include both 3.3V and 1.8V devices to be compatible with both 3.3V and 1.8V single-supply applications. However, some foundries only offer processes for 1.8V devices. These 1.8V processes cannot support applications requiring only a 3.3V external power supply. Applying 3.3V directly to a 1.8V device will cause reliability issues and may even lead to device breakdown. Therefore, the supply voltage that a 1.8V device can withstand is strictly limited. For example, to meet the specifications and safe operating range of 1.8V devices, the external power supply voltage must not exceed 2V, and the gate-source voltage (VGS or VSG) and source-drain voltage (VDS or VSD) of 1.8V devices must not exceed their respective 2V limits. Summary of the Invention

[0003] Some embodiments of the present invention address the aforementioned limitations, enabling 1.8V devices to operate with a 3.3V external power supply. Some embodiments utilize stacked 1.8V devices combined with protection circuitry to construct a MOS circuit capable of operating at 3.3V while protecting the 1.8V devices from potential breakdown.

[0004] In some embodiments, a metal-oxide-semiconductor (MOS) gate cell includes a source terminal, a drain terminal, a gate terminal, and a first MOS transistor, a second MOS transistor, and a third MOS transistor. Each of these three MOS transistors has a source, a drain, and a gate, and is configured to operate at a first operating voltage. The source of the first MOS transistor is coupled to the source terminal of the MOS gate cell, and the drain of the first MOS transistor is coupled to the source of the second MOS transistor. One of the sources or drains of the third MOS transistor is coupled to the gate of the first MOS transistor, and the other source or drain of the third MOS transistor is coupled to the gate terminal of the MOS gate cell, while the gate of the third MOS transistor is coupled to the gate of the second MOS transistor. The drain of the second MOS transistor is coupled to the drain terminal of the MOS gate cell. When a limiting voltage significantly lower than a second operating voltage is applied to the gates of the third MOS transistor and the second MOS transistor, the MOS gate cell can operate as a MOS transistor operating at the second operating voltage, which is significantly higher than the first operating voltage.

[0005] In some implementation examples, the second operating voltage is approximately twice the first operating voltage, and the limiting voltage is approximately half the second operating voltage.

[0006] In some implementation examples, the first operating voltage is about 1.8V, the second operating voltage is about 3.3V, and the limiting voltage is about 1.6V to 1.85V.

[0007] In some implementation examples, the MOS gate cell is turned on when the gate-source voltage VSG or VGS exceeds a threshold voltage, forming a conductive path between the source and drain terminals; wherein the threshold voltage is approximately 60% of the second operating voltage.

[0008] In some implementation examples, when the MOS gate cell is turned on and the gate receives a voltage signal that varies between a first level and a second level (the second level is about a second operating voltage higher than the first level), for each of the first MOS transistor, the source-gate voltage VSG or VGS does not exceed the VSG or VGS limit of the MOS transistor itself, and the source-drain voltage VSD or VDS does not exceed the VSD or VDS limit of the MOS transistor itself.

[0009] In some implementation examples, the VSG and VGS limits are significantly lower than the second operating voltage, and the VSD and VDS limits are also significantly lower than the second operating voltage.

[0010] In some implementation examples, the second operating voltage is approximately twice the first operating voltage, and the VSD and VDS limits are approximately 1.1 times the first operating voltage.

[0011] In some implementation examples, the MOS gate cell also includes a weak diode coupled between the gate of the first MOS transistor and the power supply terminal of the MOS gate cell. This weak diode is used to maintain the source-gate voltage VSG or VGS of the first MOS transistor within its own VSG or VGS limit when the voltage at the gate terminal of the MOS gate cell remains stable for an extended period. The weak diode includes multiple diodes connected in series, each configured to operate at a first operating voltage.

[0012] In some implementation examples, the MOS gate cell does not contain any MOS transistors configured to operate at a second operating voltage.

[0013] In some embodiments, an inverter includes an input terminal, an output terminal, a first voltage terminal and a second voltage terminal, a P-type metal-oxide-semiconductor (PMOS) gate cell, and an N-type metal-oxide-semiconductor (NMOS) gate cell. The PMOS gate cell includes a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, each having a source, a drain, and a gate, and is configured to operate at a first operating voltage. The NMOS gate cell includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, each having a source, a drain, and a gate, and is configured to operate at a first operating voltage.

[0014] In some implementation examples, the source of the first PMOS transistor is coupled to a first voltage terminal, the drain of the first PMOS transistor is coupled to the source of the second PMOS transistor, the source of the third PMOS transistor is coupled to the gate of the first PMOS transistor, the drain of the third PMOS transistor is coupled to the input terminal, the gate of the third PMOS transistor is coupled to the gate of the second PMOS transistor, and the drain of the second PMOS transistor is coupled to the output terminal.

[0015] In some implementation examples, the source of the first NMOS transistor is coupled to the second voltage terminal, the drain of the first NMOS transistor is coupled to the source of the second NMOS transistor, the source of the third NMOS transistor is coupled to the gate of the first NMOS transistor, the drain of the third NMOS transistor is coupled to the input terminal, the gate of the third NMOS transistor is coupled to the gate of the second NMOS transistor, and the drain of the second NMOS transistor is coupled to the output terminal.

[0016] In some implementation examples, when a first limiting voltage significantly lower than the second operating voltage is applied to the gate of the third PMOS transistor, and a second limiting voltage significantly lower than the second operating voltage is applied to the gate of the third NMOS transistor, and the second operating voltage is applied between the first voltage terminal and the second voltage terminal, the inverter can operate normally at a second operating voltage significantly higher than the first operating voltage. Attached Figure Description

[0017] Figures 1A-1C A circuit diagram of a 3.3V-tolerant PMOS gate implemented using a 1.8V device, according to certain embodiments; Figure 2 A circuit diagram of a 3.3V PMOS gate according to certain embodiments; Figures 3A-3C A circuit diagram of a 3.3V-tolerant NMOS gate implemented using a 1.8V device, according to certain embodiments; Figure 4 A circuit diagram of a 3.3V NMOS gate according to certain embodiments; Figure 5 The circuit diagram shows a 3.3V-tolerant inverter implemented using a 1.8V device according to certain embodiments. Examples of the expected node voltage operating range are provided in parentheses in the diagram, where XVDD can vary between 2.7V and 3.6V. Figure 6 A circuit diagram of a weak P-type diode (PDIO) according to certain embodiments; Figure 7 A circuit diagram of a weak N-type diode (NDIO) according to certain embodiments; Figure 8A The circuit diagram for a 3.3V-tolerant inverter according to certain embodiments shows the node voltages during normal operation when IN=0V (low level); Figure 8B The circuit diagram for an inverter that can withstand 3.3V according to certain embodiments shows the node voltages under normal operating conditions when IN=3.3V (high level); Figure 9 According to certain embodiments, Figure 8A and Figure 8B The waveform of an inverter that can withstand 3.3V is shown in normal operating condition. Figure 10A The circuit diagram for a 3.3V-tolerant inverter according to certain embodiments shows the node voltage in standby mode when IN=0V (low level); Figure 10B According to certain embodiments, Figure 10AThe waveform of the inverter shown is in standby mode when IN=0V (low level), which can withstand 3.3V. Figure 11A The circuit diagram for a 3.3V-tolerant inverter according to certain embodiments shows the node voltage in standby mode when IN = 3.3V (high level); and Figure 11B According to certain embodiments, Figure 10B The waveform diagram shown is of an inverter that can withstand 3.3V in standby mode when IN=3.3V (high level). Detailed Implementation

[0018] Main power supply and signal specifications: Power and ground: XVDD: External power supply (2.7V–3.6V) VSS: Earth Signal: VGP: A global signal whose voltage is approximately half that of XVDD, i.e., VGP ≈ XVDD / 2. For example, when XVDD = 3.3V, VGP defaults to 1.65V. VGP can track and adjust as XVDD changes, and VGP itself is also adjustable. VGP is connected to one of the stacked PMOS devices, providing breakdown protection by forming a voltage drop across the VSD of the stacked PMOS devices.

[0019] VGN: A global signal, a constant voltage (e.g., 1.8V). VGN is also adjustable. VGN is connected to one of the stacked NMOS devices and provides breakdown protection by creating a voltage drop across VDS of the stacked NMOS devices.

[0020] PG: The gate signal of a device in a stacked PMOS device. PG switches between (VGP+VTHp) and XVDD, which can both fully turn on the PMOS device and help prevent dielectric breakdown.

[0021] NG: The gate signal of a device in a stacked NMOS device. NG switches between 0 and (VGN-VTHn), which can both fully turn on the NMOS device and help prevent dielectric breakdown.

[0022] As mentioned earlier, for a semiconductor chip to operate with a 3.3V external power supply, the nodes of its internal components (such as transistors) must be able to withstand a 3.3V voltage drop. However, some chip manufacturers (or foundries) only provide processes for manufacturing 1.8V devices, which are not directly compatible with applications requiring a single 3.3V external power supply. Applying 3.3V directly to a 1.8V device will cause reliability issues and may even lead to the breakdown of the 1.8V device.

[0023] When using lower voltage (e.g., 1.8V) devices in chips applied to higher voltage (e.g., 3.3V) power supplies, there are two main breakdown mechanisms: The first is dielectric breakdown, where the gate-source voltage (source-gate voltage VSG or VGS) of the core device exceeds its limit for a period of time. This is a time-dependent dielectric breakdown (TDDB) failure mechanism: when the gate oxide layer is continuously subjected to a voltage exceeding the VGS limit for a certain period, breakdown will eventually occur. The second is hard breakdown (or source-drain VDS breakdown) mechanism. This type of breakdown occurs when the source-drain voltage (VDS or VSD) exceeds the VDS limit of the core device.

[0024] In most cases, the limits for VGS and VDS are approximately 110% of the device's operating voltage. Therefore, to address the reliability issues arising from using lower voltage (e.g., 1.8V) devices in a higher voltage (e.g., 3.3V) power supply, it is necessary to ensure that the VGS and VDS of these 1.8V devices meet the following requirements: (1) VGS ≤ VGS limit (e.g., 2V); (2) VDS ≤ VDS limit (e.g., 2V).

[0025] Figure 1A A circuit implementation of a high-voltage (e.g., 3.3V) withstand P-type metal-oxide-semiconductor (PMOS) gate cell 100, implemented using a low-voltage (e.g., 1.8V) device, is shown according to certain embodiments. As described below, the PMOS gate cell 100 functions similarly to... Figure 2 The conventional high-voltage (e.g., 3.3V) PMOS device 200 shown is completely identical and has similar operating characteristics. Figure 1A As shown, with Figure 2 Similar to the conventional high-voltage (e.g., 3.3V) PMOS device 200, the high-voltage (e.g., 3.3V) withstand PMOS gate cell 100 has a gate terminal (G), a source terminal (S), and a drain terminal (D), each of which can be coupled to a high-voltage (e.g., 3.3V) power supply XVDD or ground VSS.

[0026] The high-voltage (e.g., 3.3V) withstand-type PMOS gate cell 100 includes a first low-voltage PMOS device P0 and a second low-voltage PMOS device P1. Both PMOS devices can be, for example, P-type metal-oxide-semiconductor field-effect transistors (MOSFETs), which have a gate, a source, and a drain. PMOS devices P0 and P1 are connected in a stacked or series manner between the source terminal S and the drain terminal D, so that the voltage drop between S and D is not completely applied across the source and drain of either PMOS device, thereby preventing PMOS devices P0 or P1 from being damaged by hard breakdown (or source-drain VDS breakdown) due to the voltage difference of the entire high-voltage (e.g., 3.3V) power supply.

[0027] like Figure 1AAs shown, the source of the first PMOS device P0 is coupled to the source terminal S of the MOS gate cell 100, and the drain of the first PMOS device P0 is coupled to the source of the second PMOS device P1. The gate of the second PMOS device P1 is coupled to the VGP terminal, which is used to receive a global signal at an intermediate level, which is between ground VSS and a high voltage (such as 3.3V). The MOS gate cell 100 also includes a third low-voltage PMOS device P2. The drain of the third low-voltage PMOS device P2 is coupled to the gate of the first PMOS device P0, the source of the third low-voltage PMOS device P2 is coupled to the gate terminal G, and the gate of the third low-voltage PMOS device P2 is coupled to the gate of the second PMOS device P1.

[0028] The VGP voltage is approximately the average of XVDD (e.g., 3.3V) and VSS (e.g., 0V) (e.g., 1.65V). The VGP voltage is applied to the gate of P1 and limits the voltage at the gate of P0 via the PMOS device P2. For example, when there is a high voltage (e.g., 3.3V) between the source terminal S and the gate terminal G of the PMOS gate cell 100, the third PMOS device P2 is configured to maintain the PG node between the gate of the first PMOS device P0 and the drain of the third PMOS device P2 at an intermediate voltage (e.g., 1.74V), thereby ensuring that the VSG voltage between the source and gate of the first PMOS device P0 is below the VSG limit of the first PMOS device P0. Therefore, the voltage between either P0 or P1 will not exceed 2V, thus preventing TDDB failure in either P0 or P1. VGP (approximately half of XVDD) can be a fixed voltage or can track the XVDD level as XVDD fluctuates.

[0029] In some embodiments, the PMOS gate cell 100 further includes a weak P-type diode (weak_pdio) Pd, which is coupled between the power supply terminal for connecting to the external power supply XVDD and the PG node, as discussed in detail below.

[0030] Figure 1B The voltage distribution of the PMOS gate cell 100 in the following states is shown: source terminal voltage V S The gate voltage is 3.3V. GWith the voltage at 0V, the gate voltage VGP of the second PMOS device P1 is 1.65V, and the drain of the second PMOS device P1 is grounded (0V) through a sufficiently large resistor R, so large that the source-drain resistance of P0 and P1 in the "on" state is negligible. As shown in the figure, the voltage at node PG is 1.74V, therefore the VSG voltage of P0 is 1.56V; this condition turns on the 1.8V device P0 and connects node AA to the source terminal S. When VGP is 1.65V, the VSG voltage of P1 is 1.65V, and P1 turns on, causing the source-drain current ISD to flow from the source terminal S to the drain terminal D, and then through the resistor R to ground. In other words, when VGP is 0V, the source-drain resistance of P0 and P1 in the "on" state is negligible. S –V G At 3.3V, PMOS gate cell 100 is turned on or in the "on" state.

[0031] In the "on" state, because P2 is off, the PG node is disconnected from the gate G, and the voltage of the PG node is at an intermediate level (e.g., 1.74V). With VGP at 1.65V and the PG node voltage at 1.74V, the VSG of P0 is 1.56V, the VSG of P1 is 1.65V, and the VSG of P2 is 0.09V, all of which are lower than the 2V VSG limit for 1.8V devices. Simultaneously, the VSD of P0 and P1 is 0V, while the VSD of P2 is 1.74V, all of which are also lower than the 2V VSD limit for 1.8V devices.

[0032] As previously mentioned, the PMOS gate cell 100 also includes a weak P-type diode (Pd) coupled between the power supply terminal for connecting the external power supply XVDD and the PG node. Without this weak diode Pd, when the source terminal S is coupled to XVDD (e.g., 3.3V) and the gate terminal G remains in a stable 0V state for an extended period, the PG node would not be able to maintain an intermediate level of, for example, 1.74V. Due to leakage, the voltage of the PG node would gradually discharge and drop to zero, causing the VSG voltage of P0 to rise and exceed its VSG limit. The conduction capability of the weak diode Pd is designed to be weak enough to ensure that it does not interfere with the normal operation of the PMOS gate cell 100. When the PMOS gate cell 100 is in a stable state, once the voltage of the PG node drops below a certain value (e.g., 1.5V), the weak diode Pd conducts, charging and boosting the PG node. In this way, the weak diode Pd ensures that the voltage of the PG node does not drop to zero when the PMOS gate cell is in a stable state for an extended period. In some embodiments, such as Figure 6 As shown, the weak diode 600 may include multiple (e.g., 2-4) stacked P-type diodes (e.g., P-type diode 610) to maintain a sufficient voltage gap between the PG node and the power supply terminal.

[0033] Figure 1CThe voltage distribution of the PMOS gate cell 100 in the following states is shown: source terminal S voltage V S The voltage is 3.3V, and the gate voltage (G) is V. G The voltage is 3.3V. The gate voltage VGP of the second PMOS device P1 is 1.65V, and the drain D of the second PMOS device P1 is grounded through resistor R (0V). As shown in the figure, since the VSG voltage of P2 is 1.65V, P2 is turned on, connecting the PG node to the gate terminal G (i.e., the node PG voltage is 3.3V). Therefore, the VSG voltage of P0 is 0V, that is, P0 is in the off state, exhibiting a high source-drain resistance, causing the AA node voltage between P0 and P1 to drop to a lower value (e.g., 1.93V). Since the gate voltage of P1 is 1.65V, the AA node voltage is insufficient to turn on P1, so P1 is also turned off. In other words, when VGP is 1.65V, the drain D of the second PMOS device P1 is grounded through resistor R (0V). S –V G When the voltage is 0V, the PMOS gate cell 100 is in the off or "off" state.

[0034] In the "off" state, since P0 and P1 are stacked between the source terminal S and the drain terminal D, the voltage difference of approximately 3.3V across the source and drain is distributed across the two PMOS devices P0 and P1, resulting in a VSD voltage of 1.37V for P0 and 1.93V for P1. Both of these voltage values ​​are safely below the 2V VSD limit of the 1.8V PMOS devices P0 and P1.

[0035] Figure 3A A circuit implementation of a high-voltage (e.g., 3.3V) tolerant N-type metal-oxide-semiconductor (NMOS) gate cell 300, implemented using a low-voltage (e.g., 1.8V) device, is shown according to certain embodiments. As described below, the NMOS gate cell 300 functions similarly to... Figure 4 The conventional high-voltage (e.g., 3.3V) NMOS device 400 shown is completely identical and has similar operating characteristics. Figure 3A As shown, with Figure 4 Similar to the conventional high-voltage (e.g., 3.3V) NMOS device 400, the high-voltage (e.g., 3.3V) withstand NMOS gate cell 300 has a gate terminal (G), a source terminal (S), and a drain terminal (D), each of which can be coupled to a high-voltage (e.g., 3.3V) power supply XVDD or ground VSS.

[0036] The high-voltage (e.g., 3.3V) withstand-type NMOS gate cell 300 includes a first low-voltage NMOS device N0 and a second low-voltage NMOS device N1. Both NMOS devices can be, for example, N-type metal-oxide-semiconductor field-effect transistors (MOSFETs), which have a gate, a source, and a drain. NMOS devices N0 and N1 are connected in a stacked or series manner between the source terminal S and the drain terminal D, so that the voltage drop between S and D is not completely applied across the source and drain of either NMOS device, thereby preventing NMOS devices N0 or N1 from being damaged by hard breakdown (or source-drain VDS breakdown) due to bearing the voltage difference of the entire high-voltage (e.g., 3.3V) power supply.

[0037] like Figure 3A As shown, the source of the first NMOS device N0 is coupled to the source terminal S of the NMOS gate cell 300, and the drain of the first NMOS device P0 is coupled to the source of the second NMOS device N1. The gate of the second NMOS device N1 is coupled to the VGN terminal, and the VGP terminal is used to receive a global signal at an intermediate level, which is between ground and a high voltage (e.g., 3.3V). The NMOS gate cell 300 also includes a third NMOS device N2, the source of the third NMOS device N2 is coupled to the gate of the first NMOS device N0, the drain of the third NMOS device N2 is coupled to the gate terminal G, and the gate of the third PMOS device N2 is coupled to the gate of the second NMOS device N1.

[0038] The VGN voltage is approximately or slightly higher than the average of XVDD (e.g., 3.3V) and VSS (e.g., 0V) (e.g., 1.8V). The VGN voltage is applied to the gate of N1 and limits the voltage at the gate of N0 via the NMOS device N2. For example, when there is a high voltage (e.g., 3.3V) between the source terminal S and the gate terminal G of the NMOS gate cell 300, the third NMOS device N2 is configured to maintain the NG node between the gate of the first NMOS device N0 and the drain of the third NMOS device N2 at an intermediate voltage (e.g., 1.37V), thereby ensuring that the VSG voltage between the source and gate of the first NMOS device N0 is below the VSG limit of the first NMOS device N0. Therefore, the voltage between either N0 or N1 will not exceed 2V, thus preventing TDDB failure in either N0 or N1. VGN (approximately or slightly higher than half of XVDD) can be a fixed voltage or can track the XVDD level as XVDD fluctuates.

[0039] In some embodiments, the NMOS gate cell also includes a weak N-type diode (Nd), which is coupled between the ground terminal used for grounding and the NG node, as discussed in detail below.

[0040] Figure 3BThe voltage distribution of the NMOS gate cell 300 in the following states is shown: source terminal voltage V S The gate voltage is 0V. G The voltage is 0V. The gate voltage VGN of the second NMOS device N1 is 1.8V, and the drain of the second NMOS device N1 is coupled to the 3.3V power supply voltage through a sufficiently large resistor R. This resistor R is so large that the source-drain resistance of N0 and N1 in the "on" state is negligible. As shown in the figure, when VGN is 1.8V and VG is 0V, N2 is turned on, connecting the gate of N0 to the gate terminal G, making the VGS voltage of N0 0V, that is, N0 is in the off state, exhibiting a high source-drain resistance, thereby reducing the BB node voltage between N0 and N1 to a value that is insufficient to turn on N1 (e.g., 1.69V, because the gate voltage of N1 is 1.8V). Therefore, N1 is also turned off. In other words, when VGN is 0V, the drain voltage of the second NMOS device N1 is 1.8V, and the drain voltage of the second NMOS device N1 is coupled to the 3.3V power supply voltage through a resistor R with a sufficiently large value. G –V S When the voltage is 0V, the NMOS gate cell 300 is in the cutoff or "off" state.

[0041] In the "off" state, because N0 and N1 are stacked between the source terminal S and the drain terminal D, the voltage difference of approximately 3.3V across the source and drain is distributed across the two NMOS devices N0 and N1, resulting in a VSD voltage of 1.69V for N0 and 1.61V for N1. Both of these voltage values ​​are significantly lower than the 2V VSD limit of the 1.8V NMOS devices N0 and N1.

[0042] Figure 3C The voltage distribution of the NMOS gate cell 300 in the following states is shown: source terminal voltage V S The gate voltage is 0V. G The voltage is 3.3V. The gate voltage VGN of the second NMOS device N1 is 1.8V, and the drain D of the second NMOS device N1 is coupled to the 3.3V supply voltage through resistor R. As shown in the figure, the voltage of node NG is 1.37V, therefore the VGS voltage of N0 is 1.37V; this turns on the 1.8V device N0 and connects node BB to the source terminal S. With VGN at 1.8V, the VGS of N1 is also 1.8V, so N1 turns on, causing the source-drain current ISD to flow from the source terminal S to the drain terminal D, and then through resistor R to ground. In other words, when VGN is 1.3V, the drain current ISD flows from the source terminal S to the drain terminal D, and then through resistor R to ground. G –V S At 3.3V, the NMOS gate cell 300 is either turned on or in an "on" state.

[0043] In the "on" state, because N2 is off, the NG node is disconnected from the gate G, and the voltage of the NG node is at an intermediate level (e.g., 1.37V). With VGN at 1.8V and the NG node voltage at 1.37V, the VGS of N0 is 1.37V, the VGS of N1 is 1.8V, and the VGS of N2 is 0.43V, all of which are lower than the 2V VGS limit for a 1.8V device. Simultaneously, the VDS of N1 and N2 are both 0V, while the VDS of N2 is 1.93V, all of which are also lower than the 2V VDS limit for a 1.8V device.

[0044] As previously mentioned, the NMOS gate cell also includes a weak n-type diode (Nd), which is coupled between the NG node and the ground terminal. Without this weak diode Nd, when the source terminal S is grounded (e.g., 0V) and the gate terminal G remains in a steady state of 3.3V for an extended period, the NG node would not be able to maintain an intermediate level of, for example, 1.37V. The voltage of the NG node would gradually increase due to leakage current. The conduction capability of the weak diode Nd is designed to be weak enough to ensure that it does not interfere with the normal operation of the NMOS gate cell 300. When the NMOS gate cell 300 is in a steady state, once the voltage of the NG node rises above a certain value (e.g., 1.5V), the weak diode Nd will conduct, discharging the NG node. Therefore, the weak diode Nd ensures that the voltage of the NG node does not increase significantly when the NMOS gate cell is in a steady state for an extended period. In some embodiments, such as Figure 7 As shown, the weak diode 700 may include multiple (e.g., 2-4) stacked N-type diodes 710 to maintain a sufficient voltage gap between the NG node and the power supply terminal.

[0045] Figure 5 An inverter 500 with a 3.3V tolerance, comprising a PMOS gate cell 100 and an NMOS gate cell 300, is shown according to certain embodiments. This inverter 500 is a fundamental and core gate circuit or module in most circuit designs. This 3.3V-tolerant inverter is implemented entirely with 1.8V devices. Figure 1A and 3A As shown, the inverter 500 includes PMOS stacked devices P0 and P1, NMOS stacked devices N0 and N1, and their respective protection circuits, which can be used to build other high-voltage related circuits or functional modules such as NAND gates and NOR gates.

[0046] Reference Figure 5The power supply voltage XVDD can vary between 2.7V and 3.6V. VGP is a global signal with a voltage approximately half that of XVDD (VGP = XVDD / 2). VGP tracks and follows changes in XVDD. For example, when XVDD = 3.3V, VGP = 1.65V. VGN is another global signal, a constant voltage of 1.8V. VGP and VGN can be generated from the external power supply XVDD via an analog circuit module. The input signal "IN" can switch between 0V and XVDD. The output signal "OUT" also switches between 0V and XVDD in response to the input "IN".

[0047] In some embodiments, with VGP set, when IN=0V, the voltage of the PG node drops to VGP+VTHp, where VTHp is the threshold voltage of P2. When IN=XVDD, the voltage of the PG node reaches XVDD.

[0048] In some embodiments, with VGN set, the voltage of the NG node is 0V when IN=0V. When IN=XVDD, the voltage of the NG node drops to VGN-VTHn, where VTHn is the threshold voltage of N2.

[0049] In some embodiments, the voltage at the PG node will not drop completely to 0V, nor will the voltage at the NG node rise completely to XVDD. Otherwise, they would violate the VGS voltage limits for 1.8V devices P0 and N0. In practice, P2 limits the drop of PG to a maximum of VGP + VTHp, while N2 limits the rise of NG to a maximum of VGN - VTHn. Therefore, the range of PG is (VGP + VTHp) to XVDD, and the range of NG is 0V to (VGN - VTHn).

[0050] The limited variation ranges of VGP, VGN, and PG and NG collectively limit the VGS of these stacked devices to levels below the required VGS limit, thus protecting them from dielectric breakdown. The VGP applied to the P1 gate and the VGN applied to the N1 gate create a voltage drop from XVDD or ground at node AA or BB, which helps prevent source-drain breakdown.

[0051] Figure 8A This diagram demonstrates the operation of inverter 500 with XVDD = 3.3V and IN = 0V. As shown in the figure, when IN = 0V, the PG node voltage is 1.83V; the VSG voltage of P0 is 1.47V, and the VSG voltage of P1 is 1.65V, both less than the 2V VSG limit. Simultaneously, the VSD voltage of P0 and P1 is 0V, also less than the 2V VSD limit. Therefore, the VSG and VSD of the PMOS stacked device meet the corresponding voltage limit requirements.

[0052] Furthermore, when IN=0V, the NG node voltage is 0V; the VGS voltage of N0 is 0V, and the VGS voltage of N1 is 0.49V, both less than the 2V VGS limit; while the VDS voltage of N0 is 1.31V, and the VDS voltage of N1 is 1.99V, both also less than the 2V VDS limit. Therefore, the VGS and VDS of the NMOS stacked devices also meet the corresponding voltage limit requirements.

[0053] Figure 8B An example of inverter 500 operation is shown with XVDD = 3.3V and IN = 3.3V. As shown in the figure, when IN = 3.3V, the PG node voltage is 3.3V; the VSG voltage of P0 is 0V, and the VSG voltage of P1 is 0.28V, both less than the 2V VSG limit; simultaneously, the VSD voltage of P0 is 1.37V, and the VSD voltage of P1 is 1.93V, both also less than the 2V VSD limit. Therefore, the VSG and VSD of the PMOS stacked device meet the corresponding voltage limit requirements.

[0054] Furthermore, when IN = 3.3V, the NG node voltage is 1.23V; the VGS voltage of N0 is 1.23V, and the VGS voltage of N1 is 1.8V, both less than the 2V VGS limit; while the VDS voltage of N0 and N1 is 0V, both also less than the 2V VDS limit. Therefore, the VGS and VDS of the NMOS stacked devices also meet the corresponding voltage limit requirements.

[0055] Figure 9 This illustration shows an example of the node waveforms of inverter 500 as the input IN voltage varies between 0V and 3.3V, according to some embodiments. As shown, the output OUT voltage varies between 3.3V and 0V, in the opposite direction to the voltage variation of the input IN voltage.

[0056] Figure 10A This demonstrates an example of an inverter 500 remaining in standby mode for an extended period of time under the conditions of XVDD=3.3V and IN=0V. Figure 10B This displays the waveform corresponding to this operating state. As mentioned earlier, when the input IN switches from 3.3V to 0V, node PG, due to its small node capacitance, will eventually gradually drop to ground level through leakage in the absence of a weak PMOS diode. A PG voltage of 0V will cause the VSG voltage of P0 to exceed the corresponding limit. Therefore, a weak PMOS diode IDP (weak_pdio) Pd is placed at node PG to prevent this leakage and maintain the PG node at an intermediate level to meet the VSG limit requirement. In this example, the PG node is maintained at 1.74V, making the VSG of P0 = 1.56V, thus meeting the VSG limit requirement.

[0057] The weak PMOS diode Pd has a sufficiently weak drive capability to avoid interfering with the normal drive operation of the IN signal on the PG node. However, the weak PMOS diode Pd requires sufficient current to prevent the PG node from slowly leaking to ground. The circuit implementation of the weak PMOS diode (weak_pdio) Pd is as follows: Figure 6 As shown.

[0058] Figure 11A This demonstrates another example of an inverter remaining in standby mode for an extended period of time under the conditions of XVDD=3.3V and IN=3.3V. Figure 11B The waveform corresponding to this operating state is shown. As mentioned above, when the input IN switches from 0V to 3.3V, node NG, due to its small capacitance, will eventually be driven to a voltage close to 3.3V-VTHn (approximately 3.0V) in the absence of a weak NMOS diode. If NG reaches 3V, the VGS of N0 will exceed the voltage limit.

[0059] To address this, a weak NMOS diode IDN (weak_ndio) Nd is placed at node NG to prevent NG from being driven too high and to maintain it at an intermediate level to meet the VGS limit requirement. In this example, NG is maintained at 1.37V, making the VGS of N0 = 1.37V, thus meeting the VGS limit requirement.

[0060] The weak NMOS diode Nd has a sufficiently weak drive capability to avoid interfering with the normal drive operation of the NG node by the IN signal. However, the weak NMOS diode Nd requires sufficient current to prevent the NG node from being slowly driven to 3V. The circuit implementation of the weak NMOS diode (weak_ndio) Nd is as follows: Figure 7 As shown.

[0061] Those skilled in the art will understand that the above embodiments have been described by way of example only and do not constitute any limitation in any sense, and various changes and modifications can be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A metal-oxide-semiconductor (MOS) gate cell, characterized in that, include: Source, drain, and gate terminals; as well as The first MOS transistor, the second MOS transistor, and the third MOS transistor, each of the MOS transistors having a source, a drain, and a gate, and configured to operate at a first operating voltage; in: The source of the first MOS transistor is coupled to the source terminal of the MOS gate cell, and the drain of the first MOS transistor is coupled to the source of the second MOS transistor; One of the source or drain of the third MOS transistor is coupled to the gate of the first MOS transistor, and the other of the source or drain of the third MOS transistor is coupled to the gate terminal of the MOS gate cell, while the gate of the third MOS transistor is coupled to the gate of the second MOS transistor. The drain of the second MOS transistor is coupled to the drain terminal of the MOS gate cell; and When a limiting voltage significantly lower than the second operating voltage is applied to the gate of the third MOS transistor, the MOS gate cell can operate as a MOS transistor operating at the second operating voltage, wherein the second operating voltage is significantly higher than the first operating voltage.

2. The MOS gate cell as described in claim 1, characterized in that, The first operating voltage is approximately 50%-60% of the second operating voltage, and the limiting voltage is approximately half of the second operating voltage.

3. The MOS gate cell as described in claim 2, characterized in that, The first operating voltage is approximately 1.8V, the second operating voltage is approximately 3.3V, and the limiting voltage is approximately 1.6V to 1.85V.

4. The MOS gate cell as described in claim 1, characterized in that, The MOS gate cell turns on in response to the VSG voltage between the source terminal and the gate terminal being higher than a threshold voltage, thereby forming a conductive path between the source terminal and the drain terminal, wherein the threshold voltage is approximately 60% of the second operating voltage.

5. The MOS gate cell as described in claim 4, characterized in that, When the MOS gate cell is turned on and the gate receives a voltage signal that varies between a first voltage level and a second voltage level, for each of the first MOS transistor, the second MOS transistor, and the third MOS transistor, the VSG voltage between the source and the gate of the MOS transistor does not exceed the VSG limit of the MOS transistor, and the VSD voltage between the source and the drain of the MOS transistor does not exceed the VSD limit of the MOS transistor, wherein the second voltage level is approximately higher than the first voltage level by the second operating voltage.

6. The MOS gate cell as described in claim 5, characterized in that, The VSG limit is significantly lower than the second operating voltage, and the VSD limit is significantly lower than the second operating voltage.

7. The MOS gate cell as described in claim 6, characterized in that, The VSD limit is approximately 1.1 times the first operating voltage and approximately 60% of the second operating voltage.

8. The MOS gate cell as described in claim 1, characterized in that, It also includes a weak diode, which is coupled between the gate of the first MOS transistor and the power supply terminal of the MOS gate cell. The weak diode is configured to maintain the VSG voltage between the source and gate of the first MOS transistor within the VSG limit of the first MOS transistor when the gate voltage of the MOS gate cell remains stable for a long time. The weak diode includes a plurality of diodes connected in series, and each diode is configured to operate at the first operating voltage.

9. The MOS gate cell as claimed in claim 1, characterized in that, The MOS gate cell does not contain any MOS transistors configured to operate at the second operating voltage.

10. An inverter, characterized in that, include: Input terminal, output terminal, first voltage terminal, and second voltage terminal; A P-type metal-oxide-semiconductor (PMOS) gate cell, the PMOS gate cell including a first PMOS transistor, a second PMOS transistor, and a third PMOS transistor, each of the PMOS transistors having a source, a drain, and a gate, and configured to operate at a first operating voltage; and The N-type metal-oxide-semiconductor (NMOS) gate cell includes a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, each of which has a source, a drain, and a gate, and is configured to operate at the first operating voltage. in: The source of the first PMOS transistor is coupled to the first voltage terminal, and the drain of the first PMOS transistor is coupled to the source of the second PMOS transistor. The source of the third PMOS transistor is coupled to the gate of the first PMOS transistor, the drain of the third PMOS transistor is coupled to the input terminal, and the gate of the third PMOS transistor is coupled to the gate of the second PMOS transistor. The drain of the second PMOS transistor is coupled to the output terminal; The source of the first NMOS transistor is coupled to the second voltage terminal, and the drain of the first NMOS transistor is coupled to the source of the second NMOS transistor; The source of the third NMOS transistor is coupled to the gate of the first NMOS transistor, the drain of the third NMOS transistor is coupled to the input terminal, and the gate of the third NMOS transistor is coupled to the gate of the second NMOS transistor. The drain of the second NMOS transistor is coupled to the output terminal; and When a first limiting voltage significantly lower than the second operating voltage is applied to the gate of the third PMOS transistor, and a second limiting voltage significantly lower than the second operating voltage is applied to the gate of the third NMOS transistor, and the second operating voltage is applied between the first voltage terminal and the second voltage terminal, the inverter can operate normally at the second operating voltage, wherein the second operating voltage is significantly higher than the first operating voltage.

11. The inverter as claimed in claim 10, characterized in that, The first operating voltage is approximately 50%-60% of the second operating voltage, and the limiting voltage is approximately half of the second operating voltage.

12. The inverter as claimed in claim 11, characterized in that, The first operating voltage is approximately 1.8V, the second operating voltage is approximately 3.3V, and the limiting voltage is approximately 1.6V to 1.85V.

13. A metal-oxide-semiconductor (MOS) gate cell, characterized in that, include: Source, drain, and gate terminals; as well as The first MOS transistor, the second MOS transistor, and the third MOS transistor, each of the MOS transistors having a first current conduction terminal, a second current conduction terminal, and a control terminal, and being configured to operate at a first operating voltage; in: The first current conduction terminal of the first MOS transistor is coupled to the source terminal of the MOS gate cell, and the second current conduction terminal of the first MOS transistor is coupled to the first current conduction terminal of the second MOS transistor; The first current conduction terminal of the third MOS transistor is coupled to the control terminal of the first MOS transistor, the second current conduction terminal of the third MOS transistor is coupled to the gate terminal, and the control terminal of the third MOS transistor is connected to the control terminal of the second MOS transistor. The second current-conducting terminal of the second MOS transistor is coupled to the drain terminal of the MOS gate cell; and When a limiting voltage significantly lower than the second operating voltage is applied to the control terminal of the third MOS transistor, the MOS gate cell can operate as a MOS transistor operating at the second operating voltage, wherein the second operating voltage is significantly higher than the first operating voltage.

14. The MOS gate cell as described in claim 13, characterized in that, The first operating voltage is approximately 50%-60% of the second operating voltage, and the limiting voltage is approximately half of the second operating voltage.

15. The MOS gate cell as claimed in claim 14, characterized in that, The first operating voltage is approximately 1.8V, the second operating voltage is approximately 3.3V, and the limiting voltage is approximately 1.6V to 1.85V.

16. The MOS gate cell as claimed in claim 13, characterized in that, The MOS gate cell turns on in response to the VSG voltage between the source terminal and the gate terminal being higher than a threshold voltage, thereby forming a conductive path between the source terminal and the drain terminal, wherein the threshold voltage is approximately 60% of the second operating voltage.

17. The MOS gate cell as claimed in claim 16, characterized in that, When the MOS gate cell is turned on and the gate terminal receives a voltage signal that varies between a first voltage level and a second voltage level, for each of the first MOS transistor, the second MOS transistor, and the third MOS transistor, the voltage between any two ends of the MOS transistor does not exceed the corresponding voltage limit of the MOS transistor, wherein the second voltage level is approximately higher than the first voltage level than the second operating voltage, and the voltage limit is approximately 50%-60% of the second operating voltage.

18. The MOS gate cell as claimed in claim 13, characterized in that, It also includes a weak diode, which is coupled between the control terminal of the first MOS transistor and the power supply terminal of the MOS gate cell. The weak diode is configured to maintain the voltage between the control terminal of the first MOS transistor and the first or second current conduction terminal of the first MOS transistor within a preset limit when the gate terminal voltage of the MOS gate cell remains stable for a long time. The weak diode includes a plurality of diodes connected in series, and each diode is configured to operate at the first operating voltage.

19. The MOS gate cell as claimed in claim 13, characterized in that, The MOS gate cell does not contain any MOS transistors configured to operate at the second operating voltage.

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