A dual-stage fractionally spursynthesizer for sub-terahertz frequencies

Abstract

This invention discloses a two-stage fractional-number coordinated Asia-Pacific Hertz frequency synthesizer, comprising: a first-stage fractional-number phase-locked loop (PLL) that improves the resolution of the reference signal through low-precision fractional-number division to meet the condition of no blind zone, and uses a digital time converter to eliminate quantization noise caused by fractional-number division to generate a local oscillator signal; and a second-stage fractional-harmonic mixing PLL that improves the resolution of the local oscillator signal through high-precision fractional-number division to achieve arbitrary frequency point generation, and uses multi-path retiming to cancel quantization noise technology to eliminate quantization noise caused by fractional-number division, mixes and filters the high-frequency fundamental signal and the local oscillator signal to generate an intermediate frequency (IF) signal, performs frequency and phase discrimination and weighted summation on the IF signal and the multi-path retiming processed signal respectively to generate a quantization noise-compensated current signal, controls the harmonic extension VCO after low-pass filtering to generate a high-frequency fundamental signal, and generates an Asia-Pacific Hertz band output signal based on the high-frequency fundamental signal.

Description

Technical Field

[0001] This invention belongs to the field of radio frequency and millimeter wave integrated circuit design technology, specifically relating to a two-stage fractional-coordinated Asia-Pacific Hertz frequency synthesizer. Background Technology

[0002] As wireless communication technology evolves from 5G to 6G, communication frequency bands are rapidly expanding into millimeter wave and Sub-THz (100GHz~300GHz) bands. In these bands, the larger bandwidth of available spectrum resources enables ultra-high-speed data transmission at the Tbps level and high-precision radar sensing at the sub-millimeter level. As the heart of the transceiver system, the performance of the local oscillator directly determines the communication quality of the entire system.

[0003] However, when designing Asia-Pacific Hertz frequency synthesizers, the traditional single-loop architecture faces inherently difficult-to-reconcile physical contradictions: First, there's the issue of reference phase noise degradation. As a frequency multiplier, the phase noise of the input reference clock is amplified by a factor of 20logN when it reaches the output. If a 200MHz crystal oscillator reference signal is directly multiplied to 140GHz, the huge division ratio will cause the reference noise floor to degrade by nearly 57dB, severely impacting the signal-to-noise ratio of the output signal. Second, there's the trade-off in loop bandwidth. In the Sub-THz band, limited by the decrease in the resonant cavity quality factor (Q value), the free-running phase noise of the voltage-controlled oscillator (VCO) is typically poor, urgently requiring extremely wide loop bandwidth to suppress VCO noise. However, to filter out in-band noise such as charge pump noise and quantization noise from fractional division, the loop bandwidth needs to be sufficiently narrow. In a single-stage architecture, these two requirements are mutually exclusive and cannot be satisfied simultaneously.

[0004] A cascaded phase-locked loop (PLL) architecture proposed in recent years can precisely solve this contradiction. This architecture typically consists of a low-frequency first-stage integer PLL (Phase-Locked Loop) and a high-frequency second-stage fractional PLL, achieving noise-optimized decoupling. The first-stage PLL multiplies the low-frequency crystal oscillator signal to the microwave band. Its main design principle is to optimize the loop bandwidth to balance in-band noise (primarily reference and charge pump noise) and VCO noise, generating a local oscillator with an extremely low noise floor. The second-stage PLL uses the outputs of both stages as a feedback signal through mixing and the output of the first-stage PLL as a reference signal through fractional division. After phase detection, these two stages control the second-stage VCO for locking. Since the phase gain of the mixer is 1, the effective division ratio of the second-stage PLL is equivalent to 1, which avoids the secondary amplification of in-band noise such as reference noise and SDM (Sigma-Delta Modulation) quantization noise. Therefore, it allows for a wider loop bandwidth in the second-stage design, thereby suppressing the poor-performing VCO noise in the Asia-Pacific Hertz band.

[0005] While this "integer-level first stage + fractional-level harmonic mixer second stage" architecture effectively addresses the trade-off between noise and bandwidth, the first stage typically employs integer frequency division to optimize noise. This results in a local oscillator step size after high-order harmonic amplification that is much larger than the bandwidth of the intermediate frequency filter. Consequently, an inherent frequency coverage dead zone is created in the terahertz band, wasting VCO frequency resources. Furthermore, existing second-stage harmonic mixer PLLs often employ a Type-I structure with XOR gate phase detection to suppress the nonlinear folding noise of the SDM. This structure has limited loop DC gain and lacks an integrator, making it difficult to effectively suppress the VCO's severe near-end noise.

[0006] Therefore, a new architecture is urgently needed that can completely eliminate frequency blind spots through fine-tuning at the first stage, and deeply eliminate quantization noise at the source, thereby achieving deep suppression of VCO noise in the Asia-Pacific Hertz band. Summary of the Invention

[0007] To address the aforementioned problems in the existing technology, this invention provides a two-stage fractional-coordinated Asia-Pacific Hertz frequency synthesizer. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a two-stage fractional-harmonic-coordinated Asia-Pacific Hertz frequency synthesizer, comprising a first-stage fractional-harmonic phase-locked loop and a second-stage fractional-harmonic mixing phase-locked loop connected in series; wherein, The first-stage fractional phase-locked loop uses a fractional frequency division architecture assisted by a digital time converter. It improves the resolution of the reference signal by using low-precision fractional frequency division to meet the condition of no blind zone, and uses the digital time converter to eliminate the quantization noise caused by fractional frequency division to generate the local oscillator signal. The second-stage fractional harmonic mixing phase-locked loop (PLL) employs a Type-II charge pump frame and multipath retiming to cancel quantization noise technology. It improves the resolution of the local oscillator signal through high-precision fractional frequency division to achieve arbitrary frequency generation. Multipath retiming to cancel quantization noise eliminates quantization noise caused by fractional frequency division. Dynamic matching technology suppresses fractional spurious signals caused by current mismatch during multipath retiming. The high-frequency fundamental signal and the local oscillator signal are mixed and filtered to generate an intermediate frequency (IF) signal. The IF signal and the multipath retiming signal are then subjected to frequency and phase discrimination and weighted summation to generate a quantization noise-compensated current signal. After low-pass filtering, the current signal is harmonic-spread by a VCO to generate a high-frequency fundamental signal. The third harmonic of the high-frequency fundamental signal is extracted to generate the output signal in the Asia-Pacific Hertz band.

[0008] The beneficial effects of this invention are: This invention proposes a two-stage fractional-number coordinated Asia-Pacific Hertz frequency synthesizer. The first-stage fractional-number phase-locked loop (PLL) employs a fractional-number frequency division architecture assisted by a digital time converter. The second-stage fractional-number harmonic mixing PLL utilizes a Type-II charge pump framework and multi-path retiming to cancel quantization noise. Dynamic matching technology is introduced to solve the current mismatch problem in multi-path retiming processing. By extending the resolution through the first-stage fractional-number PLL and achieving a coordinated operation of arbitrary fractional-number frequency division through the second-stage fractional-number harmonic mixing PLL, this synthesizes low phase noise and fractional spurious emissions in the Asia-Pacific Hertz band while eliminating the inherent frequency coverage blind spot problem of harmonic mixing architectures under high-frequency reference signals.

[0009] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of a two-stage fractional-coordinated Asia-Pacific Hertz frequency synthesizer provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the specific structure of the Asia-Pacific Hertz frequency synthesizer with dual-stage fractional-coordinated operation provided in an embodiment of the present invention; Figure 3 This is provided by the embodiments of the present invention. Figure 2 A schematic diagram of the circuit of a medium-resistance discharge-time amplification frequency and phase detector; Figure 4 This is provided by the embodiments of the present invention. Figure 2 A schematic diagram of the specific circuit of the digital time converter; Figure 5 This is provided by the embodiments of the present invention. Figure 2 A schematic diagram of the specific structure of the dual-core Class F-1 VCO; Figure 6 This is provided by the embodiments of the present invention. Figure 2Schematic diagram of high and low frequency phase noise performance of a dual-core Class F-1 VCO; Figure 7 This is provided by the embodiments of the present invention. Figure 2 A schematic diagram illustrating the working principle of the multi-path data processing module; Figure 8 This is provided by the embodiments of the present invention. Figure 2 A schematic diagram illustrating the working principle of a multipath re-timer; Figure 9 This is provided by the embodiments of the present invention. Figure 2 A schematic diagram of the specific structure of the middle harmonic extended Class F23 VCO; Figure 10 This is provided by the embodiments of the present invention. Figure 2 Impedance diagram of the drain differential mode and source common mode of a mid-harmonic extended Class F23 VCO; Figure 11 This is provided by the embodiments of the present invention. Figure 2 Schematic diagram of high and low frequency phase noise performance of a Class F23 VCO with mid-harmonic extension; Figure 12 This is provided by the embodiments of the present invention. Figure 2 A detailed circuit diagram of the intermediate frequency mixer; Figure 13 This is provided by the embodiments of the present invention. Figure 2 A schematic diagram of the specific circuit of an active bandpass filter; Figure 14 This is provided by the embodiments of the present invention. Figure 2 A detailed circuit diagram of a medium-bandwidth power amplifier; Figure 15 This is provided by the embodiments of the present invention. Figure 2 A schematic diagram of the gain curve of a medium-bandwidth power amplifier; Figure 16 This is provided by the embodiments of the present invention. Figure 2 The diagram shows the overall phase noise fitting of the Asia-Pacific Hertz frequency synthesizer with dual-stage fractional-coordinated operation. Detailed Implementation

[0011] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0012] Please see Figure 1 This invention provides a two-stage fractional-harmonic-coordinated Asia-Pacific Hertz frequency synthesizer, comprising a first-stage fractional-harmonic phase-locked loop and a second-stage fractional-harmonic mixing phase-locked loop connected in series; wherein, The first-stage fractional phase-locked loop uses a fractional frequency division architecture assisted by a digital time converter. It improves the resolution of the reference signal by using low-precision fractional frequency division to meet the condition of no blind zone, and uses the digital time converter to eliminate the quantization noise caused by fractional frequency division to generate the local oscillator signal. The second-stage fractional harmonic mixing phase-locked loop (PLL) employs a Type-II charge pump frame and multipath retiming to cancel quantization noise technology. It improves the resolution of the local oscillator signal through high-precision fractional frequency division to achieve arbitrary frequency generation. Multipath retiming to cancel quantization noise eliminates quantization noise caused by fractional frequency division, and dynamic matching technology suppresses fractional spurious noise caused by current mismatch during multipath retiming. The high-frequency fundamental signal and the local oscillator signal are mixed and filtered to generate an intermediate frequency (IF) signal. The IF signal and the multipath retiming signal are then subjected to frequency and phase discrimination and weighted summation to generate a quantization noise-compensated current signal. This quantization noise-compensated current signal is low-pass filtered and then harmonic-spread VCO to generate a high-frequency fundamental signal. The third harmonic of the high-frequency fundamental signal is extracted to generate the output signal in the Asia-Pacific Hertz band.

[0013] Next, we will provide a detailed explanation of the specific implementation of the first-stage fractional phase-locked loop and the second-stage fractional harmonic mixing phase-locked loop.

[0014] To address the inherent frequency coverage blind spot problem in the terahertz band of the existing "integer first stage + harmonic mixing" architecture, this invention designs the first-stage fractional phase-locked loop as a fractional frequency division architecture assisted by a DTC (Digital Time Converter). To intuitively understand the frequency blind spot problem, Table 1 lists the frequency coverage range at all integer division ratios of the first stage when the reference frequency is 200MHz. The frequency calculation formula can be expressed as: ; in, This indicates the output frequency of the second-stage PLL. Indicates the reference signal. This represents the integer division ratio of the first-stage PLL. This represents the integer division ratio of the second-stage PLL. This represents the fractional division ratio of the second-stage PLL. This indicates the harmonic multiple of the mixing frequency.

[0015] Table 1 Output Frequency Range under First-Level Integer Frequency Division

[0016] The data in Table 1 shows that if the first stage is an integer frequency division, there are frequency blind spots in the entire frequency range achievable by the VCO: 45.4~45.6GHz (200M), 45.9~46.5GHz (600M), 46.8~47.0GHz (200M), 47.3~47.4GHz (100M), 47.7~47.9GHz (200M), 48.2~48.4GHz (100M), and 48.7~49.3GHz (600M). In other words, the PLL cannot lock into these intervals, wasting up to 2GHz (2 / 5) of the VCO's frequency range, which also contradicts the original intention of using a fractional PLL.

[0017] Note that there are two types of dead zones: one is the step dead zone caused by changes in the division ratio, and the other is the upper and lower sideband dead zones at the same division ratio. To avoid both of these situations simultaneously, it is necessary to ensure that each time the first-stage fractional PLL increases by the minimum frequency, the lowest frequency of the resulting upper (or lower) sideband is lower than the highest frequency of the previous upper (or lower) sideband, which means satisfying the following relationship: ; in, Indicates the mixing harmonic frequency. This represents the minimum step value of the mixing harmonic frequency. Indicates the coverage area of ​​the lower band. Indicates the coverage area of ​​the upper band. This represents the bandwidth of the bandpass filter after mixing, which in this embodiment of the invention is 600M - 300M = 300M. This indicates the division ratio resolution of the first-stage PLL, with a larger mixing harmonic multiple. K Taking 8 as an example, the required... .

[0018] Therefore, this invention introduces a 3-bit MASH (Multi-Stage Noise-Shaping) 1-1 modulator in the first stage, increasing the division ratio resolution of the first-stage fractional PLL to 0.125 to meet the requirement of no blind zone. To maintain the ultra-low noise requirement of the first-stage fractional PLL, the quantization noise introduced by the first fractional division needs to be eliminated. The quantization noise generated by the low-bit first MASH 1-1 modulator is also easier to completely cancel, requiring only a 4-bit resolution DTC. To solve the in-band folding noise and fractional spurious noise problems caused by the nonlinearity of the DTC, this invention designs the DTC to be 8 bits to meet more refined gain and nonlinear mapping. This complete cancellation of quantization noise in the time domain allows the first-stage low-resolution fractional PLL to achieve noise performance close to that of an integer PLL.

[0019] Finally, the first-stage fractional phase-locked loop designed in this embodiment of the invention is as follows: Figure 2 As shown, the system includes a first MASH 1-1 modulator, a first fractional frequency divider, a digital predistorter, a digital time converter, a resistor discharge-time amplification frequency and phase detector, and a dual-core Class F-1 VCO. The first MASH 1-1 modulator generates a first fractional control signal based on a received 3-bit frequency control word, and generates a 4-bit quantization noise signal based on the first fractional control signal and the 3-bit frequency control word. The first fractional frequency divider generates a first fractional frequency divided signal based on a first external integer division ratio signal and the first fractional control signal. The digital predistorter generates an 8-bit control code based on the 4-bit quantization noise signal. The digital time converter performs quantization noise cancellation processing on the first fractional frequency divided signal based on the 8-bit control code, generating a first feedback signal. The resistor discharge-time amplification frequency and phase detector generates a time-difference amplified charge pump control signal based on a 200MHz reference signal and the first feedback signal. The dual-core Class F-1 VCO generates a 6GHz~7GHz local oscillator signal based on the time-difference amplified charge pump control signal.

[0020] like Figure 3 As shown, the resistor discharge-time amplification phase-frequency detector of this invention mainly consists of a conventional PFD (Phase-Frequency Detector) logic core and two symmetrical resistor discharge time amplification units. This circuit uses passive resistors (large resistor R1 and small resistor R2) instead of the traditional active transistor current source as the discharge element for capacitor C1. During operation, the leading input phase signal first triggers rapid discharge through R1 and R2. After the lagging signal arrives, both discharge slowly through R1. This dual-slope discharge mechanism linearly stretches the small input time difference into a wider output pulse, which is then output after threshold detection by the inverter. This improves the phase detection gain without increasing the CP (Charge Pump) current. This structure significantly reduces the flicker noise and thermal noise of the phase detector itself by utilizing the inherent low noise characteristics of resistors. Simultaneously, the high phase detection gain effectively suppresses the equivalent input noise of the subsequent charge pump and loop filter, significantly improving the in-band noise performance of the phase-locked loop.

[0021] like Figure 4As shown, the first-stage fractional phase-locked loop in this embodiment introduces a Direct Current Turbocharger (DTC). This DTC employs a variable slope architecture, using 8-bit binary coding (DQ<7:0>) to control the connection state of the switched capacitor array. By adjusting the charging and discharging slope of the intermediate node Vx, the digital code is converted into a picosecond-level time delay to compensate for the phase error introduced by the first MASH 1-1 modulator in the time domain. The maximum delay of the DTC is designed to be 2.2 lowest frequency VCO cycles to cope with the delay uncertainty under PVT (Process-Voltage-Temperature) variations. When the switched capacitor unit is not connected to the circuit, its upper and lower plates are connected to VDD to clear the charge and avoid DTC nonlinearity caused by memory effect.

[0022] In the digital control path, the 4-bit quantized noise signal output from the first MASH 1-1 modulator does not directly drive the DTC. Instead, it is first fed into a DPD (Digital Pre-Distortion) based on a cubic polynomial model, which performs... Nonlinear mapping operations, where coefficients The external interface can be configured to correct third-order and second-order nonlinearities and gain errors, respectively.

[0023] To address the residual error problem caused by resolution limitations in traditional calibration, this invention employs a bit-width extension strategy. The physical resolution of the DTC is designed to be 8 bits, far exceeding the 4-bit quantization noise accuracy of the input. This additional 4-bit redundant bit width provides ample interpolation margin for the DPD algorithm. This allows the calibration code calculated by DPD to find the optimal capacitor combination with finer steps (1 / 16 SDM LSB (Sigma-Delta Modulation Least Significant Bit)), thereby significantly smoothing the DTC's transmission curve. This design not only ensures that the DTC gain always accurately matches the error amplitude of the SDM under PVT variations, but also minimizes the residual INL (Integral Non-Linearity) of the DTC, ensuring the spectral purity of the first-stage fractional PLL as a low-noise reference source.

[0024] like Figure 5 As shown, the dual-core Class F-1 VCO of this embodiment includes a set of outer coils and a set of inner coils, as well as transistors MP1, MP2, MN1, MN2, and a variable capacitor C. D1 Variable capacitor C D2 Variable capacitor C G1 Variable capacitor C G2In one set of outer coils, the two ends of one outer coil are connected to the gates of transistors MP1 and MP2, respectively, and the two ends of the other outer coil are connected to the gates of transistors MN1 and MN2, respectively. In another set of inner coils, the two ends of one inner coil are connected to the drains of transistors MP1 and MP2, respectively, and the two ends of the other inner coil are connected to the drains of transistors MN1 and MN2, respectively. The sources of transistors MP1 and MP2 are both connected to the power supply VDD, and the sources of transistors MN1 and MN2 are both grounded. The variable capacitor C... D1 Connect the drains of transistor MP1 and MN1 respectively, and the variable capacitor C D2 Connect the drains of transistor MP2 and MN2 respectively; variable capacitor C G1 Connect the gates of transistor MP1 and MN1 respectively, and the variable capacitor C G2 Connect the gates of transistor MP2 and transistor MN2 respectively.

[0025] The dual-core Class F-1 VCO in this embodiment of the invention aims to achieve extremely low phase noise while maintaining a compact area. This dual-core Class F-1 VCO comprises two symmetrical oscillating cores (Core1 and Core2). Each core employs an inverse Class F (F-1) operating mechanism, using a transformer feedback network to shape the drain voltage waveform to reduce noise contribution from active devices. The oscillator resonant cavity includes a set of outer coils and a set of inner coils. The outer coils are connected to the gate nodes of the transistors in each core, and the inner coils are connected to the drain nodes of the transistors. Magnetic coupling exists between the inner and outer coils, forming transformer feedback (feedback coefficient k) to shape the impedance. The inductors of the two cores are connected on the physical layout via a common metal trace.

[0026] The dual-core Class F-1 VCO theoretically has two oscillation modes, but by optimizing the impedance characteristics of the common path, passive selection of the oscillation mode is achieved. In the high-Q oscillation mode (the desired mode), the two cores oscillate synchronously with a specific phase relationship (opposite direction). At this time, the AC current vectors flowing through the common metal trace cancel each other out, making the net AC current at this node close to zero. Therefore, the parasitic resistance loss of the common path is "shielded," and the resonant cavity exhibits the highest quality factor (Q value), thus achieving the lowest phase noise. In the low-Q blocking mode (suppression mode), the currents of the two cores are superimposed on the common path, resulting in huge resistance losses, which makes the loop gain of this mode insufficient to maintain oscillation, and thus it is naturally suppressed.

[0027] This design significantly reduces the layout area compared to traditional dual-core designs with two independent inductors by sharing the physical space and common path of the two core inductors. Utilizing the signal power superposition resulting from dual-core coupling and the loss shielding effect of the common path, this structure achieves phase noise performance approximately 3dB better than a single-core VCO. The four sets of variable capacitors are identically designed to ensure easy tuning and impedance matching. Simulations of the high and low frequency phase noise performance of the dual-core Class F-1 VCO are shown below. Figure 6 As shown, all achieved extremely low phase noise of <-130dBc@1MHz.

[0028] Furthermore, in response to the phase noise degradation problem of VCO in the millimeter-wave band due to the decrease in resonant cavity Q value, and the quantization noise leakage dilemma faced by broadband loops, this invention adopts a Type-II architecture of charge pump phase-locked loop in the second stage to work in conjunction with multi-path retiming to cancel quantization noise.

[0029] Due to the extremely high operating frequency (45GHz~50GHz), the near-end (1 / f³) and far-end thermal noise of the VCO are typically poor. To bring the VCO noise back to the low noise floor level of the reference source, the phase-locked loop (PLL) must provide extremely high loop gain and a wide loop bandwidth (10MHz~20MHz in this embodiment). Compared to the limited DC gain of the Type-I loop, the Type-II charge pump architecture used in this invention has infinite DC gain in the low-frequency range, enabling deep suppression of near-end flicker noise of the VCO and significantly optimizing integral jitter. Wide loop bandwidth also brings other problems. To achieve Hz-level frequency steps, the second stage uses a MASH1-1 modulator to control the fractional divider at the input. The MASH1-1 modulator pushes quantization noise to higher frequencies through noise shaping technology. Although the second-stage PLL does not amplify the noise of the MASH1-1 modulator by 20logN, its main energy is concentrated at high frequencies, still contributing considerable noise. If the loop bandwidth is blindly expanded to suppress VCO noise, the high-frequency quantization noise generated by the MASH1-1 modulator cannot be filtered out and leaks directly to the output, severely degrading far-end phase noise and spurious performance. To further overcome the "bandwidth-noise" tradeoff, this invention introduces a multi-path retiming quantization noise cancellation technique with 1 bit sign and 5 bits amplitude in the reference path. This technique uses the clean high-frequency signal output from the first stage to delay the output of the second-stage divider by ±VCO period, generating multiple signals with specific phase offsets. These signals drive parallel charge pump units to cancel the quantization noise of the fractional divider in the charge domain, reducing quantization noise by nearly 36dB across the entire frequency band.

[0030] However, a 5-bit binary charge pump struggles to achieve precise current ratios, leading to higher fractional spurious emissions due to the resulting INL. Therefore, this embodiment of the invention splits it into a combination of 2-bit binary code and 7-bit equally weighted thermometer code, with the dominant high-order bits employing a more precise 1:1 current replication. For the 7-bit temperature code converted from the three high-order bits, a dynamic matching technique based on random number shifting is used in the digital domain. The number of shifts in the thermometer code space is determined based on the random code transitioning from 0 to 7, ensuring that the high-order 3 bits of data can control each physical unit with equal probability, thus "averaging" the current mismatch between the seven CP units and dispersing spurious emissions into the noise floor.

[0031] To address the problem that traditional millimeter-wave / terahertz oscillators struggle to balance phase noise and tuning complexity over a wide tuning range, this invention employs a Class-F23 VCO architecture based on differential-mode / common-mode dual impedance peak extension technology, combined with implicit third harmonic extraction technology, to achieve high-spectral-purity Sub-THz signal generation.

[0032] Traditional Class F oscillators require an additional switched-capacitor array (SCA) to precisely align the third harmonic frequency, which significantly reduces the resonant cavity's Q value in the millimeter-wave band. This invention employs a three-coil transformer-coupled resonant cavity, utilizing the transformer's distributed parameter characteristics to bandwidth-extend the impedance peak of the differential-mode (DM) third harmonic in the frequency domain. This design allows the VCO to maintain a high third harmonic impedance across the entire wide tuning range (45GHz~50GHz), maintaining an ideal "pseudo-square wave" oscillation waveform without any manual or background calibration. The square-wave voltage waveform significantly reduces the effective value of the impulse sensitivity function (ISF), thereby substantially suppressing the conversion of active device thermal noise into phase noise at the physical level. Simultaneously, removing the low-Q harmonic tuning capacitors directly improves the equivalent quality factor of the fundamental resonant cavity, further reducing the noise floor. In addition, a broadband common-mode (CM) resonator based on a figure-eight transformer was introduced at the tail of the VCO to achieve common-mode impedance peak expansion at the second harmonic. The high-impedance common-mode resonance significantly improved the symmetry of the oscillation waveform and minimized the DC component of the ISF, thereby efficiently blocking the path of transistor flicker noise up-converting to the vicinity of the carrier. This ensures that the fundamental signal, which is the core of the system, has excellent near-end phase noise performance.

[0033] Thanks to the explicit enhancement of the third harmonic component (used for waveform shaping) in the Class-F23 architecture, the oscillator contains extremely high-energy third harmonic components. This invention utilizes the electromagnetic coupling mechanism of a transformer to implicitly extract the 135GHz~150GHz third harmonic signal directly from the resonant cavity at the drain of the cross-coupler and feed it into the subsequent power amplifier. Compared to the traditional "fundamental oscillator + cascaded frequency multiplier" scheme, this scheme avoids the additional noise and DC power consumption introduced by the active frequency multiplier, achieving high-efficiency, low-noise terahertz signal output.

[0034] Finally, the second-stage fractional harmonic mixing phase-locked loop designed in this embodiment of the invention is as follows: Figure 2 As shown, the system includes a second MASH1-1 modulator, a second fractional frequency divider, a multipath data processing module, a multipath retimer, a segmented frequency and phase detector and charge pump array, a harmonic extension Class-F23 VCO, a mixer, an active bandpass filter, and a broadband power amplifier. The second MASH1-1 modulator generates a second fractional control signal based on the received 25-bit frequency control word, and generates a 26-bit quantization noise signal based on the second fractional control signal and the 25-bit frequency control word. The second fractional frequency divider generates a second fractional frequency divided signal based on the second external integer division ratio signal and the second fractional control signal. The mixer mixes the 6GHz~7GHz local oscillator signal and the 45GHz~50GHz high-frequency fundamental signal to generate a mixed signal. The active bandpass filter filters the mixed signal. The system includes: a 0.3GHz to 0.6GHz intermediate frequency signal; a multipath data processing module for generating control codes for the multipath re-timer based on the 26-bit quantization noise signal; a multipath re-timer for quantizing and noise-eliminating the second fractional frequency division signal based on the control codes required by the multipath re-timer, generating a second feedback signal; a segmented frequency and phase discriminator and charge pump array for generating a quantized noise-compensated current signal based on the 0.3GHz to 0.6GHz intermediate frequency signal and the second feedback signal; a harmonic extension Class-F23 VCO for generating a 45GHz to 50GHz high-frequency fundamental signal based on the smoothed voltage signal converted by the current signal through a low-pass filter; and a broadband power amplifier for performing third harmonic amplification on the 45GHz to 50GHz high-frequency fundamental signal, extracting the amplified signal of 135GHz to 150GHz as the output signal for the Asia-Pacific Hertz band.

[0035] The multipath data processing module of this invention is specifically used for: truncating a 26-bit quantized noise signal to retain the high 6 bits of data; separating a 1-bit sign bit and a 5-bit amplitude bit from the high 6 bits of data; dividing the 5-bit amplitude bit into a high 3-bit amplitude bit and a low 2-bit amplitude bit after absolute value processing; decoding the high 3-bit amplitude bit into a 7-bit thermometer code and sending it into a shift network based on random number control; using the modulated 7-bit thermometer code to control the branch with the maximum current output in the segmented charge pump array; and directly inputting the low 2-bit amplitude bit as a binary code to control the other two branches in the segmented charge pump array.

[0036] like Figure 7 As shown, in the multi-path data processing module of this embodiment, in order to convert the high-precision quantization error signal into control code to drive the segmented charge pump, the 26-bit quantization noise signal at the input is first truncated, retaining the high 6 bits. Then, the absolute value operation unit (ABS) separates the 1-bit sign bit (SIGN) and the 5-bit amplitude bit. To solve the static mismatch problem caused by process deviations in the current sources of each branch in the multi-path parallel charge pump, this invention introduces dynamic component matching (DEM) technology. Specifically, the 5-bit amplitude bit is divided into a high 3-bit and a low 2-bit. The high 3 bits of data are decoded into thermometer code and fed into the core shift network (Shift). This shift network is controlled by a 3-bit pseudo-random number generator (RNG). Based on the randomly generated value, the input thermometer code is cyclically shifted. When RNG=0, PSEL<5:3> controls the equally weighted CP units according to a uniform temperature spatial distribution of [6, 2, 4, 0, 3, 1, 5]. When RNG=1(n), the temperature code sequence is shifted right by 1(n) bits, dynamically shuffling the activation order of each thermometer code channel (H_SEL<6:0>), thereby converting the originally fixed charge pump mismatch error into broadband white noise, significantly reducing spurious amplitude. The low 2 bits of data are directly output as binary code (P_SEL<1:0>) to control the low-weight charge pump branch, balancing resolution and circuit complexity.

[0037] The control code generated after DEM technology processing enters as follows: Figure 8The multipath retiming timer shown uses a signed bit. This timer samples the output DIVin of the second fractional divider using the high-frequency clock CLKin, generating three timing references with different phases: lead (DELAY-1), aligned (DELAY0), and lag (DELAY1) through a cascaded chain of D flip-flops. Based on the sign bit (SIGN), a lead or lag timing signal is pre-selected as a candidate signal SEL1, which is then matched with the reference signal SEL0. Subsequently, the multiplexer array dynamically switches between SEL0 and SEL1 based on the logic states of the thermometer code (H_SEL) and binary code (P_SEL) from the DEM module. Finally, the output signals of all channels (TH<6:0> and BIN<1:0>) are globally retimed under the drive of the clock CLKin after passing through the final stage of D flip-flops. This mechanism not only accurately converts the control code in the digital domain into a clock signal with phase information, but also strictly aligns the transition times of all parallel branches, eliminating glitches caused by path delay differences and ensuring the high linearity and low noise performance of the terahertz phase-locked loop.

[0038] like Figure 9 As shown, the harmonic extension Class-F23 VCO of this embodiment includes a three-coil transformer resonant cavity, an active core, and a tail common-mode resonator; the three-coil transformer resonant cavity includes a fixed capacitor C. T Fixed capacitor C D Variable capacitor C G Three concentric metal coils: one as the drain coil, one as the gate coil, and one as an auxiliary coil; the active core includes transistors M1 and M2; the tail common-mode resonator includes a tail coil and a fixed capacitor C. S The drain coil is connected to the power supply VDD at the connection point between the drain coil and the gate coil; the two ends of the drain coil are connected to the drain of transistor M1 and the drain of transistor M2, respectively; the two ends of the gate coil are connected to the gate of transistor M2, respectively; the sources of transistors M1 and M2 are both connected to the tail coil; and a fixed capacitor C is used. T The upper and lower plates are connected to the two ends of the auxiliary coil, respectively; the fixed capacitor C D The upper and lower plates are connected to the drains of transistor M1 and M2, respectively; the variable capacitor C G The upper and lower plates of the coil are connected to the gate of transistor M2, respectively; one end of the tail coil is connected to the source of transistor M1 and the source of transistor M2, and the other end is connected to the upper plate of the fixed capacitor Cs, while the lower plate of the fixed capacitor Cs is grounded. In this embodiment of the invention, the tail coil is figure-eight shaped and is coupled using two adjacent layers of stacked metal.

[0039] In this embodiment of the invention, the core oscillator of the second-stage fractional harmonic mixer phase-locked loop adopts a Class-F23 (Class-F with 2nd and 3rd Harmonic Resonances) topology based on a three-coil transformer resonant cavity. This structure aims to simultaneously achieve impedance control of both differential-mode third harmonic and common-mode second harmonic without the need for an additional harmonic tuning capacitor array, thereby optimizing phase noise and providing abundant third harmonic components.

[0040] The oscillator mainly consists of three parts: a three-coil transformer resonant cavity, an active core, and a tail common-mode resonator. The active core comprises a pair of cross-coupled NMOS transistors (M1, M2), providing the negative resistance required to maintain oscillation. The three-coil resonant cavity is key to achieving broadband third harmonic shaping. It contains three concentric metal coils: the drain coil is connected to the drain of M1 / M2, and a fixed capacitor C is connected in parallel. D The gate coil is connected to the gate of M1 / M2, and a variable capacitor C is connected in parallel. G The variable capacitor C G It includes a 4-bit switched capacitor array and a voltage-controlled capacitor to regulate the VCO frequency; the auxiliary coil acts as a third independent winding, with an auxiliary fixed capacitor C connected in parallel. T The differential-mode (DM) impedance is shaped to achieve impedance peak expansion. Complex mutual inductance coupling (k12, k13, k23) exists between the three coils, and this multi-coupling structure forms a high-order impedance network for differential-mode signals in the frequency domain.

[0041] Traditional Class-F oscillators require precise alignment of the third harmonic frequency, typically using a low-Q switched capacitor array while simultaneously adjusting the variable capacitor C. G and fixed capacitor C D This not only worsens phase noise but also increases parasitic capacitance, making high-frequency oscillation difficult. This invention utilizes the distributed parameter characteristics of a three-coil transformer and optimizes the coupling coefficient between the coils to generate a wide-bandgap, high-impedance flat region near the third harmonic frequency. This ensures that the third harmonic impedance of the VCO remains high throughout the entire tuning range, eliminating the need for separate frequency calibration for the third harmonic. The high-impedance third harmonic component superimposed on the fundamental frequency shapes the drain voltage into a pseudo-square wave, significantly reducing the effective value of the pulse sensitivity function (ISF) near the zero-crossing point, thereby suppressing the contribution of thermal noise to phase noise.

[0042] At the common source node of M1 / M2, a tail common-mode resonator is connected in series. It consists of a transformer formed by two specially designed figure-eight inductors (to reduce magnetic interference) connected in series with a fixed capacitor Cs. This tail common-mode resonator is designed to resonate at the second harmonic frequency, exhibiting high impedance. The high common-mode impedance restricts the flow of common-mode current, improves the symmetry of the differential-mode oscillation waveform, and effectively blocks the path from transistor flicker noise up-conversion to near-end phase noise by minimizing the DC component of the tail common-mode resonator's ISF.

[0043] In summary, the harmonic extension Class-F23 VCO of this invention achieves deep suppression of both thermal noise (through Class F shaping) and flicker noise (through tail filtering) through the coordinated operation of the three coils and the tail common-mode resonator, without requiring complex harmonic calibration circuitry, making it ideal as a high-performance core for terahertz frequency synthesizers. The differential-mode impedance at the drain and the common-mode impedance at the source are as follows: Figure 10 As shown, Figure 10 The diagram on the left shows the drain-side differential mode impedance. Figure 10 The diagram on the right side shows the common-mode impedance at the source. Figure 11 This demonstrates the phase noise performance of the harmonic extended Class-F23 VCO oscillation at both high and low frequencies.

[0044] like Figure 12 As shown, the mixer in this embodiment of the invention adopts a passive switched-capacitor sampling mixer structure. This circuit mainly consists of two cascaded complementary transmission gate switches and two sampling capacitors to ground. During the sampling stage: the first-stage switches (M1 / M2) are turned on under the control of the local oscillator signal (LO), sampling the voltage of the RF input signal and storing it in the intermediate sampling capacitor C. S1 Above. During the electrical holding phase, the first stage is turned off, and the second stage switch (M3 / M4) is turned on. At this time, C S1 The stored charge and output capacitance C S2 Charge sharing is performed to establish an intermediate frequency output voltage at the IF_OUT terminal. This discrete-time sampling-based mixing mechanism effectively achieves frequency down-conversion.

[0045] like Figure 13As shown, this embodiment of the invention samples a programmable active bandpass filter for low-noise amplification and spectral cleansing of the weak local oscillator signal output from the pre-amplifier. The circuit adopts a three-stage cascaded architecture: the first two stages are self-biased inverting amplifiers based on resistor feedback (R5 / R6), providing approximately 2x and 4x voltage gain, respectively. This self-biased structure automatically clamps the transistors near the threshold voltage, thereby maintaining stable amplification capability under different process, voltage, and temperature (PVT) conditions. In terms of filtering characteristics, the DC blocking capacitor C1 at the input, the inter-stage resistors (R1~R4), and the switched capacitor unit together constitute the bandpass response. The programmable capacitor array (Cap Cell) consists of transmission gates and capacitors. The size of the connected capacitors is controlled by the digital signal BW<3:0>, which flexibly adjusts the filter bandwidth and accurately filters out high-frequency aliasing spurious signals caused by sampling and mixing. Finally, the signal, after multi-stage amplification and filtering, is shaped into a rail-to-rail square wave by the third-stage buffer, providing a clean, amplitude-saturated clock signal for the subsequent phase-locked loop circuit.

[0046] like Figure 14 As shown, the third harmonic extraction power amplifier in this embodiment of the invention adopts a two-stage cascaded differential common-source topology, aiming to provide high-gain amplification and high-power output for terahertz signals in the 135GHz~150GHz range. The first stage of the circuit is a drive amplification stage, composed of transistors M1 and M2, and the second stage is a power output stage, composed of larger transistors M3 and M4. To overcome the Miller effect and potential stability problems caused by the gate-drain parasitic capacitance of transistors in the terahertz band, both stages of the circuit introduce cross-coupling neutralizing capacitor technology. By introducing anti-phase feedback current to cancel parasitic effects, the gain and reverse isolation of the amplifier are significantly improved.

[0047] The core innovation of this circuit design lies in the use of broadband transformer matching technology in the interstage and output matching networks to address potential frequency deviations in the preceding VCO during actual manufacturing. In terahertz integrated circuit manufacturing, the actual oscillation center frequency of the VCO often deviates from the simulated design value due to process variations such as lithography precision and metal thickness. If the PA uses narrowband matching, once the VCO frequency drifts, the signal will fall into the PA gain drop region, leading to a sharp deterioration in output power. Therefore, this invention constructs a broadband matching network with flat passband characteristics by finely optimizing the coil dimensions, coupling coefficients (k1, k2), and tuning capacitors of the interstage and output transformers. This network not only achieves conjugate impedance matching between stages and the conversion of the output to a 50Ω standard load, but more importantly, it provides a frequency tolerance window for the system. This broadband design ensures that even if the VCO output frequency shifts within the 135GHz~150GHz range due to process fluctuations, the PA can still maintain high gain and high saturation power output, greatly improving chip yield and system robustness. The simulated gain curve of this PA is shown below. Figure 15 As shown, it has a high bandwidth of 37GHz, ranging from 118GHz to 155GHz.

[0048] The novel Sub-THz phase-locked loop structure proposed in this invention is as follows: Figure 1As shown, the entire system consists of a first-stage fractional phase-locked loop (PLL1) and a second-stage fractional harmonic mixer (PLL2) connected in series. The first-stage PLL1 aims to generate a flexible and clean 6GHz~7GHz local oscillator signal. This stage is configured as a low-resolution fractional divider architecture assisted by a DTC, with a loop bandwidth set at 500kHz~1MHz. Its core components include a resistor discharge time-amplified phase-discriminator to increase phase detection gain, thereby reducing PFD+CP noise, and an ultra-low noise dual-core Class F-1 VCO. A 3-bit MASH 1-1 modulator is introduced into the feedback path to modulate the first fractional divider. Its output 4-bit quantization noise is matched to the gain and nonlinearity of the DTC by the DPD module. The DTC is designed to be 8-bit, leaving sufficient margin for the DPD to minimize residual INL, thereby accurately canceling the quantization noise introduced by the fractional divider in the time domain and ensuring the spectral purity of the first-stage output signal. The second-stage PLL2 is locked to the first-stage output and configured as a multi-path harmonic mixer architecture with a loop bandwidth of 10MHz~20MHz to strongly suppress VCO noise. The core uses a harmonic-rich Class-F23 VCO, whose 45GHz~50GHz high-frequency fundamental signal is mixed with the local oscillator signal from the first-stage output in the mixer via a feedback path, generating an intermediate frequency signal of 0.3GHz~0.6GHz; its 135GHz~150GHz third harmonic is output via a power amplifier. To achieve high resolution without degrading the noise floor, the reference path uses a multi-path retiming timer to drive a segmented frequency and phase detector and a charge pump array, performing analog domain cancellation of the second-stage quantization error. To suppress fractional spurious signals caused by current mismatch during multi-path retiming processing, a dynamic matching technique based on random number shifting is used in the digital domain. The two-stage phase-locked loops work together to achieve blind-zone-free coverage and extremely low noise performance in the Asia-Pacific Hertz band. Figure 16 The invention demonstrates the contributions of each noise source and the final output phase noise when the novel Sub-THz phase-locked loop structure proposed in this invention is locked around 50G. Thanks to the low-noise design of each part, the integral jitter of 1K~100M is only 32.4fs.

[0049] It should be noted that the detailed circuit structure is not given in the embodiments of the present invention. For example, the MASH 1-1 modulator (including the first MASH 1-1 modulator and the second MASH 1-1 modulator), the fractional frequency divider (including the first fractional frequency divider and the second fractional frequency divider), and the digital predistorter can be implemented using existing circuits to achieve the corresponding functions.

[0050] In summary, the dual-stage fractional-number coordinated Asia-Pacific Hertz frequency synthesizer proposed in this invention employs a fractional-number frequency division architecture assisted by a digital time converter in the first-stage fractional-number phase-locked loop (PLL). The second-stage fractional-number harmonic mixing PLL utilizes a Type-II charge pump framework and multi-path retiming to cancel quantization noise, introducing dynamic matching technology to address current mismatch issues in multi-path retiming processing. By extending the resolution with the first-stage PLL and achieving a coordinated operation of arbitrary fractional-number frequency division with the second-stage PLL, this synthesizes low phase noise and fractional spurious emissions in the Asia-Pacific Hertz band while eliminating the inherent frequency coverage blind spot problem of harmonic mixing architectures under high-frequency reference signals.

[0051] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0052] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0053] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A two-stage fractional-coordinated Asia-Pacific Hertz frequency synthesizer, characterized in that, The frequency synthesizer comprises a first-stage fractional phase-locked loop and a second-stage fractional harmonic mixer phase-locked loop connected in series; wherein... The first-stage fractional phase-locked loop uses a fractional frequency division architecture assisted by a digital time converter. It improves the resolution of the reference signal by using low-precision fractional frequency division to meet the condition of no blind zone, and uses the digital time converter to eliminate the quantization noise caused by fractional frequency division to generate the local oscillator signal. The second-stage fractional harmonic mixing phase-locked loop (PLL) employs a Type-II charge pump frame and multipath retiming to cancel quantization noise technology. It improves the resolution of the local oscillator signal through high-precision fractional frequency division to achieve arbitrary frequency generation, and uses multipath retiming to cancel quantization noise caused by fractional frequency division. Dynamic matching technology suppresses fractional spurious noise caused by current mismatch during multipath retiming. The high-frequency fundamental signal and the local oscillator signal are mixed and filtered to generate an intermediate frequency (IF) signal. The IF signal and the multipath retiming signal are then subjected to frequency and phase discrimination and weighted summation to generate a quantization noise-compensated current signal. This current signal is low-pass filtered and then used to control the harmonic extension VCO to generate a high-frequency fundamental signal. The third harmonic of the high-frequency fundamental signal is extracted to generate the output signal in the Asia-Pacific Hertz band.

2. The Asia-Pacific Hertz frequency synthesizer with dual-stage fractional-coordinated operation according to claim 1, characterized in that, The first-stage fractional phase-locked loop includes a first MASH 1-1 modulator, a first fractional frequency divider, a digital predistorter, a digital time converter, a resistor discharge-time amplification frequency and phase detector, and a dual-core Class F-1 VCO; among which... The first MASH 1-1 modulator is used to generate a first fractional control signal based on the received 3-bit frequency control word, and to generate a 4-bit quantization noise signal based on the first fractional control signal and the 3-bit frequency control word. The first fractional frequency divider is used to generate a first fractional frequency divided signal based on a first external integer frequency division ratio signal and a first fractional control signal; A digital predistorter is used to generate an 8-bit control code based on a 4-bit quantized noise signal; A digital time converter is used to perform quantization noise cancellation processing on the first fractional frequency division signal according to an 8-bit control code, and generate a first feedback signal. A resistive discharge-time amplified frequency and phase detector is used to generate a time-difference amplified charge pump control signal based on a 200MHz reference signal and a first feedback signal. The dual-core Class F-1 VCO is used to generate a 6GHz~7GHz local oscillator signal based on the charge pump control signal amplified according to the time difference.

3. The Asia-Pacific Hertz frequency synthesizer with dual-stage fractional-coordinated operation according to claim 2, characterized in that, The dual-core Class F-1 VCO includes an outer coil and an inner coil, as well as transistors MP1, MP2, MN1, MN2, and a variable capacitor C. D1 Variable capacitor C D2 Variable capacitor C G1 Variable capacitor C G2 ;in, In a set of outer coils, the two ends of one outer coil are connected to the gates of transistor MP1 and transistor MP2, respectively, and the two ends of the other outer coil are connected to the gates of transistor MN1 and transistor MN2, respectively. A set of inner coils, one inner coil with its two ends connected to the drain of transistor MP1 and the drain of transistor MP2 respectively, and the other inner coil with its two ends connected to the drain of transistor MN1 and the drain of transistor MN2 respectively. The source of transistor MP1 and the source of transistor MP2 are both connected to power supply VDD, and the source of transistor MN1 and the source of transistor MN2 are both grounded. Variable capacitor C D1 The upper and lower plates are connected to the drains of transistor MP1 and MN1, respectively, and the variable capacitor C... D2 The upper and lower plates are connected to the drain of transistor MP2 and the drain of transistor MN2, respectively. Variable capacitor C G1 The upper and lower plates are connected to the gates of transistor MP1 and MN1, respectively, and the variable capacitor C... G2 The upper and lower plates are connected to the gates of transistor MP2 and transistor MN2, respectively.

4. The Asia-Pacific Hertz frequency synthesizer with dual-stage fractional-coordinated operation according to claim 1, characterized in that, The second-stage fractional harmonic mixer phase-locked loop includes a second MASH 1-1 modulator, a second fractional frequency divider, a multipath data processing module, a multipath retimer, a segmented frequency and phase detector and charge pump array, a harmonic extension Class-F23 VCO, a mixer, an active bandpass filter, and a broadband power amplifier; among which... The second MASH 1-1 modulator is used to generate a second fractional control signal based on the received 25-bit frequency control word, and to generate a 26-bit quantization noise signal based on the second fractional control signal and the 25-bit frequency control word. The second fractional frequency divider is used to generate a second fractional frequency divided signal based on the second external integer frequency division ratio signal and the second fractional control signal; A mixer is used to mix a 6GHz~7GHz local oscillator signal with a 45GHz~50GHz high-frequency fundamental signal to generate a mixed signal. An active bandpass filter is used to filter mixed signals to generate intermediate frequency signals in the range of 0.3 GHz to 0.6 GHz. The multipath data processing module is used to generate the control code required for the multipath retimer based on the 26-bit quantized noise signal. The multipath re-timer is used to perform quantization noise cancellation processing on the second fractional frequency division signal according to the control code required by the multipath re-timer, and generate a second feedback signal. A segmented frequency and phase detector and charge pump array are used to generate a quantized noise-compensated current signal based on an intermediate frequency signal of 0.3 GHz to 0.6 GHz and a second feedback signal. The harmonic extension Class-F23 VCO is used to generate a high-frequency fundamental signal of 45GHz~50GHz based on the smoothed voltage signal after the current signal is converted by a low-pass filter. A broadband power amplifier is used to perform third harmonic amplification on high-frequency fundamental signals from 45GHz to 50GHz, and extract the amplified signal from 135GHz to 150GHz as the output signal for the Asia-Pacific Hertz band.

5. The Asia-Pacific Hertz frequency synthesizer with dual-stage fractional-coordinated operation according to claim 4, characterized in that, The multipath data processing module is specifically used to: truncate the 26-bit quantized noise signal to retain the high 6 bits of data; separate the 1-bit sign bit and 5-bit amplitude bit from the high 6 bits of data; divide the 5-bit amplitude bit into high 3-bit amplitude bits and low 2-bit amplitude bits after absolute value processing; decode the high 3-bit amplitude bits into 7-bit thermometer code and send it to a shift network based on random number control; the modulated 7-bit thermometer code controls the branch with the maximum current output in the segmented charge pump array; and directly input the low 2-bit amplitude bits as binary codes to control the other two branches in the segmented charge pump array.

6. The Asia-Pacific Hertz frequency synthesizer with dual-stage fractional-coordinated operation according to claim 4, characterized in that, The harmonic extended Class-F23 VCO includes a three-coil transformer resonant cavity, an active core, and a tail common-mode resonator; the three-coil transformer resonant cavity includes a fixed capacitor C. T Fixed capacitor C D Variable capacitor C G Three concentric metal coils: one as the drain coil, one as the gate coil, and one as an auxiliary coil; the active core includes transistors M1 and M2; the tail common-mode resonator includes a tail coil and a fixed capacitor C. S ;in, The drain coil and gate coil are connected to the power supply VDD. The two ends of the drain coil are connected to the drain of transistor M1 and the drain of transistor M2, respectively; The two ends of the gate coil are connected to the gate of transistor M2 and the gate of transistor M2, respectively; The source of transistor M1 and the source of transistor M2 are both connected to the tail coil; Fixed capacitor C T The upper and lower plates are respectively connected to the two ends of the auxiliary coil; Fixed capacitor C D The upper and lower plates are connected to the drain of transistor M1 and the drain of transistor M2, respectively. Variable capacitor C G The upper and lower plates are connected to the gate of transistor M2 and the gate of transistor M2, respectively. One end of the tail coil is connected to the source of transistor M1 and the source of transistor M2, and the other end is connected to the upper plate of fixed capacitor Cs. The lower plate of fixed capacitor Cs is grounded.

7. The Asia-Pacific Hertz frequency synthesizer with dual-stage fractional-coordinated operation according to claim 6, characterized in that, The tail coil is figure-eight shaped and is coupled using two adjacent layers of stacked metal.

8. The Asia-Pacific Hertz frequency synthesizer with dual-stage fractional-coordinated operation according to claim 1, characterized in that, The loop bandwidth of the first-stage fractional phase-locked loop is 500kHz~1MHz; the loop bandwidth of the second-stage fractional harmonic mixing phase-locked loop is 10MHz~20MHz.

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