A digital time converter assisted harmonic mixing fractional phase-locked loop

Abstract

This invention discloses a harmonic mixing fractional phase-locked loop (PLL) assisted by a digital-to-time converter (DTC), comprising a reference path signal generation module, a mixing path signal generation module, and a harmonic mixing PLL loop module. The reference path signal generation module mainly consists of a multi-mode divider, a Delta-Sigma modulator (DSM), and a digital-to-time converter (DTC) to achieve initial cancellation of quantization noise. The mixing path signal generation module mainly consists of a prescaler to provide a suitable local oscillator signal. The harmonic mixing PLL loop module adopts a harmonic mixing feedback architecture, making the equivalent division ratio of the main loop 1. This invention eliminates the need for complex DTC nonlinear calibration, reducing power consumption and design complexity, while effectively suppressing quantization noise folding and achieving ultra-low phase noise output.

Description

Technical Field

[0001] This invention belongs to the field of phase-locked loop technology, specifically relating to a harmonic mixing fractional phase-locked loop based on a digital time converter. Background Technology

[0002] With the development of 5G millimeter-wave communication, vehicle-mounted LiDAR, and high-precision instruments, the system places extremely high demands on the phase noise and frequency resolution of the frequency synthesizer. The fractional-division phase-locked loop (PLL) has become the mainstream architecture choice due to its ability to achieve precise frequency steps and fast locking speed.

[0003] In fractional phase-locked loops (PLLs), a Delta-Sigma modulator (DSM) is typically used to dynamically control the division ratio of the multimode divider to switch rapidly between two or more integers, achieving an equivalent fractional division ratio using time-domain averaging techniques. However, this dynamic switching mechanism inevitably introduces instantaneous phase error, i.e., quantization noise.

[0004] Existing technologies face a severe bandwidth trade-off when suppressing quantization noise: On the one hand, to filter out the high-frequency quantization noise generated by the DSM, traditional PLLs are forced to use a narrower loop bandwidth. However, narrow bandwidth weakens the loop's ability to suppress near-end phase noise of the VCO and significantly increases the PLL's lock-in time, failing to meet the requirements of high-speed frequency-hopping systems. On the other hand, if the loop bandwidth is increased to suppress VCO noise and improve lock-in speed, a large amount of quantization noise introduced by the DSM will be directly transmitted to the output through the loop, severely degrading both in-band and out-of-band phase noise performance. Therefore, how to effectively suppress or even eliminate quantization noise introduced by fractional frequency division without sacrificing loop bandwidth and lock-in speed, breaking the trade-off between bandwidth and noise, is a key technical challenge that urgently needs to be solved in the design of high-performance fractional PLLs.

[0005] To address the trade-off between quantization noise introduced by fractional frequency division and loop bandwidth, existing technology 1 proposes a quantization noise cancellation technique based on a digital-to-time converter (DTC). This phase-locked loop (PLL) circuit mainly consists of the following core modules: a phase detector, a low-pass filter, a voltage-controlled oscillator (VCO), a multi-mode divider, and the DTC. This PLL architecture introduces a DTC module into the traditional reference clock path. The reference signal, delayed by the DTC, and the signal fed back from the divider enter the phase detector. Ideally, the delay introduced by the DTC precisely cancels out the phase lead or lag introduced by the divider, ensuring that the two signal edges seen by the phase detector are aligned. In this way, quantization noise is physically canceled at the phase detector input, allowing the PLL to use a wider loop bandwidth to suppress VCO noise and improve locking speed without worrying about quantization noise worsening PLL jitter. Although existing technology 1 can theoretically cancel quantization noise by introducing DTC, it suffers from two main problems in high-performance applications requiring ultra-low jitter: 1. Nonlinear noise folding and N 2 Amplification effect: The nonlinearity of the DTC "folds" the quantization noise, which would otherwise be shaped to high frequencies by the DSM, back into the low-frequency band. More seriously, because the DTC is located on the input reference path of the phase detector, this folded-back low-frequency noise is amplified by the loop gain of the phase-locked loop (PLL) by N. 2 The frequency division ratio (N) is projected onto the output. This means that even if the nonlinearity of the DTC is very small, the phase noise and spurious signals at the output will be significantly worsened after being amplified by the huge frequency division ratio. To solve this problem, the system is forced to introduce an extremely complex background nonlinearity calibration algorithm, which not only increases the complexity of the circuit design, but also significantly increases the area and power consumption of the digital logic.

[0006] 2. DTC Noise Floor Constraints and Design Trade-offs: For PLLs aiming for ultra-low jitter, the inherent noise floor of the DTC device itself becomes a performance bottleneck, as the DTC's inherent noise is also amplified by the loop. 2 To reduce the noise of the DTC to a level that does not affect the overall system performance, designers often face a severe trade-off: they must significantly increase the DTC's current to reduce noise, or limit the DTC's delay range. As a result, the system has to pay a huge price in power consumption to suppress the noise introduced by the DTC.

[0007] To address the issue of quantization noise being absorbed by N in traditional fractional frequency division phase-locked loops 2To address the amplification issue, existing technology two proposes a Harmonic Mixing PLL (HM-PLL) architecture. The advantage of this architecture is that it replaces the multi-mode divider in the feedback path of a traditional PLL with a Harmonic Mixer (HM). Unlike multi-mode dividers with a noise transfer function of N, the HM has a noise transfer function of 1, meaning the effective division ratio N of the main loop equals 1. Therefore, the quantization on the reference path will not be amplified by N by the loop. 2 This multiple allows the architecture to theoretically achieve extremely low fractional jitter. Although the harmonic mixer phase-locked loop avoids N... 2 While it exhibits noise amplification, in practical fractional frequency division applications, it faces a severe challenge from the nonlinearity of the phase detector. The phase detector in a real circuit is not an ideal linear device; its phase detection gain exhibits nonlinear characteristics. This nonlinearity "folds" quantization noise, originally located at high frequencies, back into the low-frequency band. Although the loop itself does not amplify noise, this folded-in noise directly degrades the in-band phase noise performance of the PLL, limiting its application in ultra-high-performance scenarios. Summary of the Invention

[0008] The purpose of this invention is to provide a harmonic mixing fractional phase-locked loop based on a digital time converter (DTC) to solve the quantization noise folding problem caused by DTC nonlinearity, the trade-off between DTC background noise and power consumption, and the quantization noise folding problem caused by the phase detection gain nonlinearity in the HM-PLL architecture.

[0009] The technical solution adopted in this invention is as follows: A harmonic mixing fractional phase-locked loop based on digital time converter assistance includes a reference path signal generation module, a mixing path signal generation module, and a harmonic mixing phase-locked loop circuit module. The reference path signal generation module includes a multi-mode frequency divider, a Delta-Sigma modulator (DSM), and a digital-to-time converter (DTC). The Delta-Sigma modulator controls the division ratio of the multi-mode frequency divider to dynamically switch between integers, achieving fractional division. The digital-to-time converter performs high-precision delay adjustment on the jitter signal edges output by the multi-mode frequency divider based on the instantaneous phase error in the output signal, reducing the quantization error range of the output to the harmonic mixing phase-locked loop module. The mixing path signal generation module is composed of a pre-divider, which is used to divide the input signal to a suitable frequency, and serve as the local oscillator signal of the harmonic mixer in the harmonic mixing phase-locked loop module. The harmonic mixing phase-locked loop module includes a phase-locked loop circuit based on a harmonic mixing feedback architecture. It is used to receive a reference signal with a low quantization error range output by the reference path signal generation module, and use the signal output by the mixing path signal generation module as the local oscillator. The output oscillation signal is down-converted to an intermediate frequency and phase-locked through harmonic mixing, so that the equivalent frequency division ratio of the main loop is 1.

[0010] Furthermore, the reference path signal generation module also includes an integer phase-locked loop, which is used in conjunction with a multi-mode frequency divider, a Delta-Sigma modulator, and a digital-to-time converter to generate a reference signal and initially cancel quantization noise.

[0011] Furthermore, the prescaler in the mixing path signal generation module has a division ratio of 1.

[0012] Furthermore, the prescaler in the mixing path signal generation module is configured as a frequency divider of two.

[0013] Furthermore, the harmonic mixing phase-locked loop circuit based on the harmonic mixing feedback architecture in the harmonic mixing phase-locked loop module includes a harmonic mixer, a frequency and phase detector / charge pump, a low-pass filter, and a voltage-controlled oscillator.

[0014] Furthermore, the DTC employs a constant slope architecture based on a capacitive digital-to-analog converter (C-DAC).

[0015] Furthermore, the constant slope architecture based on the capacitive digital-to-analog converter (C-DAC) consumes 200µW of power.

[0016] Furthermore, the digital-to-time converter suppresses quantization noise folding caused by the nonlinearity of the phase detection gain in the harmonic mixer phase-locked loop module.

[0017] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are: 1. This invention discloses a harmonic mixing fractional phase-locked loop (PLL) assisted by a digital time converter (DTC), which significantly reduces the phase error range of the signal entering the phase detector through the active cancellation effect of the DTC. This effectively avoids the high-frequency quantization noise folding problem caused by the large-signal nonlinearity of the phase detector, and significantly improves the in-band phase noise; 2. This invention benefits from the characteristics of the harmonic mixing architecture, with an equivalent division ratio of 1 for the main loop. This characteristic greatly relaxes the requirements for the noise floor of DTC devices. During the design process, there is no need to consume huge power consumption or sacrifice the delay range in order to reduce DTC noise, thus breaking the traditional design trade-off of "power consumption-noise-delay". 3. In this invention, since the loop gain is 1, the folding noise generated by the DTC due to its own nonlinearity will not be amplified by the loop. This means that the linearity requirement of the DTC is greatly reduced. Therefore, this invention does not require a complex background nonlinear calibration algorithm, which greatly saves the area and power consumption of the digital circuit and reduces the complexity of chip design. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort, wherein: Figure 1 It is the existing phase-locked loop architecture; Figure 2 It is the harmonic mixing phase-locked loop architecture of existing technology 2; Figure 3 This application presents a harmonic mixing fractional frequency division phase-locked loop architecture based on DTC assistance; Figure 4 This is a circuit diagram of a harmonic mixing fractional frequency division phase-locked loop based on DTC-assisted embodiment 1 of this application; Figure 5 This is a comparison diagram of quantization noise in three different structures of this application; Figure 6 This is the DTC structure in Embodiment 2 of this application; Figure 7 This is the phase noise diagram in Embodiment 2 of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only for explaining the invention and are not intended to limit the invention; that is, the described embodiments are merely some embodiments of the invention, and not all embodiments. The components of the embodiments of the invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0021] It should be noted that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0022] The features and performance of the present invention will be further described in detail below with reference to embodiments.

[0023] A harmonic mixing fractional phase-locked loop based on digital time converter assistance includes a reference path signal generation module, a mixing path signal generation module, and a harmonic mixing phase-locked loop circuit module. The reference path signal generation module includes a multi-mode frequency divider, a Delta-Sigma modulator (DSM), and a digital-to-time converter (DTC). The Delta-Sigma modulator controls the division ratio of the multi-mode frequency divider to dynamically switch between integers, achieving fractional division. The digital-to-time converter performs high-precision delay adjustment on the jitter signal edges output by the multi-mode frequency divider based on the instantaneous phase error in the output signal, reducing the quantization error range of the output to the harmonic mixing phase-locked loop module. The mixing path signal generation module is composed of a pre-divider, which is used to divide the input signal to a suitable frequency, and serve as the local oscillator signal of the harmonic mixer in the harmonic mixing phase-locked loop module. The harmonic mixing phase-locked loop module includes a phase-locked loop circuit based on a harmonic mixing feedback architecture. It is used to receive a reference signal with a low quantization error range output by the reference path signal generation module, and use the signal output by the mixing path signal generation module as the local oscillator. The output oscillation signal is down-converted to an intermediate frequency and phase-locked through harmonic mixing, so that the equivalent frequency division ratio of the main loop is 1.

[0024] In some embodiments, the reference path signal generation module further includes an integer phase-locked loop (PLL), which is used in conjunction with a multi-mode frequency divider, a Delta-Sigma modulator, and a digital-to-time converter to generate a reference signal and initially cancel quantization noise.

[0025] In some embodiments, the prescaler division ratio in the mixing path signal generation module is set to 1.

[0026] In some embodiments, the prescaler in the mixing path signal generation module is configured as a divider by two.

[0027] In some embodiments, the harmonic mixing phase-locked loop circuit based on the harmonic mixing feedback architecture in the harmonic mixing phase-locked loop module includes a harmonic mixer, a frequency and phase detector / charge pump, a low-pass filter, and a voltage-controlled oscillator; the digital-to-time converter suppresses quantization noise folding caused by the nonlinearity of the phase detection gain in the harmonic mixing phase-locked loop module.

[0028] In some embodiments, the DTC employs a constant slope architecture based on a capacitive digital-to-analog converter (C-DAC).

[0029] In some embodiments, the constant slope architecture based on a capacitive digital-to-analog converter (C-DAC) consumes 200µW of power.

[0030] The prior art related to this application is described as follows: (1) Technical solution of prior art 1 To address the trade-off between quantization noise introduced by fractional-frequency division and loop bandwidth, existing technology proposes a quantization noise cancellation technique based on a digital-to-time converter (DTC). For example... Figure 1 As shown, the phase-locked loop circuit mainly consists of the following core modules: a phase detector, a low-pass filter, a voltage-controlled oscillator, a multi-mode divider, and a DTC. The technical problems existing in the prior art have been described in detail in the background section.

[0031] Technical solution of existing technology 2 To address the issue of quantization noise being absorbed by N in traditional fractional frequency division phase-locked loops 2 To address the amplification issue, existing technology two proposes a Harmonic Mixing PLL (HM-PLL) architecture, such as... Figure 2 As shown; the advantage of this architecture is that it replaces the multi-mode divider in the feedback path of a traditional PLL with a harmonic mixer (HM). Unlike the multi-mode divider with a noise transfer function of N, the HM has a noise transfer function of 1, which means that the effective division ratio N of the main loop is equal to 1. Therefore, the quantization on the reference path will not be amplified by the loop by N. 2 This allows the architecture to theoretically achieve extremely low fractional jitter. The technical problems existing in prior art 2 have been described in detail in the background section.

[0032] This invention proposes a DTC-assisted harmonic mixing fractional frequency division phase-locked loop, such as... Figure 3As shown, the frequency synthesizer system mainly consists of three parts: a reference path signal generation module (within the dashed box), a mixing path signal generation module, and a harmonic mixing phase-locked loop module (on the right side of the figure).

[0033] The reference path signal generation module (based on quantization noise cancellation using a digital time converter) mainly consists of a multi-mode divider, a DSM, and a DTC. The DSM controls the division ratio of the multi-mode divider to dynamically switch between integers, thereby performing fractional division on the "input" signal. Although this process achieves fractional frequency synthesis, it introduces a large instantaneous phase error (i.e., quantization noise) into the output signal of the multi-mode divider. After adding the DTC, it performs high-precision delay adjustment on the jitter signal edge of the multi-mode divider output based on this error signal, which greatly reduces the quantization error range of the subsequent harmonic mixing phase-locked loop, and thus reduces the noise folding problem caused by the nonlinearity of the phase detection gain in the subsequent harmonic mixing phase-locked loop.

[0034] The mixing path signal generation module mainly consists of a prescaler (the division ratio can be 1), which is responsible for dividing the input signal to a suitable frequency and feeding it to the harmonic mixer in the harmonic mixing phase-locked loop as the local oscillator signal.

[0035] Additionally, the harmonic mixing fractional-number phase-locked loop (PLL) module mainly consists of a PLL circuit based on a harmonic mixing feedback architecture. It is configured to receive a reference signal with a low quantization error range from the reference path output and use the pre-amplifier input signal (or its frequency division signal) as the local oscillator. Through harmonic mixing, the output oscillation signal is down-converted to an intermediate frequency and phase-locked. This process benefits from the harmonic mixing architecture, which sets the equivalent frequency division ratio of the main loop to 1, ensuring that the inherent noise and nonlinear residual error of the pre-amplifier DTC are not amplified when transmitted to the output (eliminating N). 2 (Noise gain); This characteristic brings dual advantages: on the one hand, it enables the system to achieve ultra-low phase noise RF output without the need for complex nonlinear calibration of the DTC; on the other hand, it significantly reduces the design difficulty of balancing the inherent noise, delay range and power consumption of the DTC itself, allowing designers to meet the high-performance system requirements simply by using low-power DTC circuits.

[0036] Example 1

[0037] like Figure 4As shown, this embodiment proposes a DTC-assisted harmonic mixing fractional-order frequency-division phase-locked loop (PLL). Its circuit structure mainly consists of three parts: a reference path signal generation module, a mixing path signal generation module, and a harmonic mixing PLL loop module. The reference path signal generation module comprises an integer PLL, a multi-mode divider, a DSM, and a DTC. The prescaler in the mixing path signal generation module is configured as a two-way divider. The harmonic mixing PLL loop module comprises a harmonic mixer, a frequency and phase detector / charge pump, a low-pass filter, and a voltage-controlled oscillator.

[0038] like Figure 5 The diagram illustrates a comparison of quantization noise suppression performance under the introduced circuit nonlinearity (DTC nonlinearity and phase detector gain nonlinearity). The top curve (light gray) corresponds to a traditional harmonic mixer phase-locked loop (without DTC), showing that large quantization errors cause the frequency detector / charge pump to operate in the nonlinear region, leading to severe noise folding and the highest in-band noise. The middle curve (medium gray) corresponds to a traditional DTC-assisted charge pump phase-locked loop; although DTC is introduced, the large loop division ratio amplifies the DTC's own nonlinearity error and background noise by a factor of 20logN, limiting noise performance. The bottom curve (dark gray) corresponds to the technical solution of this embodiment. Simulation results show that this structure has the lowest quantization noise because the introduction of DTC compresses the error range and reduces the nonlinear folding of the frequency detector / charge pump; simultaneously, the harmonic mixer architecture achieves an equivalent division ratio of 1, avoiding the amplification of DTC's own noise and nonlinearity error, proving that this embodiment achieves optimal ultra-low noise performance without complex nonlinear calibration.

[0039] Example 2

[0040] like Figure 6 , Figure 7 As shown, this embodiment, based on embodiment 1, details the circuit structure and performance of the digital-to-time converter (DTC) in embodiment 1. This embodiment uses a constant slope architecture based on a capacitive digital-to-analog converter (C-DAC), taking advantage of its simple structure and ultra-low power consumption of only 200µW. Thanks to the fact that the architecture of this invention is insensitive to DTC noise, the small noise introduced by this low-power DTC is almost negligible in ultra-low jitter PLL systems below 50fs, thus perfectly solving the trade-off problem of high power consumption for low noise in traditional designs.

[0041] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, and improvements made by those skilled in the art within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A harmonic mixing fractional phase-locked loop based on a digital time converter, characterized in that: This includes a reference path signal generation module, a mixing path signal generation module, and a harmonic mixing phase-locked loop module. The reference path signal generation module includes a multi-mode frequency divider, a Delta-Sigma modulator, and a digital-to-time converter. The Delta-Sigma modulator controls the division ratio of the multi-mode frequency divider to dynamically switch between integers, achieving fractional division. The digital-to-time converter performs high-precision delay adjustment on the jitter signal edges output by the multi-mode frequency divider based on the instantaneous phase error in the output signal, reducing the quantization error range of the output to the harmonic mixing phase-locked loop module. The mixing path signal generation module is composed of a pre-divider, which is used to divide the input signal to a suitable frequency, and serve as the local oscillator signal of the harmonic mixer in the harmonic mixing phase-locked loop module. The harmonic mixing phase-locked loop module includes a phase-locked loop circuit based on a harmonic mixing feedback architecture. It is used to receive a reference signal with a low quantization error range output by the reference path signal generation module, and use the signal output by the mixing path signal generation module as the local oscillator. The output oscillation signal is down-converted to an intermediate frequency and phase-locked through harmonic mixing, so that the equivalent frequency division ratio of the main loop is 1.

2. The harmonic mixing fractional phase-locked loop based on a digital time converter assisted according to claim 1, characterized in that: The reference path signal generation module also includes an integer phase-locked loop, which is used in conjunction with a multi-mode frequency divider, a Delta-Sigma modulator, and a digital-to-time converter to generate a reference signal and initially cancel quantization noise.

3. The harmonic mixing fractional phase-locked loop based on a digital time converter assisted according to claim 1, characterized in that, The prescaler in the mixing path signal generation module has a division ratio of 1.

4. A harmonic mixing fractional phase-locked loop based on a digital time converter assisted according to claim 1, characterized in that, The prescaler in the mixing path signal generation module is set to divide by two.

5. A harmonic mixing fractional phase-locked loop based on a digital time converter assisted according to claim 1, characterized in that: The harmonic mixing phase-locked loop module includes a harmonic mixer, a frequency and phase detector / charge pump, a low-pass filter, and a voltage-controlled oscillator based on a harmonic mixing feedback architecture.

6. A harmonic mixing fractional phase-locked loop based on a digital time converter assisted according to claim 1, characterized in that: The DTC employs a constant slope architecture based on a capacitive digital-to-analog converter.

7. A harmonic mixing fractional phase-locked loop based on a digital time converter assisted according to claim 6, characterized in that: The constant slope architecture based on a capacitive digital-to-analog converter consumes 200µW of power.

8. A harmonic mixing fractional phase-locked loop based on a digital time converter assisted according to claim 5, characterized in that: Digital-to-time converters suppress quantization noise folding caused by phase detection gain nonlinearity in harmonic mixing phase-locked loop modules.

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