Apparatus for digital-to-analog conversion with improved performance and related methods

Abstract

The present invention relates to apparatuses for digital-to-analog conversion with improved performance and related methods. In one exemplary embodiment, an apparatus includes a DAC for converting a digital input signal to an analog output signal. The DAC includes a decoder that decodes the digital input signal and provides a first set of control signals and a second set of control signals. The DAC also includes a resistor DAC (RDAC) that provides a first voltage and a second voltage in response to the first set of control signals. The DAC further includes an interpolator that is coupled to receive the first voltage and the second voltage in response to the second set of control signals and provide a first analog signal.

Description

[0001] This application is a divisional application of Chinese Patent Application 201511017418.4, entitled "Apparatus and related method for digital-to-analog conversion with improved performance," filed on December 31, 2015.

[0002] Cross-reference to related applications This application relates to and is incorporated by reference, for various purposes, of the following patent applications: U.S. Patent Application Serial No. 14 / 732,701 (Attorney-in-charge No. SILA362), filed June 6, 2015, entitled "Apparatus for Gain Selection with Compensation for Parasitic Elements and Associated Methods"; and U.S. Patent Application Serial No. 14 / 732,702 (Attorney’s No. SILA363), entitled “Apparatus for Offset Trimming and Associated Methods”, filed on June 6, 2015. Technical Field

[0003] This disclosure generally relates to electronic devices for processing signals, and more specifically to devices and related methods for digital-to-analog conversion with improved performance. Background Technology

[0004] Electronic signal processing often requires processing both analog and digital signals simultaneously, sometimes referred to as mixed-signal processing. Some sensors or transducers, along with natural properties or characteristics such as temperature and pressure, either constitute analog quantities or, in the case of sensors, frequently generate analog signals. Additionally, some transducers receive analog signals as input.

[0005] Conversely, as those skilled in the art will understand, signal processing circuits and building blocks increasingly utilize digital signals and digital technologies for reasons such as repeatability, stability, and flexibility. Signal conversion circuits are used to interface signal processing circuits with analog circuits.

[0006] One type of signal conversion circuit constitutes a digital-to-analog converter (DAC). DACs are typically used to accept digital signals as input and provide analog signals as output. Therefore, DACs provide an interface between digital processing circuits and analog circuits such as transducers or other circuits.

[0007] Several quality factors are used to characterize or specify a DAC. These quality factors include resolution (the number of bits of information in the input digital signal), noise level, monotonicity, differential nonlinearity (DNL), cost, die area, power consumption, gain and offset levels, and stability.

[0008] The descriptions and any corresponding drawings in this section are included as background information. The materials in this section should not be construed as an admission that they constitute prior art to this patent application. Summary of the Invention

[0009] This application discloses apparatus and related methods for digital-to-analog conversion with improved performance. In one exemplary embodiment, an apparatus includes a DAC that converts a digital input signal into an analog output signal. The DAC includes a decoder that decodes the digital input signal and provides a first set of control signals and a second set of control signals. The DAC also includes a resistor DAC (RDAC) that provides a first voltage and a second voltage in response to the first set of control signals. The DAC further includes an interpolator coupled to receive the first voltage and the second voltage in response to the second set of control signals and provide a first analog signal.

[0010] In another exemplary embodiment, an apparatus includes a DAC. The DAC includes a current source network and a first switching network. The current source network has multiple current sources providing multiple currents, and the first switching network selectively provides the multiple currents provided by the multiple current sources to a first node or a second node. The DAC also includes a resistor network having multiple resistors coupled to provide an output signal. The DAC further includes a second switching network coupled to the resistor network to selectively couple resistors of the resistor network to the first node and the second node.

[0011] In another exemplary embodiment, a method for converting a digital signal into an analog signal includes: decoding the digital signal to generate a first set of control signals and a second set of control signals; and providing a first voltage and a second voltage using an RDAC in response to the first set of control signals. The method further includes: interpolating the first voltage and the second voltage in response to the second set of control signals to provide a first analog signal. Attached Figure Description

[0012] The accompanying drawings are merely illustrative of exemplary embodiments and should therefore not be considered as limiting the scope of this application or the claims. Those skilled in the art will understand that the disclosed concepts are applicable to other equally effective embodiments. In the drawings, the same numerical indicators used in more than one drawing denote the same, similar, or equivalent functions, components, or modules.

[0013] Figure 1 A block diagram of a DAC architecture is shown according to an exemplary embodiment.

[0014] Figure 2 A circuit layout for a DAC is depicted according to an exemplary embodiment.

[0015] Figure 3 A conceptual block diagram of a DAC architecture is shown according to an exemplary embodiment.

[0016] Figure 4 A circuit layout for a DAC is depicted according to an exemplary embodiment.

[0017] Figure 5 The numerical values ​​corresponding to the operation of the DAC are shown according to an exemplary embodiment.

[0018] Figure 6 A process flowchart for operating a DAC is depicted according to an exemplary embodiment.

[0019] Figure 7 A conceptual block diagram of a DAC architecture is shown according to an exemplary embodiment.

[0020] Figure 8 An exemplary embodiment illustrates a circuit arrangement for fine-tuning the gain of a buffer.

[0021] Figure 9 An exemplary embodiment illustrates a circuit arrangement for fine-tuning the interpolator offset voltage.

[0022] Figure 10 A circuit arrangement for a DAC is depicted according to an exemplary embodiment of compensating parasitic elements.

[0023] Figure 11 An exemplary embodiment illustrates a circuit arrangement for providing offset fine-tuning in a DAC.

[0024] Figure 12 An integrated circuit (IC) that combines a DAC with other circuit modules is illustrated according to an exemplary embodiment.

[0025] Figure 13 A circuit layout for information processing using a DAC is depicted according to an exemplary embodiment.

[0026] Figure 14A control system using a DAC is illustrated according to an exemplary embodiment.

[0027] Figure 15 A circuit arrangement with a feedback loop having a DAC is shown according to an exemplary embodiment.

[0028] Figure 16 A communication system using a DAC is depicted according to an exemplary embodiment. Detailed Implementation

[0029] One aspect of the disclosed concepts relates to DAC architectures and technologies that offer certain advantages and benefits. Examples of these benefits and advantages include improved performance and quality factor, as detailed below.

[0030] Various conventional DAC architectures exist. DACs that must meet relatively stringent specifications (e.g., monotonicity and relatively high resolution such as 12-bit) typically include a large number of components such as resistors, capacitors, and transistors (usually metal-oxide-semiconductor field-effect transistors or MOSFETs). Relatively simple conventional DACs use an N-bit resolution architecture with 2... N Each component typically occupies a relatively large die area.

[0031] In addition, some specifications of a DAC often compete with others. For example, monotonicity often competes with high resolution. As another example, low-noise operation often competes with the overall power consumption of the DAC.

[0032] One technique used to achieve monotonicity involves matching components. In other words, various DACs or components such as resistors, capacitors, and MOSFETs are matched to achieve monotonicity. Therefore, using component matching, a current-mode DAC can be implemented to achieve monotonicity.

[0033] In such a DAC, to achieve good matching, the components are physically relatively large, typically proportional to the square root of the component area. As DAC resolution increases, the physical size of the components also increases. Furthermore, as DAC resolution increases, the number of components doubles for each additional bit of resolution. In a simple binary implementation, the total component area increases eightfold for each additional bit of resolution. More specifically, twice as many components are used, and each component is four times larger.

[0034] In practice, while techniques to reduce the area of ​​DAC circuitry can be used, the component area still increases significantly with increasing resolution. One technique for reducing the number of components required for matching in improving DAC performance is to use thermometer decoding to select higher orders (where matching considerations tend to dominate) and simple binary decoding for lower orders. However, the die area used to implement thermometer decoding is much larger than the area used to implement binary encoding, which partially offsets the advantage of a smaller overall component area.

[0035] Another type of conventional DAC does not rely on component matching, where each input code increment adds one component, so the output voltage or current will increase regardless of component weights. The DNL is determined by absolute component variation, such that ±1 least significant bit (or lower significant bit) (LSB) DNL is obtained if the value of each component is within ±100% of the average value. A brute-force approach to implementing a monotonic DAC uses the same number of components as a simple non-monotonic DAC (2... N However, the decoding logic and switches used in DACs tend to be more complex. This is because all 2 N Each component is controlled by a unique digital signal instead of the N signals used in a simple binary DAC.

[0036] The DACs according to various embodiments of this disclosure reduce the number of DAC components and the complexity of the decoding circuitry. Therefore, the DACs according to various embodiments provide monotonic operation with relatively high resolution.

[0037] More specifically, the DAC according to the exemplary embodiment can provide 12-bit resolution, relatively low noise operation and monotonicity (DNL of ±1 LSB), and a relatively small die size. (For static operation, the DAC output is periodically maintained at a programmed voltage (i.e., the analog output voltage of the DAC corresponding to the digital input of the DAC) without the application of one or more clock signals.) Details of the DAC architecture and operating techniques are described in detail below.

[0038] In some embodiments, the DAC according to this disclosure uses an architecture that includes multiple resistors, switches, and current sources. Figure 1 A block diagram illustrating the architecture of this DAC is shown. More specifically, Figure 1 The architecture of DAC 100 is shown. DAC 100 includes a current source network 103, a switch network 106, a switch network 109, and a resistor network 112, which includes a plurality of resistors.

[0039] The current source network 103 includes a plurality of current sources labeled CS0-CSn (n+1 sources in the example shown). The output current of the current sources in the current source network 103 is supplied to the switching network 106. The switching network 106 causes the output current of the current sources in the current source network 103 to be supplied to node (or leg, branch, or channel) 106A or node (or leg, branch, or channel) 106B.

[0040] like Figure 1 As shown, the least significant bit (LSB) of the digital input signal to the DAC drives the input to the decoder 118. The decoder 118 decodes the LSB to generate control signals for the switching network 106. In response to these control signals, the switching network 106 can supply the output current of the current source network 103 to either node 106A or node 106B. In other words, the switching network 106 selectively directs the output current of the current source network 103 to nodes 106A and 106B. The switching network 106 directs the output current to maintain the monotonicity of the DAC 100.

[0041] Nodes 106A-106B are coupled to switching network 109. The most significant bit (MSB) of the digital input signal to the DAC drives the input to decoder 121. Decoder 121 decodes the MSB to generate control signals for switching network 109. In response to these control signals, switching network 109 couples nodes 106A and 106B to resistor network 112. Therefore, according to these control signals, current flowing through nodes 106A-106B flows through a selected portion of resistor network 112. Switching network 109 couples nodes 106A-106B to resistor network 112 to maintain the monotonicity of DAC 100. In response, resistor network 112 provides an analog output.

[0042] In exemplary embodiments, decoder 118 and decoder 121 may be implemented or carried out in various ways and may use various configurations or topologies. In some embodiments, decoder 118 may constitute a thermometer decoder, while decoder 121 may constitute a binary decoder.

[0043] It should be noted that, for ease of display, Figure 1 Some modules of DAC 100 have been omitted. For example, the analog output of resistor network 112 can be coupled to a buffer or amplifier (not shown) to provide an analog output signal for DAC 100, which can be used to drive an external load. As another example, in Figure 1 The bias circuit is not shown.

[0044] Figure 2A circuit layout for DAC 100 is depicted according to an exemplary embodiment. Figure 2 The DAC 100 in the middle is similar to Figure 1 The DAC shown is operating. (Reference) Figure 2 The DAC 100 includes a current source network 103, a switch network 106, a switch network 109, and a resistor network 112.

[0045] Similar to Figure 1 , Figure 2 The current source network 103 includes multiple current sources labeled CS0-CSn (n+1 sources in the example shown). The output current of the current sources in the current source network 103 is supplied to the switching network 106.

[0046] The switch network 106 includes a plurality of switches 106A1-106N2. In the example shown, switches 106A1-106N2 constitute a p-channel MOSFET. However, as those skilled in the art will understand, other types of switches can be used. As those skilled in the art will understand, the selection of switches depends on factors such as available technology, specifications for a given implementation, etc.

[0047] Referring to switch network 106, switches 106A1-106N2 are arranged in pairs and coupled to corresponding current sources in current source network 103. Therefore, switches 106A1 and 106A2 are coupled to current source CS0. As another example, switches 106B1 and 106B2 are coupled to current source CS1, and so on.

[0048] Switches 106A1-106N2 are controlled by signals labeled B0 to Bnb. The switches in the switch pairs described above are controlled by complementary signals. For example, the control signal B0 for switch 106A1 is logically complementary to the control signal B0b for switch 106A2. As another example, the control signal B1 for switch 106B1 is logically complementary to the control signal B1b for switch 106B2, and so on.

[0049] Switching network 106 causes the output current of the current source in current source network 103 to be supplied to node 106A or node 106B. The LSB of the digital input signal to the DAC drives the input of decoder 118. Decoder 118 decodes the LSB to generate control signals for switches 106A1-106N2 in switching network 106, and in response to the control signals, the corresponding output current of the current source is directed to one of the two nodes.

[0050] More specifically, such as Figure 2As shown, the LSB of the digital input signal to the DAC drives the input of decoder 118. Decoder 118 decodes the LSB to generate control signals for switch network 106, specifically for switches 106A1-106N2. In response to the control signals, switch network 106 can provide the output current of current source network 103 to node 106A or node 106B.

[0051] More specifically, the switch network 106 selectively directs the output current of the current source network 103 to nodes 106A and 106B, thereby maintaining the monotonicity of the DAC 100. For example, consider the case where signals B0 and B0b have low and high logic values, respectively. Therefore, switch 106A1 is turned on, and switch 106A2 is turned off. Thus, switch 106A1 conducts the output current of current source CS0 to node 106A.

[0052] Conversely, assume that signals B0 and B0b have high and low logic values, respectively. Therefore, switch 106A1 is turned off, and switch 106A2 is turned on. Thus, switch 106A2 conducts the output current of current source CS0 to node 106B.

[0053] Nodes 106A-106B are coupled to switch network 109. Switch network 109 includes... Figure 2 Multiple switches are labeled 109-0 to 109-m. The more significant bit (MSB) of the digital input signal to the DAC causes switches 109-0 to 109-m to be selectively turned on (according to the MSB bit, as described in detail below), and thus couples nodes 106A-106B to resistor network 112.

[0054] The MSB bit drives the input of decoder 121. Decoder 121 decodes the MSB bit and generates (m+1) output signals labeled A0-Am. Driver 124 generates switch control signals for switches 109-0 to 109-m+1, that is, it generates (m+2) switch control signals.

[0055] More specifically, driver 124 derives switch control signals from the output signals A0-Am of decoder 121. Signals A0 and Am control switches 109-0 and 109-m+1 respectively, without any further changes. However, switches 109-1 through 109-m use switch control signals obtained based on the logic operations performed on the output of decoder 121.

[0056] For example, the switch control signal for switch 109-1 is (A0⊕A1), where the symbol “⊕” represents a logical OR operation. As another example, the switch control signal for switch 109-2 is (A1⊕A2), and so on. Generally, the switch control signal for switch 109-i has (A0⊕A1)... i-1 ⊕A i The form is ), where i represents an integer. For example, ... Figure 2 The configuration shown includes (m+2) switches, with switch 109-m having (A) m-1 ⊕A m Switch control signals in the form of ).

[0057] Through nodes 106A-106B, the switching network 109 provides the current received from the switching network 106 to the resistor network 112. More specifically, as described above, the decoder 121 decodes the MSB to generate control signals for the switches in the switching network 109. In response to these control signals, the switches in the switching network 109 couple nodes 106A and 106B to the resistor network 112.

[0058] Therefore, as described in detail below, according to the control signal, the current flowing through nodes 106A-106B flows through a selected portion of resistor network 112. Switch network 109 couples nodes 106A-106B to resistor network 112 to maintain the monotonicity of DAC 100. Responding to the current supplied by switch network 109, resistor network 112 provides an analog output.

[0059] Resistor network 112 includes multiple resistors. Figure 2 In the illustrated embodiment, resistor network 112 includes (m+1) resistors labeled R0 to Rm. Current is supplied to one or more resistors in resistor network 112 depending on the state of the switches in switch network 109, i.e., whether the corresponding switch is on. The flow of current creates a voltage across resistor network 112, which is provided via analog output 115.

[0060] Therefore, in response to the digital input to DAC 100, DAC 100 generates an output voltage at analog output 115. For example, consider the case where the digital input to DAC 100 is incremented from all bits set to zero to its maximum value. As described below, in response, DAC 100 generates a signal at analog output 115.

[0061] When the MSB is set to zero, decoder 121 enables signal A0 at its output. In response, driver 124 causes switches 109-0 and 109-1, coupled to resistor R0, to turn on. When the LSB is set to zero, decoder 118 enables signals B0, B1, ..., Bn (which deactivates signals B0b, B1b, ..., Bnb).

[0062] Therefore, switches 106A1, 106B1, ..., 106Bn are turned on, providing the output current of current sources CS0-CSn to node 106A. The current flowing into node 106A flows through switch 109-0 to the circuit ground. Therefore, DAC 100 provides zero volts at analog output 115.

[0063] As the LSB code increments, the output current from current sources CS0-CSn is sequentially supplied to node 106B via switching network 106. The current supplied to node 106B then flows through resistor R0 to circuit ground, thus causing an increase in the output voltage at analog output 115.

[0064] When the output current from all current sources CS0-CSn has been supplied to node 106B, the MSB code will begin to increment, for example, it will change from 0…00 to 0…01. Therefore, decoder 121 enables signal A1 and deactivates signal A0. However, the output voltage at analog output 115 will not change because all current at that point flows through switch 109-1 controlled by the switch control signal (A0⊕A1) provided by driver 124.

[0065] As the LSB code increments further, the switches in the switching network 106 change state in reverse order. In other words, the outputs of current sources CS0-CSn will flow sequentially to node 106A, not node 106B. Therefore, each code increment switches one LSB of the current from the upper node of resistor R0 to the upper node of resistor R1. Consequently, the output voltage at analog output 115 increases.

[0066] As the digital input to the DAC 100 is incremented to the maximum code value (e.g., all binary 1s), the above process repeats. At this point, all the output current from current sources CS0-CSn will flow into the upper node of resistor Rm. Therefore, the output voltage at analog output 115 will have a value corresponding to the maximum digital input applied to the DAC 100.

[0067] The current-guided architecture described above remains independent of the constant current supplied to the digital input of DAC 100. Because each step in the digital input removes a primary current from the current sources CS0-CSn from a given resistor in resistor network 112 and supplies that primary current to the aforementioned resistors (e.g., from resistor R(m-1) to resistor Rm), the DAC architecture remains monotonic. As long as the current value does not decrease and as long as the resistors in question have positive resistance, the voltage at analog output 115 will rise in response to the code increment at the input of DAC 100.

[0068] In exemplary embodiments, the driver 124 can be implemented in various ways. For example, in some embodiments, the driver 124 may include logic circuitry, such as an OR gate, to generate switching control signals for switches in the switching network 109. However, the driver 124 can be implemented in other ways. As those skilled in the art will understand, the choice of implementation depends on factors such as available technology, available die area, performance specifications, and so on.

[0069] It should be noted that, similar to Figure 1 For ease of display, Figure 2 Some modules of DAC 100 have been omitted. For example, the analog output of resistor network 112 can be coupled to a buffer or amplifier (not shown) to provide an analog output signal for DAC 100, which can be used to drive an external load. As another example, the bias circuit is not included. Figure 2 As shown in the image.

[0070] As described above, decoder 118 and decoder 121 can be implemented or constructed in various ways, and various configurations or topologies can be used. Figure 2 In the illustrated embodiment, decoder 118 can constitute a thermometer decoder, while decoder 121 constitutes a binary decoder. As those skilled in the art will understand, other types and / or configurations of decoders can be used.

[0071] In order to control the switching network 106 compared to the switching network 109, one aspect of this disclosure relates to the allocation of digital input bits. In other words, the allocation of digital input bits includes selecting or determining the relative values ​​of m and n, which determine the number of current sources in the current source network 103 and the number of resistors in the resistor network 112.

[0072] Considering embodiments using a thermometer decoder as decoder 118 and a binary decoder as decoder 121, the bit allocation, i.e., the selection of the m and n values, can be based on the properties of the decoder. Specifically, the size of a thermometer decoder is typically about twice the size of a binary decoder (i.e., it consumes twice the die area in the IC). If the resistor and current source element sizes are similar, fewer bits can be allocated to the current source. For example, resistor network 112 uses 6 bits while current source network 103 uses 5 bits to produce decoders of approximately the same size (i.e., decoder 118 and decoder 121 use approximately the same die area). (It should be noted that DAC element sizes are generally selected based on the integral nonlinearity (INL) and noise specifications of a given implementation of DAC 100).

[0073] Another aspect of this disclosure relates to increasing the resolution of DAC 100 by modifying the switching network. More specifically, the resolution of DAC 100 can be increased by controlling the gate voltages of the current-driven switches instead of biasing them as simple current-driven switches. If the two switches corresponding to a given current source (e.g., switches 106N1 and 106N2 corresponding to current source CSn) are turned on by setting the two gate voltages to be equal or approximately equal, the output current of the corresponding current source (e.g., CSn in the previous example) will be uniformly or approximately uniformly distributed between nodes 106A-106B. In other words, the switches are biased to conduct the output current of the corresponding current source (e.g., CSn in the previous example) uniformly between them.

[0074] This configuration adds additional resolution bits to DAC 100 while preserving monotonicity. In an exemplary embodiment, an XOR gate can be used to implement digital control of the switches in the switch network 106 to determine which switches correspond to a given current source applied by the control scheme described above.

[0075] It should be noted that, in addition to using XOR gates for control, other mechanisms and circuit arrangements can be used. For example, in some embodiments, the control mechanism can be built into the thermometer decoder. It should be noted that additional bias levels can add more resolution bits at the cost of a loss of monotonicity (or a deterioration in monotonicity). Therefore, as those skilled in the art will understand, trade-offs exist and can be based on factors such as the specifications for a given application.

[0076] In some applications, relatively low noise levels are desirable. One aspect of this disclosure relates to providing a DAC with relatively low noise levels (e.g., compared to a conventional DAC) while preserving monotonicity. Figure 3 A block diagram of a low-noise DAC 200 is shown according to an exemplary embodiment.

[0077] DAC 200 includes resistor network 203, switch network 206, switch network 209, interpolator network 212, and output stage 215, wherein resistor network 203 includes multiple resistors. Additionally, DAC 200 includes decoder 218, which decodes the digital inputs applied to DAC 200 and generates control signals for switch networks 206 and 209.

[0078] Resistor network 203 is coupled to reference voltage V ref Therefore, current flows through resistor network 203. The flow of current through resistor network 203 results in the generation of multiple voltages, which are supplied to switch network 206.

[0079] As described above, decoder 218 decodes the digital input of DAC 200 and generates a control signal 218A for switching network 206. More specifically, control signal 218A is derived from the most significant bit (MSB) of the digital input of DAC 200. In response to control signal 218A, switching network 206 selectively couples the voltage from resistor network 203 to a value labeled V. even and V odd The node. More specifically, based on control signal 218A, a voltage from resistor network 203 is coupled to node V. even And a voltage is coupled to node V odd .

[0080] Switching network 209 selectively connects node V even and V odd The signal is coupled to interpolator network 212. In response, interpolator network 212 provides a signal, such as current, to output stage 215. Based on the signal from interpolator network 212, output stage 215 generates an output signal at analog output 221. In the illustrated embodiment, analog output 221 constitutes the output of DAC 200.

[0081] The switching network 209 operates in response to control signal 218B. More specifically, based on control signal 218B, the switching network 209 selectively switches node V... even and V odd Coupled to interpolator network 212. Decoder 218 decodes the digital input to DAC 200 and generates control signal 218B for switching network 209. Control signal 218B is obtained from the least significant bit (LSB) of the digital input to DAC 200.

[0082] Overall, in response to the digital input, DAC 200 uses switch networks 206 and 207 to route two output signals from the output of resistor network 203 to interpolator network 212. Therefore, DAC 200 can be considered as generating two outputs (at node V) coupled to drive the interpolator (interpolator network 212 driven by switch network 209). even and V odd The combination or cascade of RDAC (resistor network 203 driving switch network 206) at the location.

[0083] In exemplary embodiments, the interpolator network 212 can be implemented in various ways. For example, in some embodiments, the interpolator network 212 may use multiple transconductors (g) m () stage or amplifier. Therefore, the interpolator network 212 can be g m Interpolator network.

[0084] Figure 4 A circuit layout for the DAC 200 is depicted according to an exemplary embodiment. Similar to... Figure 3 The embodiment shown, Figure 4 The DAC 200 includes a resistor network 203, a switch network 206, a switch network 209, an interpolator network 212, and an output stage 215. Additionally, the DAC 200 includes a decoder 218, which decodes the digital inputs applied to the DAC 200 and generates control signals for the switch networks 206 and 209.

[0085] Resistor network 203 includes resistors connected in series at a reference voltage (V). ref Multiple resistors (labeled R0 to RN) are connected between the resistor and ground potential. In some embodiments, resistors R0-RN may have the same (or approximately the same) resistance value. Applying a reference voltage to the resistors will cause current to flow through the resistor string. Therefore, multiple voltages are formed across each identical resistor in the resistor network 203. The resulting multiple voltages are fed to the switching network 206.

[0086] The switching network 206 includes multiplexers (MUX) 206A and MUX 206B. MUX 206A-206B operate in response to control signals 218A1-218A2, respectively. Resistors R0-RN are alternately coupled to MUX 206A-206B. More specifically, the upper node of each resistor is alternately coupled to MUX 206 and MUX 206B. For example, the upper node of resistor R0 is coupled to the input of MUX 206A, while the upper node of resistor R1 is coupled to the input of MUX 206B, and so on.

[0087] In response to the digital input signal applied to the DAC 200, the decoder 218 generates control signals 218A1-21A2. Control signals 218A1-21A2 together form control signal 218A. Based on the value of the most significant bit (MSB) of the digital input to the DAC 200, the decoder 218 generates control signals 218A1-21A2. In other words, control signals 218A1-21A2 are obtained from the MSB to control MUX 206A-206B respectively.

[0088] Control signals 218A1-21A2 cause MUX 206A-206B to selectively couple resistors R0-RN to the circuit marked V. even and V odd One of the two nodes. Therefore, based on the MSB, the MUX 206A-206B selectively provides the output voltage of the resistor network 203 to node V. even and V odd In the illustrated embodiment, node V even and V odd Each of the nodes is coupled to half of the resistors in the resistor network 203 via the switch network 206, and the couplings are staggered. Therefore, node V even and V odd Spanning a range of resistor strings or steps, but coupled to V through different or alternating resistors, such as the upper node of an even number of resistors. even The node, while the upper node of the odd-numbered resistor is coupled to V. odd Nodes (or vice versa).

[0089] Node V even and V odd Coupled to the input of switch network 209. Switch network 209 includes MUX 209-0 to 209-k. Node V even Coupled to one input of MUX 209-0 to 209-k. Node V odd It is coupled to another input of MUX 209-0 to 209-k. The outputs of MUX 209-0 to 209-k drive the corresponding inputs of interpolator network 212.

[0090] Switching network 209 selectively connects node V even and V odd Coupled to interpolator network 212. Specifically, switch network 209 operates in response to control signal 218B. Therefore, based on control signal 218B, switch network 209 connects node V... even and V odd Selectively coupled to interpolator network 212.

[0091] Decoder 218 provides control signal 218B. Specifically, decoder 218 decodes the digital input of DAC 200 and generates control signal 218B for switching network 209. Control signal 218B is derived from the least significant bit (LSB) of the digital input of DAC 200.

[0092] Switching network 209 will connect node V even and V odd Selectively coupled to interpolator network 212. In the illustrated embodiment, the interpolators in interpolator network 212 constitute multiple transconductors (g m ) stage or amplifier, therefore it is g m Interpolator network. g in interpolator network 212 m The interpolator is labeled g m0 to g mk .

[0093] As described above, each g in the interpolator network 212 m One input of the interpolator, such as a non-inverting input, is coupled to the corresponding output of one of the MUXs 209-0 to 209-k. g in the interpolator network 212 m Another input in the interpolator, such as the inverting input, is coupled to a feedback network including resistors 224 and 226. Specifically, through resistors 224 and 226, g in the interpolator network 212... m The interpolator receives a signal related to the analog output at 221 (in Figure 4 In the illustrated embodiment, the signal is scaled down. By selecting appropriate values ​​for resistors 224 and 226, the total gain of the interpolator network 212 and the output stage 215 can be programmed to the desired value.

[0094] In response to the outputs of MUX 209-0 to 209-k, g m interpolator g m0 to g mk An output signal is provided, which is summed at node 212A to generate an output signal (e.g., a current signal) for interpolator network 212. The signal at node 212A drives the input of output stage 215. In response, output stage 215 generates an output signal at analog output 221. In the illustrated embodiment, analog output 221 constitutes the output of DAC 200.

[0095] Output stage 215 can be implemented in various ways. For example, in some embodiments, the output stage may include multiple transconductance stages and amplifiers, such as Class AB amplifiers. Output stage 215 provides an analog signal at analog output 221, which can drive an external load.

[0096] and Figure 2 Similar to the DAC in the example, a number of bits of the digital input of DAC 200 can be allocated to the control switch network 206, while the remaining bits can be allocated to the drive switch network 209. For example, consider a 12-bit DAC according to one embodiment, where 5 bits of the DAC's digital input implement the LSB of DAC 200. In such a DAC, the resistor strings in resistor network 203 implement 7 MSBs (128 elements) of the DAC. In such an embodiment, MUX 206A and MUX 206B are controlled by 6-bit control or selection signals 218A1 and 218A2, respectively.

[0097] The remaining 5 bits of the digital input of DAC 200 implement LSB. Therefore, the DAC includes 2 in the switching network 209. 5 Alternatively, there may be 32 MUXs. The outputs of the 32 MUXs drive one input of an interpolator in the interpolator network 212. In such an embodiment, the interpolator network 212 comprises 32 interpolators, i.e., k=31.

[0098] To illustrate the operation of such a DAC, it should be noted that the MUX 206A and 206B couple the taps in the resistor string of resistor network 203 to V. even and V odd Nodes or buses. Because the 7 MSBs in the DAC's digital input ramp from 0000000 to 1111111, the voltage from the resistor taps changes in a "leapfrog" or alternating manner. Figure 5 Example of current node V even and V odd Some voltages at that location.

[0099] like Figure 5 As shown in the table, at node V even and V odd The voltage at that point depends on the reference voltage V. ref And the MSB input code (indicated under the column heading "Code"). Note that in response to consecutive code changes, at node V... even and V odd The voltage phase difference at the point is (1 / 128)·V ref Or 0.0078125·V ref The voltage. If V ref If it has a value of 1.2 volts, then V even and V odd The difference will be approximately 10mV. Note that if the MSB code is even, then V... odd Will be compared to V even 10mV higher. Conversely, if the MSB code has an odd value, then V even Will be compared to V odd10mV higher. This is achieved by generating an output (V) that depends on the input code and the reference voltage value. even and V odd The combination of resistor strings and switch networks (and corresponding decoder circuits) can be considered an RDAC.

[0100] In the example discussed above, interpolator network 212 implements a lower 5 LSB. As the name suggests, interpolator network 212 uses 32g... m Intercalator in V even and V odd Interpolation between voltages at the nodes. As described above, the control signal 218B obtained from the LSB in the digital input of the DAC controls V. even Voltage at V and odd Which of the voltages is supplied to each corresponding interpolator in the interpolator network 212.

[0101] To illustrate the operation of interpolator network 212, assume that the 7 MSBs have a value of 0000000, i.e., all are 0. In this case, V even It is 0V, and V odd It has a value of approximately 10mV (see Figure 5 When all 5 LSBs are 0 (i.e., 00000), 32 g m The interpolators connect their non-inverting inputs to V even That is, 0V or ground potential. Assuming that output stage 215 has a gain of 3V / V, the signal at analog output 221 will have a value of 0V (ground potential).

[0102] As the LSB ramps up from 00000 to 11111, each increment of the code (LSB value) results in the code being provided to g by the switch network 209. m interpolator g m0 -g mk One of the inputs from V even (0V) Switch to V odd (≈10mV). When all LSBs are binary 1 (code 11111), the switching network 209 will turn V... odd (≈10mV) provides up to 32g m 31 of the interpolators are used as inputs. In this case, the voltage at analog output 221 will have a value of 3 × (31 / 32) × 10 mV, or approximately 29 mV.

[0103] For LSB code values ​​between 00000 and 11111, switch network 209 will connect node V even The voltage at the point provides some g m Interpolator, and will convert voltage V oddProvided to the remaining g m Interpolator. Therefore, based on the receiving node V odd The voltage at point g is part of the input signal. m The interpolator will give the signal at analog output 221 an interpolated value between 0V and approximately 29mV. even and V odd The small voltage difference between them provides linear or approximately linear interpolation performed by the interpolator network 212.

[0104] When the 12-bit input (i.e., the digital input to the DAC) increments to the next value after 0000000 11111, the "leapfrog" or alternating property described above occurs. The 7 MSBs in the digital input increment from 0000000 to 0000001, and the 5 LSBs change from 11111 to 00000. The decoder 218 provides control signals 218B to MUX 209-0 to 209-k respectively, causing the input bits to be switched when the MSB code is odd, thus enabling all 32 bits to be processed. m Interpolator receiver node V odd The voltage at that point is used as the input (which still has a value of ≈10mV).

[0105] When the LSB code input to the DAC digital input increments to 00001, 31 gigabytes... m The interpolator remains coupled (via switch network 209) to receive at node V odd The voltage at that point is used as the input, and a g m Interpolator receiver node V even The voltage at that point is used as input, and it now has a value of ≈20mV instead of 0V. In this way, as the input LSB further increases, more g... m Interpolator stage receiver at node V even The voltage at point V instead of at node V odd The voltage at that point. Therefore, the interpolated signal (at output 212A) and thus the output signal at analog output 221 continue to rise. Ultimately, all g m The interpolator receives data at node V. even The voltage at that point is used as input. At that point, the MSB code increments again, and this process repeats.

[0106] It should be noted that although DAC operation has been described above with reference to a 12-bit DAC according to exemplary embodiments, similar descriptions and operations are applicable to DACs according to other exemplary embodiments. Therefore, as will be understood by those skilled in the art, the described concepts can be applied to DACs with different resolutions, different numbers of elements, etc.

[0107] Figure 6A flowchart illustrating the operation of the DAC is depicted according to an exemplary embodiment. At 253, a digital input signal provided to the DAC is received. At 256, the digital input signal is decoded to obtain a set of control signals from the most significant bit (MSB) of the digital input signal. Another set of control signals is obtained from the least significant bit (LSB) of the digital input signal.

[0108] At position 259, a set of control signals obtained from the MSB is used to drive the RDAC in order to generate V. odd and V even At position 262, a set of control signals obtained from the LSB is used to drive the interpolator to obtain from V odd and V even An analog output signal is obtained. For example, as mentioned above, the analog output signal can be further buffered or processed by using an output stage.

[0109] Combination Figures 3-5 The disclosed DAC offers numerous benefits and advantages. For example, compared to conventional DACs, one advantage involves relatively low noise operation while maintaining monotonicity and the other characteristics described above. Another advantage involves the relative ease of setting a relatively precise gain for the DAC.

[0110] One aspect of this disclosure relates to gain selection or adjustment in electronic devices such as DACs. The following description uses a DAC as an example to illustrate the concept, but as those skilled in the art will understand, the disclosed concepts can be applied to a variety of electronic devices having selectable or adjustable gain.

[0111] As described above, the gain of the DAC according to the exemplary embodiment depends on the reference voltage (V). ref The value of V. To illustrate various values ​​such as V ref The impact of output stage gain on overall DAC characteristics Figure 7 A conceptual block diagram of a DAC200 according to an exemplary embodiment is provided.

[0112] In the illustrated embodiment, the reference voltage (i.e., V) used in the DAC is... ref ) can be the original reference voltage (V r A scaled or partitioned version of DAC 200. Optionally or additionally, the original reference voltage can be externally applied to DAC 200, for example, by passing voltage V through a pin in an IC that includes DAC 200. EXT The voltage V is applied to the DAC 200. As those skilled in the art will understand, various sources, such as external reference sources, can provide the voltage V. EXT As described in detail below, in such a configuration, the DAC 200 includes components for processing and using the signal provided by the reference source to generate V. ref The mechanism.

[0113] In either case, the desired overall DAC gain can be obtained by using an appropriate value for the scaling or partitioning factor. The scaling circuit 303 applies the desired scaling factor to V. r This is to generate a scaled version of the signal applied to the register 306 at the output 303A of the scaling circuit 303. The scaling factor of the scaling circuit 303 can have a desired value or a set of values, and can be programmable or adjustable as needed. The register 306 is V r The scaled version provides buffering or amplification, and provides the DAC reference voltage V at its output of 306A. ref Buffer 306 has a gain fine-tuning input 306B that allows fine-tuning of its gain.

[0114] As mentioned above, the reference voltage V ref It is applied to RDAC 309. As described in detail above, in response to control signals 218A and V ref The RDAC 309 provides a voltage V at its output. even and V odd As described above, decoder 218 provides control signal 218A by decoding the digital input signal applied to DAC 200.

[0115] Intercalator 312 accepts the mark V even and V odd The voltage is used as input. As described in detail above, interpolator 312 may include a switching network and several interpolator stages. As described in detail above, in response to control signal 218B, interpolator 312 forms a voltage V at output terminal 312A. even and V odd The output voltage is a function of the signal. As described above, the decoder 218 provides the control signal 218B by decoding the digital input signal applied to the DAC 200.

[0116] Interpolator 312 has an offset fine-tuning input 312B. A signal applied at input 312B can be used to fine-tune the offset voltage of interpolator 312B. As those skilled in the art will understand, doing so will improve the overall performance of DAC 200. As described in detail above, output stage 215 receives the output signal from interpolator 215 and generates the analog output of DAC 200 at output 221. In an exemplary embodiment, output stage 215 may have a programmable or adjustable gain. This feature allows setting the overall gain or full-scale voltage of DAC 200.

[0117] The scaling circuit 315 scales the analog output voltage of the DAC 200 to generate V at the output terminal 315A. rA scaled version. The scaled voltage at output 315A is provided to interpolator 312 as a feedback signal obtained from the output voltage of interpolator 312. The scaling factor of scaling circuit 315 can have a desired value or a set of values, and can be programmable or adjustable as needed. Therefore, the effective gain of the output stage (more specifically, the total gain of interpolator 312 and output stage 215) can be programmed to the desired value.

[0118] Reduce voltage V r This can offer many benefits, such as ease of implementation. In some embodiments, n-type MOS (nMOS) devices can be used in the switching network of the DAC 200. Figure 7 (Not shown in the image). Reduce V. r This allows for reducing or limiting the swing of the input voltage applied to the interpolator stage in interpolator 312. Additionally, the voltage V is scaled. r Allows programming or setting of the DAC 200's total gain or full-scale output voltage.

[0119] In an exemplary embodiment, buffer 306 has a unity gain, but the combination of buffer 306 and scaling circuit 303 can be used to provide a programmable gain setting. The programmable gain setting can have various desired values, such as 1 / 2, 1 / 2.4, and 1 / 3. The programmable gain setting allows setting or programming the total gain of DAC 200. As an example, consider a DAC with an output stage 215 having a gain of 3. If a unity gain is desired for the DAC, a scaling factor of 1 / 3 can be used for scaling circuit 303, i.e., V... ref = (1 / 3) × V r The total gain will have a value of 1 / 3 × 3 or one unit.

[0120] Buffer 306 also has gain fine-tuning capability, which allows the output offset voltage of buffer 306 to be eliminated (or approximately eliminated). If the output offset voltage is not eliminated, it will appear in the DAC as a gain error and will degrade its performance. In an exemplary embodiment, the gain fine-tuning of buffer 306 can correct (or approximately correct) temperature change effects, power supply voltage variations, etc.

[0121] The gain of the buffer 306 can be fine-tuned in many ways. In some embodiments, fine-tuning is performed during product testing, i.e., during testing after manufacturing. In some embodiments, fine-tuning is performed as needed, such as periodically or upon power-up, and / or according to other schemes. Figure 8 A circuit arrangement 350 for fine-tuning the gain of the buffer 306 is shown according to an exemplary embodiment. (See below in conjunction with...) Figure 11 Other aspects of offset fine-tuning will be discussed. refer to Figure 8 The output signal of the scaling circuit 303 is applied to the switch 353. The use of switch 353 is optional. If the switch is used under the control of the controller 359, switch 353 allows selective use of V. r A scaled version or another gain-adjusting voltage is used to fine-tune the gain of buffer 306 (the voltage for gain fine-tuning can be generated by controller 359 or another part of the DAC). The voltage selected by switch 353 is applied to the input of buffer 306. The output of buffer 306 is applied to switch 356. Under the control of controller 359, switch 356 can selectively provide the output 306A of buffer 306 to RDAC 309 or controller 359.

[0122] During normal operation (i.e., when there is no gain adjustment of buffer 306), switch 356 couples output 306A to RDAC 309. During gain adjustment operation, switch 356 couples output 306A to controller 359. Based on the actual output voltage and the expected output voltage of buffer 306 (based on the input voltage applied to buffer 306), controller 359 applies one or more control signals to the gain adjustment input 360B of buffer 306. Therefore, the gain of buffer 306 is fine-tuned to a desired value (e.g., unity in the exemplary embodiment).

[0123] It should be noted that, as described above, in some embodiments, a user of the DAC (or other devices, circuitry, modules, etc.) can cause the controller 359 to perform gain fine-tuning at one or more desired points in time. It should further be noted that, in some embodiments, the DAC can be configured to automatically perform gain fine-tuning at one or more desired points in time, such as during power-on or DAC reset. Furthermore, various other circuit arrangements are possible and conceivable. For example, in some embodiments, the controller 359 can be implemented partially or entirely outside the IC on which the DAC resides, such as in a production tester performing operations such as post-IC fabrication testing and fine-tuning. As those skilled in the art will understand, in some embodiments, switches 353 and / or 356 can be omitted, and additional inputs to the buffer 306 or parallel inputs (instead of switch 353) can be used by sensing the output of the RDAC 309 (instead of using switch 356).

[0124] Similarly, the output offset voltage of interpolator 312 can be fine-tuned. In an exemplary embodiment, fine-tuning of the output offset voltage of interpolator 312 can correct (or approximately correct) temperature change effects, power supply voltage variations, etc.

[0125] The output offset voltage of interpolator 312 can be fine-tuned in many ways. In some embodiments, fine-tuning is performed during product testing, i.e., during post-processing testing. In some embodiments, fine-tuning is performed as needed, such as periodically or upon power-up, and / or according to other schemes. Figure 9 An exemplary embodiment illustrates a circuit arrangement 400 for fine-tuning the interpolator offset voltage. (The following is in conjunction with...) Figure 11 Other aspects of offset fine-tuning will be discussed. refer to Figure 9 Voltage V even and V odd The voltage is applied to switches 403A and 403B respectively. It should be noted that the use of switches 403A-403B is optional. If the switches are used under the control of controller 359, switches 403A-403B allow selective use of V. even and V odd Alternatively, another set of offset fine-tuning voltages can be used to fine-tune the offset of interpolator 312 (controller 359 or another part of the DAC can generate voltages for offset fine-tuning).

[0126] The voltage selected by switches 403A-403B is applied to the input of interpolator 312. As described above, the output of interpolator 312 is applied to scaling circuit 315. The output 315A of scaling circuit 315 is provided to controller 359. The output signal of scaling circuit 315 is used to fine-tune the output voltage offset of interpolator 312.

[0127] Under the control of controller 359, switch 406 can selectively provide interpolator 312 with either control signal 218B (generated by decoder 218 as described in detail above) or control signal 359A (available at output 306A) generated by controller 359. Controller 359 generates control signal 359A based on the input signal to interpolator 312 to give interpolator 312 a desired output voltage (e.g., 0V), thereby determining and fine-tuning the output offset voltage of interpolator 312.

[0128] During normal operation (i.e., when no fine-tuning is performed on the offset voltage of interpolator 312), switches 403A-403B will apply voltage V even and V odd It is coupled to interpolator 312. Additionally, switch 406 provides control signal 218B (generated by decoder 218) to interpolator 312. Therefore, as described above, the DAC generates an analog output signal in response to the digital input.

[0129] However, as mentioned above, during the offset fine-tuning operation, switches 403A-403B are coupled to V. even and Vodd Alternatively, another set of offset fine-tuning voltages can be used to fine-tune the offset of interpolator 312. Furthermore, switch 406 provides control signal 359A to interpolator 312. The output 315A of scaling circuit 315 provides a scaled version of the output voltage of interpolator 312 to controller 359.

[0130] Based on the actual output voltage and the expected output voltage of the interpolator 312 (based on the input voltage applied to the interpolator 312) (or a scaled-down version at the output 315A of the scaling circuit 315), the controller 359 applies one or more control signals to the offset fine-tuning input 312B of the interpolator 312. Therefore, the offset of the interpolator 312 is fine-tuned to the desired value (e.g., zero or approximately zero).

[0131] It should be noted that, as described above, in some embodiments, a user of the DAC (or other devices, circuitry, modules, etc.) can cause the controller 359 to perform offset fine-tuning at one or more desired points in time. It should further be noted that, in some embodiments, the DAC can be configured to automatically perform offset fine-tuning at one or more desired points in time as needed, such as during power-on or DAC reset. Furthermore, various other circuit arrangements are possible and conceivable. For example, in some embodiments, the controller 359 can be implemented partially or entirely outside the IC on which the DAC resides, such as in a production tester performing operations such as post-IC fabrication testing and fine-tuning. As those skilled in the art will understand, in some embodiments, switches 403A-403B and / or switch 406 can be omitted, and instead, the offset voltage of the interpolator 312 can be adjusted using an additional or parallel input (instead of switches 403A-403B) to sense the voltage at output 221 and apply a correction voltage via 312B, etc.

[0132] Figures 8-9 Various alternative configurations of the circuit layout are possible and conceivable. For example, in some embodiments, some or all of the functions of the decoder 218 may be combined with the functions of the controller 359, or vice versa. As will be understood by those skilled in the art, the choice of circuit layout used in a particular application depends on factors such as the specifications for that application.

[0133] As described above, in an exemplary embodiment, more than one source can be used to generate the reference voltage V. ref This involves using a switch that allows selection of the source. The switch has finite parasitic elements, such as parasitic resistance (e.g., on-state resistance). Additionally, as mentioned above, changing V... ref The value of causes a change in the DAC's total gain or output full-scale value.

[0134] To maintain or provide the desired gain or full-scale value, the effective gain of the output stage can be programmed or set to correspond to the selected V. ref The effective gain of the output stage (the total gain of the interpolator and output stage 215) can be programmed via scaling circuitry 315. Programming the effective gain of the output stage involves using switches in scaling circuitry 315. These switches also have finite parasitic elements, such as parasitic resistances (e.g., on-state resistances). One aspect of this disclosure relates to gain and offset fine-tuning or adjustment in electronic devices such as DACs.

[0135] One aspect of this disclosure relates to compensating for parasitic elements or effects, such as the parasitic resistance of the aforementioned switches in electronic devices like DACs. Figure 10 The circuit arrangement of the DAC 200 according to an exemplary embodiment for compensating for parasitic elements is depicted.

[0136] Figure 10 The DAC 200 includes... Figure 7 Some of the same or similar modules or circuits shown. Figure 10 The scaling circuit 303 in the middle provides for selecting the scaling circuit used to generate V ref A mechanism with one or two sources. In the illustrated embodiment, the external voltage (V) from a source outside the DAC 200. EXT ) or another voltage V r (For example, an internally generated source) can be used to generate V. ref .

[0137] Voltage V EXT Tapped resistors 450A-450B, with resistance values ​​R1 and R2 respectively, are applied. Switch 456D couples resistor 450B to ground. Switch 456D allows power to flow from V through resistors 450A-450B when the corresponding portion of scaling circuit 303 is not in use, or when DAC200 is not in use, etc. EXT The current flowing to ground is interrupted, which results in reduced power consumption. Controller 359 controls the operation of switch 456D.

[0138] Taps in resistors 450A-450B are coupled to switches 456A and 456C, respectively. Switch 456B is coupled to one end or terminal of resistor 450A and one end of resistor 450B. Controller 359 controls the operation of each switch 456A-456C. For example, controller 359 can cause switches 456A-456B to open and switch 456C to close. By controlling the switches, controller 359 can cause a voltage V to be supplied at the output terminal 303A1 of scaling circuit 303. EXT The programmable or desired portion.

[0139] Similarly, voltage V r Resistors 453A-453B, with resistance values ​​R1 and R2 respectively, are applied. Switch 459D couples resistor 453B to ground. When the corresponding part of the scaling circuit 303 is not used, or when DAC 200 is not used, etc., switch 459D allows power to flow from V through resistors 453A-453B. r The current flowing to ground is interrupted, resulting in reduced power consumption. Controller 359 controls the operation of switch 459D.

[0140] Taps in resistors 453A-453B are coupled to switches 459A and 459C, respectively. Switch 459B is coupled to one end or terminal of resistor 453A and one end of resistor 453B. Controller 359 controls the operation of each switch 459A-459C. For example, controller 359 can cause switches 459A-459B to open and switch 459C to close. By controlling these switches, controller 359 can cause a voltage V to be supplied at the output terminal 303A2 of scaling circuit 303. r The programmable or desired portion. As shown in the figure, outputs 303A1 and 303A2 flow into the input of buffer 306.

[0141] As described above, scaling circuit 315 provides interpolator 312 with a mechanism for providing a scaled version (denoted as V0) of the output signal of output stage 215 (available at output terminal 221). Voltage V0 is applied to resistors 462A-462B, each with resistance values ​​M·R1 and M·R2, respectively, where M represents a positive integer. Switch 465D couples resistor 462B to ground. When a corresponding portion of scaling circuit 303 is not used, or when DAC 200 is not used, etc., switch 465D allows the current flowing from V0 to ground through resistors 462A-462B to be interrupted, resulting in reduced power consumption. Controller 359 controls the operation of switch 465D.

[0142] Taps in resistors 462A-462B are coupled to switches 465A and 465C, respectively. Switch 465B is coupled to one end or terminal of resistor 462A and one end of resistor 462B. Controller 359 controls the operation of each switch 465A-465C. For example, controller 359 can cause switches 465A-465B to open and switch 465C to close. By controlling these switches, controller 359 can cause a programmable or desired portion of voltage V0 to be supplied to interpolator 312 to program the gain of the output stage of DAC 200.

[0143] In actual implementation, Figure 10The circuit layout shown includes various parasitic components, such as the parasitic resistances of switches 456A-456D, 459A-459D, and 465A-465D. These parasitic resistances can cause errors when setting the gain or full-scale output value of the DAC 200. These errors can be canceled or nearly canceled by properly dimensioning the components in scaling circuits 303 and 315 to the specified dimensions.

[0144] Specifically, as mentioned above, the corresponding resistances of resistors 462A-462B are M times larger than the resistances of resistors 450A-450B. Furthermore, assume that switches 456D and 459D have a resistance of R... SW If the parasitic resistance is such that the switch 465D is scaled or designed to the specified size with M·R SW The parasitic resistance. The choice of component size and values ​​cancels or approximately cancels the gain error discussed above, provided that the effective gain G of the output stage is... out (That is, the total gain of interpolator 312 and output stage 215) is the effective gain G of the reference voltage gain setting circuit. ref The reciprocal of (i.e., the total gain of scaling circuit 303 and buffer 306).

[0145] The following equation represents the overall gain of the DAC 200 under these conditions: G ref ·G out ={(R2+R sw ) / (R1+R2+R sw )·{1+(M·R1) / ((M·R2)+(M·R sw [Equation 1] It should be noted that if the reciprocal condition described above is met, then G ref ·G out =1.

[0146] In addition, it should be noted that if G ref and G out If not set to its reciprocal value, the gain error will be partially canceled out. Therefore, G ref and G out The closer the values ​​are to each other and set to their reciprocals, the better the gain error is compensated.

[0147] The techniques described above for compensating for gain errors caused by parasitic elements have been referenced in the DAC description. However, those skilled in the art will understand that these concepts can be applied to other electronic devices with modifications.

[0148] Another aspect of this disclosure relates to trimming or correcting various offset errors in electronic devices such as DACs. Figure 11An exemplary embodiment illustrates a circuit arrangement for providing offset fine-tuning in a DAC. A constant current source 503 supplies current I to resistors 506 and 512, which are coupled as a resistor string. The flow of current through resistors 506 and 512 results in a voltage level for fine-tuning the offset.

[0149] More specifically, resistors 506 and 512 have a number of taps. As those skilled in the art will understand, for example, in some embodiments, resistor 506 may have 31 taps, and resistor 512 may have 31 taps, but other numbers of taps may be used. The taps in resistor 506 are coupled to switch 509. The lower end or terminal of resistor 506 may be used as an additional tap and coupled to one of switches 509. Thus, the current flow through resistor 506 provides several voltage levels available through the taps in resistor 506.

[0150] Switch 509 selectively couples a tap of resistor 506 to node 509A. Controller 359 controls the operation of switch 509. Specifically, controller 359 can cause one or more switches 509 to turn on. In this way, controller 359 can provide several voltage levels to node 509A. For example, by turning on a single switch of 509, controller 359 may cause a voltage level at the tap coupled to that switch to be available at node 509A.

[0151] Similarly, the taps in resistor 512 are coupled to switch 515. The lower end or terminal of resistor 512 can be used as an additional tap and coupled to one of the switches in switch 515. Thus, the current flowing through resistor 512 provides several available voltage levels through the taps in resistor 512.

[0152] Switch 515 selectively couples a tap of resistor 512 to node 515A. Controller 359 controls the operation of switch 515. Specifically, controller 359 can cause one or more switches 515 to turn on. In this way, controller 359 can provide several voltage levels to node 515A. For example, by turning on a single switch of 515, controller 359 can cause the voltage level at the tap coupled to that switch to be available at node 515A.

[0153] Switch 518 couples resistor 509 to ground. Therefore, when the offset trimming function is not used, or when the DAC is not used, switch 518 allows the current flowing from current source 503 to ground through resistors 506 and 509 to be interrupted, resulting in reduced power consumption. Controller 359 controls the operation of switch 518.

[0154] The voltage at node 509A is used to fine-tune the output offset of interpolator 312. More specifically, the voltage at node 509A drives the transconductance (g) m () stage or input of amplifier 312-2. m The output current of stage 312-2 is provided to the output terminal 312A of interpolator 312. As described above, interpolator 312 includes a voltage V received via a switching network. even and V odd Several g m Level (marked as 312-1). In response, g m Stage 312-1 generates output current, which is then supplied together to the output terminal 312A of interpolator 312.

[0155] In other words, the current available at the output terminal 312A of the interpolator 312 constitutes the current generated by g. m The current provided by stage 312-1 and by g m The sum of the currents provided by stage 312-2. By changing the current supplied by g m The magnitude and / or polarity of the current provided by stage 312-2, the output offset of interpolator 312, and therefore the output offset voltage of the DAC can be fine-tuned, canceled, or approximately canceled.

[0156] In an exemplary embodiment, g m Grade 312-2 to g m Stage 312-1 has a lower current drive or drive capability (or strength) or transconductance value. Therefore, g m Grade 312-2 and g m Compared to stage 312-1, a smaller current is injected into node 312A. In other words, the output offset of interpolator 312 can be fine-tuned with a more precise granularity.

[0157] As described above, fine-tuning of the output offset voltage of interpolator 312 can be performed in many ways. In some embodiments, fine-tuning is performed during product testing, i.e., during testing after manufacturing. Based on these results, the control level for switch 509 can be stored (e.g., in memory) for further retrieval and use of the fine-tuning of the offset of interpolator 312. Furthermore, as described above, in some embodiments, fine-tuning is performed as needed during use, such as periodically or upon power-up, and / or according to other schemes.

[0158] refer to Figure 11 The voltage at node 515A is used to fine-tune the output offset of buffer 306. Fine-tuning the output offset of buffer 306 provides gain adjustment for the overall DAC.

[0159] The voltage at node 515A is used to fine-tune the output offset of interpolator 312. More specifically, the voltage at node 515A drives the transconductance (g) m () stage or input of amplifier 306-2. m The output current of stage 306-2 is provided to the output terminal 306A of register 306. Register 306 also includes a g-type amplifier that receives the voltage from the output terminal 303A of scaling circuit 303. m Level 306-1. In response, g m Stage 306-1 generates the output current, which is then converted into V by output stage 306-3. ref .

[0160] In other words, the current available at the output terminal 306A of the register 306 constitutes the current generated by g. m The current provided by stage 306-1 and by g m The sum of the currents provided by stage 306-2. By changing the current supplied by g m The magnitude and / or polarity of the current provided by stage 306-2, the output offset of register 306, and therefore the overall gain of the DAC can be fine-tuned.

[0161] In an exemplary embodiment, g m Grade 306-2 to g m Grade 306-1 has a lower current drive or drive capability (or strength) or transconductance value. Therefore, g m Grade 306-2 and g m Compared to stage 306-1, a smaller current is injected into node 306A. In other words, the output offset of register 306 can be fine-tuned with a more granular approach.

[0162] As described above, fine-tuning of the output offset voltage of register 306 can be performed in many ways. In some embodiments, fine-tuning is performed during product testing, i.e., during testing after manufacturing. Based on these results, the control level for switch 515 can be stored (e.g., in memory) for further retrieval and use of the fine-tuning of the offset of register 306. Furthermore, as described above, in some embodiments, fine-tuning is performed as needed during use, such as periodically or upon power-up, and / or according to other schemes.

[0163] For example, according to an exemplary embodiment, by integrating the DAC and signal processing or computing circuitry within the IC, the DAC can be combined with other circuitry. Figure 12 An exemplary embodiment illustrates an integrated circuit (IC) 550 that combines a DAC with other circuit modules, such as a microcontroller unit (MCU).

[0164] IC 550 includes several modules (e.g., processor 565, data converter 605, I / O circuitry 585, etc.) that communicate with each other using link 560. In an exemplary embodiment, link 560 may constitute a coupling mechanism, such as a bus, a set of conductors, or semiconductors for conveying information (such as data, commands, status information, etc.).

[0165] IC 550 may include a link 560 coupled to one or more processors 565, clock circuitry 575, and power management circuitry 580. In some embodiments, processor 565 may include circuitry or modules for providing computational functions, such as a central processing unit (CPU), an arithmetic logic unit (ALU), etc. In some embodiments, additionally or alternatively, processor 565 may include one or more digital signal processors (DSPs). The DSP may provide various signal processing functions as needed, such as arithmetic functions, filtering, delay modules, etc.

[0166] Clock circuit 575 can generate one or more clock signals that facilitate or control the timing of operation of one or more modules in IC 550. Clock circuit 575 can also control the timing of operation using link 560. In some embodiments, clock circuit 575 can provide one or more clock signals to other modules in IC 550 via link 560.

[0167] In some embodiments, the power management circuit 580 may reduce the clock speed of the device (e.g., IC 550), turn off the clock, reduce power, turn off power, or any combination of the foregoing with respect to a portion of the circuit or all components of the circuit. Further, the power management circuit 580 may turn on the clock, increase the clock rate, turn on power, increase power, or perform any combination of the foregoing in response to a transition from an inactive state to an active state (such as when the processor 565 makes a transition from a low-power, idle, or sleep state to a normal operating state).

[0168] Link 560 can be coupled to one or more circuits 600 via serial interface 595. One or more circuits coupled to link 560 can communicate with circuit 600 via serial interface 595. As will be understood by those skilled in the art, circuit 600 can communicate using one or more serial protocols such as SMBUS, I2C, SPI, etc.

[0169] Link 560 can be coupled to one or more peripheral devices 590 via I / O circuit 585. Through I / O circuit 585, one or more peripheral devices 590 can be coupled to link 560 and thus can communicate with other modules coupled to link 560, such as processor(s) 365, memory circuit 625, etc.

[0170] In an exemplary embodiment, peripheral device 590 may include various circuits, modules, etc. Examples include I / O devices (keyboard, keyboard, speaker, display device, storage device, timer, etc.). It should be noted that in some embodiments, some peripheral devices 590 may be external to IC 550. Examples include keyboards, speakers, etc.

[0171] In some embodiments, I / O circuitry 585 may be bypassed relative to some peripheral devices. In such embodiments, some peripheral devices 590 may be coupled to and communicate with link 560 without using I / O circuitry 585. It should be noted that, as described above, in some embodiments, such peripheral devices may be external to IC 550.

[0172] Link 560 can be coupled to analog circuitry 620 via data converter 605. Data converter 605 may include one or more ADCs 615 and / or one or more DACs 200. ADCs 615 receive analog signals from analog circuitry 620 and convert the analog signals into digital format so that they can communicate with one or more modules coupled to link 560.

[0173] Conversely, the (multiple) DACs 200 receive one or more digital signals from one or more modules coupled to link 560 and convert the (multiple) digital signals into analog format. As needed, the (multiple) analog signals can be provided to circuitry within IC 550 (e.g., analog circuitry 620) or to circuitry outside IC 550.

[0174] Analog circuit 620 may include various circuits that provide and / or receive analog signals. Examples include sensors, transducers, etc., as will be understood by those skilled in the art. In some embodiments, analog circuit 620 may communicate with circuits external to IC 550, as needed, to form more complex systems, subsystems, control modules, and information processing modules.

[0175] Control circuitry 570 is coupled to link 560. Therefore, control circuitry 570 can communicate with and / or control the operation of various modules coupled to link 560. Alternatively, control circuitry 570 can facilitate communication or cooperation between various modules coupled to link 560. In some embodiments, the functions or lines of the control circuitry in DAC 200 (e.g., controller 359 described above) can be combined with the functions or lines of control circuitry 570 as needed, or the functions or lines of the control circuitry in DAC 200 (e.g., controller 359 described above) can be included in the functions or lines of control circuitry 570.

[0176] Refer again Figure 12In some embodiments, control circuitry 570 may initiate or respond to a reset operation. As those skilled in the art will understand, a reset operation may cause one or more modules, such as those on link 560 coupled to IC 550, to reset. For example, control circuitry 570 may cause DAC(s)(s)200(s) to reset to their initial state.

[0177] In an exemplary embodiment, the control circuit 570 may include various types of circuits and modules of various circuits. In some embodiments, the control circuit 570 may include logic circuits, finite state machines (FSMs), or other circuits to perform various operations, such as those described above.

[0178] Communication circuitry 640 is coupled to link 560 and also to external circuitry or modules (not shown) of IC 550. Through communication circuitry 640, various modules coupled to link 560 (or generally IC 550) can communicate with external circuitry or modules (not shown) via one or more communication protocols. Examples include Universal Serial Bus (USB), Ethernet, etc. As will be understood by those skilled in the art, other communication protocols may be used in the exemplary embodiments depending on factors such as specifications for a given application.

[0179] As described above, memory circuitry 625 is coupled to link 560. Therefore, memory circuitry 625 can communicate with one or more modules coupled to link 560, such as processor(s) 365, control circuitry 570, I / O circuitry 585, etc. In the illustrated embodiment, memory circuitry 625 includes control circuitry 610, memory array 635, and direct access memory (DMA) 630.

[0180] Control circuit 610 controls or supervises various operations of memory circuit 625. For example, control circuit 619 may provide a mechanism to perform memory read or write operations via link 360. In an exemplary embodiment, control circuit 610 may support various protocols, such as dual data rate (DDR), DDR2, DDR3, etc., as needed.

[0181] In some embodiments, memory read and / or write operations involve using one or more modules in IC 550, such as memory(s) 565. DMA 630 allows for improved memory operation performance in some cases. More specifically, DMA 630 provides a mechanism for performing memory read and write operations directly between the data source or data destination and memory circuitry 625, rather than through modules such as processor(s) 565.

[0182] Memory array 635 may include various memory circuits or modules. In the illustrated embodiment, memory array 635 includes volatile memory 635A and non-volatile (NV) memory 635B. In some embodiments, memory array 635 may include volatile memory 635A. In some embodiments, memory array 635 may include NV memory 635B.

[0183] The NV memory 635B can be used to store information related to the performance or configuration of one or more modules in the IC 550. For example, as described above, the NV memory 635B can store configuration information related to the offset or gain fine-tuning of the DAC(s)(multiple) DAC(s) 200.

[0184] According to exemplary embodiments, DACs possessing advantages such as those described above can prove beneficial in a variety of applications. Examples include applications specifying some or all of the properties listed above, such as monotonicity and relatively high resolution like 12 bits.

[0185] One example application includes a data processing application that processes analog input signals, such as... Figure 13 The circuit arrangement 700 is depicted in the diagram. More specifically, processing circuitry 705 (or generally a digital signal source, such as an MCU, CPU, microprocessor, etc.) provides a digital signal at output 705A. The digital signal is provided to DAC 200. DAC 200 converts the digital signal into an analog signal and provides the analog signal at output 221. The analog signal flows into analog destination 710 (e.g., a transducer, driver, amplifier, etc.). Thus, a digital information source such as processing circuitry 708 can use DAC 200 to control or communicate with analog destination 710.

[0186] In another application, the DAC according to the exemplary embodiment can be used to implement, for example... Figure 14 The control system 750 is shown. The control system 750 includes a process 765, which includes an analog source 755 and an analog destination 710. The analog source 755, such as a sensor or transducer, provides analog signals to an ADC 760. The ADC 760 converts the analog signals into digital signals and provides the digital signals to the control circuitry 760.

[0187] For example, control circuit 760 processes digital signals by filtering, amplifying or scaling, delaying, etc. Control circuit 760 provides a digital output signal and supplies it to DAC 200. DAC 200 converts the digital output signal of control circuit 760 into an analog signal, which is available at output terminal 221. The analog signal at the output terminal of DAC 200 is provided to an analog destination, such as a transducer, driver, motor, or other electromechanical device. Therefore, the combination of modules shown in system 750 implements a feedback control loop.

[0188] Generally, according to various embodiments, applications that use one or more DACs in a feedback loop (e.g., a servo system) can benefit from using a DAC. Figure 15 An example of such a circuit arrangement 780 is illustrated. More specifically, the feedback loop includes a source 785 that provides an output signal to a control circuit 760. In response, the control circuit 760 generates a digital signal and provides the digital signal to the DAC 200.

[0189] DAC 200 converts the digital signal received from control circuitry 760 to generate an analog signal at output 221. The analog output signal of DAC 200 flows into driver 790. Driver 790 (e.g., by providing one or more drive signals) drives source 785, thus completing the loop.

[0190] A more specific example of a feedback loop employing a DAC according to an exemplary embodiment can be a communication system. More specifically, a DAC can be used in the feedback loop to control the intensity of a light source used in an optical communication system. Figure 16 A communication system 800 using this scheme is shown.

[0191] More specifically, the communication system 800 includes a source 805, a medium 830, and a destination 835. The source 805, typically a transmitter (or transceiver), provides information signals to the medium 830, such as an optical fiber or a collection of optical fibers. The medium 830 provides the information to the destination 835, which is typically a receiver (or transceiver) and is usually located at a distance from the source 805.

[0192] In the illustrated embodiment, source 805 includes laser 810, which generates a light beam and provides the beam to beam splitter 815. It should be noted that additional circuitry (not shown) is typically used to modulate the light beam from laser 810 with information (on and off according to a digital bit mode). As described above, beam splitter 815 provides a portion of the input light from laser 810 to medium 830, which then provides the light to destination 835.

[0193] Additionally, beam splitter 815 provides a portion of the input light from laser 810 to controller 820. In other words, controller 820 receives an optical signal indicating the intensity of the beam output from laser 810. In response to the input light from beam splitter 815, controller 820 generates a digital signal, which is ultimately used to drive laser 810.

[0194] More specifically, DAC 200 converts the digital signal from controller 820 into an analog signal, providing this analog signal at output 221. The analog output signal of DAC 200 flows into driver 825. In response, driver 825 provides a bias voltage to laser 810 to cause laser 810 to provide an output beam with the desired intensity.

[0195] As described above, by receiving a signal from beam splitter 815, controller 820 receives a measure of the intensity of the beam provided by laser 810. By comparing the signal from beam splitter 815 with a reference signal, controller 820 provides a digital signal to DAC 200, which ultimately causes driver 825 to increase or decrease the bias voltage provided to laser 810 in order to adjust the intensity of the output light from laser 810.

[0196] Referring to the accompanying drawings, those skilled in the art will notice that the various modules shown primarily depict conceptual functions and signal flows. Actual circuit implementations may or may not include separately identifiable hardware for the various functional modules, and may or may not use the specific circuitry shown. For example, the functions of various modules may be combined into a single circuit module as needed. Furthermore, the functions of a single module may be implemented in several circuit modules as needed. The choice of circuit implementation depends on various factors, such as the specific design and performance specifications for a given implementation. Other modifications and alternative embodiments besides those described herein will be readily apparent to those skilled in the art. Therefore, this specification teaches those skilled in the art how to implement the disclosed concepts and should be construed as illustrative only. As those skilled in the art will understand, the drawings may be drawn to scale or not, where applicable.

[0197] The illustrated and described forms and embodiments should be considered illustrative. Those skilled in the art can make various changes to the shape, size, and arrangement of the parts without departing from the scope of the concepts disclosed herein. For example, those skilled in the art can replace the elements illustrated and described herein with equivalent elements. Furthermore, those skilled in the art can use certain features of the disclosed concepts independently of the use of other features without departing from the scope of the disclosed concepts.

Claims

1. An apparatus for converting a digital signal into an analog signal, comprising: A digital-to-analog converter (DAC) converts a digital input signal into an analog output signal. The DAC includes: A decoder that decodes the digital input signal and provides a first set of control signals and a second set of control signals; The resistor-controlled DAC, or RDAC, responds to the first set of control signals by selectively providing a first voltage and a second voltage to a pair of nodes of resistors interleaved in the resistor network, such that the first voltage and the second voltage vary alternately as the most significant bit increases; and An interpolator, coupled to receive the first voltage and the second voltage in response to the second set of control signals, and to provide a first analog signal.

2. The apparatus of claim 1, wherein the DAC provides the analog output signal having monotonicity.

3. The apparatus of claim 1, wherein the RDAC includes a resistor network coupled to a first switching network, the first switching network including a first set of switches controlled by the first set of control signals.

4. The apparatus of claim 3, wherein the decoder generates the first set of control signals by decoding the more significant bit (MSB) of the digital input signal.

5. The apparatus of claim 4, wherein the decoder comprises a binary decoder that decodes the MSB of the digital input signal to generate the first set of control signals.

6. The apparatus of claim 1, wherein the interpolator includes a second switching network coupled to a plurality of interpolator stages, the second switching network including a second set of switches controlled by the second set of control signals.

7. The apparatus of claim 6, wherein the decoder generates the second set of control signals by decoding the less significant bit (LSB) of the digital input signal.

8. The apparatus of claim 7, wherein the decoder comprises a thermometer decoder that decodes the LSB of the digital input signal to generate the second set of control signals.

9. The apparatus of claim 6, further comprising an output stage coupled to the interpolator to receive the first analog signal and provide the analog output signal.

10. An apparatus for converting a digital signal into an analog signal, comprising: Digital-to-analog converters, or DACs, include: A current source network, which includes multiple current sources to provide multiple currents; A first switching network selectively provides the plurality of currents supplied by the plurality of current sources to a first node or a second node based on the least significant bit; A resistor network coupled to provide an output signal, the resistor network comprising a plurality of resistors; and A second switching network is coupled to the resistor network to selectively couple resistors among the plurality of resistors in the resistor network to the first node and the second node based on the most significant bit.

11. The apparatus of claim 10, wherein the DAC provides the output signal having monotonicity.

12. The apparatus of claim 10, wherein the first switching network comprises a plurality of switch pairs coupled to corresponding current sources in the current source network to selectively provide the current supplied by the plurality of current sources to the first node or the second node.

13. The apparatus of claim 10, wherein the first switching network includes a pair of switches coupled to receive current from a current source in the current source network, the current flowing uniformly in the pair of switches to increase the resolution of the DAC.

14. The apparatus of claim 10, wherein the resistor network is coupled between the output of the DAC and the ground node of the DAC.

15. A method for converting a digital signal into an analog signal, the method comprising: The digital signal is decoded to generate a first set of control signals and a second set of control signals; In response to the first set of control signals, the output voltage of the resistor network is selectively supplied to a pair of nodes of resistors interleaved in the resistor network, and a first voltage and a second voltage are provided using a resistor DAC, i.e., an RDAC, such that the first voltage and the second voltage vary alternately as the most significant bit increases; and In response to the second set of control signals, the first voltage and the second voltage are interpolated to provide a first analog signal.

16. The method of claim 15, wherein the conversion from digital signal to analog signal is performed with monotonicity.

17. The method of claim 15, wherein providing the first voltage and the second voltage using the RDAC comprises, in response to the first set of control signals, selectively coupling resistors in the resistor network to nodes having the first voltage and the second voltage.

18. The method of claim 17, wherein decoding the digital signal further comprises decoding the more significant bit (MSB) of the digital signal to generate the first set of control signals.

19. The method of claim 15, wherein interpolating the first voltage and the second voltage comprises selectively providing the first voltage and the second voltage to a plurality of interpolator stages in response to the second set of control signals.

20. The method of claim 19, wherein decoding the digital signal further comprises decoding the less significant bit (LSB) of the digital signal to generate the second set of control signals.

Images