Nanometer intelligent heat chip, preparation method thereof and application of nanometer intelligent heat chip in wallboard

Abstract

This invention discloses a nano-intelligent heating chip, its preparation method, and its application in wall panels, belonging to the field of polymer composite material technology. The method includes the following steps: mixing thermoplastic polymer materials with nano-conductive fillers to obtain a chip compound; melt-blending the chip compound and extruding it to obtain a chip preform; placing the chip preform in a supercritical fluid environment for saturation treatment and depressurizing it to atmospheric pressure to obtain a composite preform; wherein the saturation treatment pressure is 10-30 MPa, the temperature is 120-180℃, and the depressurization time is 0.1-0.5 s; through an asymmetric temperature field-induced foaming process, a gradient functional partitioning from top to bottom is achieved within a single chip matrix, thereby eliminating the physical interface between heterogeneous materials in traditional multilayer composite processes; during the foaming process, the upper surface of the chip rapidly cools to below the glass transition temperature due to contact with a low-temperature mold.

Description

Technical Field

[0001] This invention relates to the field of polymer composite materials technology, and in particular to a nano-intelligent heating chip, its preparation method, and its application in wall panels. Background Technology

[0002] The nano-intelligent heating chip is a heating element based on nanocomposite electrothermal materials. It forms a three-dimensional conductive network by uniformly dispersing nano-conductive fillers within a polymer matrix. When energized, it generates heat using the Joule effect and provides radiant heating to the indoor space via far-infrared radiation. When applied to building wall panels, this chip is typically integrated with decorative panels, heat-dampening films, and reflective films to form a unified heating wall panel component. Compared to traditional electric heaters or underfloor heating systems, this integrated wall panel heating method offers significant advantages such as not occupying indoor space, uniform heat distribution, and rapid temperature control response, effectively improving living comfort and reducing building energy consumption. Furthermore, the nano-intelligent heating chip's thin and lightweight nature allows for flexible integration with various decorative materials, meeting the comprehensive needs of modern buildings for aesthetics, functionality, and energy efficiency.

[0003] To improve the overall energy efficiency of electrothermal chips in wall panel applications, existing technologies typically employ multi-layer composite structures to achieve thermal management. This involves integrating insulation and reflective layers to passively block heat loss into the deeper layers of the wall. The insulation layer often uses low-thermal-conductivity materials such as foamed polymers or aerogels, while the reflective layer uses metal films with high infrared reflectivity, such as aluminum foil. Simultaneously, a heat spreader is used to eliminate localized hot spots on the chip surface, ensuring uniform heating of the wall panel surface. For example, a nano-oxide semiconductor heating layer can be formed on the surface of a PET film using a sputtering process, combined with an infrared radiation layer to improve far-infrared radiation efficiency. Other approaches involve using nano-intelligent heating chips to replace traditional metal heating elements, supplemented with superconducting thermal coatings to enhance heat dissipation performance. These technologies optimize the performance of the heating materials themselves or improve the heat transfer path from different perspectives.

[0004] However, in practical applications, existing passive insulation materials can only slow down heat conduction through physical barriers, but cannot actively control the direction of heat flow, making it difficult to fundamentally resolve the contradiction between high heating efficiency and low back thermal conductivity. Secondly, in practical applications, electrothermal chips need to be used in conjunction with heat spreaders, reflective films, etc., but the physical bonding between different functional film layers mainly relies on conventional composite processes. During long-term thermal cycling, this heterogeneous material interface is prone to interfacial stress due to the mismatch of thermal expansion coefficients, leading to interlayer delamination, decreased contact performance, and increased interfacial contact thermal resistance, resulting in additional heat loss during interlayer transfer. In addition, existing solutions focus on improving heating efficiency and radiation performance, but lack effective structural design and process methods for how to achieve active and precise control of heat flow within the same chip, making it difficult to achieve synergistic optimization of upward conduction and downward barrier. Summary of the Invention

[0005] This invention overcomes the shortcomings of the prior art and provides a nano-intelligent heating chip, its preparation method, and its application in wall panels.

[0006] To achieve the above objectives, the technical solution adopted by this invention is: a method for preparing a nano-intelligent heating chip, comprising the following steps:

[0007] S1. Mix thermoplastic polymer materials with nano-conductive fillers to obtain chip compound;

[0008] S2. The chip compound is melt-blended and then extruded to obtain a chip blank.

[0009] S3. The chip blank is placed in a supercritical fluid environment for saturation treatment and then depressurized to atmospheric pressure to obtain a composite blank; wherein the saturation treatment pressure is 10-30MPa, the temperature is 120-180℃, and the depressurization time is 0.1-0.5s.

[0010] S4. The composite preform is placed between an upper mold and a lower mold with a temperature difference, pressure is applied, and after holding, it is cooled and shaped to obtain a composite chip; wherein the applied pressure is 0.5-2MPa, the holding time is 30-120s, the upper mold temperature is 30-60℃, and the lower mold temperature is 140-190℃.

[0011] S5. Electrodes and insulating layers are prepared on the surface of the composite chip. After cutting and edge sealing, a nano-intelligent heating chip is obtained.

[0012] In a preferred embodiment of the present invention, in step S1, the thermoplastic polymer material is at least one of polyvinylidene fluoride, polyimide, polycarbonate, polyphenylene sulfide, and polyetheretherketone.

[0013] In a preferred embodiment of the present invention, in step S1, the nano-conductive filler is at least one of single-walled carbon nanotubes, multi-walled carbon nanotubes, reduced graphene oxide, silver nanowires, and antimony-doped tin dioxide nanoparticles.

[0014] In a preferred embodiment of the present invention, in step S1, the mass fraction of the nano-conductive filler in the thermoplastic polymer material is 0.5%-8%.

[0015] In a preferred embodiment of the present invention, in step S2, the melt blending is carried out using a twin-screw extruder at 200-380°C and a rotation speed of 300-500 r / min, and the extrusion molding is performed through a die and the extrusion rate is controlled to be 0.5-2 m / min.

[0016] In a preferred embodiment of the present invention, in step S3, the supercritical fluid is supercritical carbon dioxide or supercritical nitrogen.

[0017] In a preferred embodiment of the present invention, in step S4, the cooling and shaping rate is 20-50℃ / min until the overall temperature of the composite chip drops below 50℃.

[0018] In a preferred embodiment of the present invention, in step S5, the electrode is produced by screen printing, vacuum sputtering or plasma spraying, and the electrode material is conductive silver paste or nano carbon paste with a sheet resistance of 0.1-1Ω / sq; the insulating layer is a polyimide film or a modified epoxy resin coating with a breakdown strength of not less than 20kV / mm.

[0019] Secondly, the present invention provides a nano-intelligent thermal chip, which is prepared by any one of the above-mentioned methods.

[0020] Thirdly, the present invention provides an application of a nano-intelligent heating chip in a wall panel, comprising: a wall panel and a heat equalization layer disposed at the bottom of the wall panel, wherein a reflective film and a heat insulation board are disposed sequentially below the heat equalization layer, and the nano-intelligent heating chip is located between the heat equalization layer and the reflective film.

[0021] This invention addresses the shortcomings of the prior art and has the following beneficial effects:

[0022] (1) Through the asymmetric temperature field induced foaming process, a gradient functional partitioning from top to bottom is realized in a single chip substrate, thereby eliminating the physical interface between heterogeneous materials in the traditional multilayer composite process; during the foaming process, the upper surface of the chip is rapidly cooled to below the glass transition temperature due to contact with the low temperature mold, the movement of polymer molecular chain segments is frozen, inhibiting the nucleation and growth of bubbles in this area, forming a dense and gapless solid structure; the lower surface of the chip maintains high chain segment movement capability due to contact with the high temperature mold, inducing secondary selective growth and merging of bubbles, forming a sparse structure with ultra-high porosity. The loose structure; the central region forms a transitional structure with a bimodal pore size distribution under the action of temperature gradient; this in-situ gradient foaming method enables a natural transition between different functional areas through the entanglement of molecular chains, rather than relying on adhesives for physical bonding; compared with the additional contact thermal resistance caused by the presence of adhesive interfaces and the risk of interlayer delamination caused by the mismatch of thermal expansion coefficients of heterogeneous materials in the mid-lamination composite process, this process allows heat transfer inside the chip to proceed without crossing any heterogeneous interfaces, and the thermal expansion behavior of each area is completely synchronized, effectively improving the structural stability and long-term operational reliability of the chip.

[0023] (2) By constructing a gradient distribution from dense to high-porosity state within the same polymer matrix, active directional control of heat flow along the thickness direction is achieved, which solves the technical contradiction in the prior art where passive insulation materials cannot actively control the heat flow direction and electrothermal conversion materials cannot simultaneously achieve high heating efficiency and low back thermal conductivity. The dense region of the matrix facing the heating surface has a low-defect molecular stacking structure. When phonons propagate in this region, the scattering path is short, which can quickly conduct Joule heat to the surface with low thermal resistance, ensuring efficient upward heat transfer. In the high-porosity region of the matrix facing away from the heating surface, a large number of micron-sized bubble walls form a dense solid-gas interface. When phonons pass through these interfaces, they are scattered multiple times, and the effective phonon transmission path is greatly extended, thereby reducing the thermal conductivity to an extremely low level. This asymmetric distribution of high thermal conductivity on one side and low thermal conductivity on the other side allows the heat to preferentially be transferred upward in the vertical direction when the chip is powered on, while the downward heat flow is effectively blocked by the high-porosity region, realizing the synergistic optimization of the two originally contradictory functions of heating efficiency and back insulation within the same material system.

[0024] (3) The dual-mode pore size distribution constructed in the middle of the matrix is ​​composed of nano-sized small pores and micro-sized large pores, forming a multi-scale synergistic thermal barrier mechanism, which further improves the thermal insulation performance while maintaining the mechanical toughness of the matrix; the pore size of the nano-sized small pores is close to or even smaller than the mean free path of air molecules, which can effectively suppress the gas convection heat conduction inside the pores; the micro-sized large pores reduce the solid phase heat transfer efficiency by increasing the thermal resistance path length of the solid phase skeleton; the two scales of pores are nested in space, so that infrared radiation undergoes multiple reflections and scatterings when passing through this area, which weakens the radiative heat transfer; compared with foamed materials with a single pore size distribution, it can achieve thermal barrier effect in a wider frequency range, thereby ensuring thermal insulation performance while allowing the use of a relatively low overall porosity, avoiding the deterioration of the matrix mechanical properties caused by excessive foaming, so that the chip has good pressure resistance and bending resistance during wall panel installation, transportation and use, and ensures that the chip can maintain stable function and form after integration into the wall panel. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a flowchart of a preferred embodiment of the present invention;

[0027] Figure 2 This is an exploded three-dimensional view of a preferred embodiment of the present invention.

[0028] In the diagram: 1. Wall panel; 2. Heat equalization layer; 3. Nano-intelligent heating chip; 4. Reflective film; 5. Insulation board. Detailed Implementation

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein. Therefore, the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0031] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as limiting the scope of protection of this application. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0032] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0033] Application Overview:

[0034] Traditional multilayer composite processes physically stack independent film layers with different functions. Essentially, this process assigns functions such as heat generation, heat conduction, and heat insulation to different materials, which are then combined through adhesive bonding or lamination. Although this approach has a clear division of labor, the physical interfaces between the functional layers can never be eliminated, and the differences in thermal expansion between heterogeneous materials are difficult to reconcile, which limits the long-term reliability of the overall component.

[0035] The applicant discovered that if a gradient distribution of a dense thermally conductive region and a porous thermally insulating region can be achieved simultaneously within a single polymer matrix, enabling the chip itself to possess anisotropic heat transfer characteristics of upward heat conduction and downward heat insulation, the problem of heterogeneous material interfaces can be fundamentally avoided, while simultaneously achieving active control over the direction of heat flow.

[0036] Considering the application potential of supercritical foaming technology in the field of porous polymer materials, the supercritical foaming process can significantly reduce the thermal conductivity of materials by forming a large number of nano- or micro-sized pores in the polymer matrix, and has been widely used in the field of lightweight thermal insulation materials.

[0037] However, traditional supercritical foaming processes typically pursue the uniformity of the cell structure, that is, to form a porous structure with a uniform pore size distribution throughout the material. While this uniform porous structure can effectively reduce the overall thermal conductivity, it also hinders the efficient conduction of heat to the heating surface, making it unsuitable for electric heating chip scenarios that require both thermal conductivity and thermal insulation functions.

[0038] If spatial differences in temperature fields can be introduced during the foaming process, allowing different parts of the chip to undergo different thermal processes, it is possible to achieve a gradient distribution of the pore structure within the same substrate, thereby endowing the chip with anisotropic heat transfer performance.

[0039] The applicant proposes that, firstly, thermoplastic polymer materials are mixed with nano-conductive fillers, and then melt-blended and extruded to obtain a chip preform. Subsequently, the chip preform is placed in a supercritical fluid environment for high-pressure saturation treatment, and then rapidly depressurized in a very short time to induce high-density nanoscale cell nucleation, resulting in a composite preform. Most importantly, the composite preform is transferred to an asymmetric temperature field molding device with independent temperature control. By controlling the upper mold to a low temperature and the lower mold to a high temperature, and applying mold closing pressure for a certain period of time, the differences in viscoelasticity and gas diffusion rate of the polymer matrix at different temperatures are used to induce the formation of a longitudinally gradient cell structure inside the chip.

[0040] The upper surface of the chip cools rapidly upon contact with a low-temperature mold, inhibiting bubble nucleation and growth, forming a dense, thermally conductive skin layer at the top. The lower surface, in contact with a high-temperature mold, maintains high chain segment mobility, inducing secondary selective growth and merging of bubbles, forming a bottom ultra-high porosity thermal insulation layer. In the central region of the chip, under the influence of a temperature gradient, a dual-mode thermal insulation layer composed of nanoscale micropores and micrometer-scale large pores is formed. After cooling and shaping, an electrode layer and an insulating encapsulation layer are then fabricated on the chip surface, ultimately resulting in an integrated nano-intelligent thermal chip product.

[0041] The chip's dense thermally conductive skin layer is positioned towards the heat-spreading film, while its ultra-high porosity heat-insulating layer is positioned towards the reflective film. In wall panel applications, this achieves a synergistic effect of efficient upward heat conduction and extreme downward heat insulation, effectively solving the technical problems of high interfacial thermal resistance, thermal expansion mismatch, and difficulty in actively controlling heat flow in existing technologies.

[0042] like Figure 1 As shown, a method for fabricating a nano-intelligent heating chip includes the following steps:

[0043] S1. Mix thermoplastic polymer materials with nano-conductive fillers to obtain chip compound;

[0044] S2. The chip compound is melt-blended and then extruded to obtain a chip blank.

[0045] S3. The chip blank is placed in a supercritical fluid environment for saturation treatment and then depressurized to atmospheric pressure to obtain a composite blank; wherein the saturation treatment pressure is 10-30MPa, the temperature is 120-180℃, and the depressurization time is 0.1-0.5s.

[0046] S4. The composite preform is placed between an upper mold and a lower mold with a temperature difference, pressure is applied, and after holding, it is cooled and shaped to obtain a composite chip; wherein the applied pressure is 0.5-2MPa, the holding time is 30-120s, the upper mold temperature is 30-60℃, and the lower mold temperature is 140-190℃.

[0047] S5. Electrodes and insulating layers are prepared on the surface of the composite chip. After cutting and edge sealing, a nano-intelligent heating chip is obtained.

[0048] The core innovation of this invention lies in the following: through an asymmetric temperature field-induced foaming process, a gradient continuous transformation from a dense state to a highly porous state is achieved within the same polymer matrix, fundamentally eliminating the physical interface of heterogeneous material composites, enabling a single material to simultaneously possess efficient thermal conductivity and ultimate thermal insulation performance, and achieving active directional control of heat flow direction.

[0049] Each step will be explained in detail below.

[0050] In step S1, the thermoplastic polymer material serves as the matrix, responsible for providing mechanical support and structural integrity, while also providing a processable polymer basis for the subsequent foaming process; the nano-conductive filler is used to construct a three-dimensional conductive network in the insulating polymer matrix, enabling the chip to generate Joule heat when powered on, thus achieving electrothermal conversion.

[0051] The thermoplastic polymer material is at least one of polyvinylidene fluoride, polyimide, polycarbonate, polyphenylene sulfide, and polyetheretherketone; the nano-conductive filler is at least one of single-walled carbon nanotubes, multi-walled carbon nanotubes, reduced graphene oxide, silver nanowires, and antimony-doped tin dioxide; the mass fraction of the nano-conductive filler in the thermoplastic polymer material is 0.5-8%.

[0052] During the mixing process, the thermoplastic polymer material and the nano-conductive filler are first put into a high-speed mixer for premixing. The nano-conductive filler is initially dispersed in the polymer matrix powder or particles by mechanical stirring, breaking up the agglomerates of the filler itself and laying the foundation for uniform dispersion in the subsequent melt blending stage. According to the hygroscopic characteristics of the selected polymer material, it can be dried before mixing to prevent bubble defects caused by moisture vaporization during high-temperature processing.

[0053] In step S2, the chip compound is melt-blended to ensure that the nano-conductive filler is uniformly dispersed in the polymer matrix, avoiding agglomeration and thus ensuring uniform heating of the chip when it is powered on. This process is completed using the strong shear mixing capability of a twin-screw extruder. By controlling the processing temperature and screw speed, the polymer material is fully melted while avoiding thermal degradation, and the filler is uniformly dispersed under shear action. The melt blending is carried out using a twin-screw extruder at 200-380℃ and a speed of 300-500 r / min.

[0054] The molten blend is extruded through a die into sheet or strip chip preforms with specific thickness and width, providing a uniform initial structure for subsequent supercritical fluid processing and gradient foaming; wherein, the extrusion molding is performed by extruding through a die and the extrusion rate is controlled at 0.5-2 m / min.

[0055] In step S3, the chip preform is placed in a supercritical fluid environment for saturation treatment. Under high pressure and high temperature, the supercritical fluid penetrates into the polymer matrix under high pressure, and the polymer is fully saturated and adsorbed.

[0056] The saturation treatment is carried out at a pressure of 10-30 MPa and a temperature of 120-180℃; the supercritical fluid is supercritical carbon dioxide or supercritical nitrogen.

[0057] Immediately after saturation treatment, the pressure is released to atmospheric pressure. The extremely rapid depressurization rate causes the supercritical fluid dissolved in the polymer to reach a supersaturated state instantly, uniformly inducing extremely high-density nanoscale pore nuclei throughout the entire matrix, providing initial nucleation sites for subsequent gradient foaming; the depressurization time is 0.1-0.5 s.

[0058] Step S4 involves placing the composite preform between an upper mold and a lower mold with a temperature difference, applying pressure, and setting the upper mold to a low temperature to rapidly cool the upper surface of the chip below the glass transition temperature. This freezes the movement of molecular chain segments, thereby forming a dense, gapless solid structure layer on top.

[0059] The lower mold is set to a high temperature, which keeps the lower surface of the chip at a high level of chain segment movement. The nanoscale bubble nuclei in this area undergo secondary selective growth and merging, forming a loose structure with large pore size and extremely high porosity. The upper mold temperature is 30-60℃, and the lower mold temperature is 140-190℃.

[0060] In the thickness direction of the composite preform, a gradually changing temperature gradient is formed from the upper surface to the lower surface. Under the action of the temperature gradient, the degree of cell nucleation and growth in the middle region is between that of the upper and lower surfaces, forming a dual-mode distribution structure composed of nanoscale small cells and micrometer-scale large cells, which has both thermal insulation and mechanical properties.

[0061] Apply mold clamping pressure and maintain it for a certain period of time to ensure close contact between the composite preform and the upper and lower molds, so that the asymmetric temperature field can be effectively conducted to the inside of the chip, while avoiding excessive compression that could damage the cell structure. Then, cool down at a certain rate to freeze and fix the gradient cell structure, preventing structural relaxation or further cell evolution.

[0062] The applied pressure is 0.5-2 MPa, and the holding time is 30-120 s; the cooling and shaping rate is 20-50 ℃ / min, until the overall temperature of the composite chip drops below 50 ℃.

[0063] In step S5, electrodes are fabricated on the surface of the composite chip. The sheet resistance of the electrodes is controlled within a low range to ensure that the current is evenly distributed along the chip surface, thus ensuring uniform heating. The electrode method is screen printing, vacuum sputtering, or plasma spraying. The electrode material is conductive silver paste or nano carbon paste, and its sheet resistance is 0.1-1Ω / sq.

[0064] After the electrode is fabricated, an insulating layer is set on the chip surface. The insulating layer has a high breakdown strength to ensure electrical safety and prevent leakage or breakdown accidents, while also protecting the gradient structure on the chip surface. The insulating layer is a polyimide film or a modified epoxy resin coating with a breakdown strength of not less than 20kV / mm.

[0065] After cutting and edge sealing, the nano-intelligent heating chip is obtained. The chip is cut to the required size and the edge sealing prevents moisture from entering the interior from the edge, ensuring stability and reliability during long-term use.

[0066] To further simplify and make the present invention achieve its objectives and effects, the present invention will be further illustrated in conjunction with the following specific embodiments and comparative examples, but the present invention is not limited to the scope of the embodiments described herein.

[0067] It should be noted that the raw materials used in the examples and comparative examples are described below:

[0068] Polyvinylidene fluoride: 100% purity, 25mm specification, purchased from Dongguan Hongyu Plastic Technology Co., Ltd.

[0069] Multi-walled carbon nanotubes: purity 99%, CAS number 308068-56-6, purchased from Guangzhou Hongwu Materials Technology Co., Ltd.

[0070] Conductive silver paste: content 99.9%, particle size 6-8μm, purchased from Nangong Dinghong Metal Materials Co., Ltd.

[0071] Polyimide film: thickness 0.05-0.18, temperature range -20-280°C, purchased from Kunshan Xieduo Electronic Materials Co., Ltd.

[0072] Example 1:

[0073] S1. Polyvinylidene fluoride and multi-walled carbon nanotubes are mixed at a mass fraction of 3% to obtain chip compound.

[0074] S2. The chip compound is melt-blended at 280°C and 400 r / min using a twin-screw extruder, and then extruded through a die at an extrusion rate of 1.2 m / min to obtain a chip preform.

[0075] S3. The chip blank is placed in a supercritical carbon dioxide environment and saturated at 20 MPa and 150°C. Then, it is rapidly depressurized to atmospheric pressure with a depressurization time of 0.3 s to obtain a composite blank.

[0076] S4. Place the composite preform between an upper mold with an upper mold temperature of 45°C and a lower mold temperature of 165°C, apply a pressure of 1.2MPa, maintain for 80s, and then cool it at a cooling rate of 35°C / min until the overall temperature drops below 50°C to obtain a composite chip.

[0077] S5. Conductive silver paste electrodes with a sheet resistance of 0.5Ω / sq are prepared on the surface of the composite chip by screen printing, and a polyimide film with a breakdown strength of 25kV / mm is coated as an insulating layer. After cutting and edge sealing, a nano-intelligent heating chip is obtained.

[0078] Example 2:

[0079] This embodiment is basically the same as embodiment 1, except that the upper mold temperature is different. Specifically, in step S4, the upper mold temperature is set to 30°C.

[0080] Example 3:

[0081] This embodiment is basically the same as embodiment 1, except that the upper mold temperature is different. Specifically, in step S4, the upper mold temperature is set to 60°C.

[0082] Example 4:

[0083] This embodiment is basically the same as embodiment 1, except that the lower mold temperature is different. Specifically, in step S4, the lower mold temperature is set to 140°C.

[0084] Example 5:

[0085] This embodiment is basically the same as embodiment 1, except that the lower mold temperature is different. Specifically, in step S4, the lower mold temperature is set to 190°C.

[0086] Example 6:

[0087] This embodiment is basically the same as embodiment 1, except that the saturation pressure is different. Specifically, in step S3, the saturation pressure is set to 10 MPa.

[0088] Example 7:

[0089] This embodiment is basically the same as embodiment 1, except that the saturation pressure is different. Specifically, in step S3, the saturation pressure is set to 30 MPa.

[0090] Example 8:

[0091] This embodiment is basically the same as embodiment 1, except that the saturation temperature is different. Specifically, in step S3, the saturation temperature is set to 120°C.

[0092] Example 9:

[0093] This embodiment is basically the same as embodiment 1, except that the saturation temperature is different. Specifically, in step S3, the saturation temperature is set to 180°C.

[0094] Example 10:

[0095] This embodiment is basically the same as embodiment 1, except that the depressurization time is different. Specifically, in step S3, the depressurization time is set to 0.1 s.

[0096] Example 11:

[0097] This embodiment is basically the same as embodiment 1, except that the depressurization time is different. Specifically, in step S3, the depressurization time is set to 0.5 s.

[0098] Comparative Example 1:

[0099] This comparative example is basically the same as Example 1, except that: a traditional multilayer composite process is used, and the specific steps of S1-S4 are as follows:

[0100] S1. Polyvinylidene fluoride and multi-walled carbon nanotubes are mixed at a mass fraction of 3%, and melt-blended at 280°C and 400 r / min using a twin-screw extruder. The mixture is then extruded through a die and the extrusion rate is controlled at 1.2 m / min to obtain a dense chip layer with a thickness of 0.5 mm.

[0101] S2. Take polyvinylidene fluoride resin and prepare a uniform foamed insulation layer by supercritical foaming process: under supercritical carbon dioxide saturation treatment at 20 MPa pressure and 150 ℃ temperature, the depressurization time is 0.3 s, and a uniform porous insulation layer with a thickness of 0.5 mm and a foaming ratio of 5 times is obtained.

[0102] S3. The dense chip layer and the foamed heat insulation layer are laminated together using polyurethane adhesive, and a pressure of 0.5 MPa is applied. The mixture is then cured at 80 °C for 2 h to obtain the composite chip.

[0103] S4. Conductive silver paste electrodes with a sheet resistance of 0.5 Ω / sq are prepared on the dense layer surface of the composite chip by screen printing, and a polyimide film with a breakdown strength of 25 kV / mm is coated as an insulating layer. After cutting and edge sealing, the nano-intelligent heating chip is obtained.

[0104] Comparative Example 2:

[0105] This comparative example is basically the same as Example 1, except that the temperature field direction is reversed. The specific steps of S4 are as follows: the composite blank is placed between the upper mold and the lower mold with the upper mold temperature of 165°C and the lower mold temperature of 45°C, a pressure of 1.2MPa is applied and held for 80 seconds, and then cooled at a cooling rate of 35°C / min until the overall temperature drops below 50°C to obtain the composite chip.

[0106] Comparative Example 3:

[0107] This comparative example is basically the same as Example 1, except that the supercritical foaming process step is omitted, step S3 is omitted, and the specific steps of S4 are as follows: the chip blank is placed between the upper mold and the lower mold with the upper mold temperature of 45°C and the lower mold temperature of 165°C, a pressure of 1.2 MPa is applied and held for 80 s, and then cooled at a cooling rate of 35°C / min until the overall temperature drops below 50°C to obtain the composite chip.

[0108] Comparative Example 4:

[0109] This comparative example is basically the same as Example 1, except that the depressurization time is extended. The specific steps of S3 are as follows: the chip blank is placed in a supercritical carbon dioxide environment and saturated at 20 MPa and 150°C, and then depressurized to atmospheric pressure in a depressurization time of 10 s to obtain a composite blank.

[0110] Comparative Example 5:

[0111] This comparative example is basically the same as Example 1, except that the upper mold temperature is different. The specific steps of S4 are as follows: the composite blank is placed between the upper mold and the lower mold with an upper mold temperature of 20°C and a lower mold temperature of 165°C, a pressure of 1.2MPa is applied and held for 80 seconds, and then cooled at a cooling rate of 35°C / min until the overall temperature drops below 50°C to obtain the composite chip.

[0112] Comparative Example 6:

[0113] This comparative example is basically the same as Example 1, except that the upper mold temperature is different. The specific steps of S4 are as follows: the composite blank is placed between the upper mold and the lower mold with an upper mold temperature of 70°C and a lower mold temperature of 165°C, a pressure of 1.2MPa is applied and held for 80 seconds, and then cooled at a cooling rate of 35°C / min until the overall temperature drops below 50°C to obtain the composite chip.

[0114] Comparative Example 7:

[0115] This comparative example is basically the same as Example 1, except that the lower mold temperature is different. The specific steps of S4 are as follows: the composite blank is placed between the upper mold and the lower mold with an upper mold temperature of 45°C and a lower mold temperature of 130°C, a pressure of 1.2MPa is applied and held for 80 seconds, and then cooled at a cooling rate of 35°C / min until the overall temperature drops below 50°C to obtain the composite chip.

[0116] Comparative Example 8:

[0117] This comparative example is basically the same as Example 1, except that the lower mold temperature is different. The specific steps of S4 are as follows: the composite blank is placed between the upper mold and the lower mold with an upper mold temperature of 45°C and a lower mold temperature of 200°C, a pressure of 1.2MPa is applied and held for 80 seconds, and then cooled at a cooling rate of 35°C / min until the overall temperature drops below 50°C to obtain the composite chip.

[0118] Comparative Example 9:

[0119] This comparative example is basically the same as Example 1, except that the saturation pressure is different. The specific steps of S3 are as follows: the chip blank is placed in a supercritical carbon dioxide environment and saturated at 8 MPa and 150°C. Then, the pressure is rapidly reduced to atmospheric pressure in a depressurization time of 0.3 s to obtain the composite blank.

[0120] Comparative Example 10:

[0121] This comparative example is basically the same as Example 1, except that the saturation pressure is different. The specific steps of S3 are as follows: the chip blank is placed in a supercritical carbon dioxide environment and saturated at 35 MPa and 150°C. Then, the pressure is rapidly reduced to atmospheric pressure in a depressurization time of 0.3 s to obtain the composite blank.

[0122] Comparative Example 11:

[0123] This comparative example is basically the same as Example 1, except that the saturation temperature is different. The specific steps of S3 are as follows: the chip blank is placed in a supercritical carbon dioxide environment and saturated at 20 MPa and 100°C. Then, it is rapidly depressurized to atmospheric pressure in a depressurization time of 0.3 s to obtain a composite blank.

[0124] Comparative Example 12:

[0125] This comparative example is basically the same as Example 1, except that the saturation temperature is different. The specific steps of S3 are as follows: the chip blank is placed in a supercritical carbon dioxide environment and saturated at 20 MPa and 200°C. Then, it is rapidly depressurized to atmospheric pressure in a depressurization time of 0.3 s to obtain the composite blank.

[0126] Comparative Example 13:

[0127] This comparative example is basically the same as Example 1, except that the depressurization time is different. The specific steps of S3 are as follows: the chip blank is placed in a supercritical carbon dioxide environment and saturated at 20 MPa and 150°C. Then, the pressure is rapidly depressurized to atmospheric pressure in a depressurization time of 0.05 s to obtain the composite blank.

[0128] Comparative Example 14:

[0129] This comparative example is basically the same as Example 1, except that the depressurization time is different. The specific steps of S3 are as follows: the chip blank is placed in a supercritical carbon dioxide environment and saturated at 20 MPa and 150°C. Then, the pressure is depressurized to atmospheric pressure in a depressurization time of 1.0 s to obtain the composite blank.

[0130] Performance testing: The nano-thermal chips obtained in Examples 1-11 and Comparative Examples 1-14 were subjected to performance tests in turn, including upward thermal conductivity, downward thermal conductivity, thermal rectification ratio, interfacial contact thermal resistance, resistance change rate after 500 cycles, and measured bottom temperature. The results are shown in Table 1.

[0131] Upward thermal conductivity: First, three nano-thermal chips were randomly selected from the same batch as test samples. Before testing, each chip was placed in an environment with a temperature of 23±2℃ and a relative humidity of 50±5% for no less than 24 hours to eliminate internal stress and moisture absorption effects. The chips were cut into square samples with a side length of 25mm, and a thin layer of thermally conductive silicone grease was uniformly coated on the upper and lower surfaces to reduce contact thermal resistance. A steady-state heat flow thermal conductivity tester based on the ASTM D5470 standard was used. The upper surface of the chip was facing the heat source end and the lower surface was facing the cold source end. The heat source temperature was set to 50℃ and the cold source temperature to 20℃. A contact pressure of 1 MPa was applied. After the heat flow stabilized, the heat flow rate and temperature difference through the sample were recorded. The upward thermal conductivity was calculated according to Fourier's law. Each sample was tested three times and the average value was taken.

[0132] Downward thermal conductivity: Under the same test conditions as upward thermal conductivity, the placement direction of the chip is changed, with the lower surface of the chip facing the heat source and the upper surface facing the cold source. The heat source temperature is set to 50℃ and the cold source temperature to 20℃. A contact pressure of 1 MPa is applied. After the heat flow stabilizes, the heat flow rate and temperature difference through the sample are recorded. The downward thermal conductivity is calculated according to Fourier's law. Each sample is tested three times and the average value is taken.

[0133] Thermal rectification ratio: After testing the upward and downward thermal conductivity, the upward thermal conductivity of the same chip is divided by the downward thermal conductivity; the resulting ratio is the thermal rectification ratio. This ratio characterizes the chip's ability to conduct heat flow in the thickness direction. A larger ratio indicates a more significant difference in the chip's heat flow direction between the forward and reverse directions, and a stronger ability to actively control heat flow. The thermal rectification ratio is calculated independently for each chip, and the final result is the average of three samples.

[0134] Interfacial contact thermal resistance: To simulate the interlayer composite state of the chip in actual wall panel applications, the chip was sequentially stacked with the heat spreader and reflective film according to the actual wall panel structure, and assembled into a sandwich structure sample under a pressure of 0.5 MPa. Using the same steady-state heat flow method equipment as the thermal conductivity test, the overall thermal resistance of the complete multilayer structure was first tested, and then the thermal resistance of the heat spreader, aluminum foil reflective film, and chip itself were tested individually. The thermal resistance of each single layer material was subtracted by the thermal resistance network method, and finally the sum of the contact thermal resistances at the chip-heat spreader interface and the chip-reflective film interface was obtained. During the test, the heat source temperature was maintained at 50℃ and the cold source temperature at 20℃. Data was collected after the heat flow stabilized, and each sample was tested three times and the average value was taken.

[0135] Resistance change rate after 500 cycles: The chip was connected to a DC power supply as in actual use and installed in a simulated wall panel structure. Thermocouples were placed on the chip surface to monitor the temperature. A complete heating-cooling cycle was set as follows: power was applied to heat the chip surface temperature from room temperature to 60±2℃, then power was cut off and it cooled naturally to room temperature, with the entire process completed within 15 minutes. The above process was automatically executed 500 times using a programmable temperature control system. During the entire cycle, the process was paused every 50 cycles to allow the chip to return to room temperature. The resistance between the two electrodes of the chip was measured using the four-probe method, and the change in resistance with the number of cycles was recorded. After 500 cycles, the rate of change of the last measured resistance value relative to the initial resistance value was used as the evaluation index. The resistance change rate was calculated as (resistance after cycle - initial resistance) / initial resistance × 100%. The lower the resistance change rate, the better the electrothermal performance and the stability of the internal structure of the chip.

[0136] Bottom Measured Temperature: After completing 500 cycles of aging testing, the chip was assembled according to the actual wall panel structure, from bottom to top: insulation board, reflective film, chip, heat spreader layer, and decorative layer. The entire structure was placed in a constant temperature chamber, with the ambient temperature controlled at 20±1℃. T-type thermocouples with a diameter of 0.1mm were embedded between the upper surface of the chip and the heat spreader layer, and between the lower surface of the chip and the reflective film. An additional thermocouple was added at the interface between the lower surface and the reflective film to monitor the bottom temperature. A rated voltage was applied to the chip using a DC power supply to stabilize its heating, maintaining the temperature at the interface between the upper surface of the chip and the heat spreader layer at 60±2℃. After the temperature field stabilized, the temperature value at the bottom interface was continuously recorded for at least 30 minutes, and the average value was taken as the bottom measured temperature. The lower this temperature, the less heat is conducted downwards by the chip, indicating a better back-to-back thermal barrier effect.

[0137] Table 1: Performance test results of the nano-intelligent heating chips in Examples 1-11 and Comparative Examples 1-14

[0138] Group Upward thermal conductivity (W / (m·K)) Downward thermal conductivity (W / (m·K)) thermal rectification ratio <![CDATA[Interface thermal contact resistance (m 2 ·K / W)]]> Rate of change in resistance after 500 cycles (%) Measured temperature at the bottom (°C) Example 1 1.45 0.042 34.52 0.01 1.2 31.0 Example 2 1.48 0.043 34.41 0.01 1.5 31.2 Example 3 1.32 0.041 32.19 0.01 1.3 30.8 Example 4 1.44 0.058 24.82 0.01 1.1 33.5 Example 5 1.41 0.038 37.10 0.01 2.8 29.5 Example 6 1.46 0.055 26.54 0.01 1.2 33.1 Example 7 1.35 0.039 34.61 0.01 2.5 29.8 Example 8 1.45 0.052 27.88 0.01 1.1 32.6 Example 9 1.38 0.040 34.50 0.01 2.4 30.1 Example 10 1.43 0.040 35.75 0.01 1.4 30.2 Example 11 1.46 0.048 30.41 0.01 1.1 32.0 Comparative Example 1 1.12 0.075 14.93 4.85 18.5 36.5 Comparative Example 2 0.05 1.42 0.03 0.01 1.8 58.5 Comparative Example 3 1.48 1.45 1.02 0.00 0.8 59.2 Comparative Example 4 1.47 1.38 1.06 0.00 0.9 58.0 Comparative Example 5 1.49 0.044 33.86 0.01 8.5 31.5 Comparative Example 6 0.65 0.042 15.47 0.01 1.5 31.1 Comparative Example 7 1.45 0.28 5.17 0.01 1.2 45.5 Comparative Example 8 1.35 0.15 9.00 0.01 12.4 39.8 Comparative Example 9 1.46 0.22 6.63 0.01 1.1 43.2 Comparative Example 10 1.25 0.038 32.89 0.01 15.6 29.6 Comparative Example 11 1.47 0.25 5.88 0.01 1.0 44.5 Comparative Example 12 1.20 0.045 26.66 0.01 14.2 31.8 Comparative Example 13 1.42 0.041 34.63 0.01 7.8 30.5 Comparative Example 14 1.46 0.35 4.17 0.01 1.0 48.5

[0139] A comparison of Example 1 and Comparative Example 1 reveals that: Comparative Example 1 employed a traditional multilayer composite process, laminating a dense chip layer with a separately prepared uniformly foamed insulation layer using polyurethane adhesive. This heterogeneous material composite method introduces an adhesive interface between the dense layer and the insulation layer. This interface is composed of molecules with different chemical structures, resulting in weak intermolecular forces and an inability to form molecular chain entanglement. When the chip operates under long-term thermal cycling, the mismatch in thermal expansion coefficients between the dense layer and the foamed layer leads to periodic shear stress at the interface, causing creep or even breakage of the adhesive molecular chains and the formation of microcracks at the interface. These microcracks not only increase the interfacial contact thermal resistance, but also contribute to the degradation of the thermal resistance in Example 1 (0.01 μm). 2 K / W increased significantly to 4.85 m 2 The K / W ratio hinders heat conduction and disrupts the stability of the electrode connection, causing the resistance to rise continuously during cycling, with a resistance change rate as high as 18.5% after 500 cycles. At the same time, although the uniform foam layer has a certain heat insulation effect, it cannot actively control the direction of heat flow like the gradient structure in Example 1, resulting in a still high measured temperature at the bottom, reaching 36.5℃.

[0140] A comparison of Example 1 and Comparative Example 2 reveals that Comparative Example 2 reversed the mold temperature settings of the asymmetric temperature field, with the upper mold temperature at 165°C and the lower mold temperature at 45°C. This change completely overturned the growth environment of the cells. In Example 1, the low temperature of 45°C at the top inhibited cell growth, forming a dense layer; the high temperature of 165°C at the bottom promoted cell growth, forming a heat-insulating layer. In Comparative Example 2, the high temperature of 165°C at the top caused intense movement of the molecular chains on the upper surface, allowing the cell nuclei to grow fully and form a porous structure; the low temperature of 45°C at the bottom froze the molecular chains, inhibiting cell growth and forming a dense layer. This resulted in the top of the chip, which should have been highly thermally conductive, becoming a loose, porous, low-thermal-conductivity layer, while the bottom, which should have been heat-insulating, became a high-thermal-conductivity, dense layer. Therefore, the upward thermal conductivity plummeted from 1.45 W / (m·K) in Example 1 to 0.05 W / (m·K), while the downward thermal conductivity increased to 1.42 W / (m·K). With a heat rectification ratio of only 0.03 and a heat flow completely reversed, the heat flow cannot meet the basic functional requirements of upward heating and downward blocking in wall panel applications.

[0141] A comparison of Example 1 and Comparative Example 3 reveals that Comparative Example 3 omitted the supercritical foaming process. This omission means that the chip blank did not have a pre-formed high-density nanoscale pore core before entering the asymmetric temperature field. Without nucleation points, even with a temperature gradient, a gradient-distributed pore structure could not be induced. Under the temperature difference between the upper and lower molds, the chip only underwent melting, compaction, and cooling processes, exhibiting a uniformly dense state. Therefore, its upward thermal conductivity is 1.48 W / (m·K), and its downward thermal conductivity is 1.45 W / (m·K), similar values. The thermal rectification ratio is close to 1, only 1.02, lacking any heat flow guidance function. Although its dense structure results in an extremely low resistivity change rate of only 0.8%, as an electrothermal chip, its almost indiscriminate upward and downward thermal conductivity leads to a large amount of heat being conducted downwards to the wall, with the measured temperature at the bottom reaching as high as 59.2℃, resulting in severe energy waste and completely contradicting the original design intent.

[0142] A comparison of Example 1 and Comparative Example 4 shows that Comparative Example 4 extended the depressurization time to 10s. In the supercritical foaming process, an extremely fast depressurization rate is key to achieving high-density, uniform nucleation. When the depressurization time is too long, the pressure drop rate slows down, and the dissolved gas has enough time to escape from the matrix through molecular diffusion or grow slowly at a few low-energy defect points, rather than forming a large number of uniform bubble nuclei throughout the matrix instantly. This leads to a significant reduction in nucleation density, with uneven bubble size and a small number of bubbles. In the subsequent asymmetric temperature field processing, due to the lack of a sufficient number of uniformly distributed nucleation points as a foundation, even with a temperature gradient, it is impossible to construct an ideal high-porosity gradient thermal insulation layer. The chip as a whole tends to have a uniform, low-pore or microporous structure, with a thermal rectification ratio of only 1.06, losing the advantages of the gradient structure. The upward thermal conductivity and downward thermal conductivity are 1.47 W / (m·K) and 1.38 W / (m·K), respectively, which are almost indistinguishable.

[0143] A comparison of Examples 1 / 2-3 with Comparative Examples 5-6 shows that the temperature of the upper mold is the key to controlling the formation of the dense heat-conducting layer at the top. In Examples 1, 2, and 3, the upper mold temperatures were 45°C, 30°C, and 60°C, respectively, all within the preferred range of 30-60°C. Within this temperature range, after the chip's upper surface contacts the low-temperature mold, it rapidly cools to below the glass transition temperature of the polymer material. The movement of molecular chain segments is effectively frozen, and the high-density nanoscale bubble cores formed by rapid decompression in the early stage cannot grow, thus forming a dense, gapless solid structure layer. The phonon scattering path in this region is short, and the upward thermal conductivity can be maintained at a high level of 1.32-1.48 W / (m·K). In Comparative Example 5, the upper mold temperature was lowered to 20°C. The excessively low temperature led to an excessively fast cooling rate, resulting in an excessively thick, brittle, and dense layer forming on the top of the chip and generating huge internal stress. During thermal cycling, the release of internal stress triggered microcracks, causing the resistivity change rate to rise to 8.5% after 500 cycles. In Comparative Example 6, the upper mold temperature was raised to 70°C. At this point, the ability of molecular chain segment movement was enhanced, which could not suppress bubble growth. A porous structure was formed on the top, and the upward thermal conductivity plummeted to 0.65. W / (m·K) indicates a significant decrease in thermal rectification ratio, and the chip loses its efficient upward heat conduction function.

[0144] A comparison of Examples 1 / 4-5 with Comparative Examples 7-8 reveals that the lower mold temperature is crucial in determining the cell structure of the bottom insulation layer. In Examples 1, 4, and 5, the lower mold temperatures were 165°C, 140°C, and 190°C, respectively, all within the preferred range of 140-190°C. At these temperatures, the molecular chain segments on the lower surface of the chip exhibit strong mobility, allowing the previously formed nanoscale cell nuclei to acquire sufficient energy for secondary selective growth and merging, resulting in a loose structure with ultra-high porosity. Numerous micron-sized cell walls constitute a dense solid-gas interface, significantly extending the effective propagation path after multiple phonon scattering, and achieving a downward thermal conductivity as low as 0.038-0.058 W / (m·K). In Comparative Example 7, the lower mold temperature was reduced to 130°C. Insufficient temperature resulted in a still high polymer matrix viscosity, weak cell growth driving force, and an inability to form a high-porosity structure, leading to a downward thermal conductivity of only 0.28. W / (m·K), the actual measured temperature at the bottom was as high as 45.5℃; in Comparative Example 8, the temperature of the lower mold was raised to 200℃. The excessively high temperature caused the viscosity of the matrix to be too low, the cells to grow excessively and merge or even collapse, which destroyed the continuity of the matrix. As a result, the resistivity change rate soared to 12.4% after 500 cycles, and the thermal insulation performance also decreased.

[0145] A comparison of Examples 1 / 6-7 and Comparative Examples 9-10 shows that saturation pressure directly affects the solubility and nucleation density of supercritical fluids. In Examples 1, 6, and 7, the saturation pressures were 20 MPa, 10 MPa, and 30 MPa, respectively, all within the preferred range of 10-30 MPa. Under these pressures, the supercritical fluid reached full saturation in the polymer matrix. After rapid depressurization, extremely high-density nanoscale cell nuclei were uniformly induced throughout the matrix, providing a uniform nucleation basis for subsequent gradient foaming. In Comparative Example 9, the saturation pressure was reduced to 8 MPa. Insufficient pressure resulted in the fluid dissolution amount not reaching saturation, low nucleation density, weak foundation for subsequent gradient foaming, and inability to form a high-density cell wall network at the bottom. The downward thermal conductivity was as high as 0.22 W / (m·K), and the measured temperature at the bottom was 43.2℃. In Comparative Example 10, the saturation pressure was increased to 35 MPa. Excessive pressure may cause conductive filler agglomeration or irreversible orientation of polymer chains. At the same time, excessively high nucleation density may easily cause uncontrollable cell merging during subsequent high-temperature processing, forming stress concentration points. This caused the resistivity change rate to rise to 15.6% after 500 cycles, seriously affecting the long-term reliability of the chip.

[0146] A comparison of Examples 1 / 8-9 with Comparative Examples 11-12 shows that the saturation temperature determines the polymer chain mobility and the uniformity of fluid dissolution. The saturation temperatures in Examples 1, 8, and 9 are 150°C, 120°C, and 180°C, respectively, all within the preferred range of 120-180°C. At this temperature, the polymer molecular chains have moderate mobility, which can provide sufficient free volume for the supercritical fluid to achieve uniform dissolution, and prevent fluid escape due to excessive chain segment movement, thus ensuring uniform nucleation and high density. In Comparative Example 11, the saturation temperature was reduced to 100℃. At this time, the polymer is in the glassy or early viscous flow state, with extremely weak chain segment mobility, small free volume, low fluid dissolution and extremely uneven distribution, resulting in nucleation defects, discontinuous insulation layer, and a downward thermal conductivity of 0.25 W / (m·K). In Comparative Example 12, the saturation temperature was increased to 200℃. The excessively high temperature caused thermal degradation of the molecular chains. The degradation products reduced the melt strength, and the uncontrolled growth of bubbles formed uneven macropores. After cooling, a large number of defects and stresses were generated, causing the resistivity change rate to rise to 14.2% after 500 cycles.

[0147] A comparison of Examples 1 / 10-11 and Comparative Examples 13-14 shows that the depressurization time directly determines the uniformity and density of cell nucleation. In Examples 1, 10, and 11, the depressurization times were 0.3 s, 0.1 s, and 0.5 s, respectively, all within the preferred range of 0.1-0.5 s. The extremely rapid depressurization rate caused the dissolved supercritical fluid to instantly reach a supersaturated state, uniformly inducing extremely high-density nanoscale pore nuclei within the matrix, laying a uniform nucleation foundation for subsequent gradient growth. In Comparative Example 13, the depressurization time was shortened to 0.05 s. Although the nucleation density was higher, the excessively rapid pressure release rate triggered violent pressure waves inside the chip, impacting the molecular chain entanglement network and causing microscopic damage. This damage gradually expanded into microcracks during thermal cycling, resulting in a resistivity change rate of 7.8% after 500 cycles. In Comparative Example 14, the depressurization time was extended to 1.0 s. The depressurization rate slowed down, and the nucleation process changed from instantaneous uniform nucleation to slow diffusion-controlled nucleation. Gas molecules diffused, causing at least a few defect points to grow slowly, forming a small number of large-sized pores. These pores were unevenly distributed and could not form a dense thermal insulation network, resulting in a downward thermal conductivity increase to 0.35. W / (m·K), with the actual measured temperature at the bottom reaching as high as 48.5℃.

[0148] like Figure 2 As shown, the application of a nano-intelligent heating chip in a wall panel includes a wall panel 1, a heat equalization layer 2, a nano-intelligent heating chip 3, a reflective film 4, and an insulation board 5 arranged sequentially from top to bottom. The layers are tightly bonded together by physical stacking, without relying on adhesives for bonding.

[0149] Specifically, the nano-intelligent heating chip 3 serves as the core heating element. Its top dense thermally conductive skin layer is in direct contact with the heat equalization layer 2 above it. The heat equalization layer is made of a highly thermally conductive flexible material to eliminate local temperature differences on the chip surface, so that heat can be evenly transferred to the wall panel 1. The wall panel faces the indoor space and achieves heating through heat conduction and far-infrared radiation.

[0150] Furthermore, the ultra-high porosity heat-insulating layer at the bottom of the nano-intelligent heating chip 3 is adjacent to the reflective film 4 below. The reflective film reflects a small amount of infrared heat radiated downwards upwards, further reducing heat loss. The bottom insulation board 5 is in contact with the building wall, forming a final barrier against residual heat flow.

[0151] Based on the preferred embodiments of the present invention described above, those skilled in the art can make various changes and modifications without departing from the inventive concept. The technical scope of this invention is not limited to the contents of the specification, but must be determined according to the scope of the claims.

Claims

1. A method for fabricating a nano-intelligent heating chip, characterized in that, Includes the following steps: S1. Mix thermoplastic polymer materials with nano-conductive fillers to obtain chip compound; S2. The chip compound is melt-blended and then extruded to obtain a chip blank. S3. The chip blank is placed in a supercritical fluid environment for saturation treatment and then depressurized to atmospheric pressure to obtain a composite blank; wherein the saturation treatment pressure is 10-30MPa, the temperature is 120-180℃, and the depressurization time is 0.1-0.5s. S4. The composite preform is placed between an upper mold and a lower mold with a temperature difference, pressure is applied, and after holding, it is cooled and shaped to obtain a composite chip; wherein the applied pressure is 0.5-2MPa, the holding time is 30-120s, the upper mold temperature is 30-60℃, and the lower mold temperature is 140-190℃. S5. Electrodes and insulating layers are prepared on the surface of the composite chip. After cutting and edge sealing, a nano-intelligent heating chip is obtained.

2. The method for preparing a nano-intelligent heating chip according to claim 1, characterized in that: In step S1, the thermoplastic polymer material is at least one of polyvinylidene fluoride, polyimide, polycarbonate, polyphenylene sulfide, and polyetheretherketone.

3. The method for preparing a nano-intelligent heating chip according to claim 1, characterized in that: In step S1, the nano-conductive filler is at least one of single-walled carbon nanotubes, multi-walled carbon nanotubes, reduced graphene oxide, silver nanowires, and antimony-doped tin dioxide nanoparticles.

4. The method for preparing a nano-intelligent heating chip according to claim 1, characterized in that: In step S1, the mass fraction of the nano-conductive filler in the thermoplastic polymer material is 0.5-8%.

5. The method for preparing a nano-intelligent heating chip according to claim 1, characterized in that: In step S2, the melt blending is carried out using a twin-screw extruder at 200-380℃ and a rotation speed of 300-500 r / min, and the extrusion molding is performed through a die and the extrusion rate is controlled at 0.5-2 m / min.

6. The method for preparing a nano-intelligent heating chip according to claim 1, characterized in that: In step S3, the supercritical fluid is supercritical carbon dioxide or supercritical nitrogen.

7. The method for preparing a nano-intelligent heating chip according to claim 1, characterized in that: In step S4, the cooling and shaping rate is 20-50℃ / min until the overall temperature of the composite chip drops below 50℃.

8. The method for preparing a nano-intelligent heating chip according to claim 1, characterized in that: In step S5, the electrode is produced by screen printing, vacuum sputtering, or plasma spraying, and the electrode material is conductive silver paste or nano carbon paste with a sheet resistance of 0.1-1 Ω / sq. The insulating layer is a polyimide film or a modified epoxy resin coating with a breakdown strength of not less than 20 kV / mm.

9. A nano-intelligent heating chip, characterized in that, It is prepared by any one of claims 1-8.

10. An application of a nano-intelligent heating chip according to claim 9 in a wall panel, characterized in that, include: The wall panel has a heat equalization layer at the bottom of the wall panel, and a reflective film and a heat insulation board are arranged in sequence below the heat equalization layer. The nano intelligent heating chip is located between the heat equalization layer and the reflective film.

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