A circuit board stack alignment structure of an interconnection process per layer and a manufacturing method thereof

Abstract

This invention proposes a PCB stacking alignment structure and its fabrication method for each layer of interconnect process. The PCB stacking alignment structure for each layer of interconnect process includes: a CORE layer with internal drill holes and multiple internal targets, and an inner layer with targets; a BU layer, abutting the outer layer of the CORE layer, including at least one stacking module comprising target holes, multiple PCBs, and multiple laser holes; wherein, the PCB farthest from the CORE layer in the stacking module is the alignment layer, and the alignment layer is provided with targets and multiple internal targets; the target holes of the stacking module penetrate the alignment board and all PCBs between the alignment board and the CORE layer, the number of laser holes equals the number of PCBs, and the number of dielectric layers of the PCBs penetrated by the laser holes are all different; PCBs not serving as alignment layers are provided with laser rings for LDI device positioning. According to the technical solution of this embodiment, the internal targets and targets located on the same layer are used as alignment references, thereby reducing positional tolerances and positional deviations.

Description

Technical Field

[0001] This invention relates to the field of per-layer interconnect technology, and particularly to a per-layer interconnect circuit board stacking alignment structure and its fabrication method. Background Technology

[0002] With the widespread adoption of smartphones and other portable devices, there is a growing demand for thinner, lighter, and higher-density electronic components. Everylayer interconnection (ELIC) technology, which uses stacked copper-filled micro-blind vias to achieve interconnection between any two layers, solves the high interconnection density requirement under space constraints and has become key to the development of high-density interconnect (HDI) printed circuit boards (PCBs). The 1.6T optical module market is poised for explosive growth due to AI computing power demands and technological innovation. 1.6T optical modules are primarily used in ELIC stacked structures using the Modified Semi-Additive Process (mSAP) method, making technology roadmaps and production capacity layout crucial for competitive advantage.

[0003] Because the annual ring of ELIC is relatively small, directly using through-hole alignment on the outer layer would lead to batch failures and scrap. Therefore, direct through-hole alignment on the outer layer of the PCB is not feasible. Current technology employs a single-sided stacking alignment method. This involves positioning the inner target of adjacent layers, laser-etching the prepreg above the inner target, and using Laser Direct Imaging (LDI) technology to position the single-layer laser ring of adjacent layers. Dimensions are then measured across the entire finished product to select qualified products. However, this method only considers single-sided alignment between multiple circuit boards, ensuring alignment only between adjacent boards. Multiple single-sided stackings result in uncertain positional accuracy on both sides of the HDI, making alignment uncontrollable, significantly increasing the risk of positional deviation, affecting the critical dimensions of the final product, and impacting production efficiency. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a circuit board stacking alignment structure for each layer interconnection process and its manufacturing method, using inner targets and targets located on the same layer as alignment references, thereby reducing the positional tolerance and positional deviation of the circuit board stacking alignment structure and improving production efficiency.

[0005] In a first aspect, embodiments of the present invention provide a circuit board stacking alignment structure for each interconnect process layer, comprising: The CORE layer has an internal borehole and multiple internal targets, and the inner layer of the CORE layer has a target. The BU layer abuts against the outer layer of the CORE layer. The BU layer includes at least one stacking module. The stacking module includes target holes, multiple circuit boards, and multiple laser holes. The circuit boards include a dielectric layer that can be laser-etched. Among them, the circuit board that is farthest from the CORE layer in the stacking module is the alignment layer. The alignment layer is provided with the target and multiple inner targets. The horizontal coordinates of all the inner targets and all the targets are different. Wherein, for any one of the stacking modules, the target hole passes through the alignment plate of the stacking module and all the circuit boards between the alignment plate and the CORE layer, the number of laser holes is equal to the number of circuit boards, the number of dielectric layers through which the laser holes pass are all different, and the laser holes pass through at least one dielectric layer. Wherein, the bottom end of the laser hole of the stacking module is the inner target closest to the inner layer of the stacking module, and the inner layer of the stacking module is the side of the stacking module closest to the CORE layer; Wherein, when the circuit board is not the alignment layer, the circuit board is provided with a laser ring, which is used for positioning of the LDI device.

[0006] According to some embodiments of the present invention, when the stacking module abuts against the CORE layer, the number of circuit boards of the stacking module is less than or equal to the number of inner targets of the CORE layer, the bottom end of the target hole of the stacking module is the target of the CORE layer, and the bottom end of the laser hole of the stacking module is the inner target of the CORE layer.

[0007] According to some embodiments of the present invention, when the outer layer of the alignment layer does not abut against the circuit board, the alignment layer does not have the inner target and the target.

[0008] According to some embodiments of the present invention, when the circuit board stacking alignment structure is a per-layer interconnect process based on the semi-additive method, the circuit board stacking alignment structure is a four-partition design, and the alignment targets are set based on the semi-additive method. Alternatively, when the circuit board stack alignment structure is based on a negative film process for each layer of interconnection, the circuit board alignment structure does not have a partition design, and the alignment target is set based on a high-density interconnect board.

[0009] According to some embodiments of the present invention, the alignment layer is provided with a partitioning target, which is used to partition all the inner targets and the target.

[0010] Secondly, embodiments of the present invention also provide a method for fabricating a circuit board stacking alignment structure for each interconnect process, comprising: Obtain the CORE layer, align it based on the internal drill holes of the CORE layer, and laser-drill blind vias into the CORE layer to obtain the board's internal vias. The CORE layer is aligned based on the internal drilling, and multiple internal targets are fabricated in the CORE layer, with targets fabricated in the inner layer of the CORE layer. For any circuit board that is not an alignment layer, the circuit board is placed on the outer surface of the circuit board stack alignment structure. The inner target closest to the circuit board is used as the alignment reference. The circuit board and all dielectric layers between the circuit board and the inner target are laser-etched to obtain laser holes. The circuit board is laser-etched based on the inner target at the bottom of the laser holes to obtain a laser ring. The bottom end of the laser holes is the inner target. For any outer layer that abuts against the alignment layer of the circuit board, the alignment layer and all the dielectric layers between the alignment layer and the inner target are laser-etched based on the laser ring to obtain the laser hole. The alignment layer is then pressed onto the outer layer of the circuit board stack alignment structure. Using the inner target at the bottom of the laser hole as the alignment reference, the alignment layer and all the dielectric layers between the alignment layer and the CORE layer are removed using an X-RAY device to obtain the target hole. Using the target hole as the alignment reference, multiple inner targets and targets are fabricated on the circuit board using an LDI device, wherein the target hole and the target are located at the same horizontal coordinate.

[0011] The method for fabricating the PCB stacking alignment structure of each interconnect process according to embodiments of the present invention has at least the following beneficial effects: for all PCBs in the same stacking module, the inner target and the target of the same layer are used as alignment references; for adjacent PCBs, alignment is performed by laser rings and inner targets, and the cross-layer inner target is positioned by laser holes to reduce the increase in error caused by the increase in stacking times. Combined with direct positioning of single-layer target holes, double-sided alignment is performed while completing single-sided alignment; multiple PCBs are divided into at least one stacking module, thereby reducing the positional deviation of the stacking module by reducing the number of stacking times, improving product yield and production efficiency.

[0012] According to some embodiments of the present invention, the LDI device includes a surface CCD light source; Laser-etched holes are obtained by laser etching the circuit board and all dielectric layers between the circuit board and the inner target, and the process further includes: The laser ring closest to the circuit board is located using the surface CCD light source, and the center of the laser ring is determined based on the multi-point integration of the laser ring. When the circuit board is the inner layer of the stacked module, positioning based on the laser ring is not required. Using the center of the laser ring as a alignment reference, the entire dielectric layer above the inner target is laser-etched to obtain the laser hole.

[0013] According to some embodiments of the present invention, the BU layer includes a first stacking module abutting the CORE layer, the number of circuit boards in the first stacking module is two, the first stacking module includes a first circuit board and a second circuit board, and the CORE layer includes a first inner target and a second inner target. After fabricating the target on the inner layer of the CORE layer, the process further includes: The first circuit board is placed on the outer surface of the CORE layer, and the first circuit board is laser-etched to obtain the laser hole, wherein the bottom of the first laser hole is the first inner target; Position the first inner target, and laser-etch the first circuit board to obtain the laser ring; The laser ring is positioned using the LDI device, the second circuit board is placed on the outer surface of the CORE layer, the dielectric layer of the second circuit board and the dielectric layer of the first circuit board are laser-etched to obtain the second laser hole, and the second inner target is positioned at the bottom of the second laser hole. The second circuit board is pressed onto the outer surface of the first circuit board. The target of the CORE layer is located by X-RAY equipment. The dielectric layer of the first circuit board and the dielectric layer of the second circuit board located on the horizontal coordinate of the target are removed to obtain the target hole. When the number of stacked modules in the BU layer is greater than or equal to two, the target hole of the second circuit board is located by the LDI device, and multiple inner targets and targets are made on the second circuit board, wherein the horizontal coordinates of all the inner targets and targets of the circuit board stacking alignment structure are different.

[0014] According to some embodiments of the present invention, the BU layer includes a first stacking module and a second stacking module, the second stacking module abutting against the outer surface of the first stacking module, the number of circuit boards in the second stacking module is two, the second stacking module includes a third circuit board and a fourth circuit board, and all the inner targets of the alignment layer of the first stacking module include a third inner target and a fourth inner target. After fabricating multiple inner targets and targets on the second circuit board, the process further includes: The third circuit board is placed on the outer surface of the first stacked module, and the dielectric layer of the third circuit board is laser-etched to obtain a third laser hole, wherein the bottom of the third laser hole is the third inner target; Position the third inner target, and laser-etch the third circuit board to obtain a laser ring; Positioned using the LDI device, the fourth circuit board is placed on the outer surface of the third circuit board, and the dielectric layer of the third circuit board and the dielectric layer of the fourth circuit board are laser-etched to obtain a fourth laser hole, wherein the bottom of the fourth laser hole is the fourth inner target; The fourth circuit board is pressed onto the outer surface of the third circuit board. The target of the second circuit board is located by the X-RAY device. All the dielectric layers located on the horizontal coordinate of the target are removed to obtain the target hole, wherein the horizontal coordinate of the target hole is the same as the horizontal coordinate of the target of the second circuit board. When the number of stacked modules in the BU layer is greater than two, the target hole of the fourth circuit board is located by the LDI device, and multiple inner targets and targets are made on the fourth circuit board. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the board stacking alignment structure for each interconnect process provided in one embodiment of the present invention; Figure 2 This is a flowchart of a method for fabricating a circuit board stacking alignment structure for each layer interconnect process, provided in another embodiment of the present invention. Detailed Implementation

[0016] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0017] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0018] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0019] In the description of this invention, unless otherwise explicitly defined, terms such as "set up," "install," and "connect" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0020] The embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0021] like Figure 1 As shown, Figure 1 This is a schematic diagram of a packaging carrier board for an embedded high-efficiency circuit board stacking alignment structure 100 provided in one embodiment of the present invention. The circuit board stacking alignment structure for each interconnect process provided in this embodiment includes: The CORE layer has internal boreholes and multiple internal targets 10, and the inner layer of the CORE layer has targets 20. The BU layer is adjacent to the outer layer of the CORE layer. The BU layer includes at least one stacking module. The stacking module includes target holes 30, multiple circuit boards and multiple laser holes 40. The circuit boards include a dielectric layer that can be laser-etched. Among them, the circuit board that is furthest from the CORE layer in the stacked module is the alignment layer. The alignment layer is equipped with a target 20 and multiple inner targets 10. The horizontal coordinates of all inner targets 10 and all targets 20 are different. In this context, for any stacked module, the target hole 30 passes through the alignment board of the stacked module and all circuit boards between the alignment board and the CORE layer. The number of laser holes 40 is equal to the number of circuit boards. The number of dielectric layers through which the laser holes 40 pass is different. The laser holes 40 pass through at least one dielectric layer. Among them, the bottom end of the laser hole 40 of the stacked module is the inner target 10 closest to the inner layer of the stacked module, and the inner layer of the stacked module is the side of the stacked module that is close to the CORE layer. When the circuit board is not an alignment layer, it is equipped with a laser ring, which is used for positioning of LDI equipment.

[0022] It should be noted that this application provides a PCB stacking alignment structure based on every-layer interconnection (ELIC) technology, which can effectively solve the problem of two-sided alignment accuracy in printed circuit boards (PCBs) using every-layer interconnection (ELIC) technology. This application reduces stacking errors by creating laser holes 40 for positioning and gripping the cross-layer inner target 10, and further ensures two-sided positional accuracy by using laser direct imaging (LDI) equipment to position and grip single-layer target holes 30, thus realizing the stacking design of the ELIC PCB and meeting the customer's two-sided positional tolerance requirements. Depending on the product characteristics (Annual Ring, etc.), the two-sided positional accuracy requirements (such as ±50um / ±25um, etc.) can be met through different combinations of the above alignment methods without affecting the overall quality.

[0023] It should be noted that the side of the circuit board closer to the CORE layer is the inner layer of the circuit board, and the side of the circuit board farther from the CORE layer is the outer layer of the circuit board; the side of the stacking module closer to the CORE layer is the inner layer of the stacking module, and the side of the stacking module farther from the CORE layer is the outer layer of the stacking module.

[0024] It should be noted that the medium layer is a prepreg (PP).

[0025] It should be noted that this application adopts cross-layer target recognition technology. Any stacked module of this application uses the inner target 10 and target 20 located on the same layer as the alignment reference. This application uses LAS laser to burn through at least one dielectric layer to directly identify the inner target 10 located on the CORE layer or the alignment layer. The spatial coordinate relationship of the target 20 is extracted through the bottom of the target hole 30, so as to realize the inner target 10 and target 20 on the same layer for multi-layer laser and graphic alignment reference.

[0026] It should be noted that the circuit boards located in the middle part of the stacked module, that is, the circuit boards that are not the outer or inner layers of the stacked module, are all equipped with laser rings. The laser rings are used to provide alignment references for the circuit boards that abut against the outer layer of the circuit board. That is, when making laser holes 40 on the circuit board, the inner target 10 at the bottom of the laser hole 40 of the previous layer circuit board and the laser ring of the circuit board are used as alignment references to ensure the positional accuracy of the two sides of the circuit boards.

[0027] In existing technology, an inner target 10 is set in the CORE layer. Each time a circuit board is placed, a dielectric layer is laser-etched to obtain a laser hole 40. The bottom of the laser hole 40 is the inner target 10. The inner target 10 is then fabricated on the circuit board, providing an alignment reference for adjacent circuit boards placed on the outer layer. For example, when there are 6 circuit boards in the BU layer, a total of 6 inner targets 10 and 6 laser holes 40 are set, each with a depth of one dielectric layer. During fabrication, 6 single-sided alignments are required. However, this alignment method only considers the alignment between adjacent circuit boards. Multiple single-sided stackings lead to amplification of minute positional tolerances. That is, the larger the number of circuit boards in the BU layer, the greater the positional deviation, significantly increasing the risk of positional deviation and affecting the positional accuracy of critical dimensions in the final product. This results in uncontrollable yield and impacts production efficiency.

[0028] It should be noted that the advantage of cross-layer target recognition technology lies in reducing the number of stacking operations required. For example, in this application, by using single-sided and double-sided positional alignment, when the BU layer includes a total of 6 circuit boards, all circuit boards are allocated into three stacking modules. Each stacking module contains 2 circuit boards, meaning the circuit board stacking alignment structure only requires 3 alignment operations. This significantly reduces the number of single-sided alignment operations, thereby reducing positional tolerance and positional deviation, and improving production efficiency. Furthermore, during the fabrication of the stacking modules, double-sided positional tolerance is considered alongside single-sided positional tolerance. All circuit boards in the stacking module use the inner target 10 and target 20 of the same layer as alignment references, thus achieving controllable alignment accuracy of the circuit board stacking alignment structure. Using laser equipment to position the cross-layer inner target 10 reduces the error caused by the increased number of stacking operations, and combining this with LDI equipment to position the target holes 30 of the stacking module ensures double-sided positional tolerance. This achieves stacking of ELIC PCBs with small positional deviations, reducing positional tolerance and cumulatively reducing errors by more than 60%, thereby improving the yield and production efficiency of the final product. The circuit board stacking alignment structure of this application is applicable to any layer interconnect structure, high-order HDI structure, and does not require a preset intermediate layer reference.

[0029] In another embodiment, when the stacked module abuts against the CORE layer, the number of circuit boards of the stacked module is less than or equal to the number of inner targets 10 of the CORE layer, the bottom end of the target hole 30 of the stacked module is the target 20 of the CORE layer, and the bottom end of the laser hole 40 of the stacked module is the inner target 10 of the CORE layer.

[0030] It should be noted that the inner target 10 of the CORE layer is used to provide a positioning basis for each layer of the circuit board of the stacked module that is attached to the CORE layer. In order to ensure that each layer of the circuit board of the stacked module has an alignment reference located on the CORE layer, the number of inner targets 10 set in the CORE layer is greater than or equal to the number of circuit boards of the stacked module.

[0031] It should be noted that for the circuit boards located on the outer layer of the stacked module, the depth of the target hole 30 is the same as the depth of its laser hole 40, and both penetrate the dielectric layer of all the circuit boards of the stacked module.

[0032] In another embodiment, when the outer layer of the alignment layer does not abut against the circuit board, the alignment layer does not have an inner target 10 and a target 20.

[0033] It should be noted that the inner target 10 and the target 20 in the alignment layer are both used to provide alignment references for the stacked modules that abut against the alignment layer. When the outer layer of the alignment layer does not abut against the circuit board, that is, when the stacked module to which the alignment layer belongs is the outer layer of the circuit board stacking alignment structure, there is no need to set an alignment reference for the stacked modules located on the outer layer, that is, there is no need for the inner target 10 and the target 20.

[0034] In another embodiment, when the circuit board stack alignment structure is a per-layer interconnect process based on the semi-additive method, the circuit board stack alignment structure is a four-partition design, and the alignment targets are set based on the semi-additive method. Alternatively, when the PCB stack alignment structure is based on the interconnect process of each layer of negative film process, the PCB alignment structure is not partitioned, and the alignment targets are set based on high-density interconnect boards.

[0035] It should be noted that the settings are based on the product characteristics of the PCB stacking alignment structure. When the PCB stacking alignment structure is based on the Modified Semi-Additive Process (mSAP), ELIC is designed in four zones, and the alignment target is designed according to MSAP.

[0036] When the PCB stack alignment structure is based on the tenting process, ELIC is designed without partitions, and the alignment target is designed according to HDI.

[0037] In another embodiment, a partitioned target is provided in the positioning layer, which is used to partition all inner targets 10 and targets 20.

[0038] It should be noted that the circuit board stacking alignment structure is partitioned. The partitions are designed according to the size of the Annual Ring, and the laser or pattern is partitioned. The target hole 30 is partitioned according to the laser or pattern partition. At present, the maximum number of partitions is four. The pattern includes inner target 10, target 20 and laser ring.

[0039] It should be noted that the circuit board stacking alignment structure is fabricated by lamination; when making the alignment layer of target hole 30, the alignment layer of target hole 30 is laminated to create partition targets, and the pattern is partitioned for alignment. Among them, the inner layer marking of target hole 30 is designed on a non-cross-layer layer.

[0040] Additionally, refer to Figure 2, Figure 2 The flowchart illustrates a method for fabricating a board stacking alignment structure for each interconnect process layer. The method for fabricating a board stacking alignment structure for each interconnect process layer provided in this embodiment includes, but is not limited to, the following steps: S10, Obtain the CORE layer, perform alignment based on the internal drilling of the CORE layer, and laser-drill blind vias in the CORE layer to obtain the board's internal vias; S20, based on internal drilling, aligns the CORE layer, fabricates multiple internal targets in the CORE layer, and fabricates targets in the inner layer of the CORE layer; S30, For any circuit board that is not an alignment layer, place the circuit board on the outer surface of the circuit board stack alignment structure, take the inner target closest to the circuit board as the alignment reference, and obtain laser holes for the laser-cut circuit board and all dielectric layers between the circuit board and the inner target. Based on the inner target laser-cut circuit board at the bottom of the laser hole, obtain a laser ring, wherein the bottom end of the laser hole is the inner target. S40: For any outer layer that abuts against the alignment layer of the circuit board, laser holes are obtained by laser lithography of the alignment layer and all dielectric layers between the alignment layer and the inner target based on the laser ring. The alignment layer is pressed onto the outer layer of the circuit board stacked alignment structure. Using the inner target at the bottom of the laser hole as the alignment reference, the alignment layer and all dielectric layers between the alignment layer and the CORE layer are removed by X-RAY equipment to obtain target holes. Using the target holes as the alignment reference, multiple inner targets and targets are fabricated on the circuit board by LDI equipment. The target holes and targets are located on the same horizontal coordinate.

[0041] It should be noted that this application employs a combination of three alignment methods: laser alignment, graphic alignment, and LDI (Laser Displacement) positioning, thereby reducing positional deviations in the PCB stacking alignment structure. For the laser alignment method, laser positioning is used to grip the target across layers, spanning two or three layers, the number of which is determined based on product characteristics. For the graphic alignment method, an LDI device is used to position the laser ring within the stacking area. For non-layer-crossing alignment, a single-sided laser ring is gripped to ensure single-sided accuracy; the LDI device is also used to grip the target hole. For layer-crossing alignment, the target hole is gripped to ensure consistent positional accuracy on both sides. For the LDI combined alignment method, different laser layer crossings and the number of times the LDI device grips the target hole are designed are based on the alignment accuracy requirements.

[0042] It should be noted that LDI combined alignment enables both laser ring positioning and single-layer target positioning. For laser ring positioning, for conventional laser inner target layers, LDI uses a surface CCD light source to identify the laser-made hole ring and uses the laser ring for positioning. For single-layer target hole positioning, for cross-layer laser inner layers, the LDI device directly reads the target hole in that layer and brings the two sides back to alignment. The advantage of LDI combined alignment is that, through the combination of two alignment designs, the positional deviation can be controlled within ±50 micrometers (μm), while the positional deviation of existing technologies is greater than 50 μm, thus reducing the positional deviation compared to existing technologies. This achieves automatic alignment correction and ensures that the alignment is not uncontrollable. LDI combined alignment is suitable for any layer interconnect structure and / or high-order HDI structure, without the need for a preset intermediate layer reference.

[0043] It should be noted that the manufacturing method of this application combines "laser cross-layer inner target", "LDI equipment positioning laser ring", and "LDI equipment positioning gripping target hole", which can be applied to other high-end HDI products, improving design freedom and alignment accuracy. In ELIC structure PCBs, this manufacturing method modifies the conventional single-sided stacking method of "laser gripping inner layer target" combined with "graphic gripping laser ring". Through the two-sided integrated stacking method combining multiple alignment methods, the alignment accuracy of the product changes from "uncontrollable" to "controllable", thereby reducing positional deviations, improving product yield, and increasing production efficiency.

[0044] In another embodiment, the LDI device includes a surface CCD light source; in step S30, laser holes are formed in the laser ray circuit board and all dielectric layers between the circuit board and the inner target, including but not limited to the following steps: S31, the laser ring closest to the circuit board is located by the surface CCD light source, and the center of the laser ring is determined based on the multi-point integration of the laser ring. When the circuit board is the inner layer of the stacked module, there is no need to locate based on the laser ring. S32, with the center of the laser ring as the alignment reference, the entire dielectric layer above the inner laser target is used to obtain laser holes.

[0045] It should be noted that when alignment is performed using an LDI (Laser Diode) device, the surface CCD light source of the LDI device uses multiple integrated centers to grasp the target point; the LDI device positions and grasps the laser ring obtained by laser engraving on the current layer of the circuit board, thereby ensuring the alignment of the inner and outer layer patterns of the circuit board stack alignment structure; in addition, an inner target can be created by laser engraving across layers to achieve the positioning and grasping of the inner target, ensuring that the laser reference of the multi-layer circuit board is located on the same layer of the inner target. When the target hole of the cross-layer is positioned and grasped by the LDI device, it is aligned with the inner layer of the laser engraving, thereby further ensuring the alignment of the two sides; in addition, the X-ray beam of the X-ray device can penetrate the inner layer to drill the target hole, thereby ensuring the consistency of the pattern target hole alignment and the laser ring alignment.

[0046] In another embodiment, the BU layer includes a first stacking module abutting against the CORE layer. The first stacking module has two circuit boards, including a first circuit board and a second circuit board. The CORE layer includes a first inner target and a second inner target. After step S20, the following steps are also included, but are not limited to: S21, the first circuit board is placed on the outer surface of the CORE layer, and the first circuit board is laser-cut to obtain laser holes, wherein the bottom of the first laser hole is the first inner target; S22, locate the first inner target, and laser the first circuit board to obtain the laser ring; S23, the laser ring is positioned by the LDI device, the second circuit board is placed on the outer surface of the CORE layer, the dielectric layer of the second circuit board and the dielectric layer of the first circuit board are lasered to obtain the second laser hole, and the second inner target is positioned at the bottom of the second laser hole. S24, the second circuit board is pressed onto the outer surface of the first circuit board, the target of the CORE layer is located by X-RAY equipment, and the dielectric layer of the first circuit board and the dielectric layer of the second circuit board located on the horizontal coordinate of the target are removed to obtain the target hole; S25, when the number of stacked modules in the BU layer is greater than or equal to two, the target holes of the second circuit board are located by the LDI device, and multiple inner targets and targets are made on the second circuit board. Among them, the horizontal coordinates of all inner targets and targets in the circuit board stacking alignment structure are different.

[0047] It should be noted that the number of laser holes in the stacked module is the same as the number of circuit boards in the stacked module, and the depth of each laser hole is different, that is, the number of dielectric layers lasered by each laser hole is different. Therefore, a laser hole is obtained for each circuit board placed, and then a laser ring is made based on the laser hole.

[0048] In another embodiment, the BU layer includes a first stacking module and a second stacking module, the second stacking module abutting the outer surface of the first stacking module, the second stacking module having two circuit boards, the second stacking module including a third circuit board and a fourth circuit board, and all inner targets of the alignment layer of the first stacking module including the third inner target and the fourth inner target; after step S25, the following steps are also included, but are not limited to: S251, the third circuit board is placed on the outer surface of the first stacked module, and the dielectric layer of the third circuit board is laser-etched to obtain a third laser hole, wherein the bottom of the third laser hole is a third inner target. S252, locate the third inner target, and laser the third circuit board to obtain the laser ring; S253, using LDI equipment for positioning, the fourth circuit board is placed on the outer surface of the third circuit board, and the dielectric layer of the third circuit board and the dielectric layer of the fourth circuit board are laser-etched to obtain the fourth laser hole, wherein the bottom of the fourth laser hole is the fourth inner target; S254, the fourth circuit board is pressed onto the outer surface of the third circuit board, the target of the second circuit board is located by X-RAY equipment, and all dielectric layers located on the horizontal coordinate of the target are removed to obtain the target hole, wherein the horizontal coordinate of the target hole is the same as the horizontal coordinate of the target of the second circuit board. S255, when the number of stacked modules in the BU layer is greater than two, the target hole of the fourth circuit board is located by LDI equipment, and multiple inner targets and targets are made on the fourth circuit board.

[0049] To better understand the technical solution of this application, refer to Figure 1 The following specific embodiments are provided, wherein the number of circuit boards in the BU layer is six: For the CORE layer and the laser L7 layer, the internal drilling is used for positioning and alignment, and blind vias are made on the L7 layer. For the graphic L7 layer, the internal drilling is used for positioning and alignment, and two sets of internal targets and a 2.0mm target are made on the L7 layer. For the BU layer, laser-etch the L6 layer, laser-burn through one layer of PP, grasp the inner target of the L7 layer for positioning, and laser-etch out the laser ring for the LDI device; the LDI device is aligned with the L6 layer and grasps the laser ring of the L6 layer; laser-etch the L5 layer, burn through two layers of PP (i.e., the dielectric layer of the L6 layer and the dielectric layer of the L5 layer), grasp the inner target of the L7 layer for positioning; press the L5 layer, X-ray through the target of the L7 layer, and drill a 2.0mm target hole based on the target; the LDI device is aligned with the L5 layer, grasp the 2.0mm target hole for alignment, and make two sets of inner targets and a 2.0mm target for the L5 layer. Laser-etch L4 layer, grasp the inner target of L5 layer for positioning, and laser-etch a laser ring for LDI equipment on L4 layer; align the LDI equipment with L4 layer and grasp the laser ring of L4 layer; laser-etch L3 layer, burn through two layers of PP (i.e., the dielectric layer of L3 layer and the dielectric layer of L4 layer), and grasp the inner target of L5 layer for positioning; press L3 layer, see through L5 layer target with X-ray, and punch 2.0mm target hole; align the LDI equipment with L3 layer, grasp the 2.0mm target hole of L3 layer for alignment, and make two sets of inner targets and 2.0mm target on L3 layer. Laser L2 layer, grasp the inner target of L3 layer for positioning, burn out the laser ring for LDI equipment in L3 layer; LDI equipment is aligned with L2 layer, grasp the laser ring of L2 layer; laser L1 layer, burn through two PP layers (i.e., the dielectric layers of L1 and L2 layers), grasp the inner target of L3 layer for positioning, press L1 layer, X-ray see through the target of L3 layer, punch out a 2.0mm target hole, LDI equipment is aligned with L1 layer, grasp the 2.0mm target hole for alignment.

[0050] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.

[0051] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0052] The above provides a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A circuit board stacking alignment structure for each layer of interconnection technology, characterized in that, include: The CORE layer has an internal borehole and multiple internal targets, and the inner layer of the CORE layer has a target. The BU layer abuts against the outer layer of the CORE layer. The BU layer includes at least one stacking module. The stacking module includes target holes, multiple circuit boards, and multiple laser holes. The circuit boards include a dielectric layer that can be laser-etched. Among them, the circuit board that is farthest from the CORE layer in the stacking module is the alignment layer. The alignment layer is provided with the target and multiple inner targets. The horizontal coordinates of all the inner targets and all the targets are different. Wherein, for any one of the stacking modules, the target hole passes through the alignment plate of the stacking module and all the circuit boards between the alignment plate and the CORE layer, the number of laser holes is equal to the number of circuit boards, the number of dielectric layers through which the laser holes pass are all different, and the laser holes pass through at least one dielectric layer. Wherein, the bottom end of the laser hole of the stacking module is the inner target closest to the inner layer of the stacking module, and the inner layer of the stacking module is the side of the stacking module closest to the CORE layer; Wherein, when the circuit board is not the alignment layer, the circuit board is provided with a laser ring, which is used for positioning of the LDI device.

2. The circuit board stacking alignment structure for each layer interconnection process according to claim 1, characterized in that, When the stacked module abuts against the CORE layer, the number of circuit boards in the stacked module is less than or equal to the number of inner targets in the CORE layer, the bottom end of the target hole of the stacked module is the target of the CORE layer, and the bottom end of the laser hole of the stacked module is the inner target of the CORE layer.

3. The circuit board stacking alignment structure for each layer interconnection process according to claim 1, characterized in that, When the outer layer of the alignment layer does not abut against the circuit board, the alignment layer does not have the inner target and the target.

4. The circuit board stacking alignment structure for each layer interconnection process according to claim 1, characterized in that, When the circuit board stacking alignment structure is based on the semi-additive interconnection process for each layer, the circuit board stacking alignment structure is a four-partition design, and the alignment targets are set based on the semi-additive method. Alternatively, when the circuit board stack alignment structure is based on a negative film process for each layer of interconnection, the circuit board alignment structure does not have a partition design, and the alignment target is set based on a high-density interconnect board.

5. The circuit board stacking alignment structure for each layer interconnection process according to claim 1, characterized in that, The alignment layer is provided with partitioned targets, which are used to partition all the inner targets and the target objects.

6. A method for fabricating a circuit board stacking alignment structure with interconnect processes at each layer, characterized in that, include: Obtain the CORE layer, align it based on the internal drill holes of the CORE layer, and laser-drill blind vias into the CORE layer to obtain the board's internal vias. The CORE layer is aligned based on the internal drilling, and multiple internal targets are fabricated in the CORE layer, with targets fabricated in the inner layer of the CORE layer. For any circuit board that is not an alignment layer, the circuit board is placed on the outer surface of the circuit board stack alignment structure. The inner target closest to the circuit board is used as the alignment reference. The circuit board and all dielectric layers between the circuit board and the inner target are laser-etched to obtain laser holes. The circuit board is laser-etched based on the inner target at the bottom of the laser holes to obtain a laser ring. The bottom end of the laser holes is the inner target. For any outer layer that abuts against the alignment layer of the circuit board, the alignment layer and all the dielectric layers between the alignment layer and the inner target are laser-etched based on the laser ring to obtain the laser hole. The alignment layer is then pressed onto the outer layer of the circuit board stack alignment structure. Using the inner target at the bottom of the laser hole as the alignment reference, the alignment layer and all the dielectric layers between the alignment layer and the CORE layer are removed using an X-RAY device to obtain the target hole. Using the target hole as the alignment reference, multiple inner targets and targets are fabricated on the circuit board using an LDI device, wherein the target hole and the target are located at the same horizontal coordinate.

7. The method for fabricating a circuit board stacking alignment structure for each layer interconnection process according to claim 6, characterized in that, The LDI device includes a surface CCD light source; Laser-etched holes are obtained by laser etching the circuit board and all dielectric layers between the circuit board and the inner target, and the process further includes: The laser ring closest to the circuit board is located using the surface CCD light source, and the center of the laser ring is determined based on the multi-point integration of the laser ring. When the circuit board is the inner layer of the stacked module, positioning based on the laser ring is not required. Using the center of the laser ring as a alignment reference, the entire dielectric layer above the inner target is laser-etched to obtain the laser hole.

8. The method for fabricating a circuit board stacking alignment structure for each layer interconnection process according to claim 6, characterized in that, The BU layer includes a first stacking module, which abuts against the CORE layer. The number of circuit boards in the first stacking module is two, and the first stacking module includes a first circuit board and a second circuit board. The CORE layer includes a first inner target and a second inner target. After fabricating the target on the inner layer of the CORE layer, the process further includes: The first circuit board is placed on the outer surface of the CORE layer, and the first circuit board is laser-etched to obtain the laser hole, wherein the bottom of the first laser hole is the first inner target; Position the first inner target, and laser-etch the first circuit board to obtain the laser ring; The laser ring is positioned using the LDI device, the second circuit board is placed on the outer surface of the CORE layer, the dielectric layer of the second circuit board and the dielectric layer of the first circuit board are laser-etched to obtain the second laser hole, and the second inner target is positioned at the bottom of the second laser hole. The second circuit board is pressed onto the outer surface of the first circuit board. The target of the CORE layer is located by X-RAY equipment. The dielectric layer of the first circuit board and the dielectric layer of the second circuit board located on the horizontal coordinate of the target are removed to obtain the target hole. When the number of stacked modules in the BU layer is greater than or equal to two, the target hole of the second circuit board is located by the LDI device, and multiple inner targets and targets are made on the second circuit board, wherein the horizontal coordinates of all the inner targets and targets of the circuit board stacking alignment structure are different.

9. A method for fabricating a circuit board stacking alignment structure for each layer interconnection process according to claim 8, characterized in that, The BU layer includes a first stacking module and a second stacking module. The second stacking module abuts against the outer surface of the first stacking module. The second stacking module has two circuit boards. The second stacking module includes a third circuit board and a fourth circuit board. All the inner targets of the alignment layer of the first stacking module include a third inner target and a fourth inner target. After fabricating multiple inner targets and targets on the second circuit board, the process further includes: The third circuit board is placed on the outer surface of the first stacked module, and the dielectric layer of the third circuit board is laser-etched to obtain a third laser hole, wherein the bottom of the third laser hole is the third inner target; Position the third inner target, and laser-etch the third circuit board to obtain a laser ring; Positioned using the LDI device, the fourth circuit board is placed on the outer surface of the third circuit board, and the dielectric layer of the third circuit board and the dielectric layer of the fourth circuit board are laser-etched to obtain a fourth laser hole, wherein the bottom of the fourth laser hole is the fourth inner target; The fourth circuit board is pressed onto the outer surface of the third circuit board. The target of the second circuit board is located by the X-RAY device. All the dielectric layers located on the horizontal coordinate of the target are removed to obtain the target hole, wherein the horizontal coordinate of the target hole is the same as the horizontal coordinate of the target of the second circuit board. When the number of stacked modules in the BU layer is greater than two, the target hole of the fourth circuit board is located by the LDI device, and multiple inner targets and targets are made on the fourth circuit board.

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