Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a substrate and at least one stack. The at least one stack is stacked on the substrate along a first direction, wherein the at least one stack includes a first stack, and the first stack includes a plurality of insulating layers and a plurality of conductive layers, an insulating pillar, a conductive connection structure, a dielectric layer, and a via layer. The insulating layers and the conductive layers are alternately stacked on the substrate along the first direction. The insulating pillar extends through the insulating layers and the conductive layers along the first direction. The conductive connection structure passes through the insulating layers and the conductive layers and surrounds the insulating pillar. The dielectric layer surrounds the conductive connection structure. The via layer surrounds the dielectric layer and is electrically connected to the conductive connection structure.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same. More particularly, this invention relates to a memory device and a method for manufacturing the same. Background Technology

[0002] Dynamic random access memory (DRAM) is a common type of semiconductor memory. Traditional DRAM has a fairly simple structure, requiring one transistor (1T) and one capacitor (1C) to process each bit of data, i.e., 1T1C DRAM. However, with the increasing number of modern applications, the size limitations of 1T1C DRAM are no longer sufficient. Therefore, to provide memory devices with higher storage capacity, the structure of traditional DRAM needs further improvement. Summary of the Invention

[0003] This invention addresses improvements to dynamic random access memory, particularly the formation of three-dimensional dynamic random access memory, to overcome size limitations.

[0004] According to some embodiments, the present invention provides a semiconductor device. The semiconductor device includes a substrate and at least one stack. The at least one stack is stacked on the substrate along a first direction, wherein the at least one stack includes a first stack, and the first stack includes a plurality of insulating layers and a plurality of conductive layers, an insulating pillar, a conductive connection structure, a dielectric layer, and a channel layer. The insulating layers and conductive layers are alternately stacked on the substrate along the first direction. The insulating pillar extends along the first direction, passing through the insulating layers and conductive layers. The conductive connection structure passes through the insulating layers and conductive layers and surrounds the insulating pillar. The dielectric layer surrounds the conductive connection structure. The channel layer surrounds the dielectric layer and is electrically connected to the conductive connection structure.

[0005] According to some embodiments, the present invention provides a method for fabricating a semiconductor device. The method includes providing a substrate and forming at least one stack stacked on the substrate along a first direction. The at least one stack includes a first stack, and the first stack includes a plurality of insulating layers and a plurality of conductive layers, an insulating pillar, a conductive connection structure, a dielectric layer, and a channel layer. The insulating layers and conductive layers are alternately stacked on the substrate along the first direction. The insulating pillar extends along the first direction, passing through the insulating layers and conductive layers. The conductive connection structure passes through the insulating layers and conductive layers and surrounds the insulating pillar. The dielectric layer surrounds the conductive connection structure. The channel layer surrounds the dielectric layer and is electrically connected to the conductive connection structure.

[0006] To provide a better understanding of the above and other aspects of the present invention, specific embodiments are described below in conjunction with the accompanying drawings: Attached Figure Description

[0007] Figure 1A A cross-sectional view of a semiconductor device according to an embodiment of the present invention is shown;

[0008] Figure 1B Draw Figure 1A A three-dimensional view of a semiconductor device;

[0009] Figure 1C Draw Figure 1A A partial top view of a semiconductor device;

[0010] Figure 1D A perspective view of a semiconductor device according to another embodiment of the present invention is shown; and

[0011] Figures 2A to 2J Illustration as follows Figure 1A and Figure 1B A flowchart illustrating the fabrication method of the semiconductor device.

[0012] Explanation of reference numerals in the attached figures:

[0013] 10,10': Semiconductor device

[0014] 102: Base Plate

[0015] 102s: Upper surface

[0016] 100A: First stack

[0017] 100A': First stacked structure

[0018] 100B: Second stack

[0019] 100B': Second stacked structure

[0020] 112A, 112B: First insulating layer

[0021] 114A, 114B: First conductive layer

[0022] 116A, 116B: Second insulating layer

[0023] 118A, 118B: Second conductive layer

[0024] 118A', 118B': First sacrificial layer

[0025] 120A, 120B: Third insulation layer

[0026] 122A, 122B: Third conductive layer

[0027] 122A', 122B': Second sacrificial layer

[0028] 124A, 124B: Fourth insulating layer

[0029] 130A, 130B: Channel Layer

[0030] 132A, 132B: Dielectric layers

[0031] 134, 134': Conductive connection structure

[0032] 142: Insulating Post

[0033] 144: Air gap

[0034] 152: First Covering Layer

[0035] 154: Second Covering Layer

[0036] 1241A, 1241B: First insulation section

[0037] 1242A, 1242B: Second insulation section

[0038] 1341: First connection structure

[0039] 1342: Second connection structure

[0040] 1343: Third connection structure

[0041] CE: Wire

[0042] CL: Conductive layer

[0043] CP: Plug

[0044] CT: Contact Structure

[0045] CRP: Current Path

[0046] D1: First Direction

[0047] D2: Second Direction

[0048] D3: Third direction

[0049] GOX: Gate dielectric layer

[0050] IL: Insulating layer

[0051] OP1: Opening

[0052] OP2: Lateral opening

[0053] HL1: First lateral hole

[0054] HL2: Second lateral hole

[0055] HL3: Vertical hole

[0056] SE1: First side

[0057] SE2: Second side Detailed Implementation

[0058] The following description, in conjunction with the accompanying drawings, details various embodiments. The descriptions and drawings are provided for illustrative purposes only and are not intended to be limiting. For clarity, some elements and / or symbols may be omitted in some drawings. Furthermore, elements in the drawings may not be drawn to scale. It is anticipated that elements and features in one embodiment can be advantageously incorporated into another embodiment without further repetition.

[0059] Figure 1A A cross-sectional view of a semiconductor device 10 according to an embodiment of the present invention is shown. Figure 1B Draw Figure 1A A three-dimensional view of the semiconductor device 10. Figure 1C Draw Figure 1A A partial top view of the semiconductor device 10, for example, a partial top view corresponding to the conductive connection structure 134.

[0060] Please refer to the following at the same time Figures 1A-1B This invention provides a semiconductor device 10, which includes a substrate 102 and at least one stack stacked on the substrate 102 along a first direction D1. In this embodiment, the number of at least one stack is two, namely a first stack 100A and a second stack 100B, with the second stack 100B stacked on top of the first stack 100A. However, this invention is not limited to this, and the number of at least one stack can be one, three, or more than three. The first direction D1 is, for example, parallel to the normal direction of the upper surface 102s of the substrate 102, but this invention is not limited to this.

[0061] A first stack 100A and a second stack 100B are sequentially stacked on the upper surface 102s of the base plate 102 along a first direction D1. The first stack 100A includes a plurality of insulating layers IL and a plurality of conductive layers CL alternately stacked on the upper surface 102s of the base plate 102 along the first direction D1. For example, the insulating layer IL includes a first insulating layer 112A, a second insulating layer 116A, a third insulating layer 120A, and a fourth insulating layer 124A; the conductive layer CL includes a first conductive layer 114A, a second conductive layer 118A, and a third conductive layer 122A. In other words, the first insulating layer 112A, the first conductive layer 114A, the second insulating layer 116A, the second conductive layer 118A, the third insulating layer 120A, the third conductive layer 122A, and the fourth insulating layer 124A are sequentially stacked on the upper surface 102s of the base plate 102 along the first direction D1. The fourth insulating layer 124A is, for example, a double-layer structure, which may include a first insulating portion 1241A and a second insulating portion 1242A. The second insulating portion 1242A is stacked on the first insulating portion 1241A.

[0062] According to some embodiments, the material of the insulating layer IL may include an insulating material, such as an oxide, a nitride, or other suitable insulating material. According to one embodiment, the materials of the first insulating layer 112A, the second insulating layer 116A, the third insulating layer 120A, and the fourth insulating layer 124A include oxides. For example, the first insulating layer 112A is hafnium oxide (HfO). X ) or aluminum oxide (AlO X The material of the first insulating portion 1241A in the second insulating layer 116A, the third insulating layer 120A, and the fourth insulating layer 124A may include a low-density oxide, such as low-density silicon oxide. The material of the second insulating portion 1242A in the fourth insulating layer 124A may include a high-density oxide, such as high-density silicon oxide or tetraethoxysilane (TEOS) oxide. The porosity of low-density oxides is higher than that of high-density oxides. Compared to low-density silicon oxide, high-density silicon oxide has a denser structure, generally fewer impurities, and a higher mass per unit volume. Due to the more compact atomic packing of high-density silicon oxide, it can have better mechanical and electrical properties. Conversely, compared to high-density silicon oxide, low-density silicon oxide generally has a more porous structure, a lower mass per unit volume, and usually contains more impurities or voids. The lower density of low-density silicon oxide may be due to the deposition process, which may not be able to completely compact the material, resulting in higher porosity. The etching rate (dry or wet etching) of low-density oxides is much higher than that of high-density oxides (dry or wet etching).

[0063] According to some embodiments, the material of the conductive layer CL may include a conductive material, such as polysilicon, metal, alloy, or other suitable conductive material. The material of the first conductive layer 114A may include polysilicon, such as heavily doped N-type semiconductor polysilicon; the materials of the second conductive layer 118A and the third conductive layer 122A may include titanium nitride and tungsten.

[0064] According to some embodiments, the first stack 100A of the semiconductor device 10 may further include a channel layer 130A, a dielectric layer 132A, a conductive connection structure 134, and an insulating pillar 142. The channel layer 130A, dielectric layer 132A, conductive connection structure 134, and insulating pillar 142 extend along a first direction D1, passing through the conductive layer CL and the insulating layer IL in the first stack 100A. For example, in the second direction D2 and the third direction D3, the channel layer 130A, dielectric layer 132A, conductive connection structure 134, and insulating pillar 142 may overlap the first insulating portion 1241A in the first conductive layer 114A, the second insulating layer 116A, the second conductive layer 118A, the third insulating layer 120A, the third conductive layer 122A, and the fourth insulating layer 124A. The first direction D1, the second direction D2, and the third direction D3 may be perpendicular to each other, but the invention is not limited thereto. A conductive connection structure 134 surrounds an insulating pillar 142. A dielectric layer 132A surrounds the conductive connection structure 134 and the insulating pillar 142. A channel layer 130A surrounds the dielectric layer 132A, the conductive connection structure 134, and the insulating pillar 142. Conductive layers CL (e.g., a first conductive layer 114A, a second conductive layer 118A, and a third conductive layer 122A) surround the channel layer 130A, the dielectric layer 132A, the conductive connection structure 134, and the insulating pillar 142. The dielectric layer 132A is disposed between the channel layer 130A and the first connection portion 1341 of the conductive connection structure 134 (described in detail below). The channel layer 130A is electrically connected to the conductive connection structure 134. The conductive layers CL (e.g., a first conductive layer 114A, a second conductive layer 118A, and a third conductive layer 122A) are electrically in contact with the channel layer 134. In some embodiments, the second conductive layers 118A and 118B and the third conductive layers 122A and 122B are each surrounded by a gate dielectric layer GOX. The material of the gate dielectric layer GOX may include an oxide material, such as aluminum oxide (Al₂O₃). X ), Hafnium oxide (HfO) X Zirconium oxide (ZrO) X (or other suitable materials.)

[0065] The channel layer 130A passes through at least a portion of the conductive layer CL and insulating layer IL of the first stack 100A along the first direction D1. Specifically, the channel layer 130A passes through the first insulating portion 1241A of the first conductive layer 114A, the second insulating layer 116A, the second conductive layer 118A, the third insulating layer 120A, the third conductive layer 122A, and the fourth insulating layer 124A along the first direction D1. According to one embodiment, the material of the channel layer 130A may include polycrystalline silicon.

[0066] The dielectric layer 132A passes through at least a portion of the conductive layer CL and the insulating layer IL of the first stack 100A along the first direction D1. Specifically, the channel layer 130A passes through the first insulating portion 1241A of the first conductive layer 114A, the second insulating layer 116A, the second conductive layer 118A, the third insulating layer 120A, the third conductive layer 122A, and the fourth insulating layer 124A along the first direction D1. According to one embodiment, the material of the dielectric layer 132A may include silicon nitride.

[0067] The conductive connection structure 134, for example, extends along a first direction D1 through the conductive layer CL and the insulating layer IL of the entire first stack 100A. In this embodiment, the conductive connection structure 134 includes a first connection portion 1341, a second connection portion 1342A, and a third connection portion 1343; however, the invention is not limited thereto. The second connection portion 1342A and the third connection portion 1343 are connected to the first connection portion 1341. Figure 1A In the cross-sectional view shown, the first connecting portion 1341 extends along the first direction D1, passing through the first insulating layer 112A, the first conductive layer 114A, the second insulating layer 116A, the second conductive layer 118A, the third insulating layer 120A, the third conductive layer 122A, and the fourth insulating layer 124A. Figure 1A In the cross-sectional view shown, the second connecting portion 1342A extends along the second direction D2, is disposed on the dielectric layer 132A and the channel layer 130A, and is electrically in contact with the channel layer 130A. The second connecting portion 1342A surrounds the first connecting portion 1341, overlaps the dielectric layer 132A and the channel layer 132A in the first direction D1, and overlaps the second insulating portion 1242A in the fourth insulating layer 124A in the second direction D2. In other words, the distance between the second insulating portion 1242A and the upper surface 102s of the base plate 102 in the first direction D1 can be equal to the distance between the second connecting portion 1342A and the upper surface 102s of the base plate 102 in the first direction D1. Figure 1A In the cross-sectional view shown, the third connection portion 1343 extends along the second direction, for example, connecting to the bottom of the first connection portion 1341 and contacting the base plate 102. The channel layer 130A is further away from the first connection portion 1341 than the dielectric layer 132A. The material of the conductive connection structure 134 may include a conductive material, such as a metal or other suitable conductive material.

[0068] In one embodiment, the insulating post 142 extends along a first direction D1, passing through the entire insulating layer IL and conductive layer CL of the first stack 100A. The insulating post 142 may include an air gap 144. The material of the insulating post 142 may include an insulating material, such as an oxide or other suitable insulating material.

[0069] In one embodiment, the first stack 100A and the second stack 100B may have the same or similar structures. The second stack 100B is stacked on top of the first stack 100A along a first direction D1. That is, the second stack 100B may include a first insulating layer 112B, a first conductive layer 114B, a second insulating layer 116B, a second conductive layer 118B, a third insulating layer 120B, a third conductive layer 122B, and a fourth insulating layer 124B sequentially stacked on top of the first stack 100A along the first direction D1. The fourth insulating layer 124B may include a first insulating portion 1241B and a second insulating portion 1242B. The materials and structures of the first insulating portion 1241B and the second insulating portion 1242B of the first insulating layer 112B, the first conductive layer 114B, the second insulating layer 116B, the second conductive layer 118B, the third insulating layer 120B, the third conductive layer 122B, and the fourth insulating layer 124B are the same as or similar to the first insulating portion 1241A and the second insulating portion 1242A of the first insulating layer 112A, the first conductive layer 114A, the second insulating layer 116A, the second conductive layer 118A, the third insulating layer 120A, the third conductive layer 122A, and the fourth insulating layer 124A. The repeated parts will not be described in detail.

[0070] The second stack 100B may also include a channel layer 130B and a dielectric layer 132B. The materials and structures of the channel layer 130B and the dielectric layer 132B are the same as or similar to those of the channel layer 130A and the dielectric layer 132A, respectively. The conductive connection structure 134 and the insulating pillar 142 extend along the first direction D1 and further penetrate the insulating layer IL and the conductive layer CL of the second stack 100B. Furthermore, the conductive connection structure 134 may also include another second connection portion 1342B. The materials and structures of the second connection portion 1342B are the same as or similar to those of the second connection portion 1342A.

[0071] The semiconductor device 10 may further include a first capping layer 152 and a second capping layer 154. The first capping layer 152 and the second capping layer 154 are sequentially applied to the second stack 100B along a first direction D1. The conductive connection structure 134 and the insulating pillar 142 extend further through the first capping layer 152 and the second capping layer 154 along the first direction D1. The materials of the first capping layer 152 and the second capping layer 154 may include oxides or other suitable insulating materials.

[0072] In a top view (e.g.) Figure 1C As shown, the conductive connection structure 134 is ring-shaped and may have a circular outline, an elliptical outline or other suitable shape.

[0073] like Figure 1BAs shown, the semiconductor device 10 may also include multiple plugs CP, multiple contact structures CT, and multiple wires CE. The plugs CP are electrically connected to the conductive connection structure 134, and the wires CE are electrically connected to their respective plugs CP. The contact structures CT are electrically connected to their respective conductive layers CL, for example, to the first conductive layer 114A, the second conductive layer 118A, the third conductive layer 122A, the first conductive layer 114B, the second conductive layer 118B, and the third conductive layer 122B.

[0074] According to some embodiments, the first conductive layers 114A and 114B can each serve as a source line; the second conductive layer 118A, the third conductive layer 122A, the second conductive layer 118B, and the third conductive layer 122B can each serve as a word line; and the conductive connection structure 134 serves as a bit line or is electrically connected to a bit line.

[0075] In the first stack 100A, two series transistors (2T) are formed at the intersection of the channel layer 130A with the second conductive layer 118A and the third conductive layer 122A; in the second stack 100B, two series transistors are formed at the intersection of the channel layer 130B with the second conductive layer 118B and the third conductive layer 122B. Therefore, the semiconductor device 10 of this embodiment can form a three-dimensional dual-transistor capacitorless dynamic random access memory (3D 2T capacitorless DRAM). The invention is not limited to this; in other embodiments, the number of conductive layers and the number of stacks can be greater. Since the semiconductor device of the present invention is stacked along the first direction D1 (e.g., vertically), it is a relatively easy stacking method, which is beneficial to the development of miniaturized devices. Therefore, compared to conventional 1T 1C DRAM, the semiconductor device of the present invention can solve the scaling issue and provide a memory device with higher storage capacity.

[0076] Please refer to Figure 1A The second conductive layer 118A is the first gate of the bottom 2T DRAM, the third conductive layer 122A is the second gate of the bottom 2T DRAM, and the channel layer 130A is the channel of the bottom 2T DRAM; the second conductive layer 118B is the first gate of the top 2T DRAM, the third conductive layer 122B is the second gate of the top 2T DRAM, and the channel layer 130B is the channel of the top 2T DRAM.

[0077] like Figure 1AAs shown in the current path CRP, current can flow from the first conductive layer 114B into the channel layer 130B, and then through the second connection portion 1342B and the first connection portion 1341 of the conductive connection structure 134. Similarly, current can flow from the first conductive layer 114A into the channel layer 130A, and then through the second connection portion 1342A and the first connection portion 1341 of the conductive connection structure 134.

[0078] According to some embodiments, the thicknesses of the second conductive layer 118A (or 118B) and the third conductive layer 122A (or 122B) in the first direction D1 may be the same or different. The second conductive layers 118A and 118B, and the third conductive layers 122A and 122B, may be subjected to different voltages and have different functions. For example, one of the second conductive layer 118A (or 118B) and the third conductive layer 122A (or 122B) may serve as a control gate, and the other as an auxiliary gate, to prevent leakage current.

[0079] According to some embodiments, the second conductive layer 118A (or 118B) and the third conductive layer 122A (or 122B) may have a high dielectric constant metal gate structure, so the semiconductor device 10 may have excellent operating performance.

[0080] Figure 1D A perspective view of a semiconductor device 10' according to another embodiment of the present invention is shown. The difference between semiconductor device 10' and semiconductor device 10 is that the conductive connection structure 134' includes a first connection portion 1341 and second connection portions 1342A and 1342B, but does not include a third connection portion 1343, and the number of plugs CP and wires CE are different. Other identical or similar parts will not be described in detail.

[0081] Please refer to Figure 1D The conductive connection structure 134' is electrically connected to the plug CP located on opposite sides (first side SE1 and second side SE2), so voltage can be applied to the conductive connection structure 134' through different wires CL and plug CP.

[0082] Figures 2A to 2J Illustration as follows Figure 1A and Figure 1B A flowchart illustrating the fabrication method of the semiconductor device 10 shown.

[0083] Please refer to Figure 2AThe invention provides a base plate 102 and at least one stacked structure stacked on the base plate 102 along a first direction D1. In this embodiment, the number of at least one stacked structure is two, that is, the at least one stacked structure includes a first stacked structure 100A' and a second stacked structure 100B', with the second stacked structure 100B' stacked on the first stack 100A'. However, the invention is not limited to this, and the number of at least one stacked structure can be one, three, or more than three.

[0084] The first stacked structure 100A' includes a first insulating layer 112A, a first conductive layer 114A stacked on the first insulating layer 112A, and multiple insulating layers 111A and multiple sacrificial layers 114A alternately stacked on the first conductive layer 114A. The insulating layer 111A further includes a second insulating layer 116A, a third insulating layer 120A, and a fourth insulating layer 124A. The sacrificial layers 114A and 124A include a first sacrificial layer 118A' and a second sacrificial layer 122A'. That is, the first insulating layer 112A, the first conductive layer 114A, the second insulating layer 116A, the first sacrificial layer 118A', the third insulating layer 120A, the second sacrificial layer 122A', and the fourth insulating layer 124A are sequentially stacked on the base plate 102 along the first direction D1. Since the structure and materials of the first conductive layer 114A, the first insulating layer 112A, the second insulating layer 116A, the third insulating layer 120A, and the fourth insulating layer 124A are the same as those described above... Figures 1A-1B The embodiments described herein will not be repeated in detail. The material of the sacrificial layer SAL is, for example, silicon nitride.

[0085] According to some embodiments, the material of the first insulating portion 1241A in the second insulating layer 116A, the third insulating layer 120A, and the fourth insulating layer 124A may include a low-density oxide, such as low-density silicon oxide. Low-density silicon oxide can be formed by plasma-enhanced chemical vapor deposition (PECVD). Due to the low temperature and specific process conditions, the resulting material tends to have a lower density and may contain impurities or incomplete bonding. According to some embodiments, the material of the second insulating portion 1242A in the fourth insulating layer 124A may include a high-density oxide, such as high-density silicon oxide or tetraethoxysilane (TEOS) oxide. High-density silicon oxide is typically formed using methods such as high-density plasma-enhanced chemical vapor deposition (HDP-CVD) or thermal oxidation. These methods produce denser oxide layers with fewer voids and higher purity, making them more suitable for applications requiring high-quality insulating or protective layers. Furthermore, different deposition temperatures can be used to form high-density and low-density silicon oxides. For example, low-density silicon oxide can be deposited at around 200°C, while high-density silicon oxide can be deposited in a temperature range of 400°C to 600°C.

[0086] According to some embodiments, the structure and materials of the second stacked structure 100B' may be the same as those of the first stacked structure 100A'. That is, the second stacked structure 100B' may include a first insulating layer 112B, a first conductive layer 114B, a second insulating layer 116B, a first sacrificial layer 118B', a third insulating layer 120B, a second sacrificial layer 122B', and a fourth insulating layer 124B sequentially stacked along the first direction D1 on the first stacked structure 100A'. The fourth insulating layer 124B may include a first insulating portion 1241B and a second insulating portion 1242B. The materials and structures of the first insulating portion 1241B and the second insulating portion 1242B of the first insulating layer 112B, the first conductive layer 114B, the second insulating layer 116B, the first sacrificial layer 118B', the third insulating layer 120B, the second sacrificial layer 122B', and the fourth insulating layer 124B are the same as or similar to the first insulating portion 1241A and the second insulating portion 1242A of the first insulating layer 112A, the first conductive layer 114A, the second insulating layer 116A, the first sacrificial layer 118A', the third insulating layer 120A, the second sacrificial layer 122A', and the fourth insulating layer 124A. The repeated parts will not be described in detail.

[0087] Please refer to Figure 2B In such Figure 2A An opening OP1 is formed on the structure shown, extending along a first direction D1. The opening OP1 passes through the insulating layer IL and conductive layer CL of the first stacked structure 100A' and the second stacked structure 100B', for example, along the first direction D1. The bottom of the opening OP1 exposes the base plate 102, for example. The opening OP1 is formed, for example, by an etching process.

[0088] Please refer to Figure 2C In such Figure 2B The structure shown has a first lateral aperture HL1 extending along the second direction D2, which is connected to and surrounds the opening OP1. For example, a portion of the first conductive layers 114A and 114B is removed by an etching process (e.g., an etch-back process) to form the first lateral aperture HL1.

[0089] Please refer to Figure 2D In such Figure 2C The structure shown forms a second lateral aperture HL2 extending along the second direction D2, which is connected to and surrounds the opening OP1. For example, portions of the first sacrificial layers 118A' and 118B' and the second sacrificial layers 122A' and 122B' are removed by an etching process (e.g., a back etching process) to form two second lateral apertures HL2.

[0090] Please refer to Figure 2E In such Figure 2DThe structure shown has a vertical hole HL3 extending along a first direction D1, which connects to and surrounds the opening OP1. For example, the vertical hole HL3 is formed by removing portions of the first conductive layers 114A and 114B, the first sacrificial layers 118A' and 118B', the second insulating layers 116A and 116B, the second sacrificial layers 122A' and 122B', the third insulating layers 120A and 120B, and the first insulating portions 1241A and 1241B of the fourth insulating layers 124A and 124B through an etching process (e.g., wet etching). The vertical hole HL3 connects to the opening OP1, the first lateral hole HL1, and the second lateral hole HL2.

[0091] Please refer to Figure 2F In such Figure 2E Channel layers 130A and 130B extending along a first direction D1 are formed on the structure shown. For example, channel layers 130A and 130B are formed by filling the outer side of the vertical hole HL3 with channel material, such as polysilicon. In one embodiment, a channel material film conformally to the sidewalls and bottom of the opening OP1 and the vertical hole HL3 may be formed first, and then the excess channel material film may be removed by an etching process (e.g., an etch-back process) to form channel layers 130A and 130B.

[0092] Please refer to Figure 2G In such Figure 2F The structure shown has dielectric layers 132A and 132B extending along a first direction D1. For example, dielectric layers 132A and 132B adjacent to channel layers 130A and 130B are formed by filling the inside of the vertical hole HL3 with dielectric material, such as silicon nitride. In one embodiment, a dielectric material film conforming to the opening OP1 and the sidewalls and bottom of the vertical hole HL3 having channel layers 130A and 130B can be formed first, and then the excess dielectric material film can be removed by an etching process (e.g., an etch-back process) to form dielectric layers 132A and 132B.

[0093] Please refer to Figure 2H In such Figure 2G The structure shown has a lateral opening OP2 extending along the second direction D2, which communicates with and surrounds the opening OP1. For example, the lateral opening OP2 is formed by removing portions of the second insulating portions 1242A and 1242B through an etching process (e.g., an etch-back process). The lateral opening OP2 exposes the upper surfaces of the dielectric layers 132A and 132B and the channel layers 130A and 130B.

[0094] Please refer to Figure 2I In such Figure 2HThe structure shown sequentially forms a conductive connection structure 134 and an insulating pillar 142. For example, the conductive connection structure 134 can be formed by filling the lateral opening OP2 and the sidewall of the opening OP1 with a conductive material through a deposition process. The conductive material is, for example, a metal or other suitable conductive material. Next, the insulating pillar 142 can be formed by filling the opening OP1 with an insulating material through a deposition process. The insulating material is, for example, an oxide.

[0095] Please refer to Figure 2J The sacrificial layers SAL (e.g., first sacrificial layers 118A' and 118B' and second sacrificial layers 122A' and 122B') can be removed by an etching process, and the gate dielectric layer GOX is deposited in the gap formed by removing the sacrificial layers SAL (e.g., first sacrificial layers 118A' and 118B' and second sacrificial layers 122A' and 122B'). The material of the gate dielectric layer GOX may include an oxide material, such as aluminum oxide (Al₂O₃). X ), Hafnium oxide (HfO) X Zirconium oxide (ZrO) X Alternatively, other suitable materials may be used. Subsequently, conductive material is filled into the gaps formed after the sacrificial layer SAL is removed to form second conductive layers 118A and 118B and third conductive layers 122A and 122B. This forms a first stack 100A and a second stack 100B stacked along the first direction D1 on the base plate 102, and forms as shown... Figure 1A and Figure 1B The semiconductor device 10 shown. The second conductive layers 118A and 118B and the third conductive layers 122A and 122B are respectively surrounded by the gate dielectric layer GOX.

[0096] In summary, this invention provides a semiconductor device and a method for manufacturing the same. Since the semiconductor device of this invention is stacked along a first direction (e.g., vertically stacked), it is a relatively easy stacking method, which is beneficial for the development of miniaturized components. Therefore, compared to conventional 1T 1C DRAM, the semiconductor device of this invention can solve the miniaturization problem and provide a memory device with higher storage capacity.

[0097] While the present invention has been disclosed above with reference to embodiments, it is not intended to limit the invention. Those skilled in the art will be able to make various modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A semiconductor device, comprising: One base plate; as well as At least one stack is stacked on the base plate along a first direction, wherein the at least one stack includes a first stack, and the first stack includes: Multiple insulating layers and multiple conductive layers are alternately stacked on the base plate along the first direction; An insulating pillar extends along the first direction, passing through the insulating layers and the conductive layers; A conductive connection structure passes through these insulating layers and these conductive layers and surrounds the insulating pillar; A dielectric layer surrounds the conductive connection structure; and A channel layer surrounds the dielectric layer and is electrically connected to the conductive connection structure.

2. The semiconductor device of claim 1, wherein the insulating layers include a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer, the conductive layers include a first conductive layer, a second conductive layer and a third conductive layer, and the first insulating layer, the first conductive layer, the second insulating layer, the second conductive layer, the third insulating layer, the third conductive layer and the fourth insulating layer are sequentially stacked on the substrate along the first direction.

3. The semiconductor device of claim 2, wherein the materials of the first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer comprise oxides.

4. The semiconductor device of claim 3, wherein the fourth insulating layer comprises a first insulating portion and a second insulating portion, the second insulating portion being stacked on the first insulating portion; and The material of the first insulating portion in the second insulating layer, the third insulating layer, and the fourth insulating layer comprises a low-density oxide; the material of the second insulating portion in the fourth insulating layer comprises a low-density oxide.

5. The semiconductor device of claim 4, wherein the porosity of the low-density oxide is higher than that of the high-density oxide.

6. The semiconductor device of claim 1, wherein the conductive connection structure includes a first connection portion and a second connection portion, the second connection portion being connected to the first connection portion and electrically contacting the channel layer, wherein in a cross-sectional view, the first connection portion extends along the first direction and the second connection portion extends along a second direction different from the first direction.

7. The semiconductor device of claim 1, wherein the number of the at least one stack is multiple, and the at least one stack further includes a second stack stacked on the first stack along the first direction.

8. A method for manufacturing a semiconductor device, comprising: Provide a base plate; as well as At least one stack is formed on the base plate along a first direction, wherein the at least one stack includes a first stack, and the first stack includes: Multiple insulating layers and multiple conductive layers are alternately stacked on the base plate along the first direction; An insulating pillar extends along the first direction, passing through the insulating layers and the conductive layers; A conductive connection structure passes through these insulating layers and these conductive layers and surrounds the insulating pillar; A dielectric layer surrounds the conductive connection structure; and A channel layer surrounds the dielectric layer and is electrically connected to the conductive connection structure.

9. The method for fabricating a semiconductor device according to claim 8, wherein the step of forming the first stack comprises: A first stacked structure is formed on the base plate, wherein The first stacked structure includes a first insulating layer, a first conductive layer stacked on the first insulating layer, and a plurality of insulating layers and a plurality of sacrificial layers alternately stacked on the first conductive layer. The insulating layers include a second insulating layer, a third insulating layer, and a fourth insulating layer, and the sacrificial layers include a first sacrificial layer and a second sacrificial layer. The first insulating layer, the first conductive layer, the second insulating layer, the first sacrificial layer, the third insulating layer, the second sacrificial layer, and the fourth insulating layer are sequentially stacked on the base plate along the first direction; and The fourth insulating layer includes a first insulating portion and a second insulating portion, the second insulating portion being stacked on the first insulating portion.

10. The method for fabricating a semiconductor device according to claim 9, wherein the step of forming the first stack further comprises: An opening is formed extending along the first direction, the opening passing through the first stacked structure; Remove a portion of the first conductive layer to form a first lateral hole; Remove portions of the first sacrificial layer and the second sacrificial layer to form two second lateral holes; The first insulating portion of the first conductive layer, the first sacrificial layer, the second insulating layer, the third insulating layer, and the fourth insulating layer is removed to form a vertical hole, wherein the vertical hole communicates with the opening, the first lateral hole, and the two second lateral holes. The channel layer is formed by filling the outside of the vertical hole with channel material; The dielectric layer adjacent to the channel layer is formed by filling the inside of the vertical hole with dielectric material. Remove part of the second insulating portion to form a lateral opening; The conductive connection structure is formed by filling the lateral opening and the sidewall of the opening with conductive material. The opening is filled with insulating material to form the insulating pillar; Remove these sacrifice layers; as well as Conductive material is filled into the gaps formed after these sacrificial layers are removed to form the second conductive layer and the third conductive layer.

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