Semiconductor memory device and method of manufacturing the same

Abstract

A semiconductor memory device includes: a substrate including cell regions and boundary regions; and first word lines to eighth word lines disposed in the substrate, intersecting the cell regions and extending into the boundary regions in a first direction. The first word lines to eighth word lines are sequentially disposed in a second direction, and are arranged in the following order: first word line, then second word line, then third word line, then fourth word line, then fifth word line, then sixth word line, then seventh word line, then eighth word line. In the boundary regions, the fourth and eighth word lines extend a greater distance in the first direction than the first to third word lines and the fifth to seventh word lines extend a greater distance in the first direction.

Description

[0001] Cross-references to related applications

[0002] This patent application claims priority to Korean Patent Application No. 10-2025-0003716, filed on January 9, 2025, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure relates to semiconductor memory devices and methods for manufacturing the same. Background Technology

[0004] Semiconductor memory devices are considered essential components in the electronics industry due to their small size, versatility, and / or low cost. With advancements in the electronics industry, the demand for highly integrated semiconductor memory devices is increasing. Reducing the linewidth of the patterns constituting the semiconductor memory devices is beneficial for increasing their integration density. However, reducing the linewidth requires novel and expensive exposure techniques, making it difficult to increase the integration density of semiconductor memory devices. Therefore, in recent years, various new technologies have been researched to overcome the challenge of increasing the integration density of semiconductor memory devices. Summary of the Invention

[0005] The embodiments provide semiconductor memory devices with improved reliability.

[0006] The embodiments provide methods for reducing process defects in the manufacturing process of semiconductor memory devices.

[0007] According to an embodiment, a semiconductor memory device includes: a substrate including cell regions and boundary regions; and first word lines to eighth word lines disposed in the substrate to intersect with the cell regions and extend to the boundary regions in a first direction, wherein the first word lines to eighth word lines are sequentially disposed in a second direction perpendicular to the first direction, and the first word lines to eighth word lines are sequentially disposed in the following order: first word line, then second word line, then third word line, then fourth word line, then fifth word line, then sixth word line, then seventh word line, then eighth word line, and in the boundary regions, when viewed from a plan view, the distance extended by the fourth word line and the eighth word line in the first direction is greater than the distance extended by the first word lines to the third word line and the fifth word line to the seventh word line in the first direction.

[0008] According to an embodiment, a semiconductor memory device includes: a substrate including a cell region and a boundary region; first word lines to eighth word lines disposed in the substrate, intersecting the cell region and extending to the boundary region in a first direction; a first contact plug on the boundary region and contacting the ends of the second word lines and the sixth word line; and a second contact plug on the boundary region and contacting the ends of the fourth word lines and the eighth word line, wherein the bottom surface of the first contact plug is at a first height, the first height being different from a second height of the bottom surface of the second contact plug.

[0009] According to an embodiment, a semiconductor memory device includes: a substrate including a first boundary region, a cell region, and a second boundary region arranged along a first direction; a device isolation layer disposed in the substrate, covering the first and second boundary regions, and defining an active region in the cell region, wherein the active region extends in a second direction perpendicular to the first direction; a first word line to an eighth word line disposed in the substrate, extending in the first direction through the cell region into the first and second boundary regions, the first word line to the eighth word line extending in the first direction through the active region; an impurity region disposed in the active region; a data storage pattern connected to one of the impurity regions; a bit line connected to the other in the impurity region and extending upward in a third direction perpendicular to the first and second directions; a first contact plug on the first boundary region, contacting the ends of a second word line and a sixth word line; and a second contact plug on the first boundary region, contacting the ends of a fourth word line and an eighth word line, wherein, when viewed in a plan view, the second contact plug is offset from the first contact plug relative to the first direction.

[0010] An embodiment provides a method for manufacturing a semiconductor memory device, the method comprising: forming a first line mask pattern to a ninth line mask pattern on a substrate including cell regions and boundary regions, the line mask patterns extending in a first direction and separated from each other in a second direction intersecting the first direction; forming a first overlay mask pattern to cover the ends of the first line mask patterns to the ninth line mask pattern on the boundary regions, the side surface of the first overlay mask pattern being adjacent to the cell regions in a plan view, and forming recessed portions in the first direction to expose the space between the ends of a fourth line mask pattern and a fifth line mask pattern, and the space between the ends of an eighth line mask pattern and a ninth line mask pattern; and causing... The substrate is etched using a first line mask pattern to a ninth line mask pattern and a first cover mask pattern as etching masks to form a first groove to an eighth groove; a first conductive pattern is formed in the first groove to the eighth groove; a second cover mask pattern is formed on the boundary region to cover the first conductive pattern, the second cover mask pattern including a cover linear portion extending in a second direction and a cover protrusion portion protruding from the cover linear portion in a first direction, the cover protrusion portion covering the second groove and the sixth groove and exposing the first groove, the third groove to the fifth groove, the seventh groove and the eighth groove; and the first conductive pattern is etched using the second cover mask pattern as an etching mask to form a line portion and a protrusion portion in the first conductive pattern.

[0011] The method may further include forming a second conductive pattern to cover the top surface of the line portion of the first conductive pattern and to contact the side surface of the protrusion. Attached Figure Description

[0012] Figure 1 This is a plan view of a semiconductor memory device according to an embodiment.

[0013] Figure 2A and Figure 2B It shows Figure 1 An enlarged plan view of part "P1".

[0014] Figure 3A It is along Figure 2A The cross-sectional view taken by line A1-A1'.

[0015] Figure 3B It is along Figure 2A The cross-sectional view taken from line A2-A2'.

[0016] Figure 4A It is along Figure 2A The cross-sectional view taken from line B1-B1'.

[0017] Figure 4B It is along Figure 2A The cross-sectional view taken from line B2-B2'.

[0018] Figure 5 It shows Figure 4B An enlarged cross-sectional view of part "P2".

[0019] Figure 6A It shows Figure 2A A perspective view of a portion of the image.

[0020] Figure 6B It shows Figure 2B A perspective view of a portion of the image.

[0021] Figure 7A and Figure 7B This is a plan view of a semiconductor memory device according to an embodiment.

[0022] Figure 8A It is along Figure 2A The cross-sectional view taken from line C-C'.

[0023] Figure 8B It is along Figure 2A The cross-sectional view taken by line D-D'.

[0024] Figure 8C It is along Figure 2A The cross-sectional view taken from line E-E'.

[0025] Figures 9A to 17A The manufacturing process is shown sequentially. Figure 2A A planar diagram of the fabrication process for a planar semiconductor memory device.

[0026] Figure 9B and Figures 11B to 17B It is along Figure 9A and Figures 11A to 17A The cross-sectional view taken by line A1-A1'.

[0027] Figure 9C and Figures 11C to 17C It is along Figure 9A and Figures 11A to 17A The cross-sectional view taken from line A2-A2'.

[0028] Figure 9D , Figure 10B , Figures 11D to 17D It is along Figures 9A to 17A The cross-sectional view taken from lines B1-B1' and B2-B2'. Detailed Implementation

[0029] The exemplary embodiments will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments are shown.

[0030] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it should be understood that the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with other elements to form the component, unless the context clearly and / or explicitly describes the opposite.

[0031] Ordinal numbers such as "first," "second," and "third" can simply be used as labels to distinguish certain elements, steps, etc., from one another. Terms not described using "first," "second," etc., in the specification may still be referred to as "first" or "second" in the claims. Furthermore, a term referenced with a specific ordinal number (e.g., "first" in a particular claim) may be described elsewhere with a different ordinal number (e.g., "second" in the specification or another claim).

[0032] As used herein, components described as “electrical connections” are configured to allow electrical signals to be transmitted from one component to another (although the strength of such electrical signals may attenuate during transmission and they may be transmitted selectively).

[0033] For ease of description, this article uses spatial relative terms such as “below,” “under,” “down,” “above,” “up,” “top,” “bottom,” “front,” and “back” to describe positional relationships, as shown in the figure. It will be understood that spatial relative terms, in addition to the orientations shown in the figure, also cover different orientations of the device.

[0034] Figure 1 This is a plan view of a semiconductor memory device according to an embodiment.

[0035] Reference Figure 1 The semiconductor memory device may include a substrate 100. The substrate 100 may be an initial substrate (base substrate) on which additional layers are formed, such as a crystalline semiconductor substrate (e.g., a bulk semiconductor substrate). For example, the substrate 100 may be formed of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium phosphide (GaP), or gallium arsenide (GaAs), or may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium phosphide (GaP), or gallium arsenide (GaAs). The substrate 100 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0036] The substrate 100 may include a plurality of cell regions CR, which are arranged two-dimensionally in two orthogonal directions (e.g., a second direction X2 and a third direction X3). The number and arrangement of the cell regions CR are not limited to... Figure 1The quantity and arrangement are shown, and various changes can be made. Peripheral regions (PRs) can be set between cell regions (CRs). Peripheral regions (PRs) can be configured to surround each cell region within a cell region (CR). Multiple memory cells can be set within a cell region (CR). Each memory cell within a memory cell can be connected to intersecting word lines and bit lines. Core circuitry or peripheral circuitry can be set within peripheral regions (PRs). Peripheral circuitry may include row decoders, column decoders, control logic circuitry, etc.

[0037] The core circuitry of the peripheral region PR may include a sense amplifier (SA) circuit and a sub-word line driver (SWD) circuit. The peripheral region PR may also include power supply and ground driver circuitry for driving the sense amplifier, but this application is not limited to this example.

[0038] Figure 2A and Figure 2B It shows Figure 1 An enlarged plan view of part "P1". Figure 3A It is along Figure 2A The cross-sectional view taken by line A1-A1'. Figure 3B It is along Figure 2A The cross-sectional view taken from line A2-A2'. Figure 4A It is along Figure 2A The cross-sectional view taken from line B1-B1'. Figure 4B It is along Figure 2A The cross-sectional view taken from line B2-B2'. Figure 5 It shows Figure 4B An enlarged cross-sectional view of part "P2". Figure 6A It shows Figure 2A A perspective view of a portion of the image. Figure 6B It shows Figure 2B A perspective view of a portion of the image.

[0039] Reference Figure 2A and Figure 3A The semiconductor memory device may include a substrate 100. The substrate 100 may include cell regions CR and boundary regions INT arranged parallel to each other in a second direction X2. The boundary region INT may be located in... Figure 1 The area shown is between the cell region CR and the surrounding region PR. The boundary region INT may include a dummy region DR adjacent to the cell region CR.

[0040] A first device isolation portion 20c and a second device isolation portion 20p can be disposed in the substrate 100. The first device isolation portion 20c can be disposed in the cell region CR and the dummy region DR to define the cell active region AC and the dummy active region DA. The cell active region AC and the dummy active region DA can extend in the first direction X1, such as... Figure 2AAs shown, they can be spaced apart from each other. The active region AC of the cell can be used to implement the storage function, while the dummy active region DA cannot be used to implement the storage function, which can be formed to prevent the load effect in the manufacturing process.

[0041] In the accompanying drawings, the first direction X1 to the fourth direction X4 may be parallel to the top surface of the substrate 100, and the fifth direction X5 may be perpendicular to the top surface of the substrate 100. The second direction X2 may be the opposite direction of the fourth direction X4. The first direction X1 and the third direction X3 may not be parallel to each other, and may not be parallel to the second direction X2 and the fourth direction X4. The third direction X3 may be perpendicular to the second direction X2 and the fourth direction X4.

[0042] The second device isolation portion 20p may be disposed in the boundary region INT to define the boundary between the cell region CR and the peripheral region PR. The first device isolation portion 20c may include a first insulating pad 21a, a first gap-filling pattern 21b, and a second gap-filling pattern 22a. The second device isolation portion 20p may include a second insulating pad 21, a third insulating pad 22, and a second gap-filling pattern 23. The first insulating pad 21a, the first gap-filling pattern 21b, the second insulating pad 21, and the second gap-filling pattern 23 may be formed of the same insulating material (e.g., silicon oxide). The second gap-filling pattern 22a and the third insulating pad 22 may be formed of the same insulating material (e.g., silicon nitride) or comprise the same insulating material. (See reference...) Figure 9A The second gap-filling pattern 22a can form island-like patterns (e.g., discrete discrete elements with distinct boundaries and surrounded by the first insulating pad 21a and the first gap-filling pattern 21b), which, when viewed in plan view, are located between the cell active regions AC. The first insulating pad 21a can be connected to the first gap-filling pattern 21b and the second insulating pad 21. When viewed in plan view, the second insulating pad 21 can extend in a third direction X3 and can have uneven side surfaces.

[0043] Reference Figure 2A , Figure 3A and Figure 3BWord lines WL can be disposed in the substrate 100 to intersect with active regions AC and DA in the second direction X2. Word lines WL can extend in the second direction X2 to the boundary region INT to intersect with the cell region CR. Word lines WL can include multiple word lines, for example, first word lines WL (1) to eighth word lines WL (8), which are arranged sequentially in the third direction X3. For example, by sequential arrangement or setting, first word lines WL (1) to eighth word lines WL (8) can be arranged sequentially in the following order: first word line WL (1), followed by second word line WL (2), followed by third word line WL (3), followed by fourth word line WL (4), followed by fifth word line WL (5), followed by sixth word line WL (6), followed by seventh word line WL (7), followed by eighth word line WL (8). The first character line WL(1) can be adjacent to the second character line WL(2), and there are no other character lines between the first character line WL(1) and the second character line WL(2). The second character line WL(2) can be adjacent to the third character line WL(3), and there are no other character lines between the second character line WL(2) and the third character line WL(3). The third character line WL(3) can be adjacent to the fourth character line WL(4), and there are no other character lines between the third character line WL(3) and the fourth character line WL(4). The fourth character line WL(4) can be adjacent to the fifth character line WL(5), and there are no other character lines between the fourth character line WL(4) and the fifth character line WL(5). The fifth character line WL(5) can be adjacent to the sixth character line WL(6), and there are no other character lines between the fifth character line WL(5) and the sixth character line WL(6). The sixth word line WL(6) may be adjacent to the seventh word line WL(7), and there are no other word lines between the sixth word line WL(6) and the seventh word line WL(7). The seventh word line WL(7) may be adjacent to the eighth word line WL(8), and there are no other word lines between the seventh word line WL(7) and the eighth word line WL(8). In the boundary region INT, when viewed from the plan view, the fourth word line WL(4) and the eighth word line WL(8) may extend in the second direction X2, thus protruding the third length LT3 compared to the first word line WL(1) to the third word line WL(3) and the fifth word line WL(5) to the seventh word line WL(7). In other words, when viewed from the plan view, the ends of the fourth character line WL(4) and the eighth character line WL(8) may not overlap with the ends of the first character line WL(1) to the third character line WL(3) and the ends of the fifth character line WL(5) to the seventh character line WL(7) in the third direction X3. When viewed from the plan view, the ends of the fourth character line WL(4) and the eighth character line WL(8) may be aligned with each other in the third direction X3. When viewed from the plan view, the ends of the first character line WL(1) to the third character line WL(3) and the ends of the fifth character line WL(5) to the seventh character line WL(7) may be aligned with each other in the third direction X3.

[0044] Accordingly, in the embodiments, the first group of word lines WL (e.g., one or more word lines) may each have an end extending along the second direction X2 to a first position and terminating at the first position, and the second group of word lines WL (e.g., one or more word lines) may each have an end extending along the second direction X2 to a second position and terminating at the second position. Figure 2A As shown, the first group of character lines WL includes the fourth character line WL(4) and the eighth character line WL(8), and the first group of character lines WL(4) and WL(8) can be spaced apart from each other (e.g., along a third direction X3), and can terminate at the same first position along a second direction X2. Figure 2A As shown, the second group of character lines WL includes the first character line WL(1) to the third character line WL(3) and the fifth character line WL(5) to the seventh character line WL(7), and the second group of character lines WL(1), WL(2), WL(3), WL(5), WL(6), and WL(7) can be spaced apart from each other (e.g., along a third direction X3) and can terminate at the same second position along a second direction X2. The second position can be different from the first position. In an embodiment, the first position (e.g., the end of the first group of character lines) can be farther away from the cell region CR than the second position (e.g., the end of the second group of character lines). Therefore, the first distance between the cell region CR and the first position, measured parallel to the second direction X2, is greater than the second distance between the cell region CR and the second position, measured parallel to the second direction X2. Figure 2A As shown, the third length LT3 can represent the spacing distance along the second direction X2 between the first position (e.g., the end of the first group of word lines) and the second position (e.g., the end of the second group of word lines). In an embodiment, the word lines constituting the first group of word lines (e.g., the fourth word line WL(4) and the eighth word line WL(8)) may not be adjacent to each other. Conversely, one or more word lines in the second group (e.g., the fifth word line WL(5) to the seventh word line WL(7)) may be located along the third direction X3 between the fourth word line WL(4) and the eighth word line WL(8). Accordingly, the distance by which the first group of word lines (e.g., WL(4), WL(8)) extends into the boundary region INT in the second direction X2 may be greater than the distance by which the second group of word lines (WL(1), WL(2), WL(3), WL(5), WL(6), WL(7)) extends into the boundary region INT in the second direction X2.

[0045] Reference Figure 3A and Figure 3B In the active regions AC and DA, the top surface of the substrate 100 may protrude upwards compared to the top surfaces of the device isolation portions 20c and 20p. For example, the top surface of the substrate 100 (e.g., adjacent to the device isolation portion 20c) may be at a different height relative to the fifth direction X5 than the top surfaces of the device isolation portions 20c and 20p. Figure 3A and Figure 3B As shown, the top surface of substrate 100 can be at a height higher than the top surfaces of device isolation portions 20c and 20p. Gate insulating layer 151 can be located between word line WL and substrate 100. Gate insulating layer 151 can be formed of at least one of silicon oxide and / or a high-k dielectric material with a dielectric constant higher than silicon oxide, or can include at least one of silicon oxide and / or a high-k dielectric material with a dielectric constant higher than silicon oxide. The high-k dielectric material can include a metal oxide material.

[0046] Reference Figure 3A and Figure 3B Each word line in the word line WL may include a first conductive pattern 152 and a second conductive pattern 153 thereon. The first conductive pattern 152 may be formed of or include at least one of tungsten or titanium nitride. The second conductive pattern 153 may be formed of or include doped polysilicon. The first conductive pattern 152 may include a line portion LP and a protrusion PP, the protrusion PP being disposed on and connected to the line portion LP to form a single object. The line portion LP of the first conductive pattern 152 may extend to a boundary region INT to intersect with a cell region CR. The protrusion PP may be disposed on the boundary region INT, for example, at the junction between the boundary region INT and the cell region CR, and adjacent to the cell region CR. The protrusion PP may protrude upward compared to the second conductive pattern 153. The top surface of the protrusion PP may be located at a first height LV1. The top surface of the second conductive pattern 153 may be located at a second height LV2, which is lower than the first height LV1. The protrusion PP may have a first side surface SW1 adjacent to the cell region CR, and a second side surface SW2 opposite to the first side surface SW1. The first side surface SW1 and the second side surface SW2 can extend from the top surface of the protrusion PP through the second conductive pattern 153 to the top surface of the line portion LP. In the boundary region INT, the line portion LP may have a third side surface SW3, which defines the end of the line portion LP in the boundary region INT.

[0047] For the first letter line WL(1) to the eighth letter line WL(8), the first side surface SW1 of the protrusion PP can be aligned with each other in the third direction X3. For example, the first side surface SW1 of the protrusion PP of each letter line from the first letter line WL(1) to the eighth letter line WL(8) can lie in a plane that extends in the third direction X3. For the first letter line WL(1), the third letter line WL(3) to the fifth letter line WL(5), the seventh letter line WL(7), and the eighth letter line WL(8), the protrusion PP can have a first length LT1 in the second direction X2, such as Figure 3A As shown. For the second letter line WL(2) and the sixth letter line WL(6), the protrusion PP can have Figure 3BThe second length LT2 is shown. The first length LT1 may be less than the second length LT2. Accordingly, the protrusions PP of one or more word lines may have different lengths than the protrusions PP of other word lines.

[0048] For one or more word lines (e.g., the first word line WL(1), the third word line WL(3) through the fifth word line WL(5), the seventh word line WL(7), and the eighth word line WL(8)), the third side surface SW3 may be spaced apart from the second side surface SW2 in the second direction X2. For example, as Figure 3A As shown, the second side surface SW2 may not be coplanar with the third side surface SW3, such that the second side surface SW2 and the third side surface SW3 may be located on different planes and spaced apart from each other. For one or more other word lines (e.g., the second word line WL(2) and the sixth word line WL(6)), the third side surface SW3 may be vertically aligned with the second side surface SW2 and coplanar.

[0049] In the boundary region INT, a second residual conductive pattern 153r may be disposed on the line portions LP of the first word line WL (1), the third word line WL (3) to the fifth word line WL (5), the seventh word line WL (7), and the eighth word line WL (8). The second residual conductive pattern 153r and the second conductive pattern 153 may be spaced apart from each other and may be formed of the same material, with a protrusion PP located between the second residual conductive pattern 153r and the second conductive pattern 153. The second residual conductive pattern 153r may contact the second side surface SW2, while the second conductive pattern 153 may contact the first side surface SW1.

[0050] Each word line in the word line WL can be covered by a first capping pattern 154. The first capping pattern 154 can be formed of silicon nitride. The top surface of the first capping pattern 154 can be coplanar with the top surface of the second device isolation portion 20p.

[0051] Reference Figure 3A , Figure 3B , Figure 4A , Figure 4B , Figure 5 , Figure 6A and Figure 6B The word lines WL and substrate 100 may be covered by an interlayer insulating layer 250. A first contact plug WC1 may be disposed on the boundary region INT to penetrate the interlayer insulating layer 250 and the first capping pattern 154, and to contact the top surface of the protrusion PP of the first conductive pattern 152 of the second word line WL (2) and the sixth word line WL (6). The first contact plugs WC1 may be aligned with each other in a third direction X3, for example, a first axis extending in the third direction X3 intersects the first contact plugs WC1.

[0052] The second contact plug WC2 can be disposed on the boundary region INT to penetrate the interlayer insulating layer 250, the first capping pattern 154, and the second remaining conductive pattern 153r, and to contact the top surface of the line portion LP of the first conductive pattern 152 of the fourth word line WL(4) and the eighth word line WL(8). The second contact plugs WC2 can be aligned with each other in the third direction X3, for example, a second axis extending in the third direction X3 intersects with the second contact plugs WC2. (Refer to...) Figure 2A and Figure 2B The second axis (e.g., located at the same position as line B2-B2') may be parallel to and spaced apart from the first axis (e.g., located at the same position as line B1-B1'), wherein the second axis intersects the second contact plug WC2 but not the first contact plug WC1, and the first axis intersects the first contact plug WC1 but not the second contact plug WC2. The first contact plug WC1 and the second contact plug WC2 may be formed of or comprise the same metallic material (e.g., at least one of tungsten, titanium, and cobalt).

[0053] The first contact plug WC1 can be spaced apart from the cell region CR by a first distance. The second contact plug WC2 can be spaced apart from the cell region CR by a second distance. The second distance can be greater than the first distance. Therefore, the second contact plug WC2 can be offset from the first contact plug WC1 relative to the second direction X2; for example, the first contact plug WC1 and the second contact plug WC2 are located at different positions along the second direction X2. Each of the first contact plugs WC1 can have a first width WT1 in the third direction X3. The second contact plug WC2 can have a second width WT2 in the third direction X3. The second width WT2 can be greater than the first width WT1, such as... Figure 2A , Figure 4B and Figure 6A As shown. Alternatively, the second width WT2 can be approximately equal to the first width WT1, such as... Figure 2B and Figure 6B As shown.

[0054] The bottom surface of the first contact plug WC1 can be located at a first height LV1. The bottom surface of the second contact plug WC2 can be located at a third height LV3, which is lower than the first height LV1. For example... Figure 5As shown, the second contact plug WC2 can cover the top surface 152_U and side surface 152_S of the line portion LP of the first conductive pattern 152. Correspondingly, the width of the second contact plug WC2 in the third direction X3 can be greater than the width of the line portion LP in the third direction X3, and the upper part of the line portion LP can extend to the bottom of the second contact plug WC2, so that the top surface 152_U and side surface 152_S can contact the second contact plug WC2. In this case, the contact area between the second contact plug WC2 and the line portion LP of the first conductive pattern 152 can be increased, thereby reducing the resistive characteristics of the second contact plug WC2 and the line portion LP, and improving the signal transmission speed of the device.

[0055] The first contact plugs WC1 can be spaced apart from each other by a third distance DS3 on the third direction X3, such as Figure 4A As shown. Adjacent word lines WL (e.g., where there is no word line WL between adjacent word lines WL) can be spaced apart from each other by a fourth distance DS4 in the third direction X3, as... Figure 4A As shown. The second contact plugs WC2 can be spaced apart from each other by a fifth distance DS5 on the third direction X3, as shown. Figure 4B As shown. The third distance DS3 and the fifth distance DS5 can be greater than the fourth distance DS4. The fifth distance DS5 can be equal to or less than the third distance DS3.

[0056] In an embodiment, the ends of the word lines WL can be formed to have different lengths, thereby limiting the first contact plug WC1 and the second contact plug WC2 to be on the same line along a third direction X3, for example, at the same position. The second contact plug WC2 can be offset from the first contact plug WC1 in the first direction X1. For example, a first distance between the separation unit region CR and the first contact plug WC1, measured parallel to the second direction X2, is less than a second distance between the separation unit region CR and the second contact plug WC2, measured parallel to the second direction X2. That is, according to an embodiment, the first contact plug WC1 and the second contact plug WC2 can be arranged in a zigzag shape, and in some embodiments, they can be spaced apart along the first direction X1. The first direction X1 can form an angle of less than 90 degrees, less than 60 degrees, or less than 45 degrees relative to the third direction X3, and the first direction X1 can form an angle of less than 90 degrees relative to the fourth direction X4. Therefore, by increasing the spacing between the first contact plug WC1 and the second contact plug WC2, the likelihood of short circuits or bridging problems occurring between the first contact plug WC1 and the second contact plug WC2 can be reduced.

[0057] Furthermore, the first contact plug WC1 and the second contact plug WC2 can be formed to have different depths from each other. In an embodiment, since the first height LV1 of the bottom surface forming the first contact plug WC1 is higher than the second height LV2 of the top surface forming the second residual conductive pattern 153r of the adjacent word line WL, the possibility of short circuit or bridging problems between the first contact plug WC1 and the adjacent word line WL can be limited.

[0058] Figure 7A and Figure 7B This is a plan view of a semiconductor memory device according to an embodiment.

[0059] Reference Figure 7A and Figure 7B The substrate 100 may include a first boundary region INT1, a cell region CR, and a second boundary region INT2 sequentially disposed in a fourth direction X4. A word line WL may extend through the cell region CR in the fourth direction X4 and reach the first boundary region INT1 and the second boundary region INT2. In the first boundary region INT1, the shape and arrangement of the word line WL, the first contact plug WC1, and the second contact plug WC2 may be consistent with a reference. Figure 3A The described embodiments are essentially the same. In the second boundary region INT2, the first conductive pattern 152 of the word line WL may have a protrusion PP.

[0060] Reference Figure 7A The shape of the protrusions PP of the third character line WL(3) and the seventh character line WL(7) in the second boundary region INT2 can be the same as the shape of the protrusions PP of the second character line WL(2) and the sixth character line WL(6) in the first boundary region INT1. In the second boundary region INT2, compared with the second character line WL(2) to the fourth character line WL(4) and the sixth character line WL(6) to the eighth character line WL(8), the first character line WL(1) and the fifth character line WL(5) can extend to protrude in the fourth direction X4. The third contact plug WC3 can contact the ends of the third character line WL(3) and the seventh character line WL(7). The fourth contact plug WC4 can contact the ends of the first character line WL(1) and the fifth character line WL(5). The third contact plug WC3 and the fourth contact plug WC4 can be arranged in a Z-shape. For example, similar to the arrangement of the first contact plug WC1 and the second contact plug WC2 along the first direction X1, the third contact plug WC3 and the fourth contact plug WC4 can also be arranged along the first direction X1. Figure 7A As shown, the third distance between the third contact plug WC3 and the cell region CR can be less than the fourth distance between the fourth contact plug WC4 and the cell region CR. The width of the fourth contact plug WC4 in the third direction X3 can be greater than the width of the third contact plug WC3.

[0061] Reference Figure 7B The shape of the protrusions PP of the first character line WL(1) and the fifth character line WL(5) in the second boundary region INT2 can be the same as the shape of the protrusions PP of the second character line WL(2) and the sixth character line WL(6) in the first boundary region INT1. In the second boundary region INT2, compared with the first character line WL(1), the second character line WL(2), the fourth character line WL(4) to the sixth character line WL(6) and the eighth character line WL(8), the third character line WL(3) and the seventh character line WL(7) can extend in the fourth direction X4. The third contact plug WC3 can contact the ends of the first character line WL(1) and the fifth character line WL(5). The fourth contact plug WC4 can contact the ends of the third character line WL(3) and the seventh character line WL(7). The third contact plug WC3 and the fourth contact plug WC4 can be arranged in a Z-shape. For example, similar to the arrangement of the first contact plug WC1 and the second contact plug WC2 along the first direction X1, the third contact plug WC3 and the fourth contact plug WC4 can also be arranged along the first direction X1. Figure 7B As shown, the third distance between the third contact plug WC3 and the cell region CR can be less than the fourth distance between the fourth contact plug WC4 and the cell region CR. The width of the fourth contact plug WC4 in the third direction X3 can be greater than the width of the third contact plug WC3.

[0062] This specification describes a structure with eight word lines (WL) as an example, but this application is not limited to this example. The number of word lines (WL) can be nine or more, and refer to... Figures 2A to 7B The shape and arrangement of the described word line WL and contact plugs WC1 to WC4 can be repeated along the third direction X3.

[0063] Figure 8A It is along Figure 2A The cross-sectional view taken from line C-C'. Figure 8B It is along Figure 2A The cross-sectional view taken by line D-D'. Figure 8C It is along Figure 2A The cross-sectional view taken from line E-E'.

[0064] Reference Figure 2A , Figure 3A , Figures 8A to 8C The first doped region 3d can be disposed in the central region of each of the active regions AC and DA, and the second doped region 3b can be disposed in the edge region of each of the active regions AC and DA. The first doped region 3d and the second doped region 3b can be doped with dopants of a different conductivity type than that of the substrate 100. For example, the substrate 100 can be doped with a p-type dopant, while the first doped region 3d and the second doped region 3b can be doped with an n-type dopant.

[0065] The lower insulating layer 121 may be disposed on the active region AC of the unit. The lower insulating layer 121 may be formed of or include at least one of silicon oxide, silicon nitride, or silicon oxynitride, and may have a single-layer or multi-layer structure.

[0066] Bit lines BL can be disposed in cell regions CR and on the lower insulating layer 121. Bit lines BL can extend in a third direction X3 and can be spaced apart from each other in a second direction X2. Dummy patterns DPP can be disposed in dummy regions DR and on the lower insulating layer 121. Dummy patterns DPP can extend in a third direction X3 and can be spaced apart from bit lines BL. The width of dummy patterns DPP can be greater than the width of bit lines BL, wherein the width is measured along the second direction X2. Each of bit lines BL and dummy patterns DPP can include a third conductive pattern 132, a fourth conductive pattern 133, and a fifth conductive pattern 134 stacked sequentially. The third conductive pattern 132 and the fourth conductive pattern 133 can be formed of doped polysilicon. The fifth conductive pattern 134 can be formed of a metallic material (e.g., tungsten). A second capping pattern 136 can be disposed on bit lines BL and dummy patterns DPP. The second capping pattern 136 can be formed of silicon nitride. The side surfaces of bit lines BL and dummy patterns DPP can be covered by spacer patterns SP, respectively. The spacer pattern SP may have a multilayer structure comprising three or more layers (e.g., including at least one silicon nitride layer and at least one silicon oxide layer). Alternatively, the spacer pattern SP may include an air gap region.

[0067] Reference Figure 8A and Figure 8B A bit line contact plug DC can be configured to penetrate the lower insulating layer 121 and the third conductive pattern 132, and connect the first doped region 3d to the fourth conductive pattern 133 of the bit line BL. The bit line contact plug DC can be formed or include at least one of doped polysilicon, tungsten, or titanium. The dummy pattern DPP can be electrically separated from the first doped region 3d through the lower insulating layer 121, such as... Figure 8C As shown.

[0068] Reference Figure 8B The storage contact plugs BC can be located between bit lines BL and can contact the second doped region 3b. The storage contact plugs BC can be formed of or include at least one of doped polysilicon, tungsten, or titanium. In embodiments, multiple storage contact plugs BC can be arranged in an island pattern (e.g., each storage contact plug BC is located between bit lines BL in the fourth direction X4), and these island patterns are arranged two-dimensionally in the third direction X3 and the fourth direction X4. Figure 3AThe first separation insulation pattern 240 may be located between bit lines BL and between storage contact plugs BC. The first separation insulation pattern 240 may be formed of or include at least one of silicon oxide or silicon nitride.

[0069] Reference Figure 8B The bonding pads LN may be located on the storage contact plug BC. The bonding pads LN may be formed of or comprise a metallic material (e.g., tungsten). A portion of the bonding pads LN may cover the top surface of the second capping pattern 136 on the bit line BL. In embodiments, multiple bonding pads LN may be provided and may be in an island pattern arranged two-dimensionally in the third direction X3 and the fourth direction X4. When viewed in plan view, the bonding pads LN may be arranged in a honeycomb pattern. An interlayer insulating layer 250 may be provided between the bonding pads LN to separate them from each other.

[0070] The data storage pattern DSP can be disposed on the bonding pad LN. The data storage pattern DSP can be electrically connected to the bonding pad LN. The data storage pattern DSP can be a capacitor including a bottom electrode, a dielectric layer, and a top electrode. In this case, the semiconductor memory device can be a dynamic random access memory (DRAM) device. Alternatively, the data storage pattern DSP can include a magnetic tunnel junction pattern. In this case, the semiconductor memory device can be a magnetic random access memory (MRAM) device. The data storage pattern DSP can be formed of, or include, a phase change material or a variable resistance material. In this case, the semiconductor memory device can be a phase change random access memory (PRAM) device or a resistive RAM (ReRAM) device. In embodiments, each of the data storage pattern DSPs can include various structures and / or materials capable of storing data.

[0071] Figures 9A to 17A The manufacturing process is shown sequentially. Figure 2A A planar diagram of the fabrication process for a planar semiconductor memory device. Figure 9B , Figure 11B , Figure 12B , Figure 13B , Figure 14B , Figure 15B , Figure 16B and Figure 17B It is along Figure 9A and Figures 11A to 17A The cross-sectional view taken by line A1-A1' in the diagram. Figure 9C , Figure 11C , Figure 12C , Figure 13C , Figure 14C , Figure 15C , Figure 16C and Figure 17CIt is along Figure 9A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A The cross-sectional view taken from line A2-A2' in the diagram. Figure 9D , Figure 10B , Figure 11D , Figure 12D , Figure 13D , Figure 14D , Figure 15D , Figure 16D and Figure 17D It is along Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A and Figure 17A The cross-sectional view taken from lines B1-B1' and B2-B2'.

[0072] Reference Figures 9A to 9D A substrate 100 may be provided. The substrate 100 may include a cell region CR and a boundary region INT arranged parallel to each other in the second direction X2. The boundary region INT may be located in... Figure 1 The area shown is between the cell region CR and the surrounding region PR. The boundary region INT may include a dummy region DR adjacent to the cell region CR.

[0073] The substrate 100 can be etched to form trenches defining active regions AC and DA. A first device isolation portion 20c and a second device isolation portion 20p can be formed by filling the trenches with an insulating material. The first device isolation portion 20c and the second device isolation portion 20p can be formed in the substrate 100. The first device isolation portion 20c can be formed in the cell region CR and the dummy region DR to define the cell active region AC and the dummy active region DA. The cell active region AC and the dummy active region DA can extend in a first direction X1 and can be spaced apart from each other.

[0074] The second device isolation portion 20p may be disposed in the boundary region INT to define the boundary between the cell region CR and the peripheral region PR. The first device isolation portion 20c may include a first insulating pad 21a, a first gap fill pattern 21b, and a second gap fill pattern 22a. The second device isolation portion 20p may include a second insulating pad 21, a third insulating pad 22, and a second gap fill pattern 23. The first insulating pad 21a, the first gap fill pattern 21b, the second insulating pad 21, and the second gap fill pattern 23 may be formed of the same insulating material (e.g., silicon oxide) or comprise the same insulating material. The second gap fill pattern 22a and the third insulating pad 22 may be formed of the same material (e.g., silicon nitride) or comprise the same material. The second gap fill pattern 22a may be formed as a plurality of island patterns, which, when viewed in plan view, are located between the cell active regions AC. The first insulating pad 21a may be connected to the first gap fill pattern 21b and the second insulating pad 21. When viewed in plan view, the second insulating pad 21 may extend in the third direction X3 and may have an uneven side surface. For example, as Figure 9A As shown, the second insulating pad 21 can be formed with a non-planar side surface, for example, it can have a rounded portion, a curved portion, a straight portion, etc.

[0075] Figure 9B The cross section represents along Figure 10A The cross section intercepted by line A1-A1'. Figure 9C The cross section represents along Figure 10B The cross-section intercepted by line A2-A2'. (Refer to...) Figure 9B , Figure 9C , Figure 10A and Figure 10BA line mask pattern MK1 can be formed on the substrate 100. The line mask pattern MK1 may include a first line mask pattern MK1 (1) to a ninth line mask pattern MK (9), which are sequentially arranged in a third direction X3 and spaced apart from each other. The line mask pattern MK1 may extend in a second direction X2 to the boundary region INT to intersect with the cell region CR. The line mask pattern MK1 may be formed using a dual patterning technique (DPT) or a quadruple patterning technique (QPT). The ends of some of the line mask patterns MK1 may be connected to each other in the boundary region INT. The line mask pattern MK1 may be formed of a material that has etch selectivity relative to the substrate 100 and the first device isolation portion 20c and the second device isolation portion 20p. The line mask pattern MK1 may be formed to intersect with the active regions AC and DA. Three adjacent line mask patterns MK1 may overlap with one of the active regions AC and DA. For example, three adjacent line mask patterns MK1(1), MK1(2), and MK1(3) can overlap together with a whole of one of the cell active regions AC and a whole of one of the dummy active regions DA.

[0076] Reference Figure 11A and Figure 11B The first cover mask pattern MK2 can be disposed on the boundary region INT to cover the ends of the line mask pattern MK1. When viewed in plan view, the side surface MK2_S of the first cover mask pattern MK2 faces the cell region CR and may include a recess MK2_R recessed in the second direction X2. The recess MK2_R can expose the space between the ends of the fourth line mask pattern MK1 (4) and the fifth line mask pattern MK1 (5), as well as the space between the ends of the eighth line mask pattern MK1 (8) and the ninth line mask pattern MK1 (9). The first cover mask pattern MK2 can be a photoresist pattern. Since the sixth distance between the recesses MK2_R of the first cover mask pattern MK2 (e.g., where the sixth distance is the distance between adjacent recesses MK2_R in the third direction X3) is greater than the seventh distance between the line mask patterns MK1 (e.g., where the seventh distance is the distance between adjacent line mask patterns MK1 in the third direction X3), the first cover mask pattern MK2 can be easily formed without the use of EUV exposure process.

[0077] Reference Figures 12A to 12DThe groove G can be formed by etching the substrate 100 and the first device isolation portion 20c and the second device isolation portion 20p using a line mask pattern MK1 and a first cover mask pattern MK2 as etching masks. The groove G may include a first groove G (1) to an eighth groove G (8), which are placed sequentially and spaced apart from each other in the third direction X3. Due to the recess MK2_R of the first cover mask pattern MK2, the fourth groove G (4) and the eighth groove G (8) can be formed to extend further in the second direction X2 compared with the first groove G (1) to the third groove G (3) and the fifth groove G (5) to the seventh groove G (7). For example, since the fourth groove G (4) and the eighth groove G (8) extend to the corresponding recess MK2_R, the extension distance of the fourth groove G (4) and the eighth groove G (8) can be longer than the extension distance of the first groove G (1) to the third groove G (3) and the fifth groove G (5) to the seventh groove G (7). The groove G can be formed in the active regions AC and DA. By adjusting the etching selectivity of the substrate 100 and the first device isolation portion 20c and the second device isolation portion 20p during the etching process, the first device isolation portion 20c and the second device isolation portion 20p can be etched at a faster etching rate than the substrate 100. Therefore, on the bottom surface of the groove G, the substrate 100 can be formed in a shape that protrudes upward relative to the first device isolation portion 20c and the second device isolation portion 20p.

[0078] Reference Figures 13A to 13D By removing the line mask pattern MK1 and the first cover mask pattern MK2, the top surfaces of the substrate 100, the first device isolation portion 20c, and the second device isolation portion 20p can be exposed.

[0079] Reference Figures 14A to 14D A first conductive layer can be formed on the substrate 100 to fill the groove G, and an etch-back process can be performed on the first conductive layer to form a first conductive pattern 152 in the groove G. The first conductive layer can be formed of, for example, at least one of tungsten and titanium nitride, or include, for example, at least one of tungsten and titanium nitride.

[0080] Reference Figures 15A to 15DA second overlay mask pattern MK3 can be formed on the boundary region INT to cover a portion of the first conductive pattern 152. The second overlay mask pattern MK3 may include an overlay linear portion CLP extending in the third direction X3 and an overlay protrusion CPP extending from the overlay linear portion CLP to protrude in the second direction X2. The overlay linear portion CLP may cover the middle or central region of each of the first conductive patterns 152 in the boundary region INT. In the boundary region INT, the overlay protrusion CPP may be formed to cover the ends of the second groove G(2) and the sixth groove G(6), and expose the ends of the first groove G(1), the third groove G(3) to the fifth groove G(5), the seventh groove G(7), and the eighth groove G(8). Therefore, the overlay protrusion CPP may be formed to cover some, but not all, of the ends of the first conductive pattern 152.

[0081] Reference Figures 16A to 16D The first conductive pattern 152 can be etched using the second overlay mask pattern MK3 as an etching mask, forming a line portion LP and a protrusion PP in the first conductive pattern 152. The line portion LP and the protrusion PP can be configured to have the same shape as described above, such that, as a result of etching, the thickness of the line portion LP can be reduced, while the protrusion PP is not etched. After etching the line portion LP, the second overlay mask pattern MK3 can be removed.

[0082] Reference Figures 17A to 17D A second conductive layer can be stacked on the first conductive pattern 152, and an etch-back process can be performed on the second conductive layer to form a second conductive pattern 153 and a second residual conductive pattern 153r. The second conductive pattern 153 and the second residual conductive pattern 153r can expose the upper parts of the side surfaces SW1 and SW2 of the protrusions PP of the first conductive pattern 152.

[0083] Return to reference Figures 2A to 8C This can form a first capping pattern 154, a bit line BL, an interlayer insulation layer 250, and a first contact plug WC1 and a second contact plug WC2. For example... Figure 2A , Figure 4A and Figure 4B As shown, because the distance between the first contact plug WC1 and the second contact plug WC2 is relatively large, the process margin for forming the first contact plug WC1 and the second contact plug WC2 can be increased, thereby reducing process failures. Specifically, since the other word lines WL are not located near the second contact plug WC2, the second contact plug WC2 can be formed to be wider than the first contact plug WC1. The first contact plug WC1 and the second contact plug WC2 can be formed simultaneously or through different process steps.

[0084] In the semiconductor memory device according to the embodiment, word lines of different lengths can be formed in the boundary region, thus the contact plugs can be formed in a Z-shape. The distance between the contact plugs can be greater than the distance between the word lines, in which case bridging or short-circuit problems can be prevented. Furthermore, the contact plugs can be formed with different depths, in which case bridging or short-circuit problems can be prevented more effectively. Therefore, the reliability of the semiconductor memory device can be improved.

[0085] In semiconductor device manufacturing methods, because the distance between contact plugs is greater than the distance between word lines, process margins can be increased and process defects reduced. Consequently, manufacturing yield can be improved.

[0086] While exemplary embodiments have been specifically shown and described, those skilled in the art will understand that changes in form and detail may be made therein without departing from the spirit and scope of the appended claims. Figures 1 to 8C Various combinations of embodiments are possible.

Claims

1. A semiconductor memory device, comprising: The substrate includes unit regions and boundary regions; as well as A first character line, a second character line, a third character line, a fourth character line, a fifth character line, a sixth character line, a seventh character line, and an eighth character line are disposed in the substrate to intersect with the unit region and extend to the boundary region in a first direction. The first, second, third, fourth, fifth, sixth, seventh, and eighth character lines are sequentially arranged in a second direction perpendicular to the first direction, and are arranged in the following order: first character line, then second character line, then third character line, then fourth character line, then fifth character line, then sixth character line, then seventh character line, and finally eighth character line. In the boundary region, when viewed from a plan view, the distance between the fourth and eighth character lines extending in the first direction is greater than the distance between the first, second, third, fifth, sixth, and seventh character lines extending in the first direction.

2. The semiconductor memory device according to claim 1, wherein, Each of the first, second, third, fourth, fifth, sixth, seventh, and eighth character lines includes a first conductive pattern. The first conductive pattern includes: a line portion extending through the unit region and into the boundary region; and a protrusion disposed on the line portion in the boundary region. Among the first, third, fourth, fifth, seventh, and eighth letter lines, when viewed from a plan view, the protrusion has a first length in the first direction. In the second and sixth letter lines, when viewed from a plan view, the protrusion has a second length in the first direction, and The second length is greater than the first length.

3. The semiconductor memory device according to claim 2, wherein, In each of the first, second, third, fourth, fifth, sixth, seventh, and eighth character lines, the protrusion has a first side surface adjacent to the unit region and a second side surface opposite to the first side surface. When viewed from a plan view, the first side surfaces of the protrusions of the first, third, fourth, fifth, seventh, and eighth letter lines are aligned along the second direction, and In the plan view, the second side surface of the protrusion of the second character line and the sixth character line is not aligned with the second side surface of the protrusion of the first character line, the third character line, the fourth character line, the fifth character line, the seventh character line and the eighth character line along the second direction.

4. The semiconductor memory device according to claim 3, wherein, Each of the first character line, the second character line, the third character line, the fourth character line, the fifth character line, the sixth character line, the seventh character line, and the eighth character line further includes a second conductive pattern, which is located on the line portion of the first conductive pattern and contacts the first side surface of the protrusion.

5. The semiconductor memory device according to claim 4, wherein, Each of the first character line, the second character line, the third character line, the fourth character line, the fifth character line, the sixth character line, the seventh character line, and the eighth character line further includes a second residual conductive pattern, which is located on the line portion of the first conductive pattern, contacts the second side surface of the protrusion, and is spaced apart from the second conductive pattern.

6. The semiconductor memory device according to claim 5, wherein, The first conductive pattern is formed of a first conductive material, and The second conductive pattern and the second remaining conductive pattern are formed of a second conductive material that is different from the first conductive material.

7. The semiconductor memory device according to claim 4, wherein, The top surface of the protrusion is at a first height, and The top surface of the second conductive pattern is at a second height that is lower than the first height.

8. The semiconductor memory device according to claim 1, further comprising: A first contact plug is disposed on the boundary region and contacts the ends of the second and sixth letter lines; as well as The second contact plug is disposed on the boundary region and contacts the ends of the fourth and eighth letter lines. Specifically, when viewed from a plan view, the second contact plug is offset from the first contact plug relative to the first direction.

9. The semiconductor memory device according to claim 8, wherein, The first distance between the first contact plug and the unit region is less than the second distance between the second contact plug and the unit region.

10. The semiconductor memory device according to claim 8, wherein, The bottom surface of the first contact plug is at a first height, and The bottom surface of the second contact plug is at a second height that is lower than the first height.

11. The semiconductor memory device according to claim 8, wherein, The first contact plug has a first width in the second direction, and The second contact plug has a second width in the second direction that is greater than the first width.

12. The semiconductor memory device according to claim 8, wherein, The second contact plug contacts the top and side surfaces of the ends of the fourth and eighth letter lines.

13. The semiconductor memory device according to claim 8, wherein, Each of the first, second, third, fourth, fifth, sixth, seventh, and eighth character lines comprises a first conductive pattern and a second conductive pattern stacked sequentially, and The second contact plug extends through the second conductive pattern of the fourth and eighth letter lines and contacts the top surface of the first conductive pattern.

14. A semiconductor memory device, comprising: The substrate includes unit regions and boundary regions; The first character line, the second character line, the third character line, the fourth character line, the fifth character line, the sixth character line, the seventh character line, and the eighth character line are disposed in the substrate, intersect with the unit region, and extend to the boundary region in a first direction; The first contact plug is located on the boundary region and contacts the ends of the second and sixth letter lines; as well as The second contact plug is located on the boundary region and contacts the ends of the fourth and eighth letter lines. The bottom surface of the first contact plug is at a first height, which is different from the second height of the bottom surface of the second contact plug.

15. The semiconductor memory device according to claim 14, wherein, Each of the first, second, third, fourth, fifth, sixth, seventh, and eighth character lines includes a first conductive pattern. The first conductive pattern includes: a line portion extending through the unit region and into the boundary region; and a protrusion disposed on the line portion in the boundary region. Among the first, third, fourth, fifth, seventh, and eighth letter lines, when viewed from a plan view, the protrusion has a first length in the first direction. In the second and sixth letter lines, when viewed from a plan view, the protrusion has a second length in the first direction, and The second length is greater than the first length.

16. The semiconductor memory device according to claim 15, wherein, In each of the first, second, third, fourth, fifth, sixth, seventh, and eighth character lines, the protrusion has a first side surface adjacent to the unit region and a second side surface opposite to the first side surface. When viewed from a plan view, the first side surfaces of the protrusions of the first, third, fourth, fifth, seventh, and eighth letter lines are aligned with each other along a second direction perpendicular to the first direction, and In the plan view, the second side surface of the protrusion of the second character line and the sixth character line is not aligned with the second side surface of the protrusion of the first character line, the third character line, the fourth character line, the fifth character line, the seventh character line and the eighth character line along the second direction.

17. A semiconductor memory device, comprising: The substrate includes a first boundary region, a cell region, and a second boundary region arranged along a first direction; A device isolation layer is disposed in the substrate, covering the first boundary region and the second boundary region, and defining an active region in the cell region, wherein the active region extends in a second direction perpendicular to the first direction; A first character line, a second character line, a third character line, a fourth character line, a fifth character line, a sixth character line, a seventh character line, and an eighth character line are disposed in the substrate and extend in the first direction through the cell region into the first boundary region and the second boundary region. The first character line, the second character line, the third character line, the fourth character line, the fifth character line, the sixth character line, the seventh character line, and the eighth character line extend in the first direction through the active region. Impurity regions are located in the active region; Data storage pattern, connected to one of the impurity regions; Bit lines are connected to another one in the impurity region and extend upward in a third direction perpendicular to the first and second directions; A first contact plug, on the first boundary region, contacts the ends of the second and sixth letter lines; and The second contact plug contacts the ends of the fourth and eighth letter lines on the first boundary region. Specifically, when viewed from a plan view, the second contact plug is offset from the first contact plug relative to the first direction.

18. The semiconductor memory device of claim 17, further comprising: The third contact plug is in contact with the ends of the first and fifth letter lines on the second boundary region; as well as The fourth contact plug, on the second boundary region, contacts the ends of the third and seventh letter lines. Specifically, when viewed from a plan view, the third contact plug is offset from the fourth contact plug relative to the first direction.

19. The semiconductor memory device according to claim 17, wherein, In the plan view, the distance by which the fourth and eighth character lines on the first boundary region protrude from the unit region to the first boundary region is different from that of the first, second, third, fifth, sixth, and seventh character lines.

20. The semiconductor memory device according to claim 17, wherein, Each of the first, second, third, fourth, fifth, sixth, seventh, and eighth character lines includes a first conductive pattern. The first conductive pattern includes: a line portion extending through the unit region and the first boundary region; and a protrusion disposed on the line portion in the first boundary region. Among the first, third, fourth, fifth, seventh, and eighth letter lines, when viewed from a plan view, the protrusion has a first length in the first direction. In the second and sixth letter lines, when viewed from a plan view, the protrusion has a second length in the first direction, and The second length is greater than the first length.

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