Semiconductor device and method of forming the same

Abstract

The application discloses a semiconductor device and a forming method thereof. The semiconductor device comprises a stack structure, a bit line structure and a word line structure. The stack structure comprises insulating layers and dielectric layers which are alternately stacked. The bit line structure penetrates the stack structure along a stacking direction of the stack structure. The word line structure is located between two adjacent insulating layers. The word line structure comprises gate layers and a word line. The gate layers are arranged around the sidewalls of the bit line structure. The word line extends along a first direction. The word line is in contact with the gate layers. The first direction is perpendicular to the stacking direction. A channel layer is located between two adjacent insulating layers. The channel layer is located between the word line structure and the bit line structure and between the word line structure and the dielectric layer. Since the channel layer covers the inner side and the outer side of the gate layer, the gate control ability of the gate layer to the channel layer can be improved, thereby providing a structural basis for high-speed reading and writing of the semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for forming the same. Background Technology

[0002] As semiconductor storage technology develops towards high density and low power consumption, traditional two-dimensional dynamic random access memory (2D DRAM) has faced a bottleneck in size miniaturization. 3D DRAM has become a key direction to break through the storage density limit, but insufficient gate control capability has become the core problem restricting its electrical performance improvement. Currently, 3D DRAM research is still in its early stages. Most existing solutions are of the Gate-All-Around (GAA) type, which has an electric field blind zone due to the way the gate covers the channel. This results in limited gate control efficiency or insufficient gate control capability, making it impossible to achieve precise control of channel carriers. Summary of the Invention

[0003] This application provides a semiconductor device and a method for forming the same, to improve the gate control capability of the gate layer over the channel layer.

[0004] This application provides a semiconductor device, including: a stacked structure including alternately stacked insulating layers and dielectric layers; a bit line structure extending through the stacked structure along its stacking direction; a word line structure located between two adjacent insulating layers, the word line structure including a gate layer and a word line, the gate layer being disposed around the sidewall of the bit line structure, the word line extending along a first direction and contacting a plurality of gate layers, the first direction being perpendicular to the stacking direction; and a channel layer located between two adjacent insulating layers, the channel layer being located between the word line structure and the bit line structure, and between the word line structure and the dielectric layer.

[0005] In some embodiments, the channel layer includes: a first sub-channel layer surrounding the sidewall surface of the bit line structure and located between the bit line structure and the word line structure; and a second sub-channel layer located between the word line structure and the dielectric layer; wherein the first sub-channel layer and the second sub-channel layer are also located between the word line structure and the adjacent insulating layer.

[0006] In some embodiments, each word line structure includes multiple word lines, which extend along a first direction and are spaced apart along a second direction, the second direction being perpendicular to the stacking direction and the first direction; multiple bit line structures are spaced apart in rows along the first direction, a gate layer is disposed around a bit line structure, two rows of bit line structures are disposed between two adjacent word lines, and a word line contacts a row of gate layers.

[0007] In some embodiments, a gate insulating structure is further included, the gate insulating structure comprising: a first gate insulating layer located between the first sub-channel layer and the word line structure; and a second gate insulating layer located between the second sub-channel layer and the word line structure.

[0008] In some embodiments, the system further includes: a capacitor structure extending through the stacking structure along the stacking direction; a plurality of capacitor structures are arranged in rows at intervals along the first direction; and two rows of capacitor structures are disposed between two adjacent rows of bit line structures; wherein a second sub-channel layer to which one capacitor structure is connected to one bit line structure is correspondingly connected along a third direction, the third direction being perpendicular to the stacking direction and intersecting the first direction.

[0009] In some embodiments, the capacitor structure and the channel layer connected along the third direction constitute a memory cell, and a plurality of memory cells are arranged at intervals along the first direction, wherein the angle between the third direction and the first direction is an acute angle.

[0010] In some embodiments, the adjacent rows of the bit line structures are staggered in the first direction between adjacent rows of the capacitor structures.

[0011] In some embodiments, the capacitor structure includes: a first electrode extending through the stacked structure along the stacking direction; a second electrode located between two adjacent insulating layers and disposed around the first electrode; and a dielectric layer located between the first electrode and the second electrode; wherein the sidewall of the second electrode is in contact with the sidewall of the second sub-channel layer.

[0012] In some embodiments, the dielectric layer includes a first surface that contacts the sidewall of the second electrode, the insulating layer includes a second surface that contacts the dielectric layer, the first surface is recessed relative to the second surface to form a groove between two adjacent insulating layers; the second electrode is located on the inner wall of the groove, and at least a portion of the dielectric layer is located within the groove.

[0013] In some embodiments, the sidewall of the second electrode includes an arcuate sidewall and a connecting sidewall connected to each other, the connecting sidewall connecting to the second sub-channel layer, and the distance from the connecting sidewall to the first electrode being less than the distance from the arcuate sidewall to the first electrode.

[0014] This application embodiment also provides a method for forming a semiconductor device, comprising: forming a stacked structure, the stacked structure including alternately stacked insulating layers and dielectric layers; forming a bit line via penetrating the stacked structure along a stacking direction; forming a word line isolation trench penetrating the stacked structure along a stacking direction, the word line isolation trench extending along a first direction and located on one side of the bit line via along a second direction, the first direction and the second direction being perpendicular to each other and both perpendicular to the stacking direction; etching a portion of the dielectric layer through the word line isolation trench to form a trench, the trench including a gate trench surrounding the bit line via and a word line trench extending along the first direction, the word line trench being located on one side of the gate trench along the second direction and communicating with a plurality of gate trenches; forming a channel layer on the inner wall of the gate trench and the word line trench; and forming a word line structure filling the trench on the surface of the channel layer.

[0015] In some embodiments, the method of forming the trench includes: etching a portion of the dielectric layer through the bit line via to form the gate trench; forming a first sacrificial layer in the gate trench; forming a second sacrificial layer in the bit line via; removing a portion of the dielectric layer through the word line isolation trench to form the word line trench exposing the first sacrificial layer; and removing the first sacrificial layer through the word line trench.

[0016] In some embodiments, the method of forming the word line structure includes: forming an initial word line structure in the trench and at least a portion of the word line isolation groove; performing a back etching process on the initial word line structure to remove a portion of the initial word line structure located in the word line isolation groove, thereby forming a word line structure located in the trench.

[0017] In some embodiments, the method further includes: forming an initial capacitor via through the stacked structure during the process of forming the bit line via; etching a portion of the dielectric layer through the initial capacitor via to form a groove, the groove communicating with the initial capacitor via to form a capacitor via; and forming a capacitor structure within the capacitor via, the capacitor structure being connected to the channel layer.

[0018] In some embodiments, the method of forming the capacitor structure includes: forming a second electrode on the inner wall of the groove; forming a dielectric layer in the groove and on the inner wall of the initial capacitor hole, the dielectric layer being located on the surface of the second electrode; and forming a first electrode on the surface of the dielectric layer.

[0019] In the semiconductor device of this application embodiment, since the word line extends along a first direction and contacts multiple gate layers, one word line can control multiple gate layers. The channel layer is located between the gate layer and the bit line structure, enabling electrical connection between the channel layer and the bit line structure. Since the channel layer is also located between the bit line structure and the dielectric layer, it covers the inner and outer sides of the gate layer, improving the gate control capability of the gate layer over the channel layer and providing a structural basis for high-speed read and write of the semiconductor device.

[0020] Other features and advantages of this application will be described in detail in the following detailed description section. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] To gain a more complete understanding of this application and its beneficial effects, the following description will be provided in conjunction with the accompanying drawings, wherein the same reference numerals in the following description denote the same parts.

[0023] Figure 1 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application; Figure 2 yes Figure 1 A schematic cross-sectional view of the semiconductor device at point A-A1; Figure 3 yes Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1; Figure 4 yes Figure 3 A top view of the semiconductor device at point C-C1; Figure 5 yes Figure 4 A three-dimensional structural diagram of a semiconductor device; Figure 6 This is a schematic flowchart of a method for forming a semiconductor device provided in some embodiments of this application; Figures 7 to 61 This is a schematic diagram of the semiconductor device during its formation process according to some embodiments of this application.

[0024] Explanation of reference numerals in the attached figures: 100. Semiconductor devices; 10. Stacked structure; 11. Insulating layer; 12. Dielectric layer; 121. First surface; 111. Second surface; 20. Bit line structure; 21. First conductive layer; 22. Second conductive layer; 23. Bit line via; 30. Word line structure; 31. Gate layer; 32. Word line; 34. Trench; 35. Gate trench; 36. Word line trench; 40. Channel layer; 41. First sub-channel layer; 42. Second sub-channel layer; 50. Character line isolation structure; 53. Character line isolation groove; 60. Capacitor structure; 61. First electrode; 611. Third conductive layer; 612. Fourth conductive layer; 62. Dielectric layer; 63. Second electrode; 63'. Initial second electrode; 63a. Arc-shaped sidewall; 63b. Connecting sidewall; 64. Initial capacitor hole; 65. Groove; 66. Capacitor hole; 71. First sacrificial layer; 72. Second sacrificial layer; 73. Third sacrificial layer; 80. Substrate; 90. Gate insulating structure; 91. First gate insulating layer; 92. Second gate insulating layer; X, first direction; Y2, second direction; Y1, third direction; Z, stacking direction. Detailed Implementation

[0025] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0026] Currently, research on 3D DRAM (3D Dynamic Random Access Memory) is still in its early stages. Most existing solutions are GAA (Gate-All-Around) type, which has an electric field blind zone due to the way the gate surrounds the channel. This results in limited gate control efficiency or insufficient gate control capability, making it impossible to achieve precise control of channel carriers.

[0027] Based on this, embodiments of this application provide a semiconductor device, including: a stacked structure including alternately stacked insulating layers and dielectric layers; a bit line structure extending through the stacked structure along its stacking direction; a word line structure located between two adjacent insulating layers, the word line structure including a gate layer and a word line, the gate layer being disposed around the sidewall of the bit line structure, the word line extending along a first direction and contacting a plurality of gate layers, the first direction being perpendicular to the stacking direction; and a channel layer located between two adjacent insulating layers, the channel layer being located between the word line structure and the bit line structure, and between the word line structure and the dielectric layer.

[0028] In the semiconductor device of this application embodiment, since the word line extends along a first direction and contacts multiple gate layers, one word line can control multiple gate layers. The channel layer is located between the gate layer and the bit line structure, enabling electrical connection between the channel layer and the bit line structure. Since the channel layer is also located between the bit line structure and the dielectric layer, it covers the inner and outer sides of the gate layer, improving the gate control capability of the gate layer over the channel layer and providing a structural basis for high-speed read and write of the semiconductor device.

[0029] The structure of the semiconductor device provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0030] Please see Figures 1 to 5 , Figure 1 This is a top view schematic diagram of the semiconductor device provided in some embodiments of this application. Figure 2 yes Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 3 yes Figure 1 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1. Figure 4 yes Figure 3 A top view of the semiconductor device at point C-C1. Figure 5 yes Figure 4 A three-dimensional structural diagram of a semiconductor device. It should be noted that... Figure 4 The specific membrane layers of the structure and the connections between the structures have been shown. Figure 5 The pattern filling of specific film layers is omitted, and only the overall three-dimensional structure of the semiconductor device 100 is shown.

[0031] The semiconductor device 100 includes a stacked structure 10, a bit line structure 20, and a word line structure 30. The stacked structure 10 includes alternately stacked insulating layers 11 and dielectric layers 12. The bit line structure 20 penetrates the stacked structure 10 along the stacking direction Z. The word line structure 30 is located between two adjacent insulating layers 11. The word line structure 30 includes a gate layer 31 and a word line 32. The gate layer 31 is disposed around the sidewall of the bit line structure 20. The word line 32 extends along a first direction X and contacts a plurality of gate layers 31. The first direction X is perpendicular to the stacking direction Z. A channel layer 40 is located between two adjacent insulating layers 11. The channel layer 40 is located between the word line structure 30 and the bit line structure 20, and between the word line structure 30 and the dielectric layer 12.

[0032] It should be noted that in this paper, the Z direction is used to represent the stacking direction of the insulating layer 11 and the dielectric layer 12, the extension direction of the word line 32 is the first direction X, and the direction perpendicular to X and Z is the second direction Y2.

[0033] The stacked structure 10 consists of alternating stacked insulating layers 11 and dielectric layers 12. The number of stacked layers is set according to the storage capacity requirements of 3D DRAM and is not specifically limited. The stacked structure 10 provides support and a foundation for the various functional structures of the device.

[0034] The insulating layer 11 primarily serves as an insulating layer to prevent signal interference or leakage between adjacent functional layers. The dielectric layer 12 also serves as an insulating layer and provides molding space and structural support for the channel layer 40 and capacitor structure 60. The insulating layer 11 may be made of silicon oxide, and the dielectric layer 12 may be made of silicon nitride.

[0035] Bit line structure 20, as the core conductive structure responsible for bit line signal transmission in 3D DRAM memory cell, runs through the entire stack structure 10 along the stacking direction Z, ensuring that the bit line signals of each layer of memory cell can be efficiently transmitted in the vertical direction.

[0036] In some embodiments, the bit line structure 20 may include a first conductive layer 21 and a second conductive layer 22, the second conductive layer 22 being disposed around the surface of the first conductive layer 21, and the second conductive layer 22 may reduce metal diffusion in the material of the first conductive layer 21. An exemplary material for the second conductive layer 22 includes titanium nitride, and an exemplary material for the first conductive layer 21 includes tungsten.

[0037] The word line structure 30, serving as the core structure for gate control signal transmission and gate regulation, is positioned between two adjacent insulating layers 11, thus occupying a portion of the space in the dielectric layer 12. The gate layer 31 employs a ring-shaped design, surrounding the sidewall of the bit line structure 20. Since the channel layer 40 is located between the word line structure 30 and the bit line structure 20, and between the word line structure 30 and the dielectric layer 12, it covers both the inner side (closer to the bit line structure 20) and the outer side (away from the bit line structure 20) of the gate layer 31. This enhances the gate control capability of the gate layer 31 over the channel layer 40, fundamentally solving the electric field dead zone problem inherent in traditional GAA structures and improving gate control accuracy. Furthermore, a single word line 32 can simultaneously achieve close contact with multiple gate layers 31, enabling synchronous transmission of gate control signals for multiple memory cells, simplifying array control logic, reducing signal transmission delay, and further optimizing gate control response efficiency. Correspondingly, a single word line 32 is simultaneously connected to the bit line structure 20 surrounded by multiple gate layers 31.

[0038] See Figure 4 In some embodiments, each word line structure 30 includes multiple word lines 32, which extend along the first direction X and are spaced apart along the second direction Y2. For example, Figure 4 The image shows two character lines 32 in a single character line structure 30. It can be understood that each character line structure 30 may include more character lines 32.

[0039] Multiple bit line structures 20 are arranged in rows at intervals along the first direction X. A gate layer 31 is disposed around a bit line structure 20. Two rows of bit line structures 20 and two rows of gate layers 31 are disposed between two adjacent word lines 32, and one word line 32 is in contact with one row of gate layers 31.

[0040] The channel layer 40, serving as a crucial channel for carrier transport, is positioned between two adjacent insulating layers 11 and tightly attached to the surface of the word line structure 30, ensuring that the gate electric field can act uniformly and omnidirectionally across the entire channel. Simultaneously, the channel layer 40 is precisely defined between the word line structure 30 and the bit line structure 20, and between the word line structure 30 and the dielectric layer 12, constructing a short-range carrier transport path of "bit line structure 20 - channel layer 40 - word line 32," reducing resistive losses during carrier transport and improving transport efficiency. Furthermore, this positional design of the channel layer 40 ensures close contact with the bit line structure 20, the word line structure 30, and the dielectric layer 12, guaranteeing the stability of the electrical connection and providing a structural basis for the interlocking contact with the subsequent capacitor structure 60, further optimizing the overall electrical performance of the device.

[0041] To further optimize the carrier transport efficiency and gate control response performance of the channel layer 40, the channel layer 40 includes a first sub-channel layer 41 and a second sub-channel layer 42. The two sub-channel layers 40 are integrally formed and seamlessly connected to form a complete channel layer, ensuring the continuity of carrier transport.

[0042] See Figure 4 The first sub-channel layer 41 is closely arranged around the sidewall surface of the bit line structure 20 and is precisely located between the bit line structure 20 and the word line structure 30. It is mainly used to realize the carrier transmission between the bit line structure 20 and the word line structure 30.

[0043] See Figure 2 and Figure 3 The first sub-channel layer 41 and the second sub-channel layer 42 also extend to the gap between the word line structure 30 and the adjacent insulating layer 11, i.e., the gap between the word line structure 30 and the insulating layer 11. Therefore, the channel layer 40 fully covers the gate layer 31 (i.e., the channel layer 40 is located on all surfaces of the gate layer 31), realizing a 3D DRAM architecture with a channel-all-around (CAA) structure, further enhancing the uniformity of gate control.

[0044] In this CAA structure, the channel layer 40 is directly disposed on the surface of the word line structure 30 and is in contact with the bit line structure 20 and the dielectric layer 12. This makes the channel layer 40 form a surface contact with the word line structure 30 and the bit line structure 20, rather than a point contact or line contact. This increases the contact area and effectively reduces the interlayer contact resistance. It not only ensures that the gate electric field can accurately act on the carrier transport path, but also reduces the energy loss during signal transmission. At the same time, it improves the stability of the electrical connection between each structural layer, avoids device read and write errors caused by poor contact, and ensures the working reliability of the 3D DRAM memory cell.

[0045] Furthermore, the channel layer 40 can contact the bit line structure 20 on the side closest to it, and can directly contact the capacitor structure 60 (mentioned below) on the side furthest from it, without requiring additional connection structures. This allows the bit line structure 20, channel layer 40, word line 32, and capacitor structure 60 of the 3D DRAM to form a compact integrated structure, further improving space utilization. Since there is no spatial interference between the structural layers and they are tightly fitted, the interlayer space of the stacked structure 10 is maximized, providing a reasonable structural space basis for the subsequent dense packing design of memory cells.

[0046] In some embodiments, the semiconductor device 100 further includes a gate insulating structure 90, which includes a first gate insulating layer 91 and a second gate insulating layer 92. The first gate insulating layer 91 is located between the first sub-channel layer 41 and the word line structure 30, and is used to achieve insulation isolation between the first sub-channel layer 41 and the word line structure 30, avoiding leakage caused by direct contact between the two. The second gate insulating layer 92 is located between the second sub-channel layer 42 and the word line structure 30, and is used to achieve insulation isolation between the second sub-channel layer 42 and the word line structure 30, ensuring that the gate electric field is only used to regulate carrier transport and does not cause direct conduction.

[0047] The gate insulation structure 90 uses a high-insulation material (such as silicon oxide) with a thickness controlled within a reasonable range to ensure both insulation performance and efficient penetration of the gate electric field through the insulating layer 11 to act on the channel layer 40, thus achieving a balance between gate control performance and insulation performance.

[0048] See Figure 4 and Figure 5 The semiconductor device 100 may further include a word line isolation structure 50, which extends through the entire stacked structure 10 along the Z-direction of the stacking direction and extends along the first direction X, consistent with the extension direction of the word line 32. The word line isolation structure 50 contacts the word line structure 30, enhancing the insulation effect between different layers of word line structures 30, and also utilizing the word line isolation grooves of the word line isolation structure 50 to form a channel layer 40 and a word line structure 30. Two word lines 32 are disposed between two adjacent word line isolation structures 50.

[0049] See Figure 4 The semiconductor device 100 further includes a capacitor structure 60 that extends through the stacked structure 10 along the stacking direction Z. Multiple capacitor structures 60 are arranged in rows at intervals along the first direction X, with two rows of capacitor structures 60 positioned between adjacent rows of bit line structures 20. Each capacitor structure 60 is connected to a corresponding bit line structure 20, and the capacitor structure 60 is in close contact with the second sub-channel layer 42 outside the corresponding bit line structure 20. The second sub-channel layer 42 enables signal coupling between the capacitor structure 60 and the word line structure 30 and bit line structure 20, ensuring efficient data transmission between the capacitor and the transistor, and improving data retention and read / write stability.

[0050] Each memory cell consists of a word line structure 30 (transistor gate), a channel layer 40 (transistor channel), a bit line structure 20 (transistor source / drain), and a capacitor structure 60. The transistor (composed of word line 32, channel layer 40, and bit line structure 20) controls the read / write operation of data, while the capacitor structure 60 stores charge (corresponding to data "1" or "0"), serving as the core for long-term data retention. When storing data "1", when an effective gate control voltage is applied to word line 32, the electric field of the gate layer 31 acts omnidirectionally on the channel layer 40, turning on the channel. The current signal of the bit line is coupled to the capacitor structure 60 through the channel layer 40, charging the capacitor and storing charge, corresponding to data "1". When storing data "0": when the gate control voltage of word line 32 is removed, the channel is cut off, and the capacitor cannot receive charge replenishment. If the capacitor already stores charge, it is released through leakage, resulting in a no-charge state corresponding to data "0".

[0051] In some embodiments, a capacitor structure 60 and a bit line structure 20 are connected to a second sub-channel layer 42 correspondingly along a third direction Y1, which is perpendicular to the stacking direction Z and intersects the first direction X. For example, the third direction Y1 intersects the first direction X perpendicularly or obliquely. In other words, the capacitor structure 60 and the channel layer 40 are correspondingly connected along the third direction Y1. Since the channel layer 40 (or the second sub-channel layer 42) is arranged around the bit line structure 20, that is, the position of the channel layer 40 is limited by the position of the bit line structure 20, it can also be said that the connected capacitor structure 60 and the bit line structure 20 are arranged along the third direction Y1.

[0052] In some embodiments, the capacitor structure 60 and the channel layer 40 connected along the third direction Y1 constitute a memory cell, and a plurality of memory cells are arranged at intervals along the first direction X, wherein the angle θ between the third direction Y1 and the first direction X is an acute angle. That is, the capacitor structure 60 and the channel layer 40 are obliquely connected to form a memory cell. From the positional relationship between the capacitor structure 60 and the bit line structure 20, it can be seen that the capacitor structure 60 and the bit line structure 20 are not aligned in the second direction Y2, that is, each capacitor structure 60 is obliquely arranged relative to the bit line structure 20 to which it is connected. Alternatively, it can be said that a row of capacitor structures 60 and a row of bit line structures 20 connected to them are misaligned along the first direction X. This oblique arrangement can compress the size occupied by the bit line structure 20 and the capacitor structure 60 in the second direction Y2, thus saving chip area and increasing storage density.

[0053] In some embodiments, the acute angle between the third direction Y1 and the first direction X is 55° to 65°. This limited angle range allows for a closer arrangement of the capacitor structure 60 and the bit line structure 20, thus maximizing the advantages of the oblique arrangement in saving chip area and increasing storage density.

[0054] In some embodiments, the acute angle between the third direction Y1 and the first direction X is 60°. 60° is the optimal angle for oblique arrangement, which can optimize the spacing between adjacent unit groups, save chip area to the maximum extent, and further improve storage density.

[0055] In some embodiments, adjacent rows of bit line structures 20 are staggered in the first direction X. This allows each row of structures (including bit line structures 20 and capacitor structures 60) to be staggered, fully utilizing the gaps between adjacent structures to increase the density of the arrangement and thus improve storage density. Furthermore, it reduces signal interference between adjacent capacitors, ensuring that the storage performance of each capacitor is not affected.

[0056] See Figure 2 The capacitor structure 60 includes a first electrode 61, a second electrode 63, and a dielectric layer 62. The first electrode 61 penetrates the stacked structure 10 along the stacking direction Z. The second electrode 63 is located between two adjacent insulating layers 11 and is disposed around the first electrode 61. The dielectric layer 62 is located between the first electrode 61 and the second electrode 63.

[0057] The dielectric layer 62 completely covers the surface of the first electrode 61, serving as the insulating medium of the capacitor to achieve insulation isolation between the first electrode 61 and the second electrode 63, while storing charge. The dielectric layer 62 is made of a high-k dielectric material, which can increase the capacitance and extend the data retention time within a limited space.

[0058] In this design, the sidewall of the second electrode 63 is in interlocking contact with the sidewall of the second sub-channel layer 42. This interlocking design maximizes the contact area between the second electrode 63 and the second sub-channel layer 42, improves the signal coupling efficiency between the capacitor and the transistor, ensures that data can be transmitted quickly and stably between the capacitor and the channel layer 40, and further optimizes the device's storage performance and gate control response speed.

[0059] The material of the first electrode 61 may include at least one of a metal and a metal nitride, and the material of the second electrode 63 may include at least one of a metal and a metal nitride. The materials of the first electrode 61 and the second electrode 63 may be the same or different. Figure 2 and Figure 3In this embodiment, the first electrode 61 includes a third conductive layer 611 and a fourth conductive layer 612, the fourth conductive layer 612 being disposed around the surface of the third conductive layer 611. An exemplary material for the third conductive layer 611 includes titanium nitride, and an exemplary material for the fourth conductive layer 612 includes tungsten. The material of the dielectric layer 62 may include a high dielectric constant material, such as at least one of alumina, zirconium oxide, and hafnium oxide.

[0060] In some embodiments, the dielectric layer 12 includes a first surface 121 that contacts the sidewall of the second electrode 63, and the insulating layer 11 includes a second surface 111 that contacts the dielectric layer 62. The first surface 121 is recessed relative to the second surface 111 to form a groove 65 located between two adjacent insulating layers 11. The second electrode 63 is located on the inner wall of the groove 65, and at least a portion of the dielectric layer 62 is located within the groove 65.

[0061] The shape of the groove 65 is precisely matched to the shape of the second electrode 63, providing dedicated space for the formation of the second electrode 63. The second electrode 63 is precisely located on the inner wall of the groove 65, forming a tight fit with the inner wall of the groove 65, maximizing the use of the space in the groove 65, increasing the effective area of ​​the second electrode 63, and thus improving the capacitance. In addition, at least a portion of the dielectric layer 62 is located within the groove 65, making close contact with the inner wall of the second electrode 63. This ensures that the dielectric layer 62 can completely cover the contact area between the second electrode 63 and the first electrode 61, avoiding leakage problems caused by incomplete coverage of the dielectric layer 62, and further improving the stability and storage performance of the capacitor structure 60.

[0062] To further optimize the mating contact effect between the second electrode 63 and the second sub-channel layer 42, and to increase the effective storage area of ​​the capacitor, the sidewall of the second electrode 63 adopts an irregular shape design, specifically including a connected arc-shaped sidewall 63a and a connecting sidewall 63b. The connecting sidewall 63b is specifically designed to connect to the second sub-channel layer 42, and its planar design allows for a tight fit with the surface of the second sub-channel layer 42, maximizing the contact area and improving signal coupling efficiency. The arc-shaped sidewall 63a is used to connect to the dielectric layer 62. The arc design increases the contact area between the second electrode 63 and the dielectric layer 62, thereby increasing the capacitance, while avoiding electric field concentration problems caused by sharp-angle structures and reducing the risk of leakage.

[0063] In some embodiments, the distance from the connecting sidewall 63b to the first electrode 61 is less than the distance from the arcuate sidewall 63a to the first electrode 61. That is, the connecting sidewall 63b is recessed inward relative to the arcuate sidewall 63a to achieve the interlocking contact between the second electrode 63 and the second sub-channel layer 42.

[0064] Accordingly, this application also provides a method for forming a semiconductor device, for forming the above-mentioned semiconductor device 100.

[0065] Please see Figure 6 , Figure 6 This is a schematic flowchart illustrating a method for forming a semiconductor device according to some embodiments of this application. The method for forming the semiconductor device includes: Step S1: Form a stacked structure, the stacked structure comprising alternately stacked insulating layers and dielectric layers; Step S2: Form bit line holes that penetrate the stack structure along the stacking direction of the stack structure; Step S3: Form a word line isolation groove that penetrates the stacking structure along the stacking direction of the stacking structure. The word line isolation groove extends along a first direction and is located on one side of the bit line hole along a second direction. The first direction and the second direction are perpendicular to each other and both are perpendicular to the stacking direction. Step S4: A portion of the dielectric layer is etched through the word line isolation trench to form a trench, the trench including a gate trench surrounding the bit line hole and a word line trench extending along the first direction, the word line trench being located on one side of the gate trench along the second direction and communicating with a plurality of the gate trenches; Step S5: Form a channel layer on the inner wall of the gate trench and the word line trench; Step S6: Form a letter line structure that fills the trench on the surface of the channel layer.

[0066] In the semiconductor device formation method provided in this application embodiment, word line trenches and gate trenches are formed through word line isolation trenches, and then a channel layer is formed through word line trenches and gate trenches. Subsequently, a word line structure that fills the trenches is formed on the surface of the channel layer, which can form a full coverage of the word line structure by the channel layer, which can improve the gate control capability of the gate layer on the channel layer and provide a structural basis for high-speed read and write of semiconductor devices.

[0067] The method for forming a semiconductor device provided in the embodiments of this application will be described below with reference to the accompanying drawings.

[0068] Please refer to 7 to Figure 61 , Figures 7 to 61 This is a schematic diagram of the semiconductor device during its formation process according to some embodiments of this application.

[0069] Step S1: Form a stacked structure 10, the stacked structure 10 comprising alternately stacked insulating layers 11 and dielectric layers 12.

[0070] See Figure 7 First, a substrate 80 is provided, and then an insulating layer 11 and a dielectric layer 12 are alternately formed on the substrate 80.

[0071] The substrate 80 can be a semiconductor substrate, such as a silicon (Si), germanium (Ge), SiGe substrate, silicon on insulator (SOI), or germanium on insulator (GOI). In other embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, and can also be a stacked structure, such as Si / SiGe.

[0072] The insulating layer 11 and the dielectric layer 12 have different etching selectivity. An exemplary material for the insulating layer 11 is silicon oxide, and an exemplary material for the dielectric layer 12 is silicon nitride. The formation process of the insulating layer 11 and the dielectric layer 12 includes a deposition process, which can employ, but is not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD) such as thermal oxidation, evaporation, sputtering, and other methods.

[0073] Step S2: Form a bit line hole 23 that penetrates the stack structure 10 along the stacking direction Z. See also Figures 8 to 10 .

[0074] in, Figure 8 This is a schematic diagram of the cross-sectional structure of a semiconductor device along the XY1 direction at the dielectric layer. Figure 9 yes Figure 8 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 10 yes Figure 8 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0075] In some embodiments, the method of forming the semiconductor device further includes forming an initial capacitor hole 64 penetrating the stacked structure 10 during the process of forming the bit line via 23. The initial capacitor hole 64 is used to form a capacitor structure 60, and the method of forming the capacitor structure 60 will be described below.

[0076] Bit line via 23 and initial capacitor via 64 are formed in the same etching process to prevent alignment problems caused by step etching and to simplify the process. The etching process may include anisotropic etching, such as dry etching, which can precisely control the etching direction and depth. Therefore, the initial capacitor via 64 and the bit line via 23 have the same depth. Figure 8 The arrangement of the initial capacitor hole 64 and the bit line hole 23 is shown. The arrangement can be determined based on the positional relationship between the final capacitor structure 60 and the bit line structure 20.

[0077] Step S3: Form a word line isolation groove 53 that penetrates the stacking structure 10 along the stacking direction Z. The word line isolation groove 53 extends along the first direction X and is located on one side of the bit line hole 23 along the second direction Y2. The first direction X and the second direction Y2 are perpendicular to each other and both are perpendicular to the stacking direction Z.

[0078] Step S4: A portion of the dielectric layer 12 is etched through the word line isolation trench 53 to form a trench 34. The trench 34 includes a gate trench 35 surrounding the bit line via 23 and a word line trench 36 extending along the first direction X. The word line trench 36 is located on one side of the gate trench 35 along the second direction Y2 and communicates with the plurality of gate trenches 35. See also Figures 11 to 30 .

[0079] To ensure the forming accuracy of the gate trench 35 and word line trench 36 and to avoid damage to the bit line hole 23 and insulating layer 11 during the etching process, the trench 34 is formed by adopting a sacrificial layer assisted etching process. Through the protective effect of the sacrificial layer, the trench 34 is accurately formed. The trench 34 formation method includes the following steps.

[0080] See Figures 11 to 16 A portion of the dielectric layer 12 is etched through the bit line hole 23 to form a gate trench 35.

[0081] See Figures 11 to 13 Before forming the gate trench 35, a third sacrificial layer 73 is formed within the initial capacitor hole 64. Figure 12 yes Figure 11 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 13 yes Figure 11 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0082] The formation process of the third sacrificial layer 73 may include a deposition process and a planarization process. The deposition process may be any of the above-mentioned deposition processes, and the planarization process may be a chemical mechanical polishing process.

[0083] See Figures 14 to 16 The gate trench 35 is formed by etching a portion of the dielectric layer 12. Figure 15 yes Figure 14 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 16 yes Figure 14 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0084] Gate trench 35 is disposed around bit line via 23, providing initial space for the formation of gate layer 31. During etching, either wet or dry etching processes are employed, with strict control over etching depth and range to ensure that gate trench 35 is located only within the dielectric layer 12 between two adjacent insulating layers 11, minimizing damage to the insulating layers 11. A third sacrificial layer 73 is used to protect the initial capacitor via 64 during this etching process. The material of the third sacrificial layer 73 may include polysilicon.

[0085] See Figures 17 to 20 A first sacrificial layer 71 is formed within the gate trench 35, and a second sacrificial layer 72 is formed within the bit line via 23. Figure 18 yes Figure 17 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 19 yes Figure 17 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1. Figure 20 yes Figure 17 A three-dimensional structural diagram of a semiconductor device.

[0086] The first sacrificial layer 71 and the second sacrificial layer 72 fill the gate trench 35 and the bit line hole 23, respectively. The first sacrificial layer 71 provides a positioning reference for the subsequent forming of the gate layer 31, and the second sacrificial layer 72 is used to protect the hole wall of the bit line hole 23, avoid damage to the bit line hole 23 by the subsequent etching process, and ensure the size and contour accuracy of the bit line hole 23.

[0087] In some embodiments, such as chemical vapor deposition, a sacrificial layer material different from the first sacrificial layer 71 is deposited in the bit line hole 23 to ensure that there is a significant difference in the etching selectivity between the two. Thus, when the first sacrificial layer 71 is removed in the subsequent process, only the first sacrificial layer 71 is removed without damaging the second sacrificial layer 72, ensuring that the second sacrificial layer 72 completely fills the bit line hole 23.

[0088] See Figures 21 to 24 In some embodiments, step S3 is performed before forming the word line slot 36. Figure 22 yes Figure 21 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 23 yes Figure 21 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1. Figure 24 yes Figure 21 A three-dimensional structural diagram of a semiconductor device.

[0089] The word line isolation groove 53 can be made by etching. The depth of the word line isolation groove 53 can be the same as the thickness of the stacked structure 10, ensuring that it runs through the entire stacked structure 10, providing space for the subsequent filling of the word line isolation structure 50 and the forming of the word line structure 30, and laying the foundation for the insulation and isolation between the word lines 32.

[0090] Since the first sacrificial layer 71 and the second sacrificial layer 72 are formed before the word line isolation trench 53, the word line isolation trench 53 can be precisely etched using the sacrificial layer as a positioning reference. This ensures that the word line isolation trench 53 extends along the first direction X and maintains a reasonable distance from the bit line hole 23 and the gate trench 35, thus preventing the word line isolation trench 53 from being misaligned with the gate trench 35 and the word line trench 36.

[0091] Furthermore, if the word line isolation trench 53 is etched first, the sacrificial layer material is likely to fill the isolation trench when the first sacrificial layer 71 and the second sacrificial layer 72 are subsequently deposited. This requires an additional etching step to remove the excess sacrificial layer in the isolation trench, increasing process complexity and damage risk. In the above embodiment of this application, the sacrificial layer is formed first, and then the word line isolation trench 53 is etched. This process is then connected to the etching process that forms the trench 34. This directly avoids the sacrificial layer filling area and only etches the dielectric layer 12 and the insulating layer 11. There is no need to treat the sacrificial layer in the isolation trench, simplifying the process steps and improving production efficiency and yield.

[0092] In other embodiments, the etching process of word line isolation groove 53 and bit line hole 23 can be performed simultaneously.

[0093] See Figures 25 to 27 A portion of the dielectric layer 12 is removed through the word line isolation groove 53, forming the word line groove 36 that exposes the first sacrificial layer 71. Figure 26 yes Figure 25 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 27 yes Figure 25 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0094] See Figures 28 to 30 The first sacrificial layer 71 is removed through the word line slot 36. Figure 29 yes Figure 28 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 30 yes Figure 28 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0095] This step is crucial for the formation of the word line structure 30 and the channel layer 40. The specific process is as follows: using the word line isolation trench 53 as the etching channel, a dry etching process or a wet etching process can be selected based on the material characteristics of the dielectric layer 12 and the insulating layer 11. The etched trench 34 is divided into two parts: an annular gate trench 35 surrounding the bit line hole 23 and an elongated word line trench 36 extending along the first direction X. The size of the gate trench 35 precisely corresponds to the design size of the gate layer 31, ensuring that the subsequent gate layer 31 can be tightly formed around the bit line hole 23, achieving omnidirectional coverage of the channel layer 40. The size of the word line trench 36 corresponds to the design size of the word line 32 and is seamlessly connected to multiple gate trenches 35, ensuring that the subsequent word line structure 30 can be integrally formed with multiple gate layers 31, achieving synchronous gate control.

[0096] It should be noted that, since the materials of the dielectric layer 12 and the first sacrificial layer 71 are different, the etching process for removing the dielectric layer 12 and the etching process for removing the first sacrificial layer 71 use different etchants.

[0097] Step S5: Form a channel layer 40 on the inner wall of the gate trench 35 and the word line trench 36.

[0098] See Figures 31 to 33 ,in, Figure 32 yes Figure 31 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 33 yes Figure 31 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0099] Atomic layer deposition (ALD) or other deposition processes can be used to deposit channel material on the inner walls of the gate trench 35 and word trench 36. During the deposition process, the deposition temperature, deposition cycle and film thickness can be strictly controlled to ensure that the channel layer 40 uniformly covers the entire inner wall of the trench 34 and is formed on all surfaces of the gate trench 35 and word trench 36.

[0100] The channel material is selected from oxide semiconductor materials with high carrier mobility and good compatibility with gate insulating materials (such as IGZO, IGO, ITO, etc.). After deposition, the channel layer 40 is naturally divided into a first sub-channel layer 41 surrounding the bit line hole 23 and a second sub-channel layer 42 adjacent to the dielectric layer 12. No additional etching steps are required, which simplifies the process while ensuring the integrity and continuity of the channel layer 40.

[0101] Step S6: Form a letter line structure 30 that fills the groove 34 on the surface of the channel layer 40.

[0102] See Figures 34 to 39The method for forming the character line structure 30 adopts a two-step process of "deposition-etching back", which specifically includes the following steps.

[0103] See Figures 34 to 36 First, a gate insulating structure 90 is formed within the trench 34 and at least a portion of the word line isolation trench 53. Wherein, Figure 35 yes Figure 34 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 36 yes Figure 34 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0104] Gate insulating material can be deposited on all surfaces of the channel layer 40 using physical vapor deposition or chemical vapor deposition processes.

[0105] See Figures 37 to 39 An initial word line structure is formed in the trench 34 and at least a portion of the word line isolation trench 53, the initial word line structure being located on the surface of the gate insulating structure 90; the initial word line structure is subjected to an etch-back process to remove a portion of the initial word line structure located in the word line isolation trench 53, thereby forming the word line structure 30 located in the trench 34.

[0106] in, Figure 38 yes Figure 37 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 39 yes Figure 37 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0107] The initial word line structure formation process includes physical vapor deposition or chemical vapor deposition processes, such as depositing the word line 32 conductive material on all surfaces of the gate insulating structure 90, for example, first depositing TiN and then depositing W.

[0108] The etchback process can employ wet etching, with strict control over the etchback rate and time to ensure that only the initial word line structure within the word line isolation trench 53 is removed, while the initial word line structure within the trench 34 remains. After etchback, the word line structures 30 of different layers are disconnected. It should be noted that since the gate insulation structure 90 is not a conductive material, it does not need to be cut at the bottom of the word line isolation trench 53.

[0109] Please see Figures 40 to 43 The method for forming the semiconductor device may further include: forming a word line isolation structure 50 within the word line isolation trench 53. Wherein, Figure 41 yes Figure 40 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 42 yes Figure 40 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1. Figure 43 yes Figure 40 A three-dimensional structural diagram of a semiconductor device.

[0110] Please see Figures 44 to 58 The method for forming the semiconductor device may further include: etching a portion of the dielectric layer 12 through the initial capacitor hole 64 to form a groove 65, the groove 65 communicating with the initial capacitor hole 64 to form a capacitor hole 66; forming a capacitor structure 60 in the capacitor hole 66, the capacitor structure 60 being connected to the channel layer 40.

[0111] In some embodiments, the method of forming the capacitor structure 60 includes the following steps.

[0112] See Figures 44 to 46 After forming the word line structure 30, the third sacrificial layer 73 is removed. Figure 45 yes Figure 44 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 46 yes Figure 44 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0113] A selective etching process is used to remove the third sacrificial layer 73 within the initial capacitor hole 64. During etching, selectivity must be ensured, removing only the third sacrificial layer 73 to minimize damage to the hole walls, stacked structure 10, word line structure 30, and channel layer 40 of the initial capacitor hole 64. After the removal of the third sacrificial layer 73, the initial capacitor hole 64 returns to a through-hole state, providing a clean and precise channel for subsequent etching of the groove 65 and the formation of the capacitor structure 60.

[0114] See Figures 47 to 52 A second electrode 63 is formed on the inner wall of the groove 65.

[0115] In some embodiments, the method for forming the second electrode 63 includes: see Figures 47 to 49 An initial second electrode 63' is formed within the capacitor hole 66; see also Figures 50 to 52 The portion of the initial second electrode 63' located within the initial capacitor hole 64 is removed to form the second electrode 63 located within the groove 65.

[0116] in, Figure 48 yes Figure 47 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 49 yes Figure 47 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1. Figure 51 yes Figure 50 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 52 yes Figure 50A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0117] See Figures 53 to 55 A dielectric layer 62 is formed within the groove 65 and on the inner wall of the initial capacitor hole 64, and the dielectric layer 62 is located on the surface of the second electrode 63. Figure 54 yes Figure 53 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 55 yes Figure 53 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0118] A high-k dielectric material is deposited in the groove 65 and on the inner wall of the initial capacitor hole 64. During the deposition process, the dielectric layer 62 uniformly covers the surface of the second electrode 63 and the inner wall of the initial capacitor hole 64.

[0119] See Figures 56 to 58 A first electrode 61 (including a third conductive layer 611 and a fourth conductive layer 612) is formed on the surface of the dielectric layer 62. Figure 57 yes Figure 56 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 58 yes Figure 56 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0120] A highly conductive material (such as TiN) can be deposited on the surface of the dielectric layer 62 using physical vapor deposition or chemical vapor deposition processes. During deposition, it is ensured that the first electrode 61 completely fills the remaining space within the initial capacitor hole 64 and groove 65, and is in close contact with the dielectric layer 62. After deposition, the first electrode 61 extends through the entire stacked structure 10 along the stacking direction Z, forming a complete capacitor structure 60 together with the second electrode 63 and the dielectric layer 62, realizing charge storage and release, and simultaneously achieving efficient signal coupling with the second sub-channel layer 42.

[0121] Please see Figures 59 to 61 The method for forming the semiconductor device further includes the step of forming a bit line structure 20.

[0122] See Figures 59 to 61 Remove the second sacrificial layer 72.

[0123] in, Figure 60 yes Figure 59 A schematic diagram of the cross-sectional structure of the semiconductor device at point A-A1. Figure 61 yes Figure 59 A schematic diagram of the cross-sectional structure of the semiconductor device at point B-B1.

[0124] The function of the second sacrificial layer 72 is to protect the hole wall of the bit line hole 23. At this point, the word line structure 30 and the channel layer 40 have been formed, and the hole wall of the bit line hole 23 no longer needs protection. The second sacrificial layer 72 inside the bit line hole 23 can be removed by selective etching. After the second sacrificial layer 72 is removed, a good surface foundation is provided for the subsequent deposition of the bit line structure 20.

[0125] See Figures 2 to 4 A bit line structure 20 is formed within the bit line hole 23, and the bit line structure 20 is connected to the channel layer 40.

[0126] The fabrication of the bitline structure 20 needs to ensure close contact with the first sub-channel layer 41 to achieve efficient carrier transport. Physical vapor deposition or chemical vapor deposition processes can be used to deposit highly conductive bitline material within the bitline aperture 23; for example, titanium nitride can be deposited first, followed by tungsten.

[0127] In the aforementioned semiconductor device fabrication method, the simultaneous etching of bit line vias 23 and capacitor vias 66 replaces the traditional step-by-step etching process, effectively avoiding process alignment deviations caused by step-by-step etching, improving device fabrication accuracy and production yield, and reducing the difficulty of industrial production. Furthermore, the fabrication process employs sacrificial layer-assisted etching and etch-back processes, achieving precise shaping of gate trenches 35 and word line trenches 36, as well as selective fabrication of word line structures 30 and capacitor structures 60. The process steps are highly controllable, suitable for industrial mass production, and possess excellent industrial applicability. The channel-all-around (CAA) structure design allows the gate electric field to act uniformly and omnidirectionally across the entire channel, thoroughly suppressing short-channel effects, reducing drain-induced barrier lowering (DIBL) effects and off-state leakage current, and decreasing the static power consumption of 3D DRAM, thus meeting the low-power requirements of high-density integration.

[0128] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0129] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0130] The embodiments, implementation methods, and related technical features of this application can be combined and substituted for each other without conflict.

[0131] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure, comprising alternating layers of insulating and dielectric; Bit line structure, which penetrates the stacking structure along the stacking direction of the stacking structure; A word line structure is located between two adjacent insulating layers. The word line structure includes a gate layer and a word line. The gate layer is disposed around the sidewall of the bit line structure. The word line extends along a first direction and contacts a plurality of gate layers. The first direction is perpendicular to the stacking direction. A channel layer is located between two adjacent insulating layers, between the word line structure and the bit line structure, and between the word line structure and the dielectric layer.

2. The semiconductor device according to claim 1, characterized in that, The trench layer includes: The first sub-channel layer surrounds the sidewall surface of the bit line structure and is located between the bit line structure and the word line structure; The second sub-channel layer is located between the word line structure and the dielectric layer; The first sub-channel layer and the second sub-channel layer are located between the word line structure and the adjacent insulating layer.

3. The semiconductor device according to claim 2, characterized in that, Each layer of character line structure includes multiple character lines, which extend along the first direction and are spaced apart along the second direction, wherein the second direction is perpendicular to the stacking direction and the first direction; Multiple bit line structures are arranged in rows at intervals along the first direction, a gate layer is disposed around a bit line structure, two rows of bit line structures are disposed between two adjacent word lines, and a word line is in contact with a row of gate layers.

4. The semiconductor device according to claim 2, characterized in that, It also includes a gate insulating structure, the gate insulating structure comprising: A first gate insulating layer is located between the first sub-channel layer and the word line structure; The second gate insulating layer is located between the second sub-channel layer and the word line structure.

5. The semiconductor device according to claim 3, characterized in that, Also includes: A capacitor structure extends through the stacking structure along the stacking direction. Multiple capacitor structures are arranged in rows at intervals along the first direction. Two rows of capacitor structures are provided between two adjacent rows of bit line structures. The second sub-channel layer connected to one capacitor structure and one bit line structure is correspondingly connected along a third direction. The third direction is perpendicular to the stacking direction and intersects with the first direction.

6. The semiconductor device according to claim 5, characterized in that, The capacitor structure and the channel layer connected along the third direction constitute a memory cell, and a plurality of memory cells are arranged at intervals along the first direction, wherein the angle between the third direction and the first direction is an acute angle.

7. The semiconductor device according to claim 6, characterized in that, Between two adjacent rows of bit line structures, the two adjacent rows of capacitor structures are staggered in the first direction.

8. The semiconductor device according to claim 5, characterized in that, The capacitor structure includes: The first electrode extends through the stacked structure along the stacking direction; The second electrode is located between two adjacent insulating layers and is disposed around the first electrode; A dielectric layer is located between the first electrode and the second electrode; The sidewall of the second electrode is in contact with the sidewall of the second sub-channel layer.

9. The semiconductor device according to claim 8, characterized in that, The dielectric layer includes a first surface that contacts the sidewall of the second electrode, and the insulating layer includes a second surface that contacts the dielectric layer. The first surface is recessed relative to the second surface to form a groove located between two adjacent insulating layers. The second electrode is located on the inner wall of the groove, and at least a portion of the dielectric layer is located within the groove.

10. The semiconductor device according to claim 8, characterized in that, The sidewall of the second electrode includes an arcuate sidewall and a connecting sidewall connected to each other. The connecting sidewall is connected to the second sub-channel layer, and the distance from the connecting sidewall to the first electrode is less than the distance from the arcuate sidewall to the first electrode.

11. A method for forming a semiconductor device, characterized in that, include: A stacked structure is formed, the stacked structure comprising alternately stacked insulating layers and dielectric layers; A bit line hole is formed that penetrates the stack structure along the stacking direction of the stack structure; A word line isolation groove is formed that extends through the stacking structure along the stacking direction of the stacking structure. The word line isolation groove extends along a first direction and is located on one side of the bit line hole along a second direction. The first direction and the second direction are perpendicular to each other and both are perpendicular to the stacking direction. The word line isolation trench is used to etch a portion of the dielectric layer to form a trench, the trench including a gate trench surrounding the bit line hole and a word line trench extending along the first direction, the word line trench being located on one side of the gate trench along the second direction and communicating with a plurality of the gate trenches; A channel layer is formed on the inner wall of the gate trench and the word line trench; A letter line structure that fills the groove is formed on the surface of the channel layer.

12. The method for forming a semiconductor device according to claim 11, characterized in that, The method for forming the trench includes: The gate trench is formed by etching a portion of the dielectric layer through the bit line via; A first sacrificial layer is formed within the gate trench; A second sacrificial layer is formed within the bit line hole; The word line isolation groove removes part of the dielectric layer to form the word line groove that exposes the first sacrificial layer. The first sacrificial layer is removed through the word line slot.

13. The method for forming a semiconductor device according to claim 11, characterized in that, The method for forming the word line structure includes: An initial word line structure is formed within the trench and at least a portion of the word line isolation groove; The initial word line structure is subjected to a back etching process to remove a portion of the initial word line structure located within the word line isolation groove, thereby forming a word line structure located within the groove.

14. The method for forming a semiconductor device according to claim 11, characterized in that, Also includes: In the process of forming the bit line via, an initial capacitor via is formed that penetrates the stacked structure; A portion of the dielectric layer is etched through the initial capacitor hole to form a groove, and the groove communicates with the initial capacitor hole to form a capacitor hole. A capacitor structure is formed within the capacitor hole, and the capacitor structure is connected to the channel layer.

15. The method for forming a semiconductor device according to claim 14, characterized in that, The method for forming the capacitor structure includes: A second electrode is formed on the inner wall of the groove; A dielectric layer is formed within the groove and on the inner wall of the initial capacitor hole, and the dielectric layer is located on the surface of the second electrode; A first electrode is formed on the surface of the dielectric layer.

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