Memory device

Abstract

This invention provides a memory device including a first memory array structure, a second memory array structure, and a central connection structure located between the first and second memory array structures. The memory device includes a stacked structure composed of multiple insulating layers and multiple conductive layers alternately stacked in the above configuration. Multiple ground selection line structures are included in multiple conductive layers in the lower part of the stacked structure. The stacked structure of the central connection structure further includes a first connection structure, a second connection structure, and a bridging structure. The first and second connection structures are each connected to the stacked structures of the first and second memory array structures, wherein the second connection structure is alternately arranged with the first connection structure. The bridging structure connects the first and second connection structures.

Description

Technical Field

[0001] This invention relates to a semiconductor element, and more particularly to a memory device. Background Technology

[0002] Non-volatile memory elements are widely used in personal computers and other electronic devices because they have the advantage that stored data will not be lost after power is turned off.

[0003] Currently, the most commonly used flash memory arrays in the industry include NOR flash memory and NAND flash memory. Because NAND flash memory's structure connects individual memory cells in series, its integration density and area utilization are better than NOR flash memory, and it has been widely used in various electronic products. Furthermore, to further improve the integration density of memory components, a three-dimensional NAND flash memory has been developed. However, many challenges related to three-dimensional NAND flash memory still exist. Summary of the Invention

[0004] The present invention provides a memory device that can reduce word line (WL) RC delay (RCDelay) in a memory array structure.

[0005] In one embodiment of the present invention, a memory device includes a first memory array structure, a second memory array structure, and a central connection structure located between the first and second memory array structures. The memory device includes a stacked structure. This stacked structure includes multiple insulating layers and multiple conductive layers alternately stacked in the first memory array structure, the second memory array structure, and the central connection structure, wherein multiple ground select line structures (GSLs) are contained in the conductive layers in the lower portion of the stacked structure in the first memory array structure, the second memory array structure, and the central connection structure. The stacked structure of the central connection structure further includes a first connection structure, a second connection structure, and a bridging structure. The first connection structure is connected to the stacked structure of the first memory array structure, and the second connection structure is connected to the stacked structure of the second memory array structure, wherein the second connection structure and the first connection structure are alternately arranged. The bridging structure connects the first connection structure and the second connection structure.

[0006] In one embodiment of the present invention, a memory device includes a plurality of zones, each zone being disposed between opposing first and second partition walls and separated from adjacent zones. The memory device includes a stacked structure. The stacked structure includes a plurality of insulating layers and a plurality of conductive layers alternately stacked in each zone, wherein the stacked structure at a first end of the zone includes a first memory array structure, the stacked structure at a second end of the zone includes a second memory array structure, and a plurality of ground select line structures are located at the bottom of the stacked structure. The ground select line structures extend from the first end of the zone to the second end of the zone. Each zone also includes a central connection structure disposed between the first and second memory array structures. The stacked structure of the central connection structure includes a first connection structure, a second connection structure, and a bridging structure. The first connection structure is disposed along the first partition wall to connect the first memory array structure. The second connection structure is disposed along the second partition wall to connect the second memory array structure. The bridging structure connects the first and second connection structures.

[0007] Based on the above, the central connection structure of this embodiment of the invention is a bridge structure that connects two connection structures (such as WL structures) that are respectively connected to the first and second memory array structures. Therefore, the WL structures of the first and second memory array structures at both ends can be connected with the same distance conduction path, so as to reduce the WL RC delay in the memory array structure. Attached Figure Description

[0008] Figure 1 This is a perspective view of a memory device according to an embodiment of the present invention.

[0009] Figure 2 This is a top view of a memory device according to an embodiment of the present invention.

[0010] Figure 3 yes Figure 2 A cross-sectional view of line A-A'.

[0011] Figure 4 yes Figure 2 A cross-sectional view of line B-B'.

[0012] Figure 5 yes Figure 2 A cross-sectional view of line C-C'.

[0013] Figure 6 This is a cross-sectional view of a memory device according to an embodiment of the present invention.

[0014] Explanation of reference numerals in the attached figures:

[0015] 10, 612: Base

[0016] 20: Component Layer

[0017] 30, 40: Metal interconnect structure

[0018] 32, 42, 103, 606a, 606b: Dielectric layers

[0019] 34: Metal interconnects

[0020] 44: Plug

[0021] 46: Wire

[0022] 100: Stacked structure

[0023] 102, 302: Insulation layer

[0024] 104, 304, 306, 608a, 608b: Conductor layers

[0025] 200: Block

[0026] 200a: First end

[0027] 200b: Second end

[0028] 202: First partition wall

[0029] 204: Second partition wall

[0030] 206. MA1: First memory array structure

[0031] 208, MA2: Second memory array structure

[0032] 210: Discontinuous partition wall

[0033] 308: Conductor Post

[0034] 310: Channel Layer

[0035] 312: Insulating Post

[0036] 314: Conductor plug

[0037] 316: Charge storage structure

[0038] 600: CMOS chip

[0039] 602, 604: Redistribution layer

[0040] 610: Array chip

[0041] BL: Bitline

[0042] BS: Bridging Structure

[0043] C1: First connection structure

[0044] C2: Second connection structure

[0045] CC: Central Connecting Structure

[0046] D1: First Direction

[0047] D2: Second Direction

[0048] GC: Grounding Selection Line Contact Window

[0049] GLC: Bottom Wall

[0050] GSL: Ground Select Line Structure

[0051] GSL1: First Ground Selection Line Structure

[0052] GSL2: Second Grounding Selection Line Structure

[0053] GSL3: Third Grounding Selection Line Structure

[0054] LP: Lower part

[0055] SC: Stepped section

[0056] SLC: Serial Select Line Bottom Wall

[0057] SLP: Source Plate

[0058] SSL: Serial Select Line

[0059] SSLC: Serial Select Line Contact Window

[0060] SO: Opening in partition wall

[0061] VC: Vertical Channel

[0062] WL: Word Line

[0063] WLC: Wordline Contact Window Detailed Implementation

[0064] Figure 1 This is a perspective view of a memory device according to an embodiment of the present invention.

[0065] Reference Figure 1The memory device includes a first memory array structure MA1, a second memory array structure MA2, and a central connection structure CC located between the first memory array structure MA1 and the second memory array structure MA2. The memory device is constructed from a stacked structure 100, which includes multiple insulating layers and multiple conductive layers alternately stacked in the first memory array structure MA1, the second memory array structure MA2, and the central connection structure CC. Detailed construction of the stacked structure 100, the first memory array structure MA1, and the second memory array structure MA2 will be described below. In the lower LP of the stacked structure 100 in the first memory array structure MA1, the second memory array structure MA2, and the central connection structure CC, there are multiple ground selection line structures GSL (i.e., the conductive layers of the lower LP), and in... Figure 1 The stacked structure 100 shows only conductor layers, while insulating layers (not shown) are interspersed between the conductor layers. The stacked structure 100 of the central connection structure CC also includes a first connection structure C1, a second connection structure C2, and a bridging structure BS. The first connection structure C1 is connected to the stacked structure 100 of the first memory array structure MA1, and the second connection structure C2 is connected to the stacked structure 100 of the second memory array structure MA2, wherein the second connection structure C2 and the first connection structure C1 are alternately configured. The bridging structure BS connects the first connection structure C1 and the second connection structure C2.

[0066] exist Figure 1 In the first connection structure C1, the first connection structure C1 extends in the first direction D1 and continuously extends from the first memory array structure MA1 to the bridging structure BS; the second connection structure C2 also extends in the first direction D1 and continuously extends from the second memory array structure MA2 to the bridging structure BS. Correspondingly, the bridging structure BS extends in the second direction D2, and the second direction D2 differs from the first direction D1, for example, the second direction D2 is perpendicular to the first direction D1 or there is an angle between the second direction D2 and the first direction D1. The memory device includes multiple stepped portions, for example, each ground selection line structure GSL in the central connection structure CC has multiple stepped portions SC extending in the first direction D1. The multiple stepped portions SC are separated from each other in the first direction D1.

[0067] The memory device of this embodiment also includes multiple ground selection line contact windows GC, which land on the stepped portion SC to electrically connect to ground selection line structures GSL respectively. For example, the multiple ground selection line structures GSL in this embodiment include a first ground selection line structure GSL1, a second ground selection line structure GSL2, and a third ground selection line structure GSL3, wherein the second ground selection line structure GSL2 is located between the first ground selection line structure GSL1 and the third ground selection line structure GSL3. The first ground selection line structure GSL1, the second ground selection line structure GSL2, and the third ground selection line structure GSL3 can be isolated from each other by a bottom wall (not shown). Figure 1 Four stepped sections SC are shown, located respectively in the first ground selection line structure GSL1 at one end of the first connection structure C1 relative to the first memory array structure MA1, in the third ground selection line structure GSL3 at one end of the second connection structure C2 relative to the second memory array structure MA2, in the second ground selection line structures GSL2 and GSL3 adjacent to the first memory array structure MA1, and in the second ground selection line structure GSL2 and the first ground selection line structure GSL1 adjacent to the second memory array structure MA2. Therefore, the ground selection line contact window GC can be coupled to all ground selection line structures GSL of the first memory array structure MA1 and the second memory array structure MA2 through the stepped sections SC.

[0068] In some embodiments, the first connection structure C1 is disposed directly above the first ground selection line structure GSL1 and is connected to multiple conductor layers (such as word lines (WL)) above the lower LP in the stacked structure 100 of the first memory array structure MA1. In some embodiments, the second connection structure C2 is disposed directly above the third ground selection line structure GSL3 and is connected to multiple conductor layers above the lower LP in the stacked structure 100 of the second memory array structure MA2. In some embodiments, the bridging structure BS is disposed directly above the second ground selection line structure GSL2 and is connected to the first connection structure C1 and the second connection structure C2. Since the first connection structure C1 and the second connection structure C2 are connected to the first memory array structure MA1 and the second memory array structure MA2 at approximately the same distance, the WL RC delay in the first memory array structure MA1 and the second memory array structure MA2 can be reduced.

[0069] Figure 2 This is a top view of a memory device according to an embodiment of the present invention. Figure 3 yes Figure 2 A cross-sectional view of line A-A'. Figure 4 yes Figure 2 A cross-sectional view of line B-B'. Figure 5 yes Figure 2 A cross-sectional view of line C-C'.

[0070] Reference Figure 2 and Figure 3 The memory device includes multiple zones 200, each zone 200 being disposed between opposing first slits 202 and second slits 204 and separated from adjacent zones 200. Figure 2 The device displays three blocks 200, with adjacent blocks 200 arranged in a mirror configuration. Therefore, adjacent blocks 200 can share the same second partition wall 204 (or first partition wall 202), and so on. Furthermore, the number of blocks 200 can be increased or decreased as needed, and is not limited to this. The memory device includes a stacked structure 100. This stacked structure 100 includes multiple insulating layers 102 and multiple conductive layers 104 alternately stacked in each block 200. The stacked structure 100 at the first end 200a of block 200 includes a first memory array structure 206, and the stacked structure 100 at the second end 200b of block 200 includes a second memory array structure 208.

[0071] exist Figure 3In this embodiment, components are located beneath the stacked structure 100, so the memory device belongs to the CUA (CMOS-Under-Array) structure, but the present invention is not limited thereto. In some embodiments, a component layer 20 is formed on the substrate 10. The component layer 20 may include active components or passive components. Active components are, for example, transistors, diodes, etc. Passive components are, for example, capacitors, inductors, etc. Transistors may be N-type metal-oxide-semiconductor (NMOS) transistors, P-type metal-oxide-semiconductor (PMOS) transistors, or complementary metal-oxide-semiconductor (CMOS) devices. A metal interconnect structure 30 is present on the component layer 20. The metal interconnect structure 30 may include multiple dielectric layers 32 and metal interconnects 34 (including plugs, wires, etc.) formed in the multiple dielectric layers 32. The metal interconnects 34 can be connected to the component layer 20. A source line plate SLP is present on the metal interconnect structure 30. The source line plate SLP may include multiple insulating layers 302 and multiple conductor layers 304 and conductor layers 306. In one embodiment, the material of the insulating layer 302 includes silicon oxide. The materials of conductor layers 304 and 306 include doped polysilicon. The number of insulating layers 302 and conductor layers 304 and 306 is not limited to those shown in the figures. Furthermore, a conductor post 308 may be present in the source line plate SLP. The conductor post 308 has a low resistance. In one embodiment, conductor layer 304 is doped polysilicon, and conductor post 308 is a metal, such as tungsten, titanium nitride, tantalum, or a combination thereof, with a resistance lower than that of conductor layer 304 in the source line plate SLP. Conductor post 308 can be electrically connected to the substrate 10 via metal interconnect 34 in the metal interconnect structure 30, thereby grounding. Therefore, conductor post 308 can serve as a discharge path.

[0072] Refer again Figure 3A stacked structure 100 is formed on the source line plate SLP. The number of insulating layers 102 and conductor layers 104 in the stacked structure 100 is not limited to those shown in the figures. In one embodiment, the insulating layer 102 is made of silicon oxide. The conductor layer 104 includes, for example, a barrier layer and a metal layer. In one embodiment, the barrier layer is made of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof, and the metal layer is made of tungsten (W). In some embodiments, the positions of each conductor layer 104 were originally polysilicon, and a metal material layer was formed via a gate substitution process. A first memory array and a second memory array are formed in the middle of the stacked structure 100 of the first memory array structure 206 and the second memory array structure 208. Each first memory array and the second memory array includes a plurality of word lines WL, a vertical channel pillar composed of a channel layer 310, an insulating pillar 312, and a conductor plug 314, and a charge storage structure 316 surrounding each vertical channel pillar to form a plurality of memory cells arranged in three dimensions. The word line WL is the conductor layer 104 in the middle of the stacked structure 100. In some embodiments, the material of the channel layer 310 includes polysilicon, the material of the conductor plug 314 includes polysilicon, and the material of the insulating pillar 312 includes silicon oxide, but is not limited thereto. The charge storage structure 316 vertically surrounds the outer surface of the aforementioned vertical channel pillar. In some embodiments, the charge storage structure 316 is an oxide / nitride / oxide (ONO) composite layer, but is not limited thereto. The upper part of the stacked structure 100 also includes string selection lines SSL. The string selection lines SSL are the conductor layer 104 in the upper part of the stacked structure 100. The memory device also includes a metal interconnect structure 40 disposed above the stacked structure 100. The metal interconnect structure 40 may include multiple dielectric layers 42, multiple plugs 44, and multiple wires 46, etc. The dielectric layers 42 separate each wire 46 from the underlying first memory array structure 206 and second memory array structure 208. The wires 46 can be connected via a plug 44, and the wires 46 can be coupled to the ground select contact window GC, the serial select contact window SSLC, and the word line contact window WLC, respectively. Figure 3 Although the text line contact window WLC is not shown, it should be visible from the top view ( Figure 2 To obtain its specific location, that is... Figure 3 The parts are indicated by arrows. That is to say, the middle and upper parts of the stack structure 100 also have multiple stepped sections, providing areas where word line contact windows (WLC) or serial select line contact windows (SSLC) are located. The wires 46 coupled to the conductor plugs 314 of the vertical channel posts can be used as bit lines (or local bit lines) BL.

[0073] Continue to refer to Figure 2Each block 200 has multiple ground selection line structures GSL; for example, in this embodiment, the ground selection line structure GSL includes a first ground selection line structure GSL1, a second ground selection line structure GSL2, and a third ground selection line structure GSL3, wherein the second ground selection line structure GSL2 is located between the first ground selection line structure GSL1 and the third ground selection line structure GSL3. The first ground selection line structure GSL1, the second ground selection line structure GSL2, and the third ground selection line structure GSL3 can be isolated from each other by a bottom wall GLC. The ground selection line structure GSL extends from the first end 200a of the block 200 to the second end 200b of the block 200. Each block 200 also includes a central connection structure CC. The central connection structure CC is disposed between the first memory array structure 206 and the second memory array structure 208. The central connection structure CC includes a first connection structure C1, a second connection structure C2, and a bridging structure BS. The first connection structure C1 is disposed along the first partition wall 202 to connect the first memory array structure 206. The second connection structure C2 is disposed along the second partition wall 204 to connect to the second memory array structure 208. The bridging structure BS connects the first connection structure C1 and the second connection structure C2. The positional relationship between the first connection structure C1, the second connection structure C2, and the bridging structure BS is similar to that in the previous embodiment, and therefore will not be described again. Block 200 also contains a string selection line cut (SLC), which can be located in a stacked structure (such as...). Figure 3 The upper part of the stacked structure 100 is used to separate the upper conductor layers of the stacked structure. The serial select line bottom wall SLC is an insulating material, such as silicon oxide. Therefore, two serial select lines SSL are paired with a ground select line structure GSL separated by bottom wall GLC. This design allows different sub-blocks to be controlled through the serial select lines SSL and avoids WL read interference.

[0074] For example, Figure 3 The serial select line SSL and the ground select line GSL3 are electrically coupled to opposite ends of the vertical channel VC. The serial select line SSL is electrically connected between the bit line BL and the underlying word line WL; the intersection of the serial select line SSL and the vertical channel VC can be defined as a serial select transistor. The third ground select line GSL3 is electrically connected between the source line SLP and the vertical channel VC; the intersection of the third ground select line GSL3 and the word line WL can be defined as a ground select transistor. When... Figure 3When the illustrated memory device is in a read operation, for example, a read operation is performed on a selected memory cell in the first memory array structure 206, a voltage is applied to the serial select line SSL electrically connected to the selected memory cell to turn on the serial select transistor electrically connected to the serial select line SSL, and a voltage is applied to the third ground select line GSL3 electrically connected to the selected memory cell to turn on the ground select transistor electrically connected to the third ground select line GSL3. Because Figure 2 The design of the two string select lines (SSL) paired with a ground select line (GSL) ensures that unselected memory cells remain off during this read operation. No capacitance is generated in the channel layer 310 electrically connecting these unselected memory cells, thus preventing issues such as increased word line load and read interference. In one embodiment, the channel layer 310 in the unselected memory cells may be electrically floating.

[0075] exist Figure 3 In the stacked structure 100, the third ground selection line structure GSL3 is located at the bottom and has a second connection structure C2 and a partial bridging structure BS above it. That is, the stacked structure 100 with the central connection structure CC includes the second connection structure C2 and the bridging structure BS. Each word line WL in the second memory array structure 208 shares the same conductor layer 104 as the second connection structure C2 and the bridging structure BS. Therefore, the second connection structure C2 is directly connected to the second memory array structure 208, and the bridging structure BS is directly connected to the second memory array structure 208 via the second connection structure C2. The second connection structure C2 is positioned directly above the third ground selection line structure GSL3.

[0076] exist Figure 4 In the stacked structure 100, the first ground selection line structure GSL1 is located at the bottom and has a first connection structure C1 and a partial bridging structure BS above it. That is, the stacked structure 100 with the central connection structure CC includes the first connection structure C1 and the bridging structure BS. Each word line WL in the first memory array structure 206 shares the same conductor layer 104 as the first connection structure C1 and the bridging structure BS. Therefore, the first connection structure C1 is directly connected to the first memory array structure 206, and the bridging structure BS is directly connected to the first memory array structure 206 via the first connection structure C1. The first connection structure C1 is positioned directly above the first ground selection line structure GSL1.

[0077] Reference Figure 2 and Figure 5The first ground selection line structure GSL1, the second ground selection line structure GSL2, and the third ground selection line structure GSL3 are located at the lower LP of the stacked structure 100. Furthermore, the number of layers of the first ground selection line structure GSL1, the second ground selection line structure GSL2, and the third ground selection line structure GSL3 can be increased or decreased as needed, and is not limited to the three layers shown in the figure. Between the ground selection line structures GSL are bottom walls GLC, where the bottom wall GLC is an insulating material, such as silicon oxide, SiN, SiON, SiC, SiCN, Al2O3, or a high dielectric constant material, such as HfO. In addition, the bottom wall GLC can also be used to cut dummy word lines (not shown). Each block 200 is disposed between opposing first partition walls 202 and second partition walls 204, and discontinuous partition walls 210 can be disposed between the first partition walls 202 and the second partition walls 204. Discontinuous partition wall 210 extends from the first end 200a of block 200 to the second end 200b of block 200 and has at least one partition wall opening SO, such as one or more. A bridging structure BS passes through the partition wall opening SO to achieve an electrical connection; therefore, the bridging structure BS passes directly above the second ground selection line structure GSL2 through the partition wall opening SO and connects the first connection structure C1 and the second connection structure C2. In some embodiments, the first partition wall 202, the second partition wall 204, and the discontinuous partition wall 210 are all made of insulating material, such as silicon oxide. In other embodiments, the first partition wall 202, the second partition wall 204, and the discontinuous partition wall 210, in addition to including insulating material, also include a conductive material covered by the insulating material, such as polycrystalline silicon or tungsten.

[0078] exist Figure 2 In this embodiment, the memory device further includes multiple stepped sections SC located in each ground selection line structure GSL within the central connection structure CC, and multiple ground selection line contact windows GC can be disposed on the stepped sections SC to electrically connect the multiple ground selection line structures GSL respectively. In this embodiment, the aforementioned multiple stepped sections SC are separated from each other in a first direction D1, which is the extension direction of the first partition wall 202.

[0079] exist Figure 3In the first memory array structure 206, a third ground selection line structure GSL3 extending from one end of the second connection structure C2 relative to the second memory array structure 208 has two separate stepped portions SC. Ground selection line contact windows GC land on these stepped portions SC respectively to electrically connect the plurality of third ground selection line structures GSL3 of the second memory array structure 208 and the plurality of third ground selection line structures GSL3 of the first memory array structure 206. Moreover, the stepped portions SC may be covered by a dielectric layer 103 on top of the stacked structure 100. The dielectric layer 103 may be a single layer or multiple layers. In some embodiments, the dielectric layer 103 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0080] exist Figure 4 In the first ground selection line structure GSL1, which extends from one end of the first connection structure C1 relative to the first memory array structure 206, there are also two separate stepped portions SC. Ground selection line contact windows GC land on these stepped portions SC respectively to electrically connect the plurality of first ground selection line structures GSL1 of the first memory array structure 206 and the plurality of first ground selection line structures GSL3 of the second memory array structure 208.

[0081] Besides the CUA structure, this invention can also be applied to the CBA (CMOS directly bonded to array) structure, such as... Figure 6 As shown. Figure 6 Used with Figure 3 The same element symbols are used to represent the same or similar parts and components, and the relevant content of the same or similar parts and components can also refer to the content of the previous embodiment, which will not be repeated here.

[0082] Reference Figure 6 A CMOS chip 600 is formed by a substrate 10, a component layer 20, and a metal interconnect structure 30. A redistribution layer 602 is formed on the metal interconnect structure 30, wherein the redistribution layer 602 includes a dielectric layer 606a and a conductor layer 608a. The stacked structure 100 is formed in the array chip 610, as detailed in [reference needed]. Figure 3 The stacked structure 100 in the figure is flipped. Figure 3The array chip 610 has a structure such that the stepped portion SC is on top, and the second connection structure C2 and the bridging structure BS are below the stepped portion SC. The array chip 610 also has a redistribution layer 604 connected to the CMOS chip 600, wherein the redistribution layer 604 includes a dielectric layer 606b and a conductor layer 608b. The CMOS chip 600 can be directly bonded to the array chip 610 via hybrid bonding between the redistribution layers 602 and 604. Furthermore, a metal interconnect structure 40 can be formed on the back side of the substrate 612 of the array chip 610 to form a CBA structure.

[0083] In summary, a memory device according to an embodiment of the present invention can connect the word lines of the first and second memory array structures at both ends with the same or similar conduction paths, thus reducing the WL RC delay in the memory array structure.

Claims

1. A memory device comprising a first memory array structure, a second memory array structure, and a central connection structure located between the first memory array structure and the second memory array structure, the memory device comprising: The stacked structure includes multiple insulating layers and multiple conductive layers alternately stacked in the first memory array structure, the second memory array structure, and the central connection structure, wherein... Multiple ground selection line structures are contained in the multiple conductor layers in the lower part of the stacked structure of the first memory array structure, the second memory array structure, and the central connection structure, wherein... The stacked structure of the central connection structure also includes: The first connection structure is connected to the stacked structure of the first memory array structure; A second connection structure is connected to the stacked structure of the second memory array structure, wherein the second connection structure and the first connection structure are alternately configured; and A bridging structure connects the first connection structure and the second connection structure.

2. The memory device of claim 1, wherein the first connection structure extends in a first direction and continuously extends from the first memory array structure to the bridge structure, and the second connection structure extends in the first direction and continuously extends from the second memory array structure to the bridge structure.

3. The memory device of claim 2, wherein the bridging structure extends in a second direction, and the second direction is different from the first direction.

4. The memory device of claim 2, further comprising a plurality of stepped portions located in each of the plurality of ground selection line structures in the central connection structure, and the plurality of stepped portions extending in the first direction.

5. The memory device of claim 1, wherein the plurality of ground selection line structures include a first ground selection line structure, a second ground selection line structure and a third ground selection line structure, wherein the second ground selection line structure is located between the first ground selection line structure and the third ground selection line structure, and the bridging structure is disposed directly above the second ground selection line structure.

6. A memory device comprising a plurality of blocks, each block being disposed between opposing first and second partition walls and separated from adjacent blocks, the memory device comprising: The stacked structure includes multiple insulating layers and multiple conductor layers alternately stacked in each block, wherein The stacked structure at the first end of the block includes a first memory array structure; The stacked structure at the second end of the block includes a second memory array structure; as well as Multiple ground selection line structures are located at the bottom of the stacked structure, extending from the first end of the block to the second end of the block, wherein... Each block also includes a central connection structure disposed between the first memory array structure and the second memory array structure, wherein The stacked structure in the central connection structure includes: A first connection structure is provided along the first partition wall to connect the first memory array structure; A second connection structure is disposed along the second partition wall to connect the second memory array structure; and A bridging structure connects the first connection structure and the second connection structure.

7. The memory device of claim 6 further includes a discontinuous partition wall disposed between the first partition wall and the second partition wall, wherein the discontinuous partition wall extends from the first end of the block to the second end of the block.

8. The memory device of claim 7, wherein the discontinuous partition wall has at least one partition wall opening, and the bridging structure passes through the at least one partition wall opening.

9. The memory device of claim 6 further includes a plurality of stepped portions located in each of the plurality of ground select line structures in the central connection structure.

10. The memory device of claim 6, wherein the plurality of ground selection line structures include a first ground selection line structure, a second ground selection line structure and a third ground selection line structure, wherein the second ground selection line structure is located between the first ground selection line structure and the third ground selection line structure, and the bridging structure is disposed directly above the second ground selection line structure.

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