Semiconductor device and method of manufacturing the same, memory system

Abstract

This disclosure provides a semiconductor device and a method for fabricating the same, as well as a memory system. The semiconductor device includes a stacked structure, a first interconnect structure, a first isolation layer, a second interconnect structure, and a second isolation layer. The first interconnect structure extends along a stacking direction in the stacked structure and includes a first extension and a second extension connected in the stacking direction. The first extension extends along the stacking direction, and the second extension extends in a direction intersecting the stacking direction. The first isolation layer surrounds the first extension. The second interconnect structure extends along the stacking direction in the stacked structure and includes a third extension and a fourth extension connected in the stacking direction. The third extension extends along the stacking direction, and the fourth extension extends in a direction intersecting the stacking direction. The second isolation layer surrounds the third extension. The dimension of the first extension in the stacking direction is smaller than the dimension of the third extension in the stacking direction. The second extension is in contact with the second isolation layer.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a semiconductor device, a memory system, and a method for fabricating a semiconductor device. Background Technology

[0002] Semiconductor devices can be used in memory, such as 3D NAND memory. As the number of stacked layers in 3D NAND memory gradually increases, the word line lead structure becomes one of the key factors affecting the effective utilization rate of the memory cell array. Summary of the Invention

[0003] In a first aspect, some embodiments of this disclosure provide a semiconductor device. The semiconductor device includes: a stacked structure, a first interconnect structure, a first isolation layer, a second interconnect structure, and a second isolation layer. The first interconnect structure extends in the stacked structure along a stacking direction and includes a first extension and a second extension connected in the stacking direction. The first extension extends in the stacking direction, and the second extension extends in a direction intersecting the stacking direction. The first isolation layer surrounds the first extension. The second interconnect structure extends in the stacked structure along a stacking direction and includes a third extension and a fourth extension connected in the stacking direction. The third extension extends in the stacking direction, and the fourth extension extends in a direction intersecting the stacking direction. The second isolation layer surrounds the third extension. The dimension of the first extension in the stacking direction is smaller than the dimension of the third extension in the stacking direction. The second extension is in contact with the second isolation layer.

[0004] In an exemplary embodiment, on a plane perpendicular to the stacking direction, the area of ​​the first extension is smaller than the area of ​​the second extension, and the area of ​​the third extension is smaller than the area of ​​the fourth extension.

[0005] In an exemplary embodiment, the first extension and the second extension are aligned in the stacking direction, and the third extension and the fourth extension are aligned in the stacking direction.

[0006] In an exemplary embodiment, the first end face of the first extension portion facing away from the second extension portion is coplanar with the second end face of the third extension portion facing away from the fourth extension portion.

[0007] In an exemplary embodiment, there are multiple second connection structures, and the dimensions of multiple third extensions in the multiple second connection structures are different from each other in the stacking direction.

[0008] In an exemplary embodiment, the second extension includes one or more first curved side surfaces and one or more second curved side surfaces connected to each other, the first curved side surfaces protruding in a direction away from the first extension, the second curved side surfaces protruding in a direction toward the first extension, and the second curved side surfaces contacting the second insulating layer.

[0009] In an exemplary embodiment, the stacked structure includes a first stacked portion and a second stacked portion, wherein the first stacked portion at least partially surrounds the second stacked portion in a plane perpendicular to the stacking direction; the first stacked portion includes a first dielectric layer and a gate layer alternately disposed in the stacking direction; the second stacked portion includes a first dielectric layer and a second dielectric layer alternately disposed in the stacking direction, wherein the second dielectric layer is connected to the gate layer; wherein a first connection structure and a second connection structure extend in the second stacked portion.

[0010] In an exemplary embodiment, the second extension is connected to the gate layer; the fourth extension is connected to the gate layer.

[0011] In an exemplary embodiment, the semiconductor device further includes a gate line isolation structure. The gate line isolation structure extends in a first stacked portion along a stacking direction and extends along a first direction; wherein, a plurality of gate line isolation structures are spaced apart in a second direction, and a second stacked portion is located between adjacent gate line isolation structures; wherein, a second extension is connected to a gate layer located on one side or opposite sides of it in the second direction; wherein, the stacking direction, the first direction, and the second direction intersect each other.

[0012] In an exemplary embodiment, the semiconductor device further includes a channel structure. The channel structure is located on opposite sides of the second stack portion in a first direction and extends in the first stack portion along the stacking direction.

[0013] Secondly, some embodiments of this disclosure provide a memory system. The memory system includes a memory and a controller, the memory including semiconductor devices as mentioned in any of the embodiments described above. The controller is coupled to the memory and is used to control the memory to store data.

[0014] Thirdly, some embodiments of this disclosure provide a method for fabricating a semiconductor device. The method includes: forming a first connection structure and a second connection structure extending along a stacking direction in a stacked structure, wherein the first connection structure includes a first extension and a second extension connected in the stacking direction, the first extension extending along the stacking direction and the second extension extending in a direction intersecting the stacking direction; the second connection structure includes a third extension and a fourth extension connected in the stacking direction, the third extension extending along the stacking direction and the fourth extension extending in a direction intersecting the stacking direction; and forming a first isolation layer surrounding the first extension and a second isolation layer surrounding the third extension; wherein the dimension of the first extension in the stacking direction is smaller than the dimension of the third extension in the stacking direction, and the second extension is in contact with the second isolation layer.

[0015] In an exemplary embodiment, the preparation method further includes: forming a first isolation layer surrounding the first extension and a second isolation layer surrounding the third extension, comprising: forming a first hole and a second hole extending in the stacked structure along the stacking direction, wherein the depth of the first hole is less than the depth of the second hole; forming a first isolation layer on the sidewall of the first hole; and forming a second isolation layer on the sidewall of the second hole.

[0016] In an exemplary embodiment, forming a first connection structure and a second connection structure extending along the stacking direction in a stacked structure includes: forming a first gap extending along a direction intersecting the stacking direction via a first hole having a first isolation layer, wherein the first gap exposes a second isolation layer; forming a second gap extending along a direction intersecting the stacking direction via a second hole having a second isolation layer; forming a first connection structure in the first hole and the first gap; and forming a second connection structure in the second hole and the second gap.

[0017] In an exemplary embodiment, the stacked structure includes a first stacked portion and a second stacked portion. On a plane perpendicular to the stacking direction, the first stacked portion at least partially surrounds the second stacked portion. The first stacked portion includes a first dielectric layer and a gate layer alternately disposed in the stacking direction. The second stacked portion includes a first dielectric layer and a second dielectric layer alternately disposed in the stacking direction, the second dielectric layer being connected to the gate layer. Forming a first gap extending in a direction intersecting the stacking direction via a first aperture having a first isolation layer includes: removing a portion of the second dielectric layer in the second stacked portion through the first aperture to obtain the first gap, wherein the first gap also exposes the gate layer. Forming a second gap extending in a direction intersecting the stacking direction via a second aperture having a second isolation layer includes: removing a portion of the second dielectric layer in the second stacked portion through the second aperture to obtain the second gap, wherein the second gap exposes the gate layer. Attached Figure Description

[0018] Other features, objects, and advantages of this disclosure will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0019] Figure 1A This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure;

[0020] Figure 1B This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure, taken on another plane;

[0021] Figure 1C This is a schematic cross-sectional view of the semiconductor device provided in this embodiment of the present disclosure taken on another plane;

[0022] Figure 2This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this disclosure;

[0023] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device provided in yet another embodiment of this disclosure;

[0024] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of the present disclosure;

[0025] Figure 5 This is a schematic flowchart of a method for fabricating a semiconductor device according to an embodiment of this disclosure;

[0026] Figures 6A to 6E This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this disclosure during the fabrication process;

[0027] Figure 7 This is a schematic block diagram of a system with a memory system provided in the embodiments of this disclosure; and

[0028] Figure 8A and Figure 8B This is a schematic block diagram of a memory system provided in an embodiment of this disclosure. Detailed Implementation

[0029] To better understand this disclosure, various aspects of this disclosure will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this disclosure and are not intended to limit the scope of this disclosure in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0030] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this disclosure, the first connection structure discussed herein may also be referred to as the second connection structure, and vice versa.

[0031] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0032] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this disclosure, the word "may" is used to mean "one or more embodiments of this disclosure." And the term "exemplary" is intended to refer to an example or illustration.

[0033] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that, unless expressly stated in this disclosure, terms as defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0034] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this disclosure are not limited to the order in which they are described, but can be performed in any order or in parallel.

[0035] Furthermore, when the term “connection” or “linkage” is used in this disclosure, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0036] This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] This disclosure provides a semiconductor device through some embodiments. Figure 1A This is a cross-sectional schematic diagram of a semiconductor device provided in an embodiment of this disclosure. Figure 1B This is a schematic cross-sectional view of a semiconductor device provided in an embodiment of this disclosure taken on another plane. Figure 1C This is a schematic cross-sectional view of the semiconductor device provided in this embodiment of the present disclosure, taken on another plane. For example, Figure 1A It can be along Figure 1B The diagram shows a cross-section of the plane containing line II-II'. Figure 1B It can be along Figure 1A The diagram shows a cross-section taken from the plane containing line I-I'. Figure 1C It can be along Figure 1B The diagram shows a cross-section of the plane containing line III-III'.

[0038] It should be noted that the D1, D2, and D3 directions in the following figures illustrate the spatial relationships of the components in the semiconductor device. For example, D3 may be the stacking direction, and the D1 and D2 directions may be two directions that intersect (e.g., are perpendicular) to each other on planes that intersect (e.g., are perpendicular) to the aforementioned stacking direction. The same concepts will be used throughout this disclosure to describe the spatial relationships of the components in the semiconductor device.

[0039] like Figures 1A to 1C As shown, the semiconductor device 100 may include a stacked structure 110 (e.g., a first stacked portion 111 and a second stacked portion 112), a first interconnect structure 120, a first isolation layer 141, a second interconnect structure 130a, and a second isolation layer 142a. The first interconnect structure 120 extends along the D3 direction in the stacked structure 110 (e.g., the second stacked portion 112) and includes a first extension 121 and a second extension 122 connected in the D3 direction. The first extension 121 extends along the D3 direction, and the second extension 122 extends along a direction intersecting the D3 direction (e.g., the D1 and D2 directions). The first isolation layer 141 surrounds the first extension 121. The second interconnect structure 130a extends along the D3 direction in the stacked structure 110 (e.g., the second stacked portion 112) and includes a third extension 131a and a fourth extension 132a connected in the D3 direction. The third extension 131a extends along the D3 direction, and the fourth extension 132a extends along a direction intersecting the D3 direction (e.g., the D1 and D2 directions). The second insulating layer 142a surrounds the third extension 131a. The dimension of the first extension 121 in the D3 direction is smaller than the dimension of the third extension 131a in the D3 direction. The second extension 122a contacts the second insulating layer 142a.

[0040] In the semiconductor device 100, by making the second extension 122 of the first connection structure 120, which has a smaller size in the D3 direction, contact the second isolation layer 142a surrounding the third extension 131a of the second connection structure 130a, which has a larger size in the D3 direction, the spacing between the first connection structure 120 and the second connection structure 130a can be effectively reduced, which helps to reduce the planar area occupied by the connection structures (e.g., the first connection structure 120 and the second connection structure 130a). As the number of stacked layers of the stacked structure 110 gradually increases, the demand for planar area occupied by the connection structures increases. The semiconductor device 100 provided in this disclosure can effectively address the problem of the increased demand for planar area occupied by the connection structures by optimizing the arrangement of the first connection structure 120 and the second connection structure 130a, which helps to reduce the overall planar area of ​​the semiconductor device 100.

[0041] In some implementations, such as Figures 1A to 1C As shown, viewed from the D3 direction, the stacked structure 110 can be divided into array regions AR and connection regions CR arranged in the D1 direction. In one example, in the D1 direction, two array regions AR may be located between one connection region CR. In other examples, two connection regions CR may be located between one array region AR (not shown). The connection region CR can be further divided into a first region CR1 and a second region CR2 arranged in the D2 direction. In the D2 direction, two second regions CR2 may be located between one first region CR1.

[0042] In some implementations, such as Figures 1A to 1C As shown, the stacking structure 110 may include a first stacking portion 111 and a second stacking portion 112. In a plane perpendicular to the D3 direction, the first stacking portion 111 may at least partially surround the second stacking portion 112. For example, the first stacking portion 111 may be located within array region AR and second region CR2. The second stacking portion 112 may be located within first region CR1. When the two array regions AR are located between a connecting region CR, the first stacking portion 111 may be located on opposite sides of the second stacking portion 112 in the D2 direction and on opposite sides in the D1 direction. In other words, the first stacking portion 111 may surround the second stacking portion 112. When the two connecting regions CR are located between an array region AR, the first stacking portion 111 may be located on opposite sides of the second stacking portion 112 in the D2 direction and on one side in the D1 direction. In other words, the first stacking portion 111 may partially surround the second stacking portion 112.

[0043] In some implementations, such as Figure 1B and Figure 1C As shown, the first stack portion 111 may include a first dielectric layer 113 and a gate layer 114 alternately disposed in the D3 direction. For example, each first dielectric layer 113 and each gate layer 114 may extend along the D1 and D2 directions. The material of the first dielectric layer 113 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the first dielectric layer 113 is silicon oxide. The material of the gate layer 114 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, doped semiconductor, or any other suitable conductive material. For example, the material of the gate layer 114 may be a composite material composed of titanium nitride and tungsten. Optionally, the gate layer 114 may be surrounded by a high dielectric constant layer 116. The material of the high dielectric constant layer 116 may include, but is not limited to, aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zirconium oxide, etc.

[0044] In some implementations, such as Figure 1A and Figure 1BAs shown, the second stack portion 112 may include a first dielectric layer 113 and a second dielectric layer 115 alternately disposed in the D3 direction. The second dielectric layer 115 is connected to the gate layer 114. For example, each first dielectric layer 113 in the first stack portion 111 extends along the D1 and D2 directions to serve as the first dielectric layer 113 in the second stack portion 112. In other words, a portion of each first dielectric layer 113 extending along the D1 and D2 directions is used to form the first stack portion 111, and another portion is used to form the second stack portion 112. Each second dielectric layer 115 may extend along the D1 and D3 directions. Each second dielectric layer 115 and each gate layer 114 may be disposed in the same layer. The material of the second dielectric layer 115 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the second dielectric layer 115 may be silicon nitride.

[0045] In some implementations, such as Figure 1A and Figure 1B As shown, the first connection structure 120 and the second connection structure 130a may extend in the second stack portion 112. For example, viewed from the D3 direction, the first connection structure 120 and the second connection structure 130a may be located within the first region CR1 of the connection region CR.

[0046] In some implementations, such as Figure 1A and Figure 1B As shown, the first extension 121 may be generally columnar. For example, along the opposite direction of the D3 direction, the size (e.g., diameter) of the first extension 121 in a plane perpendicular to the D3 direction decreases. The first end face 123 of the first extension 121 opposite to the second extension 122 may be coplanar with a surface of the stacked structure 110 (e.g., the second stacked portion 112) in the D3 direction.

[0047] In some embodiments, the material of the first extension 121 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, doped semiconductors, or any other suitable conductive material. For example, the first extension 121 may include two or more conductive portions that surround each other in sequence. The materials of the individual conductive portions may be different from each other. When the first extension 121 is composed of two conductive portions, the material of the outer conductive portion may be titanium nitride, and the material of the inner conductive portion may be tungsten. Optionally, the first extension 121 may also surround the first insulating post 143. Alternatively, the first extension 121 may be composed of a single conductive material.

[0048] In some embodiments, the second extension 122 may be generally disk-shaped. The second extension 122 may include an opposing surface in the D3 direction and side surfaces surrounding the opposing surface. The opposing surface of the second extension 122 in the D3 direction may contact the first dielectric layer 113. The second extension 122 may also be disposed co-layered with a second dielectric layer 115 and connected to the gate layer 114 of that layer. For example, at least a portion of the side surfaces of the second extension 122 may lie generally on the same dummy cylindrical surface.

[0049] In some embodiments, the material of the second extension 122 may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, doped semiconductors, or any other suitable conductive material.

[0050] In some embodiments, the first extension 121 and the second extension 122 are in contact. The first extension 121 and the second extension 122 may be aligned in the D3 direction. For example, the central axis of the first extension 121 and the central axis of the second extension 122 may substantially coincide. It should be noted that the central axis of the second extension 122 may be the central axis of the virtual cylindrical surface on which its side surface lies.

[0051] In some embodiments, the area of ​​the first extension 121 may be smaller than the area of ​​the second extension 122 in a plane perpendicular to the D3 direction. For example, the maximum area of ​​the first extension 121 may be smaller than the area of ​​the second extension 122 in a plane perpendicular to the D3 direction. For example, the projection of the first extension 121 may lie within the projection of the second extension 122 when viewed from the D3 direction.

[0052] In some implementations, such as Figure 1A and Figure 1B As shown, the third extension 131a may be generally columnar. For example, along the opposite direction of the D3 direction, the size (e.g., diameter) of the third extension 131a in a plane perpendicular to the D3 direction decreases. The second end face 133a of the third extension 131a away from the fourth extension 132a may be coplanar with a surface of the stacked structure 110 (e.g., the second stacked portion 112) in the D3 direction. Thus, the first end face 123 of the first extension 121 away from the second extension 122 and the second end face 133a of the third extension 131a away from the fourth extension 132a may be coplanar.

[0053] In some embodiments, the material of the third extension 131a may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, doped semiconductors, or any other suitable conductive material. For example, the third extension 131a may include two or more conductive portions that surround each other in sequence. The materials of the individual conductive portions may be different from each other. When the third extension 131a is composed of two conductive portions, the material of the outer conductive portion may be titanium nitride, and the material of the inner conductive portion may be tungsten. Optionally, the third extension 131a may also surround the second insulating post 144a. Alternatively, the third extension 131a may be composed of a single conductive material.

[0054] In some embodiments, the fourth extension 132a may be generally disk-shaped. The fourth extension 142a may include an opposing surface in the D3 direction and side surfaces surrounding the opposing surface. The opposing surface of the fourth extension 132a in the D3 direction may contact the first dielectric layer 113. The fourth extension 132a may also be disposed co-layered with a second dielectric layer 115 and connected to the gate layer 114 of that layer. For example, at least a portion of the side surfaces of the fourth extension 132a may lie generally on the same dummy cylindrical surface.

[0055] It should be noted that, since the size of the first extension 121 in the D3 direction is smaller than the size of the third extension 131a in the D3 direction, the second extension 122 and the fourth extension 132a are respectively connected to the gate layer 114 of different layers.

[0056] In some embodiments, the material of the fourth extension 132a may include one or more of titanium, titanium nitride, tantalum, tantalum nitride, tungsten, molybdenum, copper, aluminum, ruthenium, doped semiconductors or any other suitable conductive material.

[0057] In some embodiments, the third extension 131a and the fourth extension 132a are in contact. The third extension 131a and the fourth extension 132a may be aligned in the D3 direction. For example, the central axis of the third extension 131a and the central axis of the fourth extension 132a may substantially coincide. It should be noted that the central axis of the fourth extension 132a may be the central axis of the virtual cylindrical surface on which its side surface lies.

[0058] In some embodiments, the area of ​​the third extension 131a may be smaller than the area of ​​the fourth extension 132a in a plane perpendicular to the D3 direction. For example, the maximum area of ​​the third extension 131a may be smaller than the area of ​​the fourth extension 132a in a plane perpendicular to the D3 direction. For example, the projection of the third extension 131a may lie within the projection of the fourth extension 132a when viewed from the D3 direction.

[0059] The second connection structure 130a was described in detail above as an example. In some embodiments, such as Figure 1B As shown, the semiconductor device 100 may further include another second connection structure 130b. Another second isolation layer 142b may surround the third extension 131b. The second extension 122 may also contact the second isolation layer 142b. The third extension 131a of the second connection structure 130a and the third extension 131b of the other second connection structure 130b have different dimensions in the D3 direction. For example, the fourth extension 132a of the second connection structure 130a and the fourth extension (not shown) of the other second connection structure 130b are respectively connected to gate layers 114 of different layers.

[0060] In some implementations, such as Figure 1A and 1B As shown, when the second extension 122 contacts the two second isolation layers 142a and 142b, the side surface of the second extension 122 may include first curved side surfaces 124-1, 124-2, and 124-3 and second curved side surfaces 125-1 and 125-2. Optionally, the side surface of the second extension 122 may also include a flat side surface 126. The first curved side surfaces 124-1, 124-2, and 124-3 may protrude in a direction away from the first extension 121 (e.g., radial direction), and the second curved side surfaces 125-1 and 125-2 may protrude in a direction toward the first extension 121 (e.g., opposite to the radial direction). For example, the first curved side surfaces 124-1, 124-2, and 124-3 may be substantially located on the same virtual cylindrical surface. The first curved side surface 124-1, the second curved side surface 125-1, the first curved side surface 124-2, the second curved side surface 125-2, the first curved side surface 124-3, and the flat side surface 126 are connected in sequence. The second curved side surface 125-2 may contact the second isolation layer 142a, and the second curved side surface 125-1 may contact the second isolation layer 142b. Optionally, the flat side surface 126 may contact the gate layer 114.

[0061] In some implementations, such as Figure 1B and Figure 1CAs shown, the semiconductor device 100 may further include a gate isolation structure 150. The gate isolation structure 150 may extend along the D3 direction in the first stack portion 111 and along the D1 direction. For example, viewed from the D3 direction, the gate isolation structure 150 may be located within the second region CR2 of the array region AR and the connection region CR. Furthermore, there may be multiple gate isolation structures 150, which may be spaced apart along the D2 direction. The second stack portion 112 may be located between adjacent gate isolation structures 150 in the D2 direction. For example, the stack structure 110 (including the first stack portion 111 and the second stack portion 112) between adjacent gate isolation structures 110 in the D2 direction may be referred to as a memory block BLK.

[0062] In some implementations, such as Figure 1B As shown, the second extension 122 may be connected (e.g., contacted) to the gate layer 114 located on one side of it in the D2 direction.

[0063] In some implementations, such as Figure 1C As shown, the gate isolation structure 150 may include a main body 151 and an insulating layer 152. The insulating layer 152 may be located on opposite sides of the main body 151 in the D2 direction and on one side in the D1 direction. The material of the main body 151 may include polysilicon, and the material of the insulating layer 152 may include silicon oxide. The gate isolation structure 150 employs the above-described material combination, which helps to optimize structural stress. In other embodiments, the gate isolation structure 150 may be composed of one or more of suitable insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material; this disclosure is not limiting in this regard.

[0064] In some implementations, such as Figure 1B and Figure 1C As shown, the semiconductor device 100 may further include a channel structure 160 (hereinafter referred to as the first channel structure 160). The first channel structure 160 may be located on opposite sides of the second stack portion 112 in the D1 direction and extend in the first stack portion 111 along the D3 direction. For example, viewed from the D3 direction, a plurality of first channel structures 160 may be located within the array region AR and arranged in an array in the D1 and D2 directions. The first channel structure 160 may be used to implement data storage.

[0065] In some embodiments, the first channel structure 160 may be generally columnar. The first channel structure 160 may include a third insulating pillar 161, a channel layer 162, a tunneling layer 163, a charge trapping layer 164, a barrier layer 165, and a channel plug 166. For example, the third insulating pillar 161 may extend in and protrude from the first stack portion 111 along the D3 direction. The channel layer 162 may surround the portion of the third insulating pillar 161 located in the first stack portion 111 and enclose the portion of the third insulating pillar 161 protruding from the first stack portion 111. The tunneling layer 163 may surround the portion of the channel layer 162 located in the first stack portion 111, the charge trapping layer 164 may surround the tunneling layer 163, and the barrier layer 165 may surround the charge trapping layer 164. The channel plug 166 may be located on one side of the third insulating pillar 161 in the D1 direction and surrounded by the channel layer 162.

[0066] In some embodiments, the material of the third insulating pillar 161 may include one or more of silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. For example, the material of the third insulating pillar 161 may be silicon oxide. The material of the channel layer 162 may include one or more of silicon (e.g., monocrystalline silicon, polycrystalline silicon, amorphous silicon), germanium, germanium silicon, or any other suitable semiconductor material. The materials of the tunneling layer 163, the charge trapping layer 164, and the barrier layer 165 may sequentially include silicon oxide, silicon nitride, and silicon oxide. The material of the channel plug 166 may include one or more of silicon (e.g., monocrystalline silicon, polycrystalline silicon, amorphous silicon), germanium, germanium silicon, or any other suitable semiconductor material. For example, the materials of the channel plug 166 and the channel layer 162 may be the same.

[0067] In some embodiments, a portion of the first channel structure 160 surrounded by a gate layer 114 and a portion of the gate layer 114 constitute a memory cell. Multiple memory cells are arranged in series along the extension direction of the first channel structure 160 (e.g., the D3 direction) to form a memory string and share the channel layer 162.

[0068] In some implementations, such as Figure 1C As shown, the semiconductor structure 100 may further include a semiconductor layer 171. The semiconductor layer 171 may be located on one side of the stacked structure 110 (e.g., the first stack portion 111) in the D3 direction. A portion of the third insulating pillar 161 protruding from the first stack portion 111 may extend into the semiconductor layer 171. The semiconductor layer 171 may extend along both the D1 and D2 directions. The material of the semiconductor layer 171 may include one or more of silicon (e.g., monocrystalline silicon, polycrystalline silicon, amorphous silicon), germanium, germanium-silicon, or any other suitable semiconductor material. For example, a plurality of first channel structures 160 may be connected (e.g., contacted) to the semiconductor layer 171. The semiconductor layer 171 may serve as a common source.

[0069] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this disclosure. For example... Figure 2 As shown, the semiconductor device 200 may include a first connection structure 220 and three second connection structures 230a, 230b, and 230c. In the three second connection structures 230a, 230b, and 230c, the third extensions 231a, 231b, and 231c have different dimensions in the D3 direction. Second insulating layers 242a, 242b, and 242c may surround the third extensions 231a, 231b, and 231c, respectively. The second extension 222 in the first connection structure 220 may contact the three second insulating layers 242a, 242b, and 242c. Optionally, the third extensions 231a, 231b, and 231c may also surround the second insulating pillars 244a, 244b, and 244c, respectively.

[0070] The side surface of the second extension 222 may include first curved side surfaces 224-1, 224-2, 224-3, 224-4 and second curved side surfaces 225-1, 225-2, 225-3. Optionally, the side surface of the second extension 222 may also include a flat side surface 226. The first curved side surfaces 224-1, 224-2, 224-3, 224-4 may protrude in a direction away from the first extension (not shown) (e.g., radial direction), and the second curved side surfaces 225-1, 225-2, 225-3 may protrude in a direction toward the first extension (e.g., opposite to the radial direction). For example, the first curved side surfaces 224-1, 224-2, 224-3, 224-4 may be substantially located on the same virtual cylindrical surface. The first curved side surface 224-1, the second curved side surface 225-3, the first curved side surface 224-2, the second curved side surface 225-2, the first curved side surface 224-3, the second curved side surface 225-1, the first curved side surface 224-4, and the flat side surface 226 are sequentially connected. The second curved side surface 225-3 may contact the second isolation layer 242c, the second curved side surface 225-2 may contact the second isolation layer 242b, and the second curved side surface 225-1 may contact the second isolation layer 242a. Optionally, the flat side surface 226 may contact the gate layer 214. In other words, the second extension 222 may be connected (e.g., contacted) to the gate layer 214 located on one side of it in the D2 direction.

[0071] Figure 3 This is a cross-sectional schematic diagram of a semiconductor device provided in yet another embodiment of this disclosure. For example... Figure 3As shown, the semiconductor device 300 may include a first connection structure 320 and four second connection structures 330a, 330b, 330c, and 330d. In the four second connection structures 330a, 330b, 330c, and 330d, the third extensions 331a, 331b, 331c, and 331d have different dimensions in the D3 direction. Second insulating layers 342a, 342b, 342c, and 342d may surround the third extensions 331a, 331b, 331c, and 331d, respectively. The second extension 322 in the first connection structure 320 may contact the four second insulating layers 342a, 342b, 342c, and 342d. Optionally, the third extensions 342a, 342b, 342c, and 342d may also surround the second insulating pillars 344a, 344b, 344c, and 344d, respectively.

[0072] The side surface of the second extension 322 may include first curved side surfaces 324-1, 324-2, 324-3, 324-4, 324-5, 324-6 and second curved side surfaces 325-1, 325-2, 325-3, 325-4. Optionally, the side surface of the second extension 322 may also include flat side surfaces 326-1, 326-2. The first curved side surfaces 324-1, 324-2, 324-3, 324-4, 324-5, 324-6 may protrude in a direction away from the first extension (not shown) (e.g., radial direction), and the second curved side surfaces 325-1, 325-2, 325-3, 325-4 may protrude in a direction toward the first extension (e.g., opposite to the radial direction). For example, the first curved side surfaces 324-1, 324-2, 324-3, 324-4, 324-5, and 324-6 can be approximately located on the same virtual cylindrical surface. The first curved side surface 324-1, the second curved side surface 325-4, the first curved side surface 324-2, the second curved side surface 325-3, the first curved side surface 324-3, the flat side surface 326-2, the first curved side surface 324-4, the second curved side surface 325-2, the first curved side surface 324-5, the second curved side surface 325-1, the first curved side surface 324-6, and the flat side surface 326-1 are connected sequentially. The second curved side surface 325-4 may contact the second isolation layer 342d, the second curved side surface 325-3 may contact the second isolation layer 342c, the second curved side surface 325-2 may contact the second isolation layer 342b, and the second curved side surface 325-1 may contact the second isolation layer 342a. Optionally, the flat side surfaces 326-1 and 326-2 may contact the gate layer 314. In other words, the second extension 322 may be connected (e.g., contacted) to the gate layers 314 located on opposite sides of it in the D2 direction.

[0073] Figure 4 This is a cross-sectional schematic diagram of a semiconductor device provided in another embodiment of this disclosure. For example... Figure 4 As shown, the semiconductor device 400 may include a first connection structure 420 and five second connection structures 430a, 430b, 430c, 430d, and 430e. In the five second connection structures 430a, 430b, 430c, 430d, and 430e, the third extensions 431a, 431b, 431c, 431d, and 431e have different dimensions in the D3 direction. Second isolation layers 442a, 442b, 442c, 442d, and 442e may surround the third extensions 431a, 431b, 431c, 431d, and 431e, respectively. A second extension 422 in the first connection structure 420 may contact the five second isolation layers 442a, 442b, 442c, 442d, and 442e. Optionally, the third extensions 431a, 431b, 431c, 431d, and 431e may also surround the second insulating posts 444a, 444b, 444c, 444d, and 444e, respectively.

[0074] The side surface of the second extension 422 may include first curved side surfaces 424-1, 424-2, 424-3, 424-4, 424-5, 424-6 and second curved side surfaces 425-1, 425-2, 425-3, 425-4, 425-5. Optionally, the side surface of the second extension 422 may also include a flat side surface 426. The first curved side surfaces 424-1, 424-2, 424-3, 424-4, 424-5, 424-6 may protrude in a direction away from the first extension (not shown) (e.g., radial direction), and the second curved side surfaces 425-1, 425-2, 425-3, 425-4, 425-5 may protrude in a direction toward the first extension (e.g., opposite to the radial direction). For example, the first curved side surfaces 424-1, 424-2, 424-3, 424-4, 424-5, and 424-6 can be approximately located on the same virtual cylindrical surface. The first curved side surface 424-1, the second curved side surface 425-5, the first curved side surface 424-2, the second curved side surface 425-4, the first curved side surface 424-3, the second curved side surface 425-3, the first curved side surface 424-4, the second curved side surface 425-2, the first curved side surface 424-5, the second curved side surface 425-1, the first curved side surface 424-6, and the flat side surface 426 are connected in sequence. The second curved side surface 425-5 may contact the second isolation layer 442e, the second curved side surface 425-4 may contact the second isolation layer 442d, the second curved side surface 425-3 may contact the second isolation layer 442c, the second curved side surface 425-2 may contact the second isolation layer 442b, and the second curved side surface 425-1 may contact the second isolation layer 442a. Optionally, the flat side surface 426 may contact the gate layer 414. In other words, the second extension 422 may be connected (e.g., contacted) to the gate layer 414 located on one side therein in the D2 direction.

[0075] It should be noted that, as exemplarily illustrated above, the number of second isolation layers contacting the second extension may be 2, 3, 4, or 5. However, in other examples, the number of second isolation layers contacting the second extension may be one or more (e.g., more than five), and this disclosure does not impose a specific limitation on this. In other words, the number of second connection structures may be one or more. When there are multiple second connection structures, the dimensions of each third extension in these second connection structures in the D3 direction may be different from each other, and each fourth extension in these second connection structures may be connected to different gate layers respectively.

[0076] Furthermore, when the second extension contacts a second insulating layer, the side surface of the second extension may include at least one first curved side surface and one second curved side surface. When the second extension contacts multiple (e.g., more than two) second insulating layers, the side surface of the second extension may include more than two first curved side surfaces and more than one second curved side surface. For example, the number of second curved side surfaces may be equal to the number of second insulating layers it contacts.

[0077] In the above embodiments, when there are multiple second connection structures, the spacing between the first connection structure and the multiple second connection structures can be effectively reduced, further reducing the planar area occupied by the connection structures and further reducing the overall planar area of ​​the semiconductor device. Some embodiments of this disclosure also provide a method for fabricating a semiconductor device. Figure 5 This is a schematic flowchart illustrating a method for fabricating a semiconductor device according to an embodiment of this disclosure. Figure 5 As shown, the semiconductor device fabrication method 500 (hereinafter referred to as fabrication method 500) may include the following steps.

[0078] S510, a first connecting structure and a second connecting structure extending along the stacking direction are formed in the stacked structure, wherein the first connecting structure includes a first extension and a second extension connected in the stacking direction, the first extension extending along the stacking direction and the second extension extending in a direction intersecting the stacking direction; the second connecting structure includes a third extension and a fourth extension connected in the stacking direction, the third extension extending along the stacking direction and the fourth extension extending in a direction intersecting the stacking direction.

[0079] S520, forming a first isolation layer surrounding the first extension and a second isolation layer surrounding the third extension.

[0080] The first extension has a smaller dimension in the stacking direction than the third extension, and the second extension is in contact with the second isolation layer.

[0081] In the fabrication method 500 provided in this disclosure, by forming a first connection structure with a smaller size in the stacking direction and a second connection structure with a larger size in the stacking direction, and by making the second extension in the first connection structure contact the second isolation layer surrounding the third extension in the second connection structure, the spacing between the first and second connection structures can be effectively reduced, which helps to reduce the planar area occupied by the connection structures (e.g., the first and second connection structures). As the number of stacked layers of the stacked structure gradually increases, the demand for planar area occupied by the connection structure increases. The semiconductor device obtained by the fabrication method 500 provided in this disclosure can effectively address the problem of the increased demand for planar area occupied by the connection structure, which helps to reduce the overall planar area of ​​the semiconductor device. In addition, by optimizing the arrangement of the first and second connection structures, the fabrication process difficulty is not increased, which helps to improve the process window.

[0082] Figures 6A to 6E This is a cross-sectional schematic diagram of the semiconductor device provided in the embodiments of this disclosure during the fabrication process. Specifically, Figure 6A An intermediate structure containing a stacked structure is shown. Figure 6B The intermediate structure after the formation of the first and second holes is shown. Figure 6C The intermediate structure after the formation of the first and second isolation layers is shown. Figure 6D The intermediate structure after the formation of the first and second gaps is shown. Figure 6E An intermediate structure is shown after the formation of the first and second connection structures. It should be noted that the "intermediate structure" referred to in this disclosure can be a structure formed during the fabrication of a semiconductor device.

[0083] The following is combined Figures 6A to 6E The preparation method 500, which includes steps S510 and S520, will be described by way of example.

[0084] In some implementations, such as Figure 6A As shown, the stacked structure 610 may include a first stacked portion 611 and a second stacked portion 612. In a plane perpendicular to the D3 direction, the first stacked portion 611 may at least partially surround the second stacked portion 612. The first stacked portion 611 may include a first dielectric layer 613 and a gate layer 614 alternately arranged in the D3 direction. The second stacked portion 612 may include a first dielectric layer 613 and a second dielectric layer 615 alternately arranged in the D3 direction. The second dielectric layer 615 and the gate layer 614 are disposed on the same layer and connected to each other (e.g., in contact).

[0085] In some implementations, the stacked structure 610 may be obtained based on an initial stacked structure via a "gate replacement" process. Exemplarily, the initial stacked structure may be formed by alternately forming a first dielectric layer 613 and an initial second dielectric layer. The first dielectric layer 613 and the initial second dielectric layer may be located in the array region AR and the connection region CR (refer to...). Figure 1B The initial second dielectric layer extends within the array region AR and the second region CR2. Next, via trenches corresponding to the outer contour of the gate isolation structure 650, the portion of the initial second dielectric layer located in the array region AR and the second region CR2 is replaced with the gate layer 614. The initial second dielectric layer located in the first region CR1 is not replaced, and the retained initial second dielectric layer is referred to as the second dielectric layer 615. Thus, within the array region AR and the first region CR1, the first dielectric layer 613 and the gate layer 614 are alternately arranged to form the first stack portion 611. Within the second region CR2, the first dielectric layer 613 and the second dielectric layer 615 are alternately arranged to form the second stack portion 612.

[0086] In some implementations, the "gate replacement" process can be used to form Figure 1B The first channel structure 160 shown and Figure 6A The second channel structure 681 shown is executed subsequently. For example, the second channel structure 681 may be formed on opposite sides of the second stack portion 612 in the D2 direction and extend in the first stack portion 611 along the D3 direction. For example, the second channel structure 681 may be located within the second region CR2. As described above, the first channel structure 160 formed in the array region AR (refer to...) Figure 1C It can be used to realize data storage, while the second channel structure 681 formed in the second zone CR2 can play the role of mechanical support and / or load balancing.

[0087] In some embodiments, the first channel structure 160 (reference) Figure 1C The second channel structure 681 can be formed by any process known in the art. For example, the second channel structure 681 and the first channel structure 160 may have the same internal structure. Since the first channel structure 160 has been described in detail above, it will not be repeated here.

[0088] In some embodiments, the stacked structure 610 may be formed on the top side of the substrate 682. It should be noted that "top side" as used in this disclosure refers to the side where one component is on top of another when the intermediate structures are positioned as shown in the corresponding figures. The substrate 682 may include a semiconductor substrate. For example, the material of the semiconductor substrate may include silicon, germanium, gallium arsenide, or indium phosphide. As another example, the semiconductor substrate may include a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc. In some examples, the substrate 682 may be a composite layered structure. In other examples, the substrate 682 may be made of a single material. For example, the substrate 682 may serve a supporting function during manufacturing and may be removed in subsequent processes.

[0089] It should be noted that in the current step, the first channel structure and the second channel structure 681 may extend into the substrate 682.

[0090] Preparation method 500 proceeds to step S520. In some embodiments, such as Figure 6B As shown, a first via 683 and a second via 684 extending along the D3 direction in the stacked structure 610 (e.g., the second stacked portion 612) can be formed by an etching process (e.g., dry etching and / or wet etching). The depth of the first via 683 may be less than the depth of the second via 684. For example, the first via 683 and the second via 684 may expose different layers of the second dielectric layer 615. For example, there may be multiple second vias 684, and the depths of the multiple second vias 684 may be different from each other.

[0091] In some implementations, such as Figure 6C As shown, a first isolation layer 641 can be formed on the sidewall of the first hole 683 and a second isolation layer 642 can be formed on the sidewall of the second hole 684 by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof. For example, after the formation of the first isolation layer 641 and the second isolation layer 642, the bottom of the first hole 683 and the second hole 684 still exposes the second dielectric layer 615. Alternatively, the first isolation layer 641 and the second isolation layer 642 can be formed in the same thin film deposition process.

[0092] Preparation method 500 proceeds to step S510. In some embodiments, such as... Figure 6DAs shown, a first gap 685 extending in a direction intersecting the D3 direction can be formed via an etching process (e.g., wet etching) through a first hole 683 forming a first isolation layer 641, and a second gap 686 extending in a direction intersecting the D3 direction can be formed via a second hole 684 having a second isolation layer 642 formed. The first gap 685 exposes the second isolation layer 642. After the above process, the first hole 683 and the first gap 685 can communicate with each other. The second hole 684 and the second gap 686 can also communicate with each other.

[0093] In some embodiments, during the formation of the first gap 685, a portion of the second dielectric layer 615 exposed at the bottom of the first hole 683 in the second stack portion 612 may be removed via the first hole 683. The first gap 685 exposes not only the second isolation layer 642 described above, but also the gate layer 614 (e.g., located within the second region CR2). Similarly, during the formation of the second gap 686, a portion of the second dielectric layer 615 exposed at the bottom of the second hole 684 in the second stack portion 612 may be removed via the second hole 684. The second gap 686 may expose the gate layer 614 (e.g., located within the second region CR2). For example, during the formation of the first gap 685 and the second gap 686 described above, the first isolation layer 641 and the second isolation layer 642 may serve to isolate the etching material (e.g., etchant) from the first dielectric layer 613 and / or the second dielectric layer 615 on its outer side.

[0094] Furthermore, such as Figure 6D and Figure 6E As shown, a first connection structure 620 can be formed by filling at least one conductive material in the first hole 683 and the first gap 685 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof, and a second connection structure 630 can be formed by filling at least one conductive material in the second hole 684 and the second gap 686. The conductive material filled in the first gap 685 can serve as a second extension 622 of the first connection structure 620, and the conductive material filled in the first hole 683 can serve as a first extension 621 of the first connection structure 620. The conductive material filled in the second gap 686 can serve as a fourth extension 632 of the second connection structure 630, and the conductive material filled in the second hole 684 can serve as a third extension 631 of the second connection structure 630. For example, the first connection structure 620 and the second connection structure 630 can be formed in the same thin film deposition process.

[0095] In some embodiments, the fabrication method 500 may further include the steps of removing a portion of the substrate 682 and the first channel structure and the second channel structure 681 extending into the substrate 682, and the step of forming a semiconductor layer. For example, as Figure 6EAs shown, portions of the tunneling layer 663, charge trapping layer 664, and barrier layer 665 extending into the substrate 682 in the first and second channel structures 681 can be removed to expose the channel layer 662. Next, a semiconductor layer connected to the channel layer 662 can be formed.

[0096] This disclosure also provides a memory system. Figure 7 This is a schematic block diagram of a system with a memory system provided in an embodiment of this disclosure. Figure 8A and Figure 8B This is a schematic block diagram of a memory system provided in an embodiment of this disclosure.

[0097] like Figure 7 As shown, system 10 can be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a memory system 11 located therein). Figure 7 As shown, system 10 may include a host 14 and a memory system 11, the memory system 11 having one or more memories 12 and a controller 13. The host 14 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 14 may be configured to send or receive data to and from the memory 12.

[0098] Memory 12 may include, for example, the semiconductor devices described in any embodiment of this disclosure. According to some embodiments, controller 13 is coupled to memory 12 and host 14 and is configured to control memory 12. Controller 13 can manage data stored in memory 12 and communicate with host 14. In some embodiments, controller 13 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, compact flash (CF) card, universal serial bus (USB) flash drive, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, controller 13 is designed to operate in a high duty cycle environment, such as an SSD or embedded multi-media card (eMMC) used as a data storage device in mobile devices such as smartphones, tablets, laptops, etc. Controller 13 may be configured to control operations of memory 12, such as read, erase, and program operations. Controller 13 may also be configured to manage various functions related to data stored in or to be stored in memory 12, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, controller 13 is further configured to process error correction codes (ECCs) related to data read from or written to memory 12. Controller 13 may also perform any other appropriate functions, such as formatting memory 12. Controller 13 may communicate with external devices (e.g., host 14) according to specific communication protocols. For example, controller 13 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0099] The controller 13 and one or more memories 12 can be integrated into various types of memory systems, for example, included in the same package (such as a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 11 can be implemented and packaged into different types of end electronic products. Figure 8AIn one example shown, controller 13 and a single memory 12 may be integrated into memory card 15. Memory card 15 may include PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc. Memory card 15 may further include a connector for connecting memory card 15 to a host computer (e.g., Figure 7 The host 14) is coupled to the memory card connector 16. In such a way... Figure 8B In another example shown, controller 13 and multiple storage units 12 may be integrated into SSD 17. SSD 17 may further include components for connecting SSD 17 to a host (e.g., Figure 7 The host 14) is coupled to the SSD connector 18. In some embodiments, the storage capacity and / or operating speed of the SSD 17 is higher than that of the memory card 15.

[0100] The above description is merely an illustration of the embodiments of this disclosure and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

Claims

1. A semiconductor device, comprising: Stacked structure; A first connecting structure extends along the stacking direction in the stacking structure and includes a first extension and a second extension connected in the stacking direction, the first extension extending along the stacking direction and the second extension extending along a direction intersecting the stacking direction; A first insulating layer surrounds the first extension; The second connecting structure extends along the stacking direction in the stacking structure and includes a third extension and a fourth extension connected in the stacking direction, the third extension extending along the stacking direction and the fourth extension extending in a direction intersecting the stacking direction; as well as A second insulating layer surrounds the third extension; Wherein, the dimension of the first extension in the stacking direction is smaller than the dimension of the third extension in the stacking direction, and the second extension is in contact with the second isolation layer.

2. The semiconductor device according to claim 1, wherein, On a plane perpendicular to the stacking direction, the area of ​​the first extension is smaller than the area of ​​the second extension, and the area of ​​the third extension is smaller than the area of ​​the fourth extension.

3. The semiconductor device according to claim 1, wherein, In the stacking direction, the first extension and the second extension are center-aligned, and the third extension and the fourth extension are center-aligned.

4. The semiconductor device according to claim 3, wherein, The first end face of the first extension that is opposite to the second extension is coplanar with the second end face of the third extension that is opposite to the fourth extension.

5. The semiconductor device according to claim 1, wherein, The number of the second connection structures is multiple, and the dimensions of the multiple third extensions in the multiple second connection structures are different from each other in the stacking direction.

6. The semiconductor device according to claim 1, wherein, The second extension includes one or more first curved side surfaces and one or more second curved side surfaces connected to each other, the first curved side surfaces protruding in a direction away from the first extension, the second curved side surfaces protruding in a direction toward the first extension, and the second curved side surfaces contacting the second insulating layer.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The stacking structure includes a first stacking portion and a second stacking portion, wherein, in a plane perpendicular to the stacking direction, the first stacking portion at least partially surrounds the second stacking portion; The first stacked portion includes a first dielectric layer and a gate layer alternately disposed in the stacking direction; The second stacked portion includes a first dielectric layer and a second dielectric layer alternately disposed in the stacking direction, wherein the second dielectric layer is connected to the gate layer; The first connection structure and the second connection structure extend in the second stacked portion.

8. The semiconductor device according to claim 7, wherein, The second extension is connected to the gate layer; the fourth extension is connected to the gate layer.

9. The semiconductor device according to claim 7, further comprising: A grid isolation structure extends in the first stacked portion along the stacking direction and extends along the first direction; The plurality of the gate line isolation structures are arranged at intervals in the second direction, and the second stacked portion is located between adjacent gate line isolation structures; The second extension is connected to the gate layer located on one side or opposite sides of it in the second direction; The stacking direction, the first direction, and the second direction intersect each other.

10. The semiconductor device according to claim 9, further comprising: The channel structure is located on opposite sides of the second stack portion in the first direction and extends in the first stack portion along the stacking direction.

11. A memory system, comprising: The memory includes the semiconductor device as described in any one of claims 1 to 10; as well as A controller, coupled to the memory, is used to control the memory to store data.

12. A method for fabricating a semiconductor device, comprising: A first connecting structure and a second connecting structure extending along a stacking direction are formed in a stacked structure. The first connecting structure includes a first extension and a second extension connected in the stacking direction, the first extension extending along the stacking direction and the second extension extending in a direction intersecting the stacking direction. The second connecting structure includes a third extension and a fourth extension connected in the stacking direction, the third extension extending along the stacking direction and the fourth extension extending in a direction intersecting the stacking direction. A first isolation layer is formed around the first extension and a second isolation layer is formed around the third extension; Wherein, the dimension of the first extension in the stacking direction is smaller than the dimension of the third extension in the stacking direction, and the second extension is in contact with the second isolation layer.

13. The preparation method according to claim 12, wherein, The formation of a first isolation layer surrounding the first extension and a second isolation layer surrounding the third extension includes: A first hole and a second hole are formed extending in the stacked structure along the stacking direction, wherein the depth of the first hole is less than the depth of the second hole; The first isolation layer is formed on the sidewall of the first hole; and The second isolation layer is formed on the sidewall of the second hole.

14. The preparation method according to claim 13, wherein, Forming a first connection structure and a second connection structure extending along the stacking direction in the stacked structure includes: A first gap is formed through the first hole in which the first isolation layer is formed, extending in a direction intersecting the stacking direction, wherein the first gap exposes the second isolation layer; A second gap is formed through the second hole in which the second isolation layer is formed, extending in a direction intersecting the stacking direction; The first connecting structure is formed in the first hole and the first gap; and The second connection structure is formed in the second hole and the second gap.

15. The preparation method according to claim 14, wherein, The stacking structure includes a first stacking portion and a second stacking portion, wherein the first stacking portion at least partially surrounds the second stacking portion in a plane perpendicular to the stacking direction; The first stacked portion includes a first dielectric layer and a gate layer alternately disposed in the stacking direction; The second stack portion includes a first dielectric layer and a second dielectric layer alternately disposed in the stacking direction, wherein the second dielectric layer is connected to the gate layer; Wherein, forming a first gap extending in a direction intersecting the stacking direction via the first hole through which the first isolation layer is formed includes: A portion of the second dielectric layer in the second stacked portion is removed through the first aperture to obtain the first gap, wherein the first gap also exposes the gate layer; The formation of a second gap extending in a direction intersecting the stacking direction via the second hole through which the second isolation layer is formed includes: A portion of the second dielectric layer in the second stack portion is removed through the second aperture to obtain the second gap, wherein the second gap exposes the gate layer.

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