Method for manufacturing semiconductor device, semiconductor device, and memory
By forming a self-aligned patterned film structure on the stacked layer, and using self-aligned technology to etch the top selection gate grooves and spacing lines, the mask layer etching problem in the prior art is solved, and the performance of semiconductor devices is improved.
CN122373352APending Publication Date: 2026-07-10YANGTZE MEMORY TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2021-11-30
- Publication Date
- 2026-07-10
AI Technical Summary
Technical Problem
In existing semiconductor devices, it is difficult to effectively etch the top selected gate groove in the mask layer, which makes optical proximity correction difficult and overlay control difficult, thus affecting device performance.
Method used
A film structure is formed on the stacked layer using a self-aligned pattern. A top selection gate groove is formed by etching using a self-aligned technique, and an insulating layer is filled in the groove to form a top selection gate line, thus avoiding the use of a mask layer for etching.
Benefits of technology
This reduces the difficulty of fabricating top-selective gate slots and separators, solves the overlay alignment problem, and improves the performance of semiconductor devices.
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Smart Images
Figure CN122373352A_ABST
Abstract
This invention discloses a method for fabricating a semiconductor device, a semiconductor device, and a memory. The method includes: providing a substrate and a stacked layer on the substrate, the stacked layer including a top select gate; forming a film structure on the stacked layer, the film structure including a self-aligned pattern; forming a top select gate trench along the self-aligned pattern, the top select gate trench penetrating the top select gate; and forming a top select gate isolation line in the top select gate trench. This invention simplifies the fabrication of the top select gate isolation line and improves the performance of the semiconductor device.
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