Semiconductor device and method of manufacturing the same, storage system

Abstract

This application discloses a semiconductor device and its fabrication method, as well as a memory system. The semiconductor device includes: a stacked structure, including a core region with multiple channel structures; a semiconductor layer located on one side of the stacked structure along its stacking direction, with the channel structures extending to the semiconductor layer, and the projections of the semiconductor layer and the channel structures in a plane parallel to the stacking direction not overlapping; a first insulating layer located at least on a first surface of the semiconductor layer away from the stacked structure; and a first lead-out portion penetrating the portion of the first insulating layer corresponding to the core region along the stacking direction and contacting the semiconductor layer. In this application, the first lead-out portion of the semiconductor device can be formed at any position corresponding to the first insulating layer and the core region, no longer limited to the position corresponding to the gate gap structure, thus reducing the process difficulty. Furthermore, it can be directly formed using aluminum, thereby eliminating the need for the process of forming the first connection portion, thus reducing the complexity and cost of the lead-out process.

Description

[0001] This application is a divisional application of Chinese patent application filed on November 16, 2022, with application number 202211461085.4 and entitled "Semiconductor Device and Preparation Method Thereof, Storage System". Technical Field

[0002] The embodiments of this application relate to the field of semiconductor technology, and in particular to semiconductor devices and their fabrication methods and storage systems. Background Technology

[0003] As semiconductor manufacturing process feature sizes shrink and memory device density increases, 3D memory has emerged. To improve the storage capacity of 3D memory, the number of stacked layers and the number of initial channel structures in the stacked structure are continuously increasing. However, with the increase in the number of stacked layers, the depth of the channel vias also increases. This makes it difficult to ensure that the extension depth of each channel via is the same during the etching process, resulting in a misalignment of the initial channel structures formed in subsequent processes. Consequently, the formation location of the lead-out components used for connecting hook structures is limited, further increasing the difficulty of the lead fabrication process. Summary of the Invention

[0004] The semiconductor devices, their fabrication methods, and storage systems provided in this application can solve or partially solve the above-mentioned deficiencies or other deficiencies in the prior art.

[0005] The semiconductor device provided according to the first aspect of this application includes: The stacked structure includes a core area with multiple channel structures; A semiconductor layer is located on one side of the stacked structure along the stacking direction of the stacked structure, the channel structure extends to the semiconductor layer, and the projections of the semiconductor layer and the channel structure in a plane parallel to the stacking direction do not overlap; A first insulating layer is located at least on a first surface of the semiconductor layer away from the stacked structure; and The first lead-out portion penetrates the portion of the first insulating layer corresponding to the core region along the stacking direction and contacts the semiconductor layer.

[0006] The method for fabricating a semiconductor device according to the second aspect of this application includes: A first insulating layer is formed on one side of an intermediate semiconductor device, wherein the intermediate semiconductor device includes a stacked structure and a semiconductor layer located on one side of the stacked structure along a stacking direction of the stacked structure, the stacked structure including a core region having a plurality of channel structures extending to the semiconductor layer, and the projections of the semiconductor layer and the channel structures in a plane parallel to the stacking direction do not overlap, and the first insulating layer is formed at least on a first surface of the semiconductor layer away from the stacked structure; and In the portion of the first insulating layer corresponding to the core region, a first lead-out portion is formed that penetrates the first insulating layer along the stacking direction and contacts the semiconductor layer.

[0007] The storage system provided according to the third aspect of this application includes a controller and the semiconductor device described in the first aspect of this application, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

[0008] The semiconductor device fabrication method provided in this application employs an intermediate semiconductor device in which the projections of the semiconductor layer and the channel structure in a plane parallel to the stacking direction do not overlap. A first insulating layer is formed on at least a first surface of the semiconductor layer away from the stacking structure, and a first lead-out portion is formed at the portion of the first insulating layer corresponding to the core region, contacting the semiconductor layer. This not only removes the limitation on the formation position of the first lead-out portion due to the different depths of each channel structure, allowing the first lead-out portion to be formed at any position corresponding to the first insulating layer and the core region, rather than being limited to the position corresponding to the gate gap structure, thereby reducing process difficulty and increasing the overlap window, but also significantly reduces the difficulty of subsequent CMP processes. Simultaneously, it reduces the aspect ratio of the first lead-out portion, expands the range of selectable materials for the first lead-out portion, and makes it possible to directly form the first lead-out portion using aluminum, thus eliminating the need for tungsten filling and reducing the complexity and cost of the lead-out process.

[0009] The semiconductor layer and channel structure of the semiconductor device provided in this application do not overlap in the projection of their respective directions in a plane parallel to the stacking direction. In other words, the side of each channel structure facing the semiconductor layer is basically flush, and the portion of the semiconductor layer formed on the channel structure is also basically flush. Therefore, this application not only allows the first insulating layer to have a thinner thickness, thereby enabling the first lead to have a smaller aspect ratio and expanding the material range of the first lead, making it possible to directly use aluminum to form the first lead, thus eliminating the step of forming the first connection portion and reducing the complexity of the lead wire process, but also eliminates the need to specify the formation position of the first lead due to the different depths of each channel structure. This allows the first lead to be formed at any position corresponding to the first insulation and the core region, rather than being limited to the position corresponding to the gate gap structure, thereby reducing the process difficulty of fabricating the first lead and increasing the overlap window.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0011] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. The drawings are provided for a better understanding of the invention and are not intended to limit the scope of the application. In the drawings: Figures 1 to 11 These are schematic diagrams illustrating the fabrication method of a semiconductor device according to one embodiment of this application. Figure 12 This is a flowchart of a method for fabricating a semiconductor device according to one embodiment of this application; Figures 13 to 21 These are partial process schematic diagrams of a method for fabricating a semiconductor device according to another embodiment of this application; Figure 22 This is a schematic diagram of the structure of a semiconductor device according to yet another embodiment of this application; Figure 23 This is a flowchart of a method for fabricating a semiconductor device according to another embodiment of this application; Figure 24 This is a flowchart of a method for fabricating a semiconductor device according to yet another embodiment of this application.

[0012] Figure label: 100. First insulating layer; 101. Protrusion; 102. First lead-out hole; 103. Second lead-out hole; 110. Third insulating layer; 120. Fourth insulating layer; 121. First connecting hole; 122. Second connecting hole; 200. Semiconductor layer; 201, First surface; 202, Isolation hole; 210, Doped semiconductor layer; 220. Undoped semiconductor layer; 230. Doped amorphous silicon layer; 300. Stacked structure; 301, Core region; 302, Peripheral region; 310, Gate layer; 320, Second insulating layer; 400' Initial channel structure; 400, Channel structure; 401, Sacrificial structure; 402. Confinement structure; 410. Channel layer; 420. Functional layer; 430. Dielectric layer; 440. Insulating layer; 510. First lead-out section; 520. Second lead-out section; 530. First connecting part; 540. Second connecting part; 550. Third connecting part; 560, Fourth connecting part; 600, Substrate; 610, Substrate insulating layer; 700. Word line connector; 800. Intermediate semiconductor device; 800', Initial semiconductor device; 900, Gate line gap structure. Detailed Implementation

[0013] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0014] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence.

[0015] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0016] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0017] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0018] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0019] Furthermore, in this application, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a structure below or above, or may have a range smaller than that of the structure below or above. Additionally, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers. Furthermore, in this application, the use of "connection" or "joint" may indicate direct or indirect contact between corresponding components, unless otherwise expressly defined or inferred from the context.

[0020] To increase the storage capacity of 3D memory, the number of stacked layers in the stacked structure of 3D memory is constantly increasing. However, with the increase in the number of stacked layers, the depth of the channel holes also increases, making it difficult to ensure that the extension depth of each channel hole is the same during the etching process. This results in the initial channel structures in the initial semiconductor device being staggered in height. Specifically, for example... Figure 1As shown, the initial semiconductor device 800' generally includes a stacked structure 300 and an undoped semiconductor layer 220, a substrate insulating layer 610, and a substrate 600 arranged sequentially along the stacking direction of the stacked structure 300. The stacked structure 300 includes a core region 301 in which multiple initial channel structures 400' are formed and a peripheral region 302 located on one side of the core region 301. The stacked structure 300 in the core region 301 includes a gate layer 310 and a second insulating layer 320 that are alternately stacked along the stacking direction. A word line connection portion 700 electrically connected to the gate layer 310 is formed in the peripheral region 302. The initial channel structures 400' sequentially penetrate the stacked structure 300, the undoped semiconductor layer 220, and the substrate insulating layer 610 and extend into the substrate 600.

[0021] Based on the aforementioned initial semiconductor device 800', one embodiment of this application provides a method for fabricating a semiconductor device. For ease of description, as follows... Figure 1 As shown, the portion of the initial channel structure 400' located in the substrate 600 and the substrate insulating layer 610 can be referred to as the sacrificial structure 401, the portion of the initial channel structure 400' located in the undoped semiconductor layer 220 can be referred to as the confinement structure 402, and the portion of the initial channel structure 400' located in the stacked structure 300 can be referred to as the channel structure 400.

[0022] Figure 12 A flowchart illustrating a method for fabricating a semiconductor device according to one embodiment of this application is shown; as follows: Figure 12 As shown, the preparation method 1000 may include: S100, Remove substrate 600 to expose the portion of the initial channel structure 400' located within substrate 600 (see...) Figure 1 and Figure 2 ).

[0023] S110, remove the substrate insulating layer 610 and the functional layer 420 of the sacrificial structure 401 to expose the side of the undoped semiconductor layer 220 away from the stacked structure 300 and the channel layer 410 of the sacrificial structure 401 (see S110). Figure 2 and Figure 3 ).

[0024] S120, a doped amorphous silicon layer 230 is formed on the side of the undoped semiconductor layer 220 away from the stacked structure 300 and on the side of the channel layer 410 of the sacrificial structure 401 (see...). Figure 3 and Figure 4The doped amorphous silicon layer 230 is formed on one side of the undoped semiconductor layer 220 and the channel layer 410 using a thin film deposition process. The thin film deposition process can be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof. Given that bonding processes in related technologies are low-temperature processes, in this embodiment, the doped amorphous silicon layer 230 is preferably grown on one side of the undoped semiconductor layer 220 and the channel layer 410 at approximately 400°C using an atomic layer deposition (ALD) process.

[0025] S130, Perform laser annealing to convert the doped amorphous silicon layer 230 into a doped polycrystalline silicon layer (see...). Figure 4 and Figure 5 At this point, the doped polycrystalline silicon layer obtained through heat treatment, namely the doped semiconductor layer 210 and the undoped semiconductor layer 220, together constitute the semiconductor layer 200.

[0026] S140. A third insulating layer 110 is formed on one side of the doped polysilicon layer to fill the partial gap between the remaining portion of the sacrificial structure 401 and the gate gap structure 900, as well as the partial gap between the remaining portions of two adjacent sacrificial structures 401 (see [link]). Figure 5 and Figure 6 ).

[0027] S150, forming an isolation hole 202 that penetrates the third insulating layer 110 and the semiconductor layer 200 along the stacking direction to expose one side of the word line connection portion 700 (see...). Figure 6 and Figure 7 ).

[0028] S160, Forming a fourth insulating layer 120 covering the third insulating layer 110 and filling the isolation holes 202 (see...) Figure 7 and Figure 8 The fourth insulating layer 120 can be formed by a thin film deposition process. Furthermore, after forming the fourth insulating layer 120 by thin film deposition, a portion of the fourth insulating layer 120 can be removed by a chemical mechanical polishing (CMP) process to form a flat surface on the side of the fourth insulating layer 120 away from the third insulating layer 110 (see...). Figure 8 ).

[0029] S170. At the portion of the fourth insulating layer 120 corresponding to the gate wire slot structure 900, a first connection hole 121 is formed that penetrates the fourth insulating layer 120 and the third insulating layer 110 along the stacking direction (see...). Figure 8 and Figure 9 ); and in the portion of the fourth insulating layer 120 located within the isolation hole 202, a second connection hole 122 is formed penetrating the fourth insulating layer 120 along the stacking direction (see Figure 7 and Figure 9 ).

[0030] S180, tungsten is filled into the first connecting hole 121 and the second connecting hole 122 to form the first connecting portion 530 and the second connecting portion 540 respectively (see Figure 9 and Figure 10 ).

[0031] S190, a third connecting portion 550 that contacts the first connecting portion 530 and a fourth connecting portion 560 that contacts the second connecting portion 540 are formed on the side of the fourth insulating layer 120 away from the third insulating layer 110 (see S190). Figure 10 and Figure 11 The materials of the third connecting part 550 and the fourth connecting part 560 are aluminum.

[0032] Because the core region 301 is filled with initial channel structures 400', and the spacing between each initial channel structure 400' is very small, and the depth of each initial channel structure 400' along the stacking direction is different, the exposed channel layer 410 after removing part of the functional layer 420 from each initial channel structure 400' is uneven. The part of the semiconductor layer 200 formed on the above-mentioned channel layer 410 is obviously uneven. Therefore, only the side of the gate line slot structure 900 away from the stacking structure 300 has a certain space. Thus, the first connection hole 121 can only be formed in the part of the fourth insulating layer 120 corresponding to the gate line slot structure 900. However, the space here is still small, which limits the overlap window and makes the process more difficult (see Figure 8 and Figure 9 Furthermore, in order to form a flat surface on the side of the fourth insulating layer 120 away from the semiconductor layer 200, a thicker fourth insulating layer 120 needs to be deposited on the side of the third insulating layer 110, and the thickness of the portion of the fourth insulating layer 120 located in the peripheral region 302 will be much greater than the thickness of the portion of the fourth insulating layer 120 located in the core region 301 (see...). Figure 8This not only significantly increases the difficulty of the CMP process in step S160, but also results in deeper and wider holes in the first connecting hole 121 and the second connecting hole 122 along the stacking direction. Consequently, due to the limitations of current process technology, aluminum cannot be directly filled, restricting the type of filling material. Therefore, in related technologies, tungsten needs to be filled into the first connecting hole 121 and the second connecting hole 122 respectively, and then aluminum is used to form the third connecting part 550 that contacts the first connecting part 530 and the fourth connecting part 560 that contacts the second connecting part 540 on the fourth insulating layer 120 (see...). Figure 11 This increases the complexity and cost of the lead wire process.

[0033] Furthermore, since the depths of each initial channel structure 400' along the stacking direction are different, the exposed channel layers 410 after removing part of the functional layer 420 of each initial channel structure 400' are uneven, resulting in the doped amorphous silicon layer 230 formed on the channel layer 410 being uneven. Since the dimensions of the initial channel structure 400' along the direction perpendicular to the stacking direction are very small, the portion of the doped amorphous silicon layer 230 formed on the channel layer 410 is prone to having sharp corners. However, since the temperature of the laser annealing process is as high as 1400℃~1500℃, the bonding interface cannot be directly baked by the high temperature. Therefore, in step S130, the laser annealing process can only make the surface of the doped amorphous silicon layer 230 crystallize quickly. The doped amorphous silicon layer 230 formed on the channel layer 410 is uneven and has sharp corners. This makes it very easy for the part of the doped amorphous silicon layer 230 formed on the channel layer 410 to melt, collapse or even crack during the laser annealing process. At the same time, it is also easy to cause uneven crystallization of the doped amorphous silicon layer 230.

[0034] To at least address some of the aforementioned problems, this application provides another method for fabricating a semiconductor device. Figure 23 A flowchart illustrating a method for fabricating a semiconductor device according to another embodiment of this application is shown; as follows: Figure 23 As shown, the preparation method 2000 includes: S210, A first insulating layer 100 is formed on one side of the intermediate semiconductor device 800 (see...) Figure 17 and Figure 19 ); among them, such as Figure 17 As shown, the intermediate semiconductor device 800 includes a stacked structure 300 and a semiconductor layer 200 located on one side of the stacked structure 300 along the stacking direction of the stacked structure 300. The stacked structure 300 includes a core region 301 having a plurality of channel structures 400 formed thereon. The channel structures 400 extend to the semiconductor layer 200, and the projections of the semiconductor layer 200 and the channel structures 400 in a plane parallel to the stacking direction do not overlap. A first insulating layer 100 is formed at least on a first surface 201 of the semiconductor layer 200 away from the stacked structure 300.

[0035] S220, In the portion of the first insulating layer 100 corresponding to the core region 301, a first lead-out portion 510 is formed that penetrates the first insulating layer 100 along the stacking direction, i.e., the z-direction, and contacts the semiconductor layer 200 (see...). Figure 21 ).

[0036] Since the projections of the semiconductor layer 200 and the channel structure 400 of the intermediate semiconductor device 800 used in this application do not overlap in a plane parallel to the stacking direction, in other words, the side of each channel structure 400 facing the semiconductor layer 200 is basically flush, and the part of the semiconductor layer 200 formed on the channel structure 400 is also basically flush, this application can not only remove the restriction on the formation position of the first lead 510 due to the different depths of each initial channel structure 400', but also significantly reduce the difficulty of the subsequent CMP process by forming a first insulating layer 100 on at least the first surface 201 of the semiconductor layer 200 away from the stacking structure 300, and forming a first lead 510 in contact with the semiconductor layer 200 on the part of the first insulating layer 100 corresponding to the core region 301. Furthermore, since the projections of the semiconductor layer 200 and the channel structure 400 in a plane parallel to the stacking direction do not overlap—that is, the portion of the semiconductor layer 200 formed on the channel structure 400 is substantially flush—this application allows for the formation of a thinner first insulating layer 100 on the first surface 201 of the semiconductor layer 200 away from the stack structure 300, while the first lead-out portion 510 is formed on the first insulating layer 100. This reduces the aspect ratio of the first lead-out portion 510, expands the range of materials that can be selected for the first lead-out portion 510, and makes it possible to directly form the first lead-out portion 510 using aluminum. This eliminates the need for a tungsten filling process, thereby reducing the complexity and cost of the lead wire process. Therefore, in the embodiments of this application, the first lead-out portion 510 can replace the first connection portion 530 and the third connection portion 550.

[0037] It should be noted that the phrase "the projections of the semiconductor layer 200 and the channel structure 400 in a plane parallel to the stacking direction do not overlap" in the above text generally refers to the fact that the sides of each channel structure 400 facing the semiconductor layer 200 are basically aligned. It should not be interpreted in an idealized or overly formal sense. In other words, slight overlap of the projections of the semiconductor layer 200 and the channel structure 400 in a plane parallel to the stacking direction due to process errors should also fall within the scope of protection claimed in this application.

[0038] Additionally, before performing step S210, such as Figure 24As shown, the fabrication method further includes: S200, forming an intermediate semiconductor device 800 based on the initial semiconductor device 800' (see... Figure 1 and Figure 17 The initial semiconductor device 800' includes multiple initial channel structures 400', a stacked structure 300, and a substrate insulating layer 610 and a substrate 600 sequentially disposed along the stacking direction of the stacked structure 300. The initial channel structures 400' sequentially penetrate the stacked structure 300 and the substrate insulating layer 610 and extend into the substrate 600. The channel structure 400 includes the portion of the initial channel structure 400' located in the stacked structure 300.

[0039] Furthermore, such as Figure 24 As shown, before performing step S200, the method further includes the step of forming an initial semiconductor device 800'. Specifically, the method further includes: S000, forming a substrate insulating layer 610 on one side of the substrate 600; S001, forming a stacked structure 300 on the side of the substrate insulating layer 610 away from the substrate 600; S002, forming a plurality of initial channel structures 400' that sequentially penetrate the stacked structure 300 and the substrate insulating layer 610 and extend into the substrate 600.

[0040] The following is a detailed description of each step in the method for fabricating semiconductor devices in the embodiments of this application.

[0041] Step S000

[0042] like Figure 1 As shown, a substrate insulating layer 610 is formed on one side of the substrate 600. The substrate insulating layer 610 may be, but is not limited to, a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. As an example, the thickness of the substrate insulating layer 610 is not less than 600 Å; for example, in the embodiments of this application, the thickness of the substrate insulating layer 610 is 600 Å, 650 Å, or 700 Å. Here, "thickness of the substrate insulating layer 610" generally refers to the distance between the side of the substrate insulating layer 610 facing the substrate 600 and the side away from the substrate 600 along the stacking direction of the stacked structure 300, i.e., the z-direction.

[0043] Additionally, it should be noted that the substrate 600 can be a currently fabricated substrate, meaning that the method includes a step of preparing the substrate 600 before performing step S000. Alternatively, an existing substrate can be used directly, meaning the step of preparing the substrate 600 can be omitted. The substrate 600 can be a single-layer structure or a multi-layer structure. For example, the substrate 600 can be a single-layer structure made of semiconductor material. The semiconductor material can be, but is not limited to, single-crystal silicon (Si), single-crystal germanium (Ge), silicon-germanium (GeSi), silicon carbide (SiC), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or gallium arsenide, etc., as III-V compounds. As an example, the substrate 600 is a single-crystal silicon layer. For example, substrate 600 may have a multilayer structure with at least two layers made of different materials. Substrate 600 may employ processes such as Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or any combination thereof. When substrate 600 has a multilayer structure, it may include a substrate sacrificial layer. This sacrificial layer may have various structural forms: for example, it may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. Alternatively, the substrate sacrificial layer may include a dielectric layer, a sacrificial layer, and a dielectric layer sequentially disposed, wherein the dielectric layer may be a silicon nitride layer, and the sacrificial layer may be a silicon oxide layer. Another example is that the substrate sacrificial layer may include at least one of a dielectric layer, a semiconductor layer, and a conductive layer. Furthermore, substrate 600 may also include a buffer layer formed on one side of the substrate sacrificial layer. As an example, the buffer layer may include at least one of a dielectric layer, a semiconductor layer, and a conductive layer. For example, the buffer layer may be a polysilicon layer. Of course, ion implantation or diffusion processes can also be used to form well regions doped with N-type or P-type dopants in a portion of the substrate 600. The dopants may include at least one of phosphorus (P), arsenic (As), and antimony (Sb). It should be noted that the well regions can be prepared using the same or different dopants, and the doping concentration of each well region can be the same or different; this application does not impose any limitations on this.

[0044] Step S001

[0045] Please continue to refer to this. Figure 1 A stacked structure 300 may be formed on the side of the substrate insulating layer 610 away from the substrate 600. Specifically, a stacked structure is formed on the side of the substrate insulating layer 610 away from the substrate 600, wherein the stacked structure includes alternately stacked sacrificial layers and second insulating layers 320; the sacrificial layers are replaced with gate layers 310 to form the stacked structure 300.

[0046] The stacked structure can be formed on one side of the substrate insulating layer 610 using a thin-film deposition process. This thin-film deposition process can be, but is not limited to, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Atomic Layer Deposition (ALD), or any combination thereof. In some embodiments, the stacked structure may include paired sacrificial layers and second insulating layers 320. For example, the stacked structure may include, but is not limited to, 64, 128, or more pairs of sacrificial layers and second insulating layers 320. The second insulating layer 320 can be a silicon oxide layer, and the sacrificial layer can be a silicon nitride layer. The silicon oxide layer serves as an isolation layer, and the silicon nitride layer can be replaced with the gate layer 310 in subsequent processes.

[0047] It should be noted that the above mainly describes the fabrication method of a single stacked structure, that is, the case where the number of layers in the stacked structure is small. However, as the storage capacity of 3D memory continues to increase, the number of layers in the stacked structure also continues to increase. Related technologies typically employ dual-stack or multi-stack techniques to fabricate semiconductor devices. That is, multiple sub-stacked structures are sequentially stacked along the direction away from the substrate 600, on the side of the substrate insulating layer 610 away from the substrate 600, to form a stacked structure. Each sub-stacked structure includes multiple alternately stacked sacrificial layers and a second insulating layer 320. The number of layers in each sub-stacked structure can be the same or different. Since the fabrication method of a single stacked structure can be fully or partially applied to multiple sub-stacked structures, related or similar content will not be elaborated further.

[0048] Step S002

[0049] Please continue to refer to this. Figure 1 This forms multiple initial channel structures 400' that sequentially penetrate the stacked structure 300 and the substrate insulating layer 610 and extend into the substrate 600, specifically including: Multiple channel holes are formed sequentially through the stacked structure 300 and the substrate insulating layer 610 and extending into the substrate 600. Given the lateral drilling problem inherent in wet etching, the channel holes can be formed using dry etching, a combination of dry and wet etching processes, or a patterning process. The patterning process includes photolithography, cleaning, and chemical mechanical polishing. The cross-sectional shape of the channel holes, i.e., the cross-sectional shape perpendicular to the stacking direction, can be, but is not limited to, circular, elliptical, or polygonal. As an example, the steps for forming the channel holes may include: forming a mask layer on the side of the stacked structure 300 away from the substrate insulating layer 610, wherein the mask layer defines a cross-sectional image of the channel holes, and the mask layer can be, but is not limited to, a silicon nitride layer or a titanium nitride layer; etching the channel holes at the locations where the cross-sectional image of the channel holes is defined in the mask layer using a plasma dry etching process; and removing the mask layer.

[0050] A functional layer 420 and a channel layer 410 are sequentially formed on the inner wall of the channel aperture. Both the functional layer 420 and the channel layer 410 can be formed using a thin-film deposition process, which can be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination thereof. As an example, the steps for forming the functional layer 420 and the channel layer 410 may include: forming a barrier layer on the inner wall of the channel aperture to prevent charge outflow; forming a charge trapping layer on the side of the barrier layer away from the inner wall of the channel aperture to store charge; forming a tunneling layer on the layer of the charge trapping layer away from the barrier layer; and forming the channel layer 410 on the side of the tunneling layer away from the charge trapping layer to transport the desired charge, i.e., electrons or holes. The barrier layer and tunneling layer may be, but are not limited to, oxide layers, and the charge trapping layer may be, but is not limited to, a nitride layer. That is, functional layer 420 includes an ONO structure, and channel layer 410 may be, but is not limited to, an amorphous silicon layer, a polycrystalline silicon layer, or a monocrystalline silicon layer. It should be noted that those skilled in the art should understand that, without departing from the teachings of this application, the formation position of functional layer 420 on the inner wall of the channel hole can be controlled according to different semiconductor device architectures. That is, functional layer 420 may be formed on the sidewalls and bottom surface of the channel hole, or it may be formed only on the sidewalls of the channel hole; this application does not limit this.

[0051] A dielectric layer 430 is filled within the pores formed by the channel layer 410. The dielectric layer 430 can be formed using a channel filling process, and the material of the dielectric layer 430 can be, but is not limited to, a silicon oxide layer. Furthermore, to reduce structural stress, multiple insulating gaps can be formed within the dielectric layer 430 by controlling the corresponding parameters of the channel filling process during its formation.

[0052] A channel plug electrically connected to the channel layer 410 is formed at one end of the dielectric layer 430 away from the substrate 600, wherein the material of the channel plug can be the same as the material of the channel layer 410.

[0053] As can be seen from the above, the cross-sectional dimensions of the initial channel structure 400' formed by the above steps are basically the same along the stacking direction. A portion of the initial channel structure 400' is located in the substrate 600 and the substrate insulating layer 610, and another portion is located in the stacked structure 300. For ease of description, the portion of the initial channel structure 400' located in the substrate 600 and the substrate insulating layer 610 can be referred to as the sacrificial structure 401, and the portion of the initial channel structure 400' located in the stacked structure 300 can be referred to as the channel structure 400.

[0054] Of course, considering that subsequent processes require the removal of the portion of the initial channel structure 400' located in the substrate 600 and the substrate insulating layer 610, i.e., the sacrificial structure 401, to prevent polishing slurry or etching slurry from entering the channel structure 400, a shrinkage layer can be formed on the surface of the channel hole before the functional layer 420 and the channel layer 410 are sequentially formed on the inner wall of the channel hole. This allows the channel structure 400 to be sealed based on the shrinkage layer after the sacrificial structure 401 is removed. Specifically, before performing step S001, i.e., before forming the stacked structure 300 on the side of the substrate insulating layer 610 away from the substrate 600, the fabrication method further includes: forming an undoped semiconductor layer 220 on the side of the substrate insulating layer 610 away from the substrate 600 (see...). Figure 1 The stacked structure 300 may be formed on the side of the undoped semiconductor layer 220 away from the substrate insulating layer 610. Therefore, the step of forming the initial channel structure 400' may include: forming a constriction layer that sequentially penetrates the stacked structure 300, the undoped semiconductor layer 220, and the substrate insulating layer 610 and extends into the substrate 600; forming a constriction layer on the surface of the undoped semiconductor layer 220 exposed to the channel hole, the constriction layer surrounding the constriction hole having a smaller aperture than the channel hole; sequentially forming a functional layer 420 and a channel layer 410 on the inner wall of the channel and the surface of the constriction layer; filling the aperture formed by the channel layer 410 with a dielectric layer 430; and forming a channel plug electrically connected to the channel layer 410 at the end of the dielectric layer 430 away from the substrate 600.

[0055] As can be seen from the above, the cross-sectional dimensions of the initial channel structure 400' formed by the above steps are not the same along the stacking direction. A portion of the initial channel structure 400' is located in the substrate 600 and the substrate insulating layer 610, a portion is located in the undoped semiconductor layer 220, and another portion is located in the stacked structure 300. The portion of the initial channel structure 400' located in the undoped semiconductor layer 220 has the smallest cross-sectional dimension. For ease of description, as... Figure 1 As shown, the portion of the initial channel structure 400' located in the substrate 600 and the substrate insulating layer 610 can be referred to as the sacrificial structure 401, the portion of the initial channel structure 400' located in the undoped semiconductor layer 220 can be referred to as the confinement structure 402, and the portion of the initial channel structure 400' located in the stacked structure 300 can be referred to as the channel structure 400. The cross-sectional dimension of the confinement structure 402 is smaller than that of the sacrificial structure 401 and the channel structure 400. That is, in a plane perpendicular to the stacking direction, the projected area of ​​the confinement structure 402 is smaller than that of the sacrificial structure 401 and the channel structure 400.

[0056] As an example, the confinement layer can be formed by oxidizing a portion of the undoped semiconductor layer 220 exposed to the channel hole. In other words, in this embodiment, the confinement layer can be an oxide layer. Based on the oxidation principle, the growth of the confinement layer during oxidation requires the consumption of the undoped semiconductor layer 220. That is, for every x thickness of the confinement layer grown, y thickness of the undoped semiconductor layer 220 is consumed, where x is greater than y. Therefore, as the confinement layer grows during oxidation, it gradually protrudes into the channel hole, making the diameter of the confinement hole formed by the confinement layer smaller than the diameter of the channel hole. The confinement layer can be an annular protrusion structure, and the growth rate of the confinement layer along the stacking direction is basically the same; in other words, the diameter of the confinement hole is basically the same along the stacking direction. Of course, in actual processes, the growth rate of the confinement layer along the stacking direction may differ. For example, the oxidation rate at both ends of the confinement layer along the stacking direction is less than the oxidation rate in the middle of the confinement layer, resulting in the side of the confinement layer away from the undoped semiconductor layer 220 exhibiting an arc-shaped surface protruding radially from the channel hole and away from the undoped semiconductor layer 220. In this case, the shape of the limiting aperture formed by the limiting layer is similar to that of an hourglass. The aperture of the limiting aperture gradually decreases and then gradually increases towards the substrate 600. In other words, the limiting aperture includes a tapered aperture and a dipping aperture that are connected sequentially towards the substrate 600. As the names suggest, a tapered aperture indicates that its aperture gradually decreases towards the substrate 600, and a dipping aperture indicates that its aperture gradually increases towards the substrate 600. The minimum aperture of the limiting aperture is generally located at the junction of the tapered aperture and the dipping aperture.

[0057] It should be noted that when the substrate 600 is a polycrystalline silicon layer, during the formation of the shrinkage layer using an oxidation process such as wet oxidation, the portion of the substrate 600 exposed within the channel vias will also be oxidized, thus forming an oxide layer. Furthermore, those skilled in the art should understand that the formation of the shrinkage layer via an oxidation process is merely an example, and any other suitable process can be used to form the shrinkage layer without departing from the teachings of this application.

[0058] Step S200

[0059] Forming an intermediate semiconductor device 800 based on the initial semiconductor device 800' specifically includes: removing the substrate 600 to expose the portion of the initial channel structure 400' located within the substrate 600 (see...). Figure 1 and Figure 2 ); Remove the substrate insulating layer 610 and the exposed portion of the initial channel structure 400' (see Figure 14 ); Form semiconductor layer 200 (see Figure 17 ).

[0060] As can be seen from step S002 above, the cross-sectional dimensions of the initial channel structure 400' can be substantially the same or different along the stacking direction. The specific steps for forming the intermediate semiconductor device 800 based on the initial semiconductor device 800' differ for these two different initial channel structure 400' forms. Specifically: Scenario 1: When the cross-sectional dimensions of the initial channel structure 400' differ along the stacking direction, i.e., when the initial channel structure 400' includes a sacrificial structure 401 located in the substrate 600 and substrate insulating layer 610, a constriction structure 402 located in the undoped semiconductor layer 220, and a channel structure 400 located in the stacked structure 300, step S200 may include: removing the substrate 600 to expose the portion of the initial channel structure 400' located within the substrate 600 (see...). Figure 1 and Figure 2 ); Remove the substrate insulating layer 610 and the functional layer 420 of the sacrificial structure 401 to expose the side of the undoped semiconductor layer 220 away from the stacked structure 300 and the channel layer 410 of the sacrificial structure 401 (see Figure 2 and Figure 3 ); Remove the channel layer 410 and dielectric layer 430 of the sacrificial structure 401 to expose part of the confinement structure 402; fill the first gap formed by the dielectric layer 430 of the confinement structure 402 with an insulating layer 440 to seal the first gap (see Figure 15 A doped amorphous silicon layer 230 is formed on the side of the undoped semiconductor layer 220 away from the stacked structure 300 (see...). Figure 16 ); heat treatment is performed to convert the doped amorphous silicon layer 230 into a doped polycrystalline silicon layer (see Figure 17The semiconductor layer 200 includes a doped polysilicon layer and an undoped semiconductor layer 220.

[0061] The channel layer 410 and dielectric layer 430 of the sacrificial structure 401 can be removed simultaneously using a low-selectivity etchant, or they can be removed in two steps. As an example, removing the channel layer 410 and dielectric layer 430 of the sacrificial structure 401 may include: removing the channel layer 410 of the sacrificial structure 401 to expose the dielectric layer 430 of the sacrificial structure 401 (see...). Figure 13 The dielectric layer 430 of the sacrificial structure 401 is removed to expose a portion of the confined structure 402. It should be noted that the lengths of the functional layer 420, channel layer 410, and dielectric layer 430 removed along the stacking direction can be different. For example, the length of the channel layer 410 removed can be slightly shorter than the lengths of the functional layer 420 and dielectric layer 430 removed. In other words, after removing the portion of the initial channel structure 400' to expose it, the channel layer 410 protrudes beyond the functional layer 420 and dielectric layer 430 along the stacking direction. This arrangement increases the contact area between the channel layer 410 and the subsequently formed doped polysilicon layer, which is beneficial for subsequent process connections. Additionally, during the removal of the channel layer 410, a portion of the undoped semiconductor layer 220 may also be removed. Since the thickness of the undoped semiconductor layer 220 along the stacking direction is generally greater than the thickness of the channel layer 410, after removing the channel layer 410 of the sacrificial structure 401, a certain thickness of the undoped semiconductor layer 220 remains on one side of the stacked structure 300. In other words, the undoped semiconductor layer 220 will be thinned.

[0062] Furthermore, it should be noted that in the embodiments of this application, the depth to which the initial channel structure 400' is removed can be controlled by adjusting the concentration of the etching solution, the etching time, or by setting a corresponding stop layer. For example, only the portion of the initial channel structure 400' located between the substrate 600 and the substrate insulating layer 610 can be removed, that is, only the sacrificial structure 401 can be removed, and the undoped semiconductor layer 220 can be used as the stop layer for the etching process. Of course, in addition to removing the sacrificial structure 401, a portion of the confinement structure 402 can also be removed to expose part of the inner wall of the confinement hole.

[0063] In some embodiments, filling the first gap formed within the dielectric layer 430 of the constriction structure 402 with an insulating layer 440 to seal the first gap may include: forming an insulating layer 440 on the side of the undoped semiconductor layer 220 away from the stacked structure 300 to cover the surface of the undoped semiconductor layer 220 away from the stacked structure 300 and to fill the first gap (see [link to documentation]). Figure 14 At least the portion of the isolation insulating layer 440 covering the undoped semiconductor layer 220 away from the surface of the stacked structure 300 is removed, so that the remaining isolation insulating layer 440 closes the first gap (see...). Figure 15As described above regarding the steps for forming the initial channel structure 400', before the functional layer 420 and the channel layer 410 are sequentially formed on the inner wall of the channel hole, a confinement layer (not shown in the figure) can be formed on the surface of the channel hole based on the undoped semiconductor layer 220 exposed thereon. Since the aperture of the confinement hole formed by the confinement layer is smaller than the aperture of the channel hole, the cross-sectional dimension of the confinement structure 402 subsequently formed thereon is much smaller than the cross-sectional dimensions of the sacrificial structure 401 and the channel structure 400. Therefore, after removing the channel layer 410 and the dielectric layer 430 of the sacrificial structure 401, the first gap formed by the dielectric layer 430 will be exposed. Since the aperture of this first gap is very small, the first gap will be quickly partially closed by the isolation insulating layer 440 during the deposition of the isolation insulating layer 440 on the side of the undoped semiconductor layer 220 away from the stacked structure 300. Subsequently, the portion of the isolation insulating layer 440 covering the undoped semiconductor layer 220 away from the surface of the stacked structure 300 is removed. The portion of the isolation insulating layer 440 in the first gap can prevent polishing slurry or etching slurry in subsequent processes from entering the first gap.

[0064] Scenario 2: When the cross-sectional dimensions of the initial channel structure 400' are substantially the same along the stacking direction, that is, when the initial channel structure 400' includes the sacrificial structure 401 located in the substrate 600 and the substrate insulating layer 610 and the channel structure 400 located in the stacked structure 300, step S200 may include: removing the substrate 600 to expose the portion of the initial channel structure 400' located within the substrate 600; removing the substrate insulating layer 610 and the functional layer 420 of the sacrificial structure 401 to expose one side of the stacked structure 300 and the channel layer 410 of the sacrificial structure 401; removing at least the channel layer 410 and the dielectric layer 430 of the sacrificial structure 401 to expose a portion of the channel structure 400; and filling the second gap formed by the dielectric layer 430 of the channel structure 400 with an insulating layer 440 to seal the second gap. A doped amorphous silicon layer 230 is formed on one side of the stacked structure 300; a heat treatment is performed to convert the doped amorphous silicon layer 230 into a doped polycrystalline silicon layer, wherein the semiconductor layer 200 includes the doped polycrystalline silicon layer.

[0065] It should be noted that, since the cross-sectional dimensions of the initial channel structure 400' in scenario two are basically the same along the stacking direction, the aperture of the second gap is significantly larger than that of the first gap in scenario one. Therefore, a thicker insulating layer 440 needs to be deposited on one side of the stacked structure 300 to seal the second gap. After forming the insulating layer 440, removing the portion of the insulating layer 440 covering the surface of the stacked structure 300 can easily reopen the second gap due to its relatively thick thickness, making the filling process relatively difficult. Thus, the presence of the shrinkage structure 402 in scenario one can reduce the difficulty of the filling process. Of course, the step of filling the insulating layer 440 can also be omitted in the embodiments of this application. In this case, although the second gap formed by the dielectric layer 430 of the channel structure 400 will gradually be exposed during the removal of the channel layer 410 and dielectric layer 430 of the sacrificial structure 401, and etching or polishing fluid may enter the second gap, research has shown that the entry of certain etching or polishing fluids, such as HF acid, into the second gap does not affect the overall electrical performance of the semiconductor device.

[0066] It should be noted that in both scenarios described above, the substrate 600 can be removed using the following steps: First, a chemical mechanical polishing (CMP) process can be used to rough-polish the side of the substrate 600 away from the substrate insulating layer 610 to thin the substrate 600; for example, the CMP process can be used to thin the thickness of the substrate 600 from approximately 700 μm to approximately 7 μm; then, a low-selectivity etchant can be used to etch the substrate 600 to increase the etching rate; next, a high-selectivity etchant can be used to remove the remaining substrate 600, with the substrate insulating layer 610 serving as the stop layer for the etching process. Alternatively, in addition to the above method, a low-selectivity etchant can be used to etch the substrate 600 until the portion of the initial channel structure 400' located within the substrate 600 is exposed. The former method, of course, has a faster etching rate and lower cost. Furthermore, in both scenarios, the heat treatment process used to form the semiconductor layer 200 can be, but is not limited to, laser annealing. In scenario one, after removing the exposed portion of the initial channel structure 400', the subsequently formed doped amorphous silicon layer 230 comes into contact with the confinement structure 402. During laser annealing, the confinement structure 402, the doped amorphous silicon layer 230, and the undoped semiconductor layer 220 melt and crystallize together. In other words, after laser annealing, the confinement structure 402 forms an integral, undetectable interface with the doped amorphous silicon layer 230 and the undoped semiconductor layer 220.

[0067] As can be seen from the above, in both scenario one and scenario two, by removing part of the initial channel structure 400', this application ensures that the projections of the remaining initial channel structure 400', i.e., the channel structure 400 and the semiconductor layer 200 in the plane parallel to the stacking direction do not overlap. This not only removes the restriction on the formation position of the first lead 510 due to the different depths of each channel structure 400, allowing the first lead 510 to be formed at any position corresponding to the first insulating layer 100 and the core region 301, but is no longer limited to the position corresponding to the gate gap structure 900, thereby reducing the process difficulty and increasing the overlap window, but also significantly reduces the difficulty of the subsequent CMP process. At the same time, it also makes the part of the doped polysilicon layer formed in the subsequent process corresponding to the channel structure 400 basically flush, thereby avoiding melting, collapse, or even cracking due to unevenness or sharp corners of the doped polysilicon layer during the subsequent heat treatment process, and also avoiding the occurrence of uneven crystallization of the doped amorphous silicon layer 230.

[0068] In some embodiments, the initial semiconductor device 800' further includes a plurality of gate line slot structures 900, which penetrate the stacked structure 300 along the stacking direction and extend along a first direction perpendicular to the stacking direction, namely the y-direction, wherein the y-direction is perpendicular to the x-direction and the z-direction, and the z-direction is the stacking direction. Thus, for the first scenario, before forming the doped amorphous silicon layer 230 on the side of the undoped semiconductor layer 220 away from the stacked structure 300, the fabrication method may further include: removing the portion of the gate line slot structure 900 exposed on the side of the undoped semiconductor layer 220, so that the portion of the undoped semiconductor layer 220 away from the stacked structure 300 and corresponding to the core region 301 forms a flat surface (see...). Figure 22 Similarly, for scenario two, before forming a doped amorphous silicon layer 230 on one side of the stacked structure 300, the fabrication method may further include: removing the portion of the gate gap structure 900 exposed on one side of the stacked structure 300, so that one side of the stacked structure 300 and the portion corresponding to the core region 301 forms a flat surface.

[0069] Step S210

[0070] A first insulating layer 100 is formed on one side of the intermediate semiconductor device 800 (see...). Figure 17 and Figure 19The first insulating layer 100 is formed on the first surface 201 of the semiconductor layer 200 by a thin film deposition process. The material forming the first insulating layer 100 may be, but is not limited to, silicon dioxide, silicon nitride, or other materials. The aforementioned thin film deposition process may be, but is not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or any combination of the above processes. The thickness of the portion of the first insulating layer 100 located in the core region 301 may be less than or equal to 1000 nm.

[0071] In some embodiments, such as Figure 17 As shown, the stacked structure 300 also includes a peripheral region 302 located on at least one side of the core region 301. Within the core region 301, the stacked structure 300 includes gate layers 310 and second insulating layers 320 alternately stacked along the stacking direction. The intermediate semiconductor device 800 also includes a word line connection portion 700 located in the peripheral region 302 and electrically connected to the gate layer 310. In this case, step S210 includes: forming an isolation via 202 penetrating the semiconductor layer 200 along the stacking direction in the portion of the semiconductor layer 200 corresponding to the word line connection portion 700 (see...). Figure 18 ); forming a first insulating layer 100 covering the first surface 201 and filling the isolation holes 202 (see Figure 19 Thus, the first insulating layer 100 formed includes a horizontal portion covering the first surface 201 and a protrusion 101 located within the isolation hole 202.

[0072] Since the projections of the semiconductor layer 200 and the channel structure 400 in a plane parallel to the stacking direction do not overlap, that is, the portion of the semiconductor layer 200 formed on the channel structure 400 is basically flush, this application only needs to form a thinner first insulating layer 100 to cover the first surface 201 and fill the isolation via 202. Furthermore, the thickness of the portion of the first insulating layer 100 located on the periphery is not much different from the thickness of the portion of the first insulating layer 100 located in the core region 301. This not only reduces the difficulty of subsequently planarizing the first insulating layer 100 using CMP technology, but also reduces the aspect ratio of the first lead 510 and the second lead 520 subsequently formed on the first insulating layer 100, expanding the range of selectable materials for the first lead 510 and the second lead 520, making it possible to directly form the first lead 510 and the second lead 520 using aluminum, thereby eliminating the need for a tungsten filling process and reducing the complexity and cost of the lead wire process.

[0073] Step S220

[0074] In the portion of the first insulating layer 100 corresponding to the core region 301, a first lead-out portion 510 is formed that penetrates the first insulating layer 100 along the stacking direction and contacts the semiconductor layer 200 (see [link]). Figure 21 The material of the first lead-out part 510 may be, but is not limited to, tungsten with a density of less than 10 g / cm³. 3 Metals and / or metal alloys.

[0075] In some embodiments, step S220 may include: forming a first lead-out hole 102 penetrating the first insulating layer 100 along the stacking direction to expose a portion of the first surface 201 of the semiconductor layer 200 (see...). Figure 20 ); and fill the first lead-out hole 102 with conductive material to form the first lead-out portion 510 (see Figure 21 Since the projections of the semiconductor layer 200 and the channel structure 400 of the intermediate semiconductor device 800 used in this application do not overlap in a plane parallel to the stacking direction, in other words, the sides of each channel structure 400 facing the semiconductor layer 200 are basically flush, and the portion of the semiconductor layer 200 formed on the channel structure 400 is also basically flush, a thinner first insulating layer 100 can be formed in step S210. Since the first lead-out hole 102 forms the first insulating layer 100, the thickness of the first insulating layer 100 determines the depth of the first lead-out hole 102. Therefore, the first lead-out hole 102 can have a smaller aspect ratio, thereby expanding the range of wire materials used to fill the first lead-out hole 102. This makes it possible to directly fill the first lead-out hole 102 with aluminum, thus eliminating the need for a tungsten filling process and reducing the complexity and cost of the lead wire process. In this embodiment, the conductive material used to fill the first lead-out hole 102 can be, but is not limited to, tungsten with a density less than 10 g / cm³. 3 Metals and / or metal alloys.

[0076] As can be seen from the above, since the first lead-out hole 102 has a small aspect ratio, aluminum can be directly used to fill the first lead-out hole 102. Specifically, a thin film deposition process can be used to deposit aluminum on the side of the first insulating layer 100 away from the semiconductor layer 200 to cover the side of the first insulating layer 100 away from the semiconductor layer 200 and fill the first lead-out hole 102; the aluminum covering the side of the first insulating layer 100 is removed, wherein the aluminum in the first lead-out hole 102 constitutes the first lead-out portion 510. It should be noted that although the width of the first lead-out hole 102 perpendicular to the stacking direction is relatively large in this application, in other words, the internal space of the first lead-out hole 102 is large and a large amount of conductive material needs to be filled, since the first lead-out hole 102 has a small aspect ratio, aluminum can be directly used to fill it, and aluminum has a very low density, only 2.7 g / cm³. 3Therefore, even if a thicker layer of aluminum is deposited on one side of the first insulating layer 100 to fill the first lead-out hole 102, the entire intermediate semiconductor device 800 will not be bent. Of course, tungsten can also be used to fill the first lead-out hole 102 in this application, but compared with aluminum, tungsten has a relatively higher density. If the internal space of the first lead-out hole 102 is relatively large, then a thicker layer of tungsten needs to be deposited on one side of the first insulating layer 100, which may bend the intermediate semiconductor device 800.

[0077] In some embodiments, the width of the first lead-out portion 510 along the second direction, i.e. the width in the x-direction, is 200nm to 1200nm, wherein the x-direction is perpendicular to the y-direction and the z-direction, and the z-direction is the stacking direction of the stacked structure 300.

[0078] In some embodiments, the preparation method further includes: forming a second lead-out hole 103 penetrating the first insulating layer 100 along the stacking direction in the portion of the first insulating layer 100 located within the isolation hole 202, to expose the word line connection portion 700 (see...). Figure 20 ); and fill the second lead-out hole 103 with conductive material to form the second lead-out portion 520 (see Figure 21 Because this application can form a relatively thin first insulating layer 100 in step S210, and the second lead-out hole 103 is also formed with the first insulating layer 100, the second lead-out hole 103 can also have a smaller aspect ratio. This expands the range of conductive materials that can fill the second lead-out hole 103, making it possible to directly fill the second lead-out hole 103 with aluminum, eliminating the need for tungsten filling, thereby reducing the complexity and cost of the lead wire process. In this embodiment, the conductive material filling the second lead-out hole 103 can be, but is not limited to, tungsten, metals with a density less than 10 g / cm³, and / or metal alloys.

[0079] It should be noted that, as described in step S210 above, when the intermediate semiconductor device 800 includes a word line connection portion 700, before depositing the first insulating layer 100 on the first surface 201 of the semiconductor layer 200, it is necessary to form an isolation hole 202 penetrating the semiconductor layer 200 along the stacking direction in the portion of the semiconductor layer 200 corresponding to the word line connection portion 700 (see [link to documentation]). Figure 18Therefore, the first insulating layer 100 formed in step S210 may include a horizontal portion covering the first surface 201 and a protrusion 101 located within the isolation hole 202. Thus, the second lead-out portion 520 formed in this step has a protrusion 101 between it and the semiconductor layer 200, that is, along the x and y directions, the protrusion 101 is located between the second lead-out portion 520 and the semiconductor layer 200. In other words, the first insulating layer 100 at least partially covers the sidewall of the second lead-out portion 520 along the stacking direction, i.e., the z direction, to isolate the second lead-out portion 520 and the semiconductor layer 200. Furthermore, it should be noted that the first lead-out portion 510 and the second lead-out portion 520 can be formed simultaneously. In other words, the first lead-out hole 102 and the second lead-out hole 103 can be formed in the same process step, so that the first lead-out hole 102 and the second lead-out hole 103 can be filled simultaneously during subsequent deposition of conductive material.

[0080] As can be seen from the above, since the second lead-out hole 103 has a small aspect ratio, aluminum can be directly used to fill the second lead-out hole 103. Specifically, a thin-film deposition process can be used to deposit aluminum on the side of the first insulating layer 100 away from the semiconductor layer 200 to cover the side of the first insulating layer 100 away from the semiconductor layer 200 and fill the second lead-out hole 103; the aluminum covering the side of the first insulating layer 100 is then removed, wherein the aluminum in the second lead-out hole 103 constitutes the second lead-out portion 520. Similarly, since aluminum has a low density, even if a thicker layer of aluminum is deposited on the side of the first insulating layer 100 to fill the second lead-out hole 103, the entire intermediate semiconductor device 800 will not be bent. Of course, tungsten can also be used to fill the second lead-out hole 103 in this application. Similarly, as above, there is a risk of bending the intermediate semiconductor device 800 when using tungsten to fill the second lead-out hole 103.

[0081] In some embodiments, the aspect ratio of the second lead-out portion 520 is less than 1:4, which is the ratio of the depth of the second lead-out portion 520 along the stacking direction to the maximum width of its projection onto a plane perpendicular to the stacking direction.

[0082] In addition, such as Figure 21As shown, this application also provides a semiconductor device, which includes a stacked structure 300, a semiconductor layer 200, a first insulating layer 100, and a first lead-out portion 510. The stacked structure 300 includes a core region 301 with a plurality of channel structures 400 formed thereon. The semiconductor layer 200 is located on one side of the stacked structure 300 along the stacking direction of the stacked structure 300. The channel structures 400 extend to the semiconductor layer 200, and the projections of the semiconductor layer 200 and the channel structures 400 in a plane parallel to the stacking direction do not overlap. The first insulating layer 100 is located at least on a first surface 201 of the semiconductor layer 200 away from the stacked structure 300. The first lead-out portion 510 penetrates the portion of the first insulating layer 100 corresponding to the core region 301 along the stacking direction and contacts the semiconductor layer 200.

[0083] Since the projections of the semiconductor layer 200 and the channel structure 400 of the semiconductor device in this application do not overlap in a plane parallel to the stacking direction, in other words, the side of each channel structure 400 facing the semiconductor layer 200 is basically flush, and the portion of the semiconductor layer 200 formed on the channel structure 400 is also basically flush, this application not only allows the first insulating layer 100 to have a thinner thickness, thereby allowing the first lead 510 to have a smaller aspect ratio, expanding the material range of the first lead 510, making it possible to directly use aluminum to form the first lead 510, thus eliminating the step of forming the first connection portion 530, reducing the complexity of the lead wire process, but also eliminates the need to display the formation position of the first lead 510 due to the different depths of each channel structure 400, allowing the first lead 510 to be formed at any position corresponding to the first insulation and the core region 301, instead of being limited to the position corresponding to the gate gap structure 900, thereby reducing the process difficulty of fabricating the first lead 510 and increasing the overlap window.

[0084] In some embodiments, the material of the first lead-out portion 510 includes a metal and / or metal alloy with a density of less than 10 g / cm3. As an example, the material of the first lead-out portion 510 is aluminum.

[0085] In some embodiments, all channel structures 400 have the same depth along the stacking direction, that is, all channel structures 400 have the same depth along the z-direction.

[0086] In some embodiments, the thickness of the portion of the first insulating layer 100 located in the core region 301 is less than or equal to 1000 nm.

[0087] In some embodiments, the semiconductor device further includes a plurality of gate line slot structures 900, which penetrate the stacked structure 300 along the stacking direction and extend along a first direction perpendicular to the stacking direction, i.e., the y-direction, wherein the y-direction is perpendicular to the x-direction and the z-direction, and the z-direction is the stacking direction; wherein the portion of the first surface 201 between two adjacent gate line slot structures 900 is a flat surface, and the first lead-out portion 510 is located on the flat surface (see...). Figure 21 ).

[0088] In some embodiments, the first surface 201 of the semiconductor layer 200 is a flat surface (see...). Figure 22 This flat surface can be achieved by removing part of the initial channel structure 400' and part of the gate line slot structure 900. The specific steps can be found above and will not be repeated here.

[0089] In some embodiments, the width of the first lead-out portion 510 along the second direction is 200nm~1200nm, and the second direction is perpendicular to the first direction and the stacking direction. The first direction can be the y-direction, the second direction can be the x-direction, and the stacking direction can be the z-direction.

[0090] In some embodiments, the semiconductor layer 200 may include an undoped semiconductor layer 220 and a doped semiconductor layer 210, with the doped semiconductor layer 210 located on the side of the undoped semiconductor layer 220 away from the stacked structure 300. As an example, each channel structure 400 extends to the undoped semiconductor layer 220. The undoped semiconductor layer 220 and the doped semiconductor layer 210 may be made of the same or different materials; for example, both may be polycrystalline silicon layers, differing only in whether they are doped. Taking the example that both the undoped semiconductor layer 220 and the doped semiconductor layer 210 are polycrystalline silicon layers, and the undoped semiconductor layer 220 and the doped semiconductor layer 210 are in direct contact, although both are polycrystalline silicon, since the undoped semiconductor layer 220 and the doped semiconductor layer 210 are formed through two processes respectively, and the polycrystalline silicon layer is easily oxidized, a very thin oxide film (not shown in the figure) will quickly form on the surface of the undoped semiconductor layer 220 after it is formed. As a result, the subsequently formed doped semiconductor layer 210 is located on this oxide film. In other words, there is a detectable interface between the undoped semiconductor layer 220 and the doped semiconductor layer 210, namely the oxide film mentioned above.

[0091] In some embodiments, the stacked structure 300 further includes a peripheral region 302 located on at least one side of the core region 301. Within the core region 301, the stacked structure 300 includes a gate layer 310 and a second insulating layer 320 alternately stacked along the stacking direction. The semiconductor device may further include a word line connection portion 700 and a second lead-out portion 520. The word line connection portion 700 is located in the peripheral region 302 and is electrically connected to the gate layer 310. The second lead-out portion 520 penetrates the first insulating layer 100 along the stacking direction and is electrically connected to the word line connection portion 700. The first insulating layer 100 at least partially covers the sidewall of the second lead-out portion 520 extending along the stacking direction.

[0092] Similarly, since the projections of the semiconductor layer 200 and the channel structure 400 of the semiconductor device in this application do not overlap in a plane parallel to the stacking direction, in other words, the side of each channel structure 400 facing the semiconductor layer 200 is basically flush, and the portion of the semiconductor layer 200 formed on the channel structure 400 is also basically flush, this application allows the first insulating layer 100 to have a thinner thickness. The thickness of the portion of the first insulating layer 100 located in the core region 301 is not much different from the thickness of the portion located in the peripheral region 302, thereby allowing the second lead 520 to have a smaller aspect ratio, expanding the material range of the second lead 520, making it possible to directly use aluminum to form the second lead 520, thereby eliminating the step of forming the second connection portion 540 and reducing the complexity of the lead wire process.

[0093] In some embodiments, the material of the second lead-out portion 520 includes a metal and / or metal alloy with a density of less than 10 g / cm3. As an example, the material of the second lead-out portion 520 is aluminum.

[0094] In some embodiments, the aspect ratio of the second lead-out portion 520 is less than 1:4, and the aspect ratio is the ratio of the depth of the second lead-out portion 520 along the stacking direction to the maximum width of its projection onto a plane perpendicular to the stacking direction.

[0095] In some embodiments, the second lead-out portion 520 can be integrally formed, that is, the second lead-out portion 520 can be directly electrically connected to an external device. In other words, the second lead-out portion 520 in the embodiments of this application can replace the second connecting portion 540 and the fourth connecting portion 560.

[0096] In addition, this application embodiment also provides a storage system, which includes a controller and the aforementioned semiconductor device. The controller is coupled to the semiconductor device and is used to control the semiconductor device to store data. The semiconductor device includes at least one of a three-dimensional NAND flash memory and a three-dimensional NOR flash memory.

[0097] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. As an example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this application can be achieved, and this is not limited herein.

[0098] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure, the stacked structure comprising gate layers and a second insulating layer alternately stacked along a stacking direction; A semiconductor layer located on one side of the stacked structure along the stacking direction; Multiple channel structures are respectively provided, passing through the stacked structure and extending to the semiconductor layer along the stacking direction; A first gate line slot structure extends through the stacked structure and into the semiconductor layer along the stacking direction; the first gate line slot structure also extends along a first direction. The first gate slot structure includes a first part and a second part along the stacking direction, wherein the dimension of the first part in the second direction is smaller than the dimension of the second part in the second direction; The first portion is in contact with the semiconductor layer, and the second portion is located in the stacked structure; The first direction, the second direction, and the stacking direction intersect each other.

2. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes: A first insulating layer is located at least on the side of the semiconductor layer away from the stacked structure along the stacking direction; and The first lead-out portion passes through the first insulating layer along the stacking direction and contacts the semiconductor layer.

3. The semiconductor device according to claim 2, characterized in that, It also includes a second gate line slot structure that extends through the stacked structure along the stacking direction and into the semiconductor layer, the second gate line slot structure also extending along the first direction. The first gate line slot structure and the second gate line slot structure are arranged along the second direction; the first lead-out portion overlaps with the plurality of channel structures located between the first gate line slot structure and the second gate line slot structure in the stacking direction, and the contact surface between the first lead-out portion and the semiconductor layer is located between the first gate line slot structure and the second gate line slot structure.

4. The semiconductor device according to claim 2, characterized in that, The first lead-out portion includes a first end and a second end opposite to each other along the stacking direction, the second end being in contact with the semiconductor layer, and the dimension of the first end in the second direction being greater than the dimension of the second end in the second direction.

5. The semiconductor device according to claim 2, characterized in that, The dimension of the first lead in the second direction gradually decreases along the stacking direction from the first lead toward the semiconductor layer.

6. The semiconductor device according to claim 1, characterized in that, The portion of the channel structure located in the semiconductor layer has a different dimension in the second direction than the portion of the channel structure located in the stacked structure.

7. The semiconductor device according to claim 1, characterized in that, The channel structure includes a dielectric layer, a channel layer, and a functional layer, wherein the channel layer surrounds the dielectric layer, and the functional layer surrounds the channel layer; the semiconductor layer is in contact with at least the dielectric layer of the channel structure.

8. The semiconductor device according to claim 7, characterized in that, The semiconductor layer also contacts the functional layer and the channel layer of the channel structure along the stacking direction.

9. The semiconductor device according to claim 8, characterized in that, In the stacking direction, the contact interface between the semiconductor layer and the functional layer is higher than the contact interface between the semiconductor layer and the dielectric layer.

10. The semiconductor device according to claim 8, characterized in that, In the stacking direction, the contact interface between the semiconductor layer and the channel layer is higher than the contact interface between the semiconductor layer and the dielectric layer.

11. The semiconductor device according to claim 2, characterized in that, The semiconductor layer includes a first semiconductor layer and a second semiconductor layer stacked along the stacking direction, wherein the first semiconductor layer is located between the stacked structure and the second semiconductor layer along the stacking direction.

12. The semiconductor device according to claim 11, characterized in that, The first portion of the first gate line slot structure is in contact with the second semiconductor layer, and the second portion of the first gate line slot structure is in contact with the first semiconductor layer.

13. The semiconductor device according to claim 11, characterized in that, The semiconductor device further includes: A contact structure extends from the semiconductor layer along the stacking direction toward the other side of the stacking structure; The second lead-out portion passes through the first insulating layer, the first semiconductor layer, and the second semiconductor layer along the stacking direction and is connected to the contact structure.

14. The semiconductor device according to claim 13, characterized in that, The dimension of the second lead-out portion in the second direction gradually decreases along the stacking direction from the second lead-out portion toward the contact structure.

15. The semiconductor device according to claim 13, characterized in that, The material of the first lead-out portion is the same as the material of the second lead-out portion.

16. The semiconductor device according to claim 13, characterized in that, The first insulating layer further includes portions located in the first semiconductor layer and the second semiconductor layer; The second lead also passes through the portion of the first insulating layer located in the first semiconductor layer and the second semiconductor layer; The dimension of the portion of the first insulating layer located in the first semiconductor layer and the second semiconductor layer in the second direction gradually decreases along the stacking direction from the first insulating layer toward the contact structure.

17. A semiconductor device, characterized in that, include: A stacked structure, a semiconductor layer, and a first insulating layer are stacked along the stacking direction; Multiple channel structures are respectively provided, passing through the stacked structure and extending to the semiconductor layer along the stacking direction; The first lead-out portion passes through the first insulating layer along the stacking direction and contacts the semiconductor layer; The dimension of the first lead-out portion in the second direction gradually decreases along the stacking direction from the first lead-out portion toward the semiconductor layer; The second direction is perpendicular to the stacking direction; The surface of the first lead-out portion connected to the semiconductor layer and the plurality of the channel structures overlap in the stacking direction.

18. The semiconductor device according to claim 17, characterized in that, The semiconductor device further includes: The first gate line slot structure and the second gate line slot structure respectively pass through the stacked structure along the stacking direction and extend to the semiconductor layer, and both extend along the first direction; the first direction intersects both the stacking direction and the second direction; The first gate wire slot structure and the second gate wire slot structure are arranged along the second direction; The first lead-out portion overlaps with a plurality of channel structures located between the first gate line slot structure and the second gate line slot structure in the stacking direction, and the contact surface between the first lead-out portion and the semiconductor layer is located between the first gate line slot structure and the second gate line slot structure.

19. The semiconductor device according to claim 17, characterized in that, The semiconductor device further includes: A contact structure extends from the semiconductor layer toward one side of the stacking structure along the stacking direction; The second lead-out portion passes through the first insulating layer, the semiconductor layer, and connects to the contact structure along the stacking direction.

20. The semiconductor device according to claim 19, characterized in that, The dimension of the second lead-out portion in the second direction gradually decreases along the stacking direction from the second lead-out portion toward the contact structure.

21. The semiconductor device according to claim 19, characterized in that, The material of the first lead-out portion is the same as the material of the second lead-out portion.

22. The semiconductor device according to claim 19, characterized in that, The first insulating layer also includes a portion located within the semiconductor layer; The second lead also passes through the portion of the first insulating layer located in the semiconductor layer; The dimension of the portion of the first insulating layer located in the semiconductor layer in the second direction gradually decreases along the stacking direction from the first insulating layer toward the contact structure.

23. A semiconductor device, characterized in that, include: A stacked structure, a first semiconductor layer, a second semiconductor layer, and a first insulating layer are stacked along the stacking direction; A channel structure extends through the stacked structure along the stacking direction and into the first semiconductor layer; A contact structure extends from the first semiconductor layer along the stacking direction toward one side of the stacking structure; The second lead-out portion passes through the first insulating layer, the first semiconductor layer and the second semiconductor layer along the stacking direction and is connected to the contact structure; The dimension of the second lead-out portion in the second direction gradually decreases along the stacking direction from the second lead-out portion toward the contact structure; The second direction is perpendicular to the stacking direction.

24. The semiconductor device according to claim 23, characterized in that, The semiconductor device further includes: A first lead-out portion passes through the first insulating layer along the stacking direction and contacts the second semiconductor layer; the size of the first lead-out portion in the second direction gradually decreases along the stacking direction from the first lead-out portion toward the second semiconductor layer.

25. The semiconductor device according to claim 24, characterized in that, The first lead-out portion and the plurality of channel structures overlap in the stacking direction.

26. The semiconductor device according to claim 24, characterized in that, The semiconductor device further includes: The first gate line slot structure and the second gate line slot structure respectively pass through the stacked structure along the stacking direction and extend to the semiconductor layer, and both extend along the first direction; the first direction intersects both the stacking direction and the second direction; The first gate wire slot structure and the second gate wire slot structure are arranged along the second direction; The first lead-out portion overlaps with a plurality of channel structures located between the first gate line slot structure and the second gate line slot structure in the stacking direction, and the contact surface between the first lead-out portion and the second semiconductor layer is located between the first gate line slot structure and the second gate line slot structure.

27. The semiconductor device according to claim 24, characterized in that, The material of the first lead-out portion is the same as the material of the second lead-out portion.

28. The semiconductor device according to claim 23, characterized in that, The first insulating layer also includes portions located in the first semiconductor layer and the second semiconductor layer; The second lead also passes through the portion of the first insulating layer located in the first semiconductor layer and the second semiconductor layer; The dimension of the portion of the first insulating layer located in the first semiconductor layer and the second semiconductor layer in the second direction gradually decreases along the stacking direction from the first insulating layer toward the contact structure.

29. A semiconductor device, characterized in that, include: A stacked structure, the stacked structure comprising gate layers and a second insulating layer alternately stacked along a stacking direction; A semiconductor layer located on one side of the stacked structure along the stacking direction; Multiple channel structures are respectively provided, passing through the stacked structure and extending to the semiconductor layer along the stacking direction; The channel structure includes a third portion and a fourth portion along the stacking direction, wherein the dimension of the third portion in the second direction is smaller than the dimension of the fourth portion in the second direction; the third portion is in contact with the semiconductor layer, and the fourth portion is located in the stacking structure; The second direction is perpendicular to the stacking direction.

30. The semiconductor device according to claim 29, characterized in that, The semiconductor device further includes: A first insulating layer is located at least on the side of the semiconductor layer away from the stacked structure along the stacking direction; and The first lead-out portion passes through the first insulating layer along the stacking direction and contacts the semiconductor layer.

31. The semiconductor device according to claim 30, characterized in that, The semiconductor device further includes: The dimension of the first lead in the second direction gradually decreases along the stacking direction from the first lead toward the semiconductor layer.

32. The semiconductor device according to claim 31, characterized in that, The semiconductor device further includes: The first gate line slot structure and the second gate line slot structure respectively pass through the stacked structure along the stacking direction and extend to the semiconductor layer, and both extend along the first direction; the first direction intersects both the stacking direction and the second direction; The first gate wire slot structure and the second gate wire slot structure are arranged along the second direction; The first lead-out portion overlaps with a plurality of channel structures located between the first gate line slot structure and the second gate line slot structure in the stacking direction, and the contact surface between the first lead-out portion and the semiconductor layer is located between the first gate line slot structure and the second gate line slot structure.

33. The semiconductor device according to claim 30, characterized in that, The semiconductor device further includes: A contact structure extends from the semiconductor layer along the stacking direction toward the other side of the stacking structure; The second lead-out portion passes through the first insulating layer, the semiconductor layer, and connects to the contact structure along the stacking direction.

34. The semiconductor device according to claim 33, characterized in that, The dimension of the second lead-out portion in the second direction gradually decreases along the stacking direction from the second lead-out portion toward the contact structure.

35. The semiconductor device according to claim 33, characterized in that, The material of the first lead-out portion is the same as the material of the second lead-out portion.

36. The semiconductor device according to claim 33, characterized in that, The first insulating layer also includes a portion located within the semiconductor layer; The second lead also passes through the portion of the first insulating layer located in the semiconductor layer; The dimension of the portion of the first insulating layer located in the semiconductor layer in the second direction gradually decreases along the stacking direction from the first insulating layer toward the contact structure.

37. A storage system, characterized in that, include: The storage system includes a controller and a semiconductor device as described in any one of claims 1 to 16, 17 to 22, 23 to 28, or 29 to 36, wherein the controller is coupled to the semiconductor device and is used to control the semiconductor device to store data.

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