Semiconductor device having local lines between cell matrices

Abstract

This disclosure relates to a semiconductor device having local circuitry between cell matrices. The semiconductor device includes a cell array having a first cell matrix and a second cell matrix. The first cell matrix includes: first to fourth cell slabs; a first local X-switch disposed between the first and second cell slabs; a first X-line extending in the first cell slab; and a second X-line extending in the second cell slab. The second cell matrix includes: first to fourth cell slabs; a first local X-switch disposed between the first and second cell slabs; a first X-line extending in the first cell slab; and a second X-line extending in the second cell slab. The first local X-switch is electrically shared by the first X-line of the first cell matrix, the second X-line of the first cell matrix, and the first X-line of the second cell matrix.

Description

[0001] Cross-references to related applications

[0002] This patent document claims priority to Korean Patent Application No. 10-2025-0003250, filed on January 9, 2025, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to semiconductor devices having a cell matrix (cellMAT) and local circuitry. Background Technology

[0004] A cell matrix refers to the cells arranged in a matrix in a semiconductor memory device. Each cell matrix includes multiple memory cells. Multiple memory cells can be selected or enabled by turning on local switches set within the cell matrix. Summary of the Invention

[0005] Embodiments of this disclosure provide a structure and method for configuring storage cells to select or enable on both sides.

[0006] Embodiments of this disclosure provide a structure and method in which a memory cell can be selected or enabled by turning on a local switch of another adjacent cell matrix.

[0007] Embodiments of this disclosure provide a structure and method configured to simultaneously select or enable adjacent memory cells by simultaneously turning on corresponding local switches in two adjacent cell matrices.

[0008] According to one embodiment of this disclosure, a semiconductor device includes a cell array comprising a first cell matrix and a second cell matrix adjacent to each other in a first direction. The first cell matrix includes: first to fourth cell slabs arranged in a matrix; a first local X-switch disposed between the first and second cell slabs; a first X-line extending from the first local X-switch in a first direction through the first cell slab; and a second X-line extending from the first local X-switch in a first direction through the second cell slab. The second cell matrix includes: first to fourth cell slabs arranged in a matrix; a first local X-switch disposed between the first and second cell slabs; a first X-line extending from the first local X-switch in a first direction through the first cell slab; and a second X-line extending from the first local X-switch in a first direction through the second cell slab. The first local X-switch of the first cell matrix is ​​electrically shared by the first X-line of the first cell matrix, the second X-line of the first cell matrix, and the first X-line of the second cell matrix. The first local X switch of the second unit matrix is ​​electrically shared by the second X line of the first unit matrix, the first X line of the second unit matrix, and the second X line of the second unit matrix.

[0009] According to one embodiment of this disclosure, a semiconductor device includes a cell array having a first cell matrix to a fourth cell matrix. Each of the first cell matrix to the fourth cell matrix includes: a first cell slice to a fourth cell slice arranged in a matrix; a first local X switch disposed between the first cell slice and a second cell slice; a second local X switch disposed between a third cell slice and a fourth cell slice; a first local Y switch disposed between the first cell slice and the third cell slice; a second local Y switch disposed between the second cell slice and the fourth cell slice; a first Y line extending from the first local Y switch to pass through the first cell slice; a second Y line extending from the second local Y switch to pass through the second cell slice; a third Y line extending from the first local Y switch to pass through the third cell slice; and a fourth Y line extending from the second local X switch to pass through the fourth cell slice. The first local Y switch of the first cell matrix is ​​electrically shared by the first Y line of the first cell matrix, the third Y line of the first cell matrix, and the first Y line of the third cell matrix.

[0010] According to one embodiment of this disclosure, a semiconductor device includes a cell array comprising a first cell matrix and a second cell matrix adjacent to each other. Each of the first and second cell matrices includes: first to fourth cell segments arranged in a matrix configuration, wherein a first direction and a second direction are perpendicular to each other; a first local Y-switch disposed between the first and third cell segments; a second local Y-switch disposed between the second and fourth cell segments; a first Y-line extending from the second local Y-switch in a first direction through the first cell segment; a second Y-line extending from the second local Y-switch through the second cell segment; a third Y-line extending from the first local Y-switch in a second direction through the third cell segment; and a fourth Y-line extending from the second local Y-switch through the fourth cell segment. The first local Y-switch of the first cell matrix is ​​electrically shared by the first Y-line of the first cell matrix, the third Y-line of the first cell matrix, and the first Y-line of the second cell matrix.

[0011] These and other features and advantages of the embodiments of this disclosure will become apparent to those skilled in the art from the following detailed description taken in conjunction with the accompanying drawings. Attached Figure Description

[0012] Figure 1A This is a block diagram illustrating a semiconductor device according to an embodiment of the present disclosure. Figure 1B It is shown Figure 1A An enlarged view of the unit matrix.

[0013] Figure 2This is a schematic diagram illustrating the line connection structure of two unit matrices adjacent to each other in a first direction according to an embodiment of the present disclosure.

[0014] Figure 3 This is a schematic diagram illustrating the wiring connection structure of two unit matrices adjacent to each other in the second direction according to an embodiment of the present disclosure.

[0015] Figure 4 This is a schematic diagram illustrating the connection structure of the X and Y lines of the unit matrix according to an embodiment of the present disclosure.

[0016] Figure 5A This is a block diagram of a semiconductor device according to embodiments of the present disclosure. Figure 5B It is located in Figure 5A A schematic enlarged view of the cell matrix in the edge region of the cell array. Detailed Implementation

[0017] The embodiments disclosed herein will be described in detail with reference to the accompanying drawings. The specific structural or functional descriptions of the particular embodiments are provided merely as examples to illustrate the technical concepts disclosed in this application. However, it should be understood that those skilled in the art can implement various other examples or embodiments based on the technical concepts of this disclosure in various forms without departing from the scope of this disclosure. Therefore, the present invention is not limited to only the described examples or embodiments.

[0018] All the crosshairs in the diagram represent corresponding or similar areas between the diagrams, rather than representing the material related to those areas.

[0019] When one element is labeled "connected" or "coupled" to another element, the two elements can be directly connected or coupled, or they can be connected or coupled through an intermediate element between the elements. When two elements are labeled "directly connected" or "directly coupled," one element is directly connected or directly coupled to the other element, and there is no intermediate element between the two elements.

[0020] When one element is identified as being "above", "on top of", "below", or "under" another element, the two elements can be in direct contact with each other, or an intermediate element can be placed between the two elements.

[0021] Terms such as “vertical,” “horizontal,” “top,” “bottom,” “above,” “below,” “under,” “below,” “above,” “upper,” “side,” “upper part,” “topmost,” “lower part,” “bottommost,” “front,” “back,” “left,” “right,” “column,” “row,” and “horizontal,” and other terms that suggest relative spatial relationships or orientations, are used for descriptive convenience or reference to the accompanying drawings and are not intended to limit the scope of this disclosure. Other spatial relationships or orientations not shown in the drawings or described in the specification are possible within the scope of this disclosure.

[0022] Terms such as "first" and "second" are used to distinguish between multiple elements and do not imply the size, order, priority, number, or importance of the elements. For example, a first element may be named a second element in one example, while a second element may be named a first element in another example.

[0023] In the description, when an element included in an embodiment is described in the singular, the element can be interpreted as including multiple elements that perform the same or similar functions.

[0024] The concepts have been disclosed above with reference to examples and embodiments. Those skilled in the art will understand that various modifications, additions, and substitutions can be made without departing from the scope and technical concept of this disclosure. The embodiments disclosed in this specification should be considered exemplary and not restrictive. Therefore, the scope of this disclosure is not limited to the foregoing description. All variations within the meaning and scope of the equivalents of the claims are included within their scope.

[0025] Throughout the manual, "selected" and "enabled" can mean supplying or drawing current. For example, "selected" and "enabled" can be interpreted as data being written to or read from.

[0026] Figure 1A To illustrate a block diagram of a semiconductor device 1000 according to an embodiment of the present disclosure, Figure 1B To show Figure 1A An enlarged view of unit matrix 110. (Reference) Figure 1A and Figure 1BThe semiconductor device 1000 may include a cell array 100A, an X decoding block 200, and a Y decoding block 300. The cell array 100A may include multiple cell matrices 110 arranged in a matrix. Each cell matrix 110 may include multiple memory cells MC1 to MC4 arranged in a matrix. The X decoding block 200 may be electrically connected to the cell array 100A in a first direction X. The Y decoding block 300 may be electrically connected to the cell array 100A in a second direction Y. The first direction X may be perpendicular to the second direction Y. For example, the X decoding block 200 may selectively enable memory cells MC1 to MC4 in the cell array 100A according to address signals, etc. The Y decoding block 300 may provide voltage or current to selected memory cells MC1 to MC4, or may read data stored in selected memory cells MC1 to MC4. The X decoding block 200 may include address encoding circuitry, word line driving circuitry, and / or global X-switching circuitry. The Y decoding block 300 may include global Y-switching circuitry and / or sensing amplifier circuitry.

[0027] refer to Figure 1B Each unit matrix 110 may include unit segments T1 to T4 and local switch blocks 112, 113, 124, and 134. Unit segments T1-T4 may include first unit segments T1 to fourth unit segments T4 arranged in a matrix along a first direction X and a second direction Y. For example, the first unit segment T1 may be located in the upper left position (first row R1, first column (left) C1), the second unit segment T2 may be located in the upper right position (first row R1, second column (right) C2), the third unit segment T3 may be located in the lower left position (second row R2, first column C1), and the fourth unit segment T4 may be located in the lower right position (second row R2, second column C2).

[0028] Each unit matrix 110 may include a first X-line XL1, a second X-line XL2, a third X-line XL3, and a fourth X-line XL4, each X-line extending parallel to each other along a first direction X. The first X-line XL1 may pass through the first unit segment T1, the second X-line XL2 may pass through the second unit segment T2, the third X-line XL3 may pass through the third unit segment T3, and the fourth X-line XL4 may pass through the fourth unit segment T4.

[0029] Each unit matrix 110 may include a first Y-line YL1, a second Y-line YL2, a third Y-line YL3, and a fourth Y-line YL4, each Y-line extending parallel to each other along the second direction Y. The first Y-line YL1 can pass through the first unit segment T1, the second Y-line YL2 can pass through the second unit segment T2, the third Y-line YL3 can pass through the third unit segment T3, and the fourth Y-line YL4 can pass through the fourth unit segment T4.

[0030] The first unit segment T1 may include a first storage unit MC1 arranged in a matrix at the intersection of the first X line XL1 and the first Y line YL1. The second unit segment T2 may include a second storage unit MC2 arranged in a matrix at the intersection of the second X line XL2 and the second Y line YL2. The third unit segment T3 may include a third storage unit MC3 arranged in a matrix at the intersection of the third X line XL3 and the third Y line YL3. The fourth unit segment T4 may include a fourth storage unit MC4 arranged in a matrix at the intersection of the fourth X line XL4 and the fourth Y line YL4.

[0031] Local switching blocks 112, 113, 124, and 134 may include a first local X switching block 112, a second local X switching block 134, a first local Y switching block 113, and a second local Y switching block 124. The first local X switching block 112 may be disposed between the first unit segment T1 and the second unit segment T2, while the second local X switching block 134 may be disposed between the second unit segment T3 and the fourth unit segment T4. The first local Y switching block 113 may be disposed between the first unit segment T1 and the third unit segment T3, while the second local Y switching block 124 may be disposed between the second unit segment T2 and the fourth unit segment T4. That is, the first unit segment T1, the first local X switching block 112, and the second unit segment T2 may be aligned side-by-side in the first direction X on the first row R1. The third unit segment T3, the second local X switching block 134, and the fourth unit segment T4 may be aligned side-by-side in the first direction X on the second row R2. The first unit segment T1, the first local Y-switch block 113, and the third unit segment T3 can be aligned side-by-side in the second direction Y along the first column C1. The second unit segment T2, the second local Y-switch block 124, and the fourth unit segment T4 can be aligned side-by-side in the second direction Y along the second column C2.

[0032] The first local X-switch block 112 may include a plurality of first local X-switch S12. The first local X-switch S12 may be arranged in the first local X-switch block 112 to be aligned in the second direction Y. The second local X-switch block 134 may include a plurality of second local X-switch S34. The second local X-switch S34 may be arranged in the second local X-switch block 134 to be aligned in the second direction Y.

[0033] Each first local X switch S12 can be electrically connected to the corresponding first X line XL1 and the corresponding second X line XL2. When each first local X switch S12 is turned on, current can be supplied to the corresponding first X line XL1 and the corresponding second X line XL2, and the first storage unit MC1 in the first unit segment T1 on the corresponding first X line XL1 and the second storage unit MC2 in the corresponding second X line XL2 can be selected simultaneously.

[0034] Each second local X switch S34 can be electrically connected to the corresponding third X line XL3 and the corresponding fourth X line XL4. When each second local X switch S34 is turned on, current can be supplied to the corresponding third X line XL3 and the corresponding fourth X line XL4, and the third storage unit MC3 in the third unit segment T3 set on the corresponding third X line XL3 and the fourth storage unit MC4 set on the corresponding fourth X line XL4 can be selected simultaneously.

[0035] The first local Y switch block 113 may include a plurality of first local Y switches S13. The first local Y switches S13 may be arranged in the first local Y switch block 113 and aligned in the first direction X. The second local Y switch block 124 may include a plurality of second local Y switches S24. The second local Y switches S24 may be arranged in the second local Y switch block 124 and aligned in the first direction X.

[0036] Each first local Y switch S13 can be electrically connected to the corresponding first Y line YL1 and the corresponding third Y line YL3. When each first local Y switch S13 is turned on, current can be supplied to the corresponding first Y line YL1 and the corresponding third Y line YL3, and the first storage unit MC1 in the first unit segment T1 on the corresponding first Y line YL1 and the third storage unit MC3 in the corresponding third Y line YL3 can be selected simultaneously.

[0037] Each second local Y switch S24 can be electrically connected to the corresponding second Y line YL2 and the corresponding fourth Y line YL4. When each second local Y switch S24 is turned on, current can be supplied to the corresponding second Y line YL2 and the fourth Y line YL4, and the second memory unit MC3 in the second unit segment T2 on the corresponding second Y line YL2 and the fourth memory unit MC4 in the corresponding fourth Y line YL4 can be selected simultaneously.

[0038] exist Figure 1A and Figure 1B In this configuration, the first direction X and the second direction Y can be interchanged. Therefore, the structure and function of X lines XL1-XL4 and Y lines YL1-YL4 are interchangeable.

[0039] Figure 2 This is a schematic diagram illustrating the wiring connection structure of two unit matrices 110A and 110B that are adjacent to each other in the first direction X according to an embodiment of the present disclosure.

[0040] refer to Figure 2 The semiconductor device according to embodiments of the present disclosure may include a first cell matrix 110A and a second cell matrix 110B that are adjacent to each other in a first direction X in a cell array.

[0041] The first unit matrix 110A may include four unit segments T1A-T4A arranged in a matrix form, local switch blocks 112A, 134A, 113A and 124A arranged between unit segments T1A-T4A, X lines XA1-XA4 passing through unit segments T1A-T4A in the first direction X, and Y lines YA1-YA4 passing through unit segments T1A-T4A in the second direction Y.

[0042] In the first unit matrix 110A, the local switching blocks 112A, 134A, 113A and 124A may include: a first local X switching block 112A, which is disposed in the first direction X between the first unit segment T1A and the second unit segment T2A; a second local X switching block 134A, which is disposed in the first direction X between the third unit segment T3A and the fourth unit segment T4A; a first local Y switching block 113A, which is disposed in the second direction Y between the first unit segment T1A and the third unit segment T3A; and a second local Y switching block 124A, which is disposed in the second direction Y between the second unit segment T2A and the fourth unit segment T4A.

[0043] In the first unit matrix 110A, the first local X switch block 112A may include a first local X switch S12A arranged in alignment in the second direction Y, the second local switch block 134A may include a second local X switch S34A arranged in alignment in the second direction Y, the first local Y switch block 113A may include a first local Y switch S13A arranged in alignment in the first direction X, and the second local Y switch block 124A may include a second local Y switch S24A arranged in alignment in the first direction X.

[0044] In the first unit matrix 110A, X-lines XA1-XA4 may include a first X-line XA1, a second X-line XA2, a third X-line XA3, and a fourth X-line XA4. The first X-line XA1 can pass through the first unit segment T1A from the first local X-switch S12A to be electrically connected to the first memory cell MC1A. The second X-line XA2 can pass through the second unit segment T2A from the first local X-switch S12A to be electrically connected to the second memory cell MC2A. The third X-line XA3 can pass through the third unit segment T3A from the second local X-switch S34A to be electrically connected to the third memory cell MC3A. The fourth X-line XA4 can pass through the fourth unit segment T4A from the second local X-switch S34A to be electrically connected to the fourth memory cell MC4A.

[0045] In the first unit matrix 110A, Y lines YA1-YA4 may include a first Y line YA1, a second Y line YA2, a third Y line YA3, and a fourth Y line YA4. The first Y line YA1 can pass through the first unit segment T1A from the first local Y switch S13A to be electrically connected to the first memory cell MC1A. The second Y line YA2 can pass through the second unit segment T2A from the second local Y switch S24A to be electrically connected to the second memory cell MC2A. The third Y line YA3 can pass through the third unit segment T3A from the first local Y switch S13A to be electrically connected to the third memory cell MC3A. The fourth Y line YA4 can pass through the fourth unit segment T4A from the second local Y switch S24A to be electrically connected to the fourth memory cell MC4A.

[0046] The second unit matrix 110B may include four unit segments T1B-T4B arranged in a matrix form, local switch blocks 112B, 134B, 113B and 124B arranged between unit segments T1B-T4B, X lines XB1-XB4 passing through unit segments T1B-T4B in the first direction X, and Y lines YB1-YB4 passing through unit segments T1B-T4B in the second direction Y.

[0047] In the second unit matrix 110B, the local switching blocks 112B, 134B, 113B, and 124B may include: a first local X switching block 112B, which is disposed in the first direction X between the first unit segment T1B and the second unit segment T2B; a second local X switching block 134B, which is disposed in the first direction X between the third unit segment T3B and the fourth unit segment T4B; a first local Y switching block 113B, which is disposed in the second direction Y between the first unit segment T1B and the third unit segment T3B; and a second local Y switching block 124B, which is disposed in the second direction Y between the second unit segment T2B and the fourth unit segment T4B.

[0048] In the second unit matrix 110B, the first local X switch block 112B may include a first local X switch S12B arranged aligned in the second direction Y, the second local switch block 134B may include a second local X switch S34B arranged aligned in the second direction Y, the first local Y switch block 113B may include a first local Y switch S13B arranged aligned in the first direction X, and the second local Y switch block 124B may include a second local Y switch S24B arranged aligned in the first direction X.

[0049] In the second unit matrix 110B, X lines XB1-XB4 may include a first X line XB1, a second X line XB2, a third X line XB3, and a fourth X line XB4. The first X line XB1 can pass through the first unit segment T1B from the first local X switch S12B to be electrically connected to the first memory cell MC1B. The second X line XB2 can pass through the second unit segment T2B from the first local X switch S12B to be electrically connected to the second memory cell MC2B. The third X line XB3 can pass through the third unit segment T3B from the second local X switch S34B to be electrically connected to the third memory cell MC3B. The fourth X line XB4 can pass through the fourth unit segment T4B from the second local X switch S34B to be electrically connected to the fourth memory cell MC4B.

[0050] In the second unit matrix 110B, Y lines YB1-YB4 may include a first Y line YB1, a second Y line YB2, a third Y line YB3, and a fourth Y line YB4. The first Y line YB1 can pass through the first unit segment T1B from the first local Y switch S13B to be electrically connected to the first memory cell MC1A. The second Y line YB2 can pass through the second unit segment T2B from the second local Y switch S24B to be electrically connected to the second memory cell MC2B. The third Y line YB3 can pass through the third unit segment T3B from the first local Y switch S13B. The fourth Y line YB4 can pass through the fourth unit segment T4B from the second local Y switch S24B to be electrically connected to the fourth memory cell MC4B.

[0051] In the first direction X, X-line XA2 passing through the second unit segment T2A of the first unit matrix 110A and X-line XB1 passing through the first unit segment T1B of the second unit matrix 110B can be electrically connected to each other. In the first direction X, X-line XA4 passing through the fourth unit segment T4A of the first unit matrix 110A and X-line XB3 passing through the third unit segment T3B of the second unit matrix 110B can be electrically connected to each other.

[0052] When the corresponding first local X switch S12A of the first unit matrix 110A is turned on, the corresponding storage unit MC1A in the first unit segment T1A of the first unit matrix 110A, which is electrically connected through the corresponding X line XA1, the corresponding storage unit MC2A in the second unit segment T2A of the first unit matrix 110A, which is electrically connected through the corresponding X line XA2, and the corresponding storage unit MC1B in the first unit segment T1B of the second unit matrix 110B, which is electrically connected through the corresponding X line XB1, can simultaneously select and enable current to be received from the first local X switch S12A of the first unit matrix 110A. The first storage unit MC1A in the first unit segment T1A of the first unit matrix 110A, the second storage unit MC2A in the second unit segment T2A of the first unit matrix 110A, and the first storage unit MC1B in the first unit segment T1B of the second unit matrix 110B can electrically share the first local X switch S12A of the first unit matrix 110A. For example, the first local X switch S12A of the first unit matrix 110A can be electrically shared by the first X line XA1 of the first unit matrix 110A, the second X line XA2 of the first unit matrix 110A, and the first X line XB1 of the second unit matrix 110B.

[0053] When the first local X switch S12B of the second unit matrix 110B is turned on, the corresponding storage unit MC2A in the second unit segment T2A of the first unit matrix 110A, which is electrically connected via the corresponding X line XA2, the corresponding storage unit MC1B in the first unit segment T1B of the second unit matrix 110B, which is electrically connected via the corresponding X line XB1, and the corresponding storage unit MC2B in the second unit segment T2B of the second unit matrix 110B, which is electrically connected via the corresponding X line XB2, can simultaneously select and enable current to be received from the first local X switch S12B of the second unit matrix 110B. The second storage unit MC2A in the second unit segment T2A of the first unit matrix 110A, the first storage unit MC1B in the first unit segment T1B of the second unit matrix 110B, and the second storage unit MC2B in the second unit segment T2B of the second unit matrix 110B can electrically share the first local X switch S12B of the second unit matrix 110B. For example, the first local X switch S12A of the second unit matrix 110B can be electrically shared by the second X line XA2 of the first unit matrix 110A, the first X line XB1 of the second unit matrix 110B, and the second X line XB2 of the second unit matrix 110B.

[0054] When the corresponding first local X switch S12A of the first unit matrix 110A and the corresponding second local X switch S12B of the second unit matrix 110B, which are electrically connected through the corresponding X lines XA2 and XB1, are simultaneously turned on, the corresponding memory units MC1A, MC2A, MC1B and MC2B, which are electrically connected through the corresponding X lines XA1, XA2, XB1 and XB2, can be selected and enabled at the same time.

[0055] When the corresponding second local X switch S34A of the first unit matrix 110A is turned on, the corresponding storage unit MC3A in the third unit segment T3A of the first unit matrix 110A, which is electrically connected via the corresponding X line XA3, the corresponding storage unit MC4A in the fourth unit segment T4A of the first unit matrix 110A, which is electrically connected via the corresponding X line XA4, and the corresponding storage unit MC3B in the third unit segment T3B of the second unit matrix 110B, which is electrically connected via the corresponding X line XB3, can simultaneously select and enable current to be received from the second local X switch S34A of the first unit matrix 110A. The third storage unit MC3A in the third unit segment T3A of the first unit matrix 110A, the fourth storage unit MC4A in the fourth unit segment T4A of the first unit matrix 110A, and the third storage unit MC3B in the third unit segment T3B of the second unit matrix 110B can share the second local X switch S34A of the first unit matrix 110A.

[0056] When the corresponding second local X switch S34B of the second unit matrix 110B is turned on, the corresponding storage unit MC4A in the fourth unit segment T4A of the first unit matrix 110A, which is electrically connected through the corresponding X line XA4, the corresponding storage unit MC3B in the third unit segment T3B of the second unit matrix 110B, which is electrically connected through the corresponding X line XB3, and the corresponding storage unit MC4B in the fourth unit segment T4B of the fourth unit matrix 110B, which is electrically connected through the corresponding X line XB4, can be selected and enabled simultaneously.

[0057] When the corresponding second local X switch S34A of the first unit matrix 110A and the corresponding second local X switch S34B of the second unit matrix 110B, which are electrically connected through the corresponding X lines XA4 and XB3, are simultaneously turned on, the corresponding storage units MC3A, MC4A, MC3B, and MC4B, which are electrically connected through the corresponding X lines XA3, XA4, XB3, and XB4, can be simultaneously selected and enabled. The fourth storage unit MC4A in the fourth unit segment T4A of the first unit matrix 110A, the third storage unit MC3B in the third unit segment T3B of the second unit matrix 110B, and the fourth storage unit MC4B in the fourth unit segment T4B of the second unit matrix 110B can receive current from the second local X switch S34B of the second unit matrix 110B. The fourth storage unit MC4A in the fourth unit segment T4A of the first unit matrix 110A, the third storage unit MC3B in the third unit segment T3B of the second unit matrix 110B, and the fourth storage unit MC4B in the fourth unit segment T4B of the second unit matrix 110B can share the second local X switch S34B of the second unit matrix 110B electrically.

[0058] The memory cells MC2A, MC1B, MC4A, and MC3B in cell slices T2A, T1B, T4A, and T3B, which are positioned adjacent to the boundary regions (or edge regions) of the first cell matrix 110A and the second cell matrix 110B, can simultaneously receive current from switches S12A, S12B, S34A, and S34B. Therefore, in each of cell slices T2A, T1B, T4A, and T3B, the memory cells MC2A, MC1B, MC4A, and MC3B located away from the two switches S12A, S34A, S12B, and S34B can receive sufficient current, can be stably selected, and can operate.

[0059] You can refer to this. Figure 1B To understand the local Y switches S13A, S24A, S13B and S24B, and the Y lines YA13, YA24, YB13 and YB24.

[0060] Figure 3 This is a schematic diagram illustrating the wiring connection structure of two unit matrices 110C and 110D that are adjacent to each other in the second direction Y according to an embodiment of the present disclosure.

[0061] refer to Figure 3 The semiconductor device according to embodiments of the present disclosure may include cell matrices 110C and 110D that are adjacent to each other in a second direction Y in a cell array.

[0062] The first unit matrix 110C may include four unit segments T1C-T4C arranged in a matrix form, local switch blocks 112C, 134C, 113C and 124C arranged between unit segments T1C-T4C, X lines XC1-XC4 passing through unit segment T1C in the first direction X, and Y lines YC1-YC4 passing through unit segments T1C-T4C in the second direction Y.

[0063] In the first unit matrix 110C, the local switching blocks 112C, 134C, 113C, and 124C may include: a first local X switching block 112C, which is disposed in the first direction X between the first unit segment T1C and the second unit segment T2C; a second local X switching block 134C, which is disposed in the first direction X between the third unit segment T3C and the fourth unit segment T4C; a first local Y switching block 113C, which is disposed in the second direction Y between the first unit segment T1C and the third unit segment T3C; and a second local Y switching block 124C, which is disposed in the second direction Y between the second unit segment T2C and the fourth unit segment T4C.

[0064] In the first unit matrix 110C, the first local X switch block 112C may include a first local X switch S12C arranged in alignment in the second direction Y, the second local switch block 134C may include a second local X switch S34C arranged in alignment in the second direction Y, the first local Y switch block 113C may include a first local Y switch S13C arranged in alignment in the first direction X, and the second local Y switch block 124C may include a second local Y switch S24C arranged in alignment in the first direction X.

[0065] In the first unit matrix 110C, X-line XC1-XC4 may include a first X-line XC1, a second X-line XC2, a third X-line XC3, and a fourth X-line XC4. The first X-line XC1 can pass through the first unit segment T1C from the first local X-switch S12C to be electrically connected to the first memory cell MC1C. The second X-line XC2 can pass through the second unit segment T2C from the first local X-switch S12C to be electrically connected to the second memory cell MC2C. The third X-line XC3 can pass through the third unit segment T3C from the second local X-switch S34C to be electrically connected to the third memory cell MC3C. The fourth X-line XC4 can pass through the fourth unit segment T4C from the second local X-switch S34C to be electrically connected to the fourth memory cell MC4C.

[0066] In the first unit matrix 110C, Y lines YC1-YC4 may include a first Y line YC1, a second Y line YC2, a third Y line YC3, and a fourth Y line YC4. The first Y line YC1 can pass through the first unit segment T1C from the first local Y switch S13C to be electrically connected to the first memory cell MC1C. The second Y line YC2 can pass through the second unit segment T2C from the second local Y switch S24C to be electrically connected to the second memory cell MC2C. The third Y line YC3 can pass through the third unit segment T3C from the first local Y switch S13C to be electrically connected to the third memory cell MC3C. The fourth Y line YC4 can pass through the fourth unit segment T4C from the second local Y switch S24C to be electrically connected to the fourth memory cell MC4C.

[0067] The second unit matrix 110D may include four unit segments T1D-T4D arranged in a matrix form, local switch blocks 112D, 134D, 113D and 124D arranged between unit segments T1D-T4D, X lines XD1-XD4 passing through unit segment T1D in the first direction X, and Y lines YD1-YD4 passing through unit segments T1D-T4D in the second direction Y.

[0068] In the second unit matrix 110D, the local switching blocks 112D, 134D, 113D, and 124D may include: a first local X switching block 112D, which is disposed in the first direction X between the first unit segment T1D and the second unit segment T2D; a second local X switching block 134D, which is disposed in the first direction X between the third unit segment T3D and the fourth unit segment T4D; a first local Y switching block 113D, which is disposed in the second direction Y between the first unit segment T1D and the third unit segment T3D; and a second local Y switching block 124D, which is disposed in the second direction Y between the second unit segment T2D and the fourth unit segment T4D.

[0069] In the second unit matrix 110D, the first local X switch block 112D may include a first local X switch S12D arranged in alignment in the second direction Y, the second local X switch block 134D may include a second local X switch S34D arranged in alignment in the second direction Y, the first local Y switch block 113D may include a first local Y switch S13D arranged in alignment in the first direction X, and the second local Y switch block 124D may include a second local Y switch S24D arranged in alignment in the first direction X.

[0070] In the second unit matrix 110D, X-line XD1-XD4 may include a first X-line XD1, a second X-line XD2, a third X-line XD3, and a fourth X-line XD4. The first X-line XD1 can pass through the first unit segment T1D from the first local X-switch S12D and be electrically connected to the first memory cell MC1D. The second X-line XD2 can pass through the second unit segment T2D from the first local X-switch S12D and be electrically connected to the second memory cell MC2D. The third X-line XD3 can pass through the third unit segment T3D from the second local X-switch S12D and be electrically connected to the third memory cell MC3D. The fourth X-line XD4 can pass through the fourth unit segment T4D from the second local X-switch S34D and be electrically connected to the fourth memory cell MC4D.

[0071] In the second unit matrix 110D, Y lines YD1-YD4 may include a first Y line YD1, a second Y line YD2, a third Y line YD3, and a fourth Y line YD4. The first Y line YD1 can be electrically connected to the first memory cell MC1D by passing through the first unit segment T1D from the first local Y switch S13D. The second Y line YD2 can be electrically connected to the second memory cell MC2D by passing through the second unit segment T2D from the second local Y switch S24D. The third Y line YD3 can be electrically connected to the third memory cell MC3D by passing through the third unit segment T3D from the first local Y switch S13D. The fourth Y line YD4 can be electrically connected to the fourth memory cell MC4D by passing through the fourth unit segment T4D from the second local Y switch S24D.

[0072] In the second direction Y, the Y-line YC3 passing through the third unit segment T3C of the first unit matrix 110C and the Y-line YD3 passing through the first unit segment T1D of the second unit matrix 110D can be electrically connected to each other. In the second direction Y, the Y-line YC4 passing through the fourth unit segment T4C of the first unit matrix 110C and the Y-line YD4 passing through the second unit segment T2D of the second unit matrix 110D can be electrically connected to each other.

[0073] When the corresponding first local Y switch S13C of the first unit matrix 110C is turned on, the corresponding storage unit MC1C in the first unit segment T1C of the first unit matrix 110C, which is electrically connected through the corresponding Y line YC1, the corresponding storage unit MC3C in the third unit segment T3C of the first unit matrix 110C, which is electrically connected through the corresponding Y line YC3, and the corresponding storage unit MC1D in the first unit segment T1D of the second unit matrix 110D, which is electrically connected through the corresponding Y line YD1, can simultaneously select and enable current to be received from the first local Y switch S13C of the first unit matrix 110C. The first storage unit MC1C in the first unit segment T1C of the first unit matrix 110C, the third storage unit MC3C in the third unit segment T3C of the first unit matrix 110C, and the first storage unit MC1D in the first unit segment T1D of the second unit matrix 110D can share the first local Y switch S13C of the first unit matrix 110C.

[0074] When the first local X switch S12D of the second unit matrix 110D is turned on, the corresponding storage cell MC3C in the third unit segment T3C of the first unit matrix 110C, which is electrically connected via the corresponding Y line YC3, the corresponding storage cell MC1D in the first unit segment T1D of the second unit matrix 110D, which is electrically connected via the corresponding Y line YD1, and the corresponding storage cell MC3D in the third unit segment T3D of the second unit matrix 110D, which is electrically connected via the corresponding Y line YD3, can simultaneously select and enable current to be received from the first local Y switch S13D of the second unit matrix 110D. The third storage unit MC3C in the third unit segment T3C of the first unit matrix 110C, the first storage unit MC1D in the first unit segment T1D of the second unit matrix 110D, and the third storage unit MC3D in the third unit segment T3D of the second unit matrix 110D can share the first local Y switch S13D of the second unit matrix 110D.

[0075] When the corresponding first local Y switch S13C of the first unit matrix 110D and the corresponding first local X switch S13D of the second unit matrix 110D, which are electrically connected through the corresponding Y lines YC3 and YD1, are simultaneously turned on, the corresponding memory units MC1C, MC3C, MC1D and MC3D, which are electrically connected through the corresponding Y lines YC1, YC3, YD1 and YD3, can all be selected and enabled at the same time.

[0076] When the corresponding second local Y switch S24C of the first unit matrix 110C is turned on, the corresponding storage unit MC2C in the second unit segment T2C of the first unit matrix 110C, which is electrically connected via the corresponding Y line YC2, the corresponding storage unit MC4C in the fourth unit segment T4C of the first unit matrix 110C, which is electrically connected via the corresponding Y line YC4, and the corresponding storage unit MC2D in the second unit segment T2D of the second unit matrix 110D, which is electrically connected via the corresponding Y line YD2, can simultaneously select and enable current to be received from the second local Y switch S24C of the first unit matrix 110C. The second storage unit MC2C in the second unit segment T2C of the first unit matrix 110C, the fourth storage unit MC4C in the fourth unit segment T4C of the first unit matrix 110C, and the second storage unit MC2D in the second unit segment T2D of the second unit matrix 110D can share the second local Y switch S24C of the first unit matrix 110C.

[0077] When the corresponding second local Y switch S24D of the second unit matrix 110D is turned on, the corresponding storage unit MC4C in the fourth unit segment T4C of the first unit matrix 110C, which is electrically connected via the corresponding Y line YC4, the corresponding storage unit MC2D in the second unit segment T2D of the second unit matrix 110D, which is electrically connected via the corresponding Y line YD2, and the corresponding storage unit MC4D in the fourth unit segment T4D of the second unit matrix 110D, which is electrically connected via the corresponding Y line YD4, can simultaneously select and enable current to be received from the second local Y switch S24D of the second unit matrix 110D. The fourth storage unit MC4C in the fourth unit segment T4C of the first unit matrix 110C, the second storage unit MC2D in the second unit segment T2D of the second unit matrix 110D, and the fourth storage unit MC4D in the fourth unit segment T4D of the second unit matrix 110D can share the second local Y switch S24D of the second unit matrix 110D.

[0078] When the corresponding second local Y switch S24C of the first unit matrix 110C and the corresponding second local Y switch S24D of the second unit matrix 110D, which are electrically connected through the corresponding Y lines YC4 and YD2, are simultaneously turned on, the corresponding memory units MC2C, MC4C, MC2D and MC4D, which are electrically connected through the corresponding Y lines YC2, YC4, YD2 and YD4, can be selected and enabled at the same time.

[0079] The memory cells MC3C, MC1D, MC4C, and MC2D in cell shards T3C, T1D, T4C, and T2D, which are positioned adjacent to the boundary regions (or edge regions) of the first cell matrix 110C and the second cell matrix 110D, can simultaneously receive current from both types of switches S13C, S13D, S24C, and S2D. Therefore, in each of cell shards T3C, T1D, T4C, and T2D, the memory cells MC3C, MC1D, MC4C, and MC2D located away from the two types of switches S13C, S24C, S13D, and S24D can receive sufficient current, be stably selected, and operate.

[0080] You can refer to this. Figure 1B To understand the local X switches S12C, S34C, S12D and S34D, and the X lines XC12, XC34, XD12 and XD34.

[0081] Figure 4This diagram schematically illustrates the connection structure of the X-lines (X1_1-X1_4, X2_1-X2_4, X3_1-X3_4, X4_1-X4_4) and Y-lines (Y1_1-Y1_4, Y2_1-Y2_4, Y3_1-Y3_4, and Y4_1-Y4_4) of unit matrices 110_1, 110_2, 110_3, and 110_4. In the first direction X, the first unit matrices 110_1 and 110_2 can be arranged adjacent to each other in the first row, and the third unit matrix 110_3 and the fourth unit matrix 110_4 can be arranged adjacent to each other in the second row. In the second direction Y, the first unit matrix 110_1 and the third unit matrix 110_3 can be arranged adjacent to each other in the first column, while the second unit matrix 110_2 and the fourth unit matrix 110_4 can be arranged adjacent to each other in the second column.

[0082] refer to Figure 4 In the first direction X, X-line X1_2 passing through the second unit segment 1_T2 of the first unit matrix 110_1 and X-line X2_1 passing through the first unit segment 2_T1 of the second unit matrix 110_2 can be electrically connected to each other. X-line X1_4 passing through the fourth unit segment 1_T4 of the first unit matrix 110_1 and X-line X2_3 passing through the third unit segment 2_T3 of the second unit matrix 110_2 can be electrically connected to each other. X-line X3_2 passing through the second unit segment 3_T2 of the third unit matrix 110_3 and X-line X4_1 passing through the first unit segment 4_T1 of the fourth unit matrix 110_4 can be electrically connected to each other. X-line X3_4 passing through the fourth unit segment 3_T4 of the third unit matrix 110_3 and X-line X4_3 passing through the third unit segment 4_T3 of the fourth unit matrix 110_4 can be electrically connected to each other.

[0083] Furthermore, the Y-line Y1_3 passing through the third unit segment 1_T3 of the first unit matrix 110_1 can be electrically connected to the Y-line Y3_1 passing through the first unit segment 3_T1 of the third unit matrix 110_3; the Y-line Y1_4 passing through the fourth unit segment 1_T4 of the first unit matrix 110_1 can be electrically connected to the Y-line Y3_2 passing through the second unit segment 3_T2 of the third unit matrix 110_3; the Y-line Y2_13 passing through the third unit segment 2_T3 of the second unit matrix 110_2 can be electrically connected to the Y-line Y4_13 passing through the first unit segment 4_T1 of the fourth unit matrix 110_4; and the Y-line Y2_4 passing through the fourth unit segment 2_T4 of the second unit matrix 110_2 can be electrically connected to the Y4_2 passing through the second unit segment 4_T2 of the fourth unit matrix 110_4.

[0084] refer to Figure 2 and Figure 3 Understandable Figure 4 The operation of the cell array 100 shown. That is, refer to... Figure 2 Technical concepts and references described Figure 3 The described technical concepts can be combined.

[0085] Figure 5A This is a block diagram of a semiconductor device 2000 according to an embodiment of the present disclosure. Figure 5B It is located in Figure 5A A schematic enlarged view of the cell matrix 110 in the edge region of the cell array 100C.

[0086] refer to Figure 5A and Figure 5B The semiconductor device 2000 may include a cell array 100C, an X decoding block 200, a Y decoding block 300, an edge local X switch block 150, and / or an edge local Y switch block 160. The edge local X switch block 150 may be configured to be adjacent to each edge of the edge cell matrix 110E located at the outermost edge of the first direction X of the cell array 100C. That is, each edge local X switch block 150 may be symmetrically arranged to face each local X switch block (in...). Figure 5B Similarly depicted as edge local X-switch blocks 150 (but not shown by reference numerals in the figures), corresponding cell segments T1e-T4e of each cell matrix 110E are located therebetween. Edge local Y-switch blocks 160 can be configured to be adjacent to each edge of the edge cell matrix 110E located at the outermost edge of the second direction Y of the cell array 100C. That is, each edge local Y-switch block 160 can be arranged symmetrically to face each local Y-switch block (in Figure 5B Similarly, edge local Y switch blocks 160 (not indicated by reference numerals) are depicted, with corresponding cell segments T1e-T4e of each cell matrix 110E located therebetween. Edge local X switch blocks 150 may include edge local X switches SX, and edge local Y switch blocks 160 may include edge local Y switches SY. Thus, each edge local X switch SX may be symmetrically arranged with each local X switch (not indicated by reference numerals) with corresponding cell segments T1e-T4e of each cell matrix 110E located therebetween, and each edge local Y switch SY may be symmetrically arranged with each local X switch (not indicated by reference numerals) with corresponding cell segments T1e-T4e of each cell matrix 110E located therebetween.

[0087] Each edge local X switch SX can be simultaneously turned on with its corresponding edge local X switch SwX in the edge element matrix 110E to supply current to the edge X lines (not indicated by reference numerals) in the outermost edge element segments T1e-T4e of the edge element matrix 110E. Each edge local Y switch SY can be simultaneously turned on with its corresponding edge local Y switch SwY in the edge element matrix 110E to supply current to the edge Y lines (not indicated by reference numerals) in the outermost edge element segments T1e-T4e of the edge element matrix 110E. Therefore, the edge X lines (not indicated by reference numerals) and / or edge Y lines (not indicated by reference numerals) in the outermost edge element segments T1e-T4e

[0088] (Indication) can be obtained from two edge switches (edge ​​local X switch SwX and SX (and / or edge local Y switch SwY)).

[0089] And SY)) receive current.

[0090] According to embodiments of this disclosure, sufficient current can be provided to all memory cells MC in cell matrices 110, 110A-110E, and 110_1-110_4. Therefore, semiconductor devices 1000 and 2000 can operate stably. Furthermore, since the current transport capability can be improved, the area of ​​cell matrices 110, 110A-110E, and 110_1-110_4 can be set to be larger. That is, more memory cells MC can be arranged in cell shards T1 to T4, and the integration density and area efficiency of semiconductor device 1000 can be improved.

[0091] refer to Figures 2 to 4 The described technical concept and the technical concept described with reference to Figure 5 can be combined.

[0092] According to embodiments of this disclosure, each memory cell can receive current from two local switches located on both sides. Therefore, the selection or enabling of the memory cell can be performed reliably.

[0093] While the invention has been described in conjunction with specific embodiments, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical concept and scope of this disclosure as defined in the following claims. Furthermore, these embodiments can be combined to form additional embodiments.

Claims

1. A semiconductor device, comprising: A cell array comprising a first cell matrix and a second cell matrix that are adjacent to each other in a first direction. The first unit matrix includes: The first to fourth unit partitions are arranged in a matrix. A first local X switch is disposed between the first unit segment and the second unit segment; A first X-line, which extends in the first direction from the first local X-switch to pass through the first unit segment; and The second X-line extends in the first direction from the first local X-switch to pass through the second unit segment. The second unit matrix includes: The first to fourth unit partitions are arranged in a matrix. A first local X switch is disposed between the first unit segment and the second unit segment; A first X-line, which extends in the first direction from the first local X-switch to pass through the first unit segment; and The second X-line extends in the first direction from the first local X-switch to pass through the second unit segment. Wherein, the first local X switch of the first unit matrix is ​​electrically shared by the first X line of the first unit matrix, the second X line of the first unit matrix, and the first X line of the second unit matrix, and The first local X switch of the second unit matrix is ​​electrically shared by the second X line of the first unit matrix, the first X line of the second unit matrix, and the second X line of the second unit matrix.

2. The semiconductor device according to claim 1, in, The first unit matrix also includes: A second local X switch is disposed between the third unit segment and the fourth unit segment; A third X-line, which extends in the first direction from the second local X-switch to pass through the third unit segment; and A fourth X-line, which extends in the first direction from the second local X-switch to pass through the fourth unit segment, The second unit matrix further includes: A second local X switch is disposed between the third unit segment and the fourth unit segment; A third X-line, which extends in the first direction from the second local X-switch to pass through the third unit segment; and A fourth X-line, which extends in the first direction from the second local X-switch to pass through the fourth unit segment, Wherein, the second local X switch of the first unit matrix is ​​electrically shared by the third X line of the first unit matrix, the fourth X line of the first unit matrix, and the third X line of the second unit matrix, and The second local X switch of the second unit matrix is ​​electrically shared by the fourth X line of the first unit matrix, the third X line of the second unit matrix, and the fourth X line of the second unit matrix.

3. The semiconductor device according to claim 2, further comprising: The third element matrix is ​​adjacent to the first element matrix in a second direction perpendicular to the first direction. The third unit matrix includes the first to fourth unit fragments arranged in a matrix form. The first unit matrix includes: A first local Y switch is located between the first unit segment and the third unit segment; The second local Y switch is located between the second unit segment and the fourth unit segment; A first Y-line extends in the second direction from the first local Y-switch to pass through the first cell segment; The second Y-line extends from the second local Y-switch in the second direction to pass through the second unit segment; A third Y-line, extending in the second direction from the first local Y-switch to pass through the third unit segment; and A fourth Y-line, which extends in the second direction from the second local Y-switch to pass through the fourth unit segment, The third unit matrix includes: A first local Y switch is located between the first unit segment and the third unit segment; The second local Y switch is located between the second unit segment and the fourth unit segment; A first Y-line extends in the second direction from the first local Y-switch to pass through the first cell segment; The second Y-line extends from the second local Y-switch in the second direction to pass through the second unit segment; A third Y-line, extending in the second direction from the first local Y-switch to pass through the third unit segment; and A fourth Y-line, which extends in the second direction from the second local Y-switch to pass through the fourth unit segment, Wherein, the first local Y switch of the first unit matrix is ​​electrically shared by the first Y line of the first unit matrix, the third Y line of the first unit matrix, and the first Y line of the third unit matrix, and The first local Y switch of the third unit matrix is ​​electrically shared by the third Y line of the first unit matrix, the first Y line of the third unit matrix, and the third Y line of the third unit matrix.

4. The semiconductor device according to claim 3, in, The second local Y switch of the first unit matrix is ​​electrically shared by the second Y line of the first unit matrix, the fourth Y line of the first unit matrix, and the second Y line of the third unit matrix. The second local Y switch of the third unit matrix is ​​electrically shared by the fourth Y line of the first unit matrix, the second Y line of the third unit matrix, and the fourth Y line of the third unit matrix.

5. The semiconductor device according to claim 3, in, The first unit matrix also includes: A first edge local Y-switch, which is adjacent to the edge region of the first cell segment of the first cell matrix in the second direction; and The second edge local Y-switch is adjacent to the edge region of the second cell segment of the first cell matrix in the second direction. Wherein, the first edge local Y-switch of the first cell matrix provides current to the memory cells in the first cell slice of the first cell matrix, and Specifically, the second edge local Y-switch of the first cell matrix provides current to the storage cells in the second cell segment of the first cell matrix.

6. The semiconductor device according to claim 5, in, The second unit matrix also includes: A first edge local Y-switch, which is adjacent to the edge region of the first cell segment of the second cell matrix in the second direction; and The second edge local Y-switch is adjacent to the edge region of the second cell segment of the second cell matrix in the second direction. Wherein, the first edge local Y-switch of the second cell matrix provides current to the memory cells in the first cell slice of the second cell matrix, and Specifically, the second edge local Y-switch of the second cell matrix provides current to the storage cells in the second cell segment of the second cell matrix.

7. The semiconductor device according to claim 3, in, The first unit matrix also includes: A first edge local X switch, which is adjacent to the edge region of the first cell segment of the first cell matrix in the first direction; and The second edge local X switch is adjacent to the edge region of the third cell segment of the first cell matrix in the first direction. Wherein, the first edge local X switch of the first cell matrix provides current to the memory cells of the first cell slice of the first cell matrix, and Specifically, the second edge local X switch of the first cell matrix provides current to the storage cells of the third cell segment of the first cell matrix.

8. The semiconductor device according to claim 7, in, The third unit matrix also includes: A first local X switch is disposed between the first unit segment and the second unit segment; A second local X switch is disposed between the third unit segment and the fourth unit segment; A first edge local X switch is adjacent to the first unit segment in the first direction; A second edge local X switch is adjacent to the third unit segment in the first direction; A first X-line extends from the first local X-switch in the first direction to pass through the first cell segment and is electrically connected to the first edge local X-switch. A second X-line extends from the first local X-switch in the first direction to pass through the second unit segment; A third X-line, which extends in the first direction from the second local X-switch to pass through the third unit segment and is electrically connected to the second edge local X-switch; and A fourth X line extends in the first direction from the second local X switch to pass through the fourth unit segment.

9. The semiconductor device according to claim 3, in, Each cell fragment from the first cell matrix to the fourth cell fragment in each of the cell matrices from the first cell matrix to the third cell matrix includes: Multiple storage units arranged in a matrix, Each of the plurality of storage units is disposed at the intersection of the first X line and the first Y line, the intersection of the second X line and the second Y line, the intersection of the third X line and the third Y line, and the intersection of the fourth X line and the fourth Y line.

10. The semiconductor device according to claim 1, further comprising: The X decoding block is adjacent to the cell array in the first direction; as well as The Y-decoding block is adjacent to the cell array in a second direction perpendicular to the first direction. The X decoding block includes an address encoding circuit, and The Y decoding block includes a global Y-switch circuit and a sensing amplifier circuit.

11. A semiconductor device, comprising: A cell array having a first cell matrix to a fourth cell matrix. Each of the first to fourth unit matrices includes: The first to fourth unit partitions are arranged in a matrix. A first local X switch is disposed between the first unit segment and the second unit segment; A second local X switch is disposed between the third unit segment and the fourth unit segment; A first local Y switch is disposed between the first unit segment and the third unit segment; A second local Y switch is disposed between the second unit segment and the fourth unit segment; A first Y-line extends from the first local Y-switch to pass through the first unit segment; A second Y-line extends from the second local Y-switch to pass through the second unit segment; A third Y-line extends from the first local Y-switch to pass through the third unit segment; and The fourth Y-line extends from the second local X-switch to pass through the fourth unit segment. The first local Y switch of the first unit matrix is ​​electrically shared by the first Y line of the first unit matrix, the third Y line of the first unit matrix, and the first Y line of the third unit matrix.

12. The semiconductor device according to claim 11, in, The first local Y switch of the third unit matrix is ​​electrically shared by the third Y line of the first unit matrix, the first Y line of the third unit matrix, and the third Y line of the third unit matrix.

13. The semiconductor device according to claim 11, in, The second local Y switch of the first unit matrix is ​​electrically shared by the second Y line of the first unit matrix, the fourth Y line of the first unit matrix, and the second Y line of the third unit matrix.

14. The semiconductor device according to claim 13, in, The second local Y switch of the third unit matrix is ​​electrically shared by the fourth Y line of the first unit matrix, the second Y line of the third unit matrix, and the fourth Y line of the third unit matrix.

15. The semiconductor device according to claim 11, in, The first element matrix and the second element matrix are adjacent to each other in a first direction, and the third element matrix and the fourth element matrix are adjacent to each other in the first direction. Wherein, the first unit matrix and the third unit matrix are adjacent to each other in the second direction, and the second unit matrix and the fourth unit matrix are adjacent to each other in the second direction, and Wherein, the first direction and the second direction are perpendicular to each other.

16. The semiconductor device according to claim 15, in, The first unit segment and the second unit segment are adjacent to each other in the first direction, and the third unit segment and the fourth unit segment are adjacent to each other in the first direction. The first unit segment and the third unit segment are adjacent to each other in the second direction, and the second unit segment and the fourth unit segment are adjacent to each other in the second direction.

17. A semiconductor device, comprising: A cell array comprising a first cell matrix and a second cell matrix that are adjacent to each other. Each of the first unit matrix and the second unit matrix includes: The first unit segmentation to the fourth unit segmentation are arranged in a matrix form, wherein the first direction and the second direction are perpendicular to each other; A first local Y switch is disposed between the first unit segment and the third unit segment; A second local Y switch is disposed between the second unit segment and the fourth unit segment; A first Y-line extends in the second direction from the first local Y-switch to pass through the first cell segment; A second Y-line extends from the second local Y-switch to pass through the second unit segment; A third Y-line, extending in the second direction from the first local Y-switch to pass through the third unit segment; and A fourth Y-line extends from the second local Y-switch to pass through the fourth unit segment. The first local Y switch of the first unit matrix is ​​electrically shared by the first Y line of the first unit matrix, the third Y line of the first unit matrix, and the first Y line of the second unit matrix.

18. The semiconductor device according to claim 17, in, The first local Y switch of the second unit matrix is ​​electrically shared by the third Y line of the first unit matrix, the first Y line of the second unit matrix, and the third Y line of the second unit matrix.

19. The semiconductor device according to claim 17, in, The second local Y switch is electrically shared by the second Y line of the first unit matrix, the fourth Y line of the first unit matrix, and the second Y line of the second unit matrix.

20. The semiconductor device according to claim 19, in, The second local Y switch is electrically shared by the fourth Y line of the first unit matrix, the second Y line of the second unit matrix, and the fourth Y line of the second unit matrix.

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