Semiconductor device and manufacturing method thereof, electronic device

Abstract

A semiconductor device and its manufacturing method, and an electronic device, are disclosed. The semiconductor device includes: a stacked structure disposed on a substrate; at least one capacitor hole penetrating the stacked structure in a direction perpendicular to the substrate; and a plurality of capacitors distributed in the capacitor hole in a direction perpendicular to the substrate. Each capacitor includes a first sub-electrode, a first dielectric layer, a first capacitor electrode, a second dielectric layer, and a second sub-electrode, sequentially distributed from the outside to the inside in the capacitor hole. The first capacitor electrodes of the plurality of capacitors are spaced apart. The plurality of first sub-electrodes are connected to form an integral structure, and the plurality of second sub-electrodes are connected to form an integral structure. The first capacitor electrode surrounds the second sub-electrode, and the first sub-electrode surrounds the first capacitor electrode. The solution provided in this disclosure has electrodes disposed both inside and outside the first capacitor electrode of the capacitor, which maximizes the capacitance value of the capacitor without increasing the occupied area and is easy to manufacture.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, device design and manufacturing in the field of semiconductor technology, and particularly to a semiconductor device and its manufacturing method, and electronic equipment. Background Technology

[0002] With the development of integrated circuit technology, the critical dimensions of devices are shrinking, and the types and number of devices contained in a single chip are increasing, which means that any slight difference in the manufacturing process can affect the performance of the devices.

[0003] To minimize product costs, the goal is to fabricate as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet current product demands. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This application provides a semiconductor device and its manufacturing method, as well as an electronic device, which can increase the capacitance value of the capacitor structure without increasing the occupied area and is easy to manufacture.

[0006] This application provides a semiconductor device, comprising: a stacked structure disposed on a substrate, the stacked structure including a plurality of first insulating layers and a plurality of sacrificial layers alternately distributed along a direction perpendicular to the substrate, at least one capacitor aperture penetrating the stacked structure along a direction perpendicular to the substrate, a plurality of capacitors distributed in the capacitor aperture along a direction perpendicular to the substrate, each capacitor including a first sub-electrode, a first dielectric layer, a first capacitor electrode, a second dielectric layer, and a second sub-electrode sequentially distributed from the outside to the inside in the capacitor aperture; the first capacitor electrodes of the plurality of capacitors in the same capacitor aperture being spaced apart along a direction perpendicular to the substrate; the plurality of first sub-electrodes of the plurality of capacitors in the same capacitor aperture being connected to form an integral structure extending along a direction perpendicular to the substrate, the plurality of second sub-electrodes of the plurality of capacitors in the same capacitor aperture being connected to form an integral structure extending along a direction perpendicular to the substrate, the first capacitor electrode surrounding the second sub-electrode, and the first sub-electrode surrounding the first capacitor electrode.

[0007] In some embodiments, the first dielectric layers of a plurality of capacitors in the same capacitor hole are spaced apart along a direction perpendicular to the substrate.

[0008] In some embodiments, the second sub-electrode fills the capacitor hole.

[0009] In some embodiments, the capacitor hole includes a first sub-hole located in the sacrificial layer and a second sub-hole located in the first insulating layer. The first sub-hole has a first transverse groove extending in a horizontal direction relative to the second sub-hole. The first dielectric layer and the first capacitor electrode are sequentially distributed on the bottom wall and side wall of the first transverse groove.

[0010] In some embodiments, multiple second dielectric layers of multiple capacitors in the same capacitor hole are connected to form an integral structure extending in a direction perpendicular to the substrate. The integral structure formed by connecting multiple second dielectric layers is distributed on the bottom wall and side wall of the capacitor hole, and the second dielectric layer is connected to the first dielectric layer distributed in the first transverse groove.

[0011] In some embodiments, the semiconductor device further includes a plurality of transistors distributed along a direction perpendicular to the substrate and respectively connected to the plurality of capacitors, wherein the capacitors and the connected transistors are distributed along a first direction;

[0012] The first sub-electrode extends continuously to the sidewall of the capacitor hole and has a first opening on the side facing the transistor to expose the first capacitor electrode; the first dielectric layer extends to the bottom wall and sidewall of the first transverse groove and has a second opening on the side facing the transistor to expose the first capacitor electrode; the transistor includes a semiconductor layer, and the semiconductor layer of the transistor is connected to the first capacitor electrode through the first opening of the first sub-electrode and the second opening of the first dielectric layer.

[0013] In some embodiments, the capacitor further includes a third dielectric layer disposed at a first opening of the first sub-electrode and connected to the first sub-electrode, the first capacitor electrode, the first dielectric layer, and the semiconductor layer.

[0014] In some embodiments, the semiconductor device includes a plurality of capacitor holes arrayed along the first direction and the second direction, and first sub-electrodes in the plurality of capacitor holes in the same column distributed along the second direction are connected to form an integral structure on the side of the stacked structure away from the substrate, and second sub-electrodes in the plurality of capacitor holes in the same column are connected to form an integral structure on the side of the stacked structure away from the substrate; and second dielectric layers in the plurality of capacitor holes in the same column are connected to form an integral structure on the side of the stacked structure away from the substrate.

[0015] This disclosure provides a method for manufacturing a semiconductor device, including:

[0016] A stacked structure comprising alternating stacked first insulating layers and multiple sacrificial layers is formed on a substrate;

[0017] Form at least one first hole through the stacked structure along a direction perpendicular to the substrate;

[0018] Based on the first hole, the sacrificial layer is etched along a direction parallel to the substrate to form a first lateral groove;

[0019] Within the first hole and the first transverse groove, a plurality of capacitors are sequentially formed, comprising a first sub-electrode, a first dielectric layer, a first capacitor electrode, a second dielectric layer, and a second capacitor electrode, distributed perpendicular to the substrate direction. The first capacitor electrodes of the plurality of capacitors in the same capacitor hole are spaced apart perpendicular to the substrate direction. The plurality of first sub-electrodes of the plurality of capacitors in the same capacitor hole are connected to form an integral structure extending perpendicular to the substrate direction. The plurality of second sub-electrodes of the plurality of capacitors in the same capacitor hole are connected to form an integral structure extending perpendicular to the substrate direction. The first capacitor electrode surrounds the second sub-electrode, and the first sub-electrode surrounds the first capacitor electrode.

[0020] In some embodiments, forming a first sub-electrode, a first dielectric layer, a first capacitor electrode, a second dielectric layer, and a second capacitor electrode of a plurality of capacitors distributed perpendicular to the substrate direction within the first hole and the first lateral groove includes:

[0021] A first conductive film, a first dielectric film, and a second conductive film are sequentially deposited in the first hole and the first transverse groove, with the first conductive film, the first dielectric film, and the second conductive film sequentially covering the inner walls of the first hole and the first transverse groove; the second conductive film and the first dielectric film on the sidewall of the first hole are etched away, while the first conductive film in the first hole and the first transverse groove is retained, and the first dielectric film and the second conductive film in the first transverse groove are retained, forming the first sub-electrode, the first dielectric layer, and the first capacitor electrode;

[0022] A second dielectric film and a third conductive film are deposited sequentially. The second dielectric film covers the inner wall of the first hole and the first lateral groove where the first sub-electrode, the first dielectric layer and the first capacitor electrode are formed. The third conductive film fills the first hole and the first lateral groove to form the second dielectric layer and the second sub-electrode.

[0023] In some embodiments, before forming the first sub-electrode, the first dielectric layer, the first capacitor electrode, the second dielectric layer, and the second capacitor electrode of a plurality of capacitors distributed in a direction perpendicular to the substrate in the first hole and the first lateral groove, the method further includes: etching the first insulating layer based on the first hole and the first lateral groove, such that the first lateral groove is expanded by a first predetermined length in a dimension perpendicular to the substrate.

[0024] In some embodiments, the method further includes: forming at least one second hole corresponding to the first hole in a direction perpendicular to the substrate and penetrating the stacked structure, wherein the first hole and the corresponding second hole are distributed along a first direction;

[0025] After forming the second dielectric layer and the second sub-electrode, the method further includes:

[0026] Based on the second hole, the sacrificial layer is etched along a direction parallel to the substrate to expose the first sub-electrode, forming a second lateral groove;

[0027] Based on the second lateral groove, the first sub-electrode and the first dielectric layer are etched to expose the first capacitor electrode;

[0028] A third dielectric film is deposited in the second hole and the second lateral groove. The third dielectric film covering the sidewall of the first capacitor electrode facing the second hole and the third dielectric film on the sidewall of the first insulating layer are etched away. The third dielectric film connected to the first sub-electrode, the first capacitor electrode and the first dielectric layer are retained to form the third dielectric layer.

[0029] In some embodiments, before etching the first sub-electrode and the first dielectric layer based on the second lateral groove to expose the first capacitor electrode, the method further includes: etching the first insulating layer based on the second hole and the second lateral groove, such that the second lateral groove is expanded to a second predetermined length along a dimension perpendicular to the substrate direction.

[0030] This disclosure provides an electronic device, including any of the semiconductor devices described above, or a semiconductor device formed according to the manufacturing method of any of the semiconductor devices described above.

[0031] This application includes a semiconductor device and a method for manufacturing the same, as well as an electronic device. The semiconductor device includes: a stacked structure disposed on a substrate, the stacked structure including a plurality of first insulating layers and a plurality of sacrificial layers alternately distributed along a direction perpendicular to the substrate, at least one capacitor aperture penetrating the stacked structure along a direction perpendicular to the substrate, and a plurality of capacitors distributed in the capacitor aperture along a direction perpendicular to the substrate. Each capacitor includes a first sub-electrode, a first dielectric layer, a first capacitor electrode, a second dielectric layer, and a second sub-electrode sequentially distributed from the outside to the inside of the capacitor aperture. The first capacitor electrodes of the plurality of capacitors in the same capacitor aperture are spaced apart along a direction perpendicular to the substrate. The plurality of first sub-electrodes of the plurality of capacitors in the same capacitor aperture are connected to form an integral structure extending along a direction perpendicular to the substrate, and the plurality of second sub-electrodes of the plurality of capacitors in the same capacitor aperture are connected to form an integral structure extending along a direction perpendicular to the substrate. The first capacitor electrode surrounds the second sub-electrode, and the first sub-electrode surrounds the first capacitor electrode. The solution provided by the embodiments of this disclosure realizes the fabrication of multiple capacitors in the same aperture, and electrodes are provided both inside and outside the first capacitor electrode of the capacitor. While maximizing the capacitance value of the capacitor, it does not increase the occupied area and is easy to manufacture.

[0032] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the embodiments described in the description and the accompanying drawings.

[0033] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0034] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0035] Figure 1A A cross-sectional view of a semiconductor device provided in an embodiment of this disclosure along the AA' direction parallel to the substrate; Figure 1B A cross-sectional view of the semiconductor device provided in an embodiment of this disclosure along the BB' direction perpendicular to the substrate.

[0036] Figure 2 This is a cross-sectional view along the BB' direction perpendicular to the substrate after the stacked structure is formed, as provided in some embodiments;

[0037] Figure 3 This is a cross-sectional view along the BB' direction perpendicular to the substrate after the formation of the first and second holes, as provided in some embodiments;

[0038] Figure 4 A cross-sectional view along the BB' direction perpendicular to the substrate after the formation of the second insulating layer and the first dummy layer, provided for some embodiments;

[0039] Figure 5 A cross-sectional view along the BB' direction perpendicular to the substrate after the formation of the first lateral groove, provided for some embodiments;

[0040] Figure 6 A cross-sectional view along the BB' direction perpendicular to the substrate after forming the first sub-electrode, the first dielectric layer, and the first capacitor electrode, as provided in some embodiments;

[0041] Figure 7 A cross-sectional view along the direction perpendicular to the substrate after the formation of the second dielectric layer and the second sub-electrode, provided for some embodiments;

[0042] Figure 8 A cross-sectional view along the BB' direction perpendicular to the substrate after the formation of the fourth insulating layer, provided for some embodiments;

[0043] Figure 9 A cross-sectional view along the direction perpendicular to the substrate after the formation of the second lateral groove, provided for some embodiments;

[0044] Figure 10 A cross-sectional view along the BB' direction perpendicular to the substrate after exposing the first capacitor electrode, provided for some embodiments;

[0045] Figure 11 A cross-sectional view along the direction perpendicular to the substrate after the formation of the third dielectric layer, provided for some embodiments;

[0046] Figure 12 A cross-sectional view along the direction perpendicular to the substrate after the formation of a semiconductor layer, a first gate insulator layer, and a first portion of a word line in some embodiments;

[0047] Figure 13 A cross-sectional view along the direction perpendicular to the substrate after the formation of the second gate insulator layer and the second portion of the word line in some embodiments. Detailed Implementation

[0048] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Unless otherwise specified, the embodiments of this disclosure and the features thereof can be combined arbitrarily with each other.

[0049] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure pertains.

[0050] The embodiments disclosed herein are not necessarily limited to the dimensions shown in the drawings, and the shapes and sizes of the components in the drawings do not reflect actual proportions. Furthermore, the drawings schematically illustrate ideal examples, and the embodiments of this disclosure are not limited to the shapes or values ​​shown in the drawings.

[0051] The ordinal numbers “first,” “second,” “third,” etc., used in this disclosure are provided to avoid confusion among the constituent elements and do not indicate any order, quantity, or importance.

[0052] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the disclosure is not limited to the terms used herein and may be appropriately replaced as appropriate.

[0053] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to physical or signal connections, contact or integral connections; direct connections, indirect connections via intermediate components, or internal communication between two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure according to the specific circumstances.

[0054] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0055] In this disclosure, the first electrode may be the drain electrode and the second electrode may be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or where the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0056] In this disclosure, "connection" includes the situation where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0057] In this disclosure, "parallel" means approximately parallel or nearly parallel, for example, two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" means approximately perpendicular, for example, two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0058] In this embodiment of the disclosure, "A and B are an integral structure" can refer to a structure without obvious boundaries such as discontinuities or gaps in its microstructure. Generally, an integral structure is formed by patterning interconnected membrane layers on a single membrane layer. For example, A and B may be formed using the same material as a single membrane layer and simultaneously created through the same patterning process, resulting in a structure with interconnected relationships.

[0059] In this embodiment of the disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0060] Figure 1A A cross-sectional view of a semiconductor device provided in an embodiment of this disclosure along the AA' direction parallel to substrate 1; Figure 1B A cross-sectional view of the semiconductor device provided in an embodiment of this disclosure along the BB' direction perpendicular to the substrate 1. (See figure) Figure 1A and Figure 1BAs shown, the semiconductor device provided in this embodiment may include: a stacked structure disposed on a substrate 1, the stacked structure may include a plurality of first insulating layers and a plurality of sacrificial layers alternately distributed along a direction perpendicular to the substrate 1, at least one capacitor hole penetrating the stacked structure along a direction perpendicular to the substrate 1, a plurality of capacitors distributed in the capacitor hole along a direction perpendicular to the substrate 1, the capacitors including a first sub-electrode 421, a first dielectric layer 431, a first capacitor electrode 41, a second dielectric layer 432 and a second sub-electrode 422 sequentially distributed from the outside to the inside in the capacitor hole; the first capacitor electrodes 41 of the plurality of capacitors in the same capacitor hole are spaced apart along a direction perpendicular to the substrate 1; the plurality of first sub-electrodes 421 of the plurality of capacitors in the same capacitor hole are connected to form an integral structure extending along a direction perpendicular to the substrate 1, the plurality of second sub-electrodes 422 of the plurality of capacitors in the same capacitor hole are connected to form an integral structure extending along a direction perpendicular to the substrate 1, the first capacitor electrode 41 surrounds the second sub-electrode 422, and the first sub-electrode 421 surrounds the first capacitor electrode 41. The first dielectric layer 431 separates the first sub-electrode 421 and the first capacitor electrode 41; the second dielectric layer 432 separates the second sub-electrode 422 and the first capacitor electrode 41.

[0061] The solution provided in this embodiment enables the fabrication of multiple capacitors within the same hole, and electrodes are provided both inside and outside the first capacitor electrode of the capacitor. While maximizing the capacitance value of the capacitor, no additional area is required, and it is easy to manufacture. In addition, the electrodes outside the first capacitor electrode can shield adjacent first capacitor electrodes along the direction perpendicular to the substrate, reducing signal interference between adjacent first capacitor electrodes and improving device performance.

[0062] In some embodiments, the second sub-electrode 422 may fill the capacitor hole. However, the embodiments disclosed herein are not limited thereto, and the second sub-electrode 422 may be a hollow structure.

[0063] In some embodiments, the first dielectric layers 431 of a plurality of capacitors in the same capacitor hole are spaced apart along a direction perpendicular to the substrate 1. The first dielectric layers 431 surround the first capacitor electrode 41.

[0064] In some embodiments, the capacitor via may include a first sub-via located in the sacrificial layer and a second sub-via located in the first insulating layer. The first sub-via has a first lateral groove A1 extending horizontally relative to the second sub-via. The first dielectric layer 431 and the first capacitor electrode 41 are sequentially distributed on the bottom wall and sidewall of the first lateral groove A1. In the solution provided by this embodiment, the first capacitor electrode 41 is distributed in the first lateral groove A1, which facilitates disconnecting the first capacitor electrode 41 of the capacitors in different layers by removing the conductive material from the sidewall of the second sub-via.

[0065] In some embodiments, multiple second dielectric layers 432 of multiple capacitors in the same capacitor hole can be connected to form an integral structure extending in a direction perpendicular to the substrate 1. The integral structure formed by connecting multiple second dielectric layers 432 is distributed on the bottom wall and side wall of the capacitor hole, and the second dielectric layer 432 is connected to the first dielectric layer 431 distributed in the first transverse groove A1. The first dielectric layer 431 and the second dielectric layer 432 are connected at the opening of the first transverse groove A1. The connection between the second dielectric layer 432 and the first dielectric layer 431 can prevent leakage between the first sub-electrode 421 and the first capacitor electrode 41.

[0066] In some embodiments, in the second sub-hole, the first sub-electrode 421 and the second sub-electrode 422 are spaced apart by the second dielectric layer 432.

[0067] In some embodiments, the first sub-electrode 421 may be distributed on the bottom wall and side wall of the first transverse groove A1.

[0068] In some embodiments, the semiconductor device may further include a plurality of transistors distributed along a direction perpendicular to the substrate 1 and respectively connected to a plurality of capacitors, the capacitors and the connected transistors being distributed along a first direction X, and the transistors including a semiconductor layer 23 connected to the first capacitor electrode 41;

[0069] The first sub-electrode 421 extends continuously on the sidewall of the capacitor hole and has a first opening on the side facing the transistor to expose the first capacitor electrode 41; the first dielectric layer 431 extends and connects the bottom wall and sidewall of the first transverse groove A1 and has a second opening on the side facing the transistor to expose the first capacitor electrode 41.

[0070] The first capacitor electrode 41 is connected to the semiconductor layer 23 through the first opening of the first sub-electrode 421 and the second opening of the first dielectric layer 431. That is, on the plane parallel to the substrate 1, the cross section of the first dielectric layer 431 parallel to the substrate 1 is an open ring, and the cross section of the first sub-electrode 421 located in the first sub-hole parallel to the substrate is an open ring.

[0071] In this embodiment, transistors and capacitors are connected to form a 1T1C memory cell. The semiconductor device may include a multilayer memory cell array stacked along a direction perpendicular to the substrate 1. The memory cell array includes a plurality of memory cells distributed along a first direction X and a second direction Y.

[0072] In some embodiments, the cross-section of the first capacitor electrode 41 parallel to the substrate 1 can be a closed loop.

[0073] In some embodiments, the second dielectric layer 432 may be a closed loop in a cross section parallel to the substrate 1.

[0074] In some embodiments, the semiconductor device may further include a word line 40, with the semiconductor layer 23 surrounding the word line 40. The transistor further includes a gate insulating layer 24 disposed between the semiconductor layer 23 and the word line 40, surrounding the word line 40. Semiconductor layers 23 at the same locations on different layers are spaced apart on the sidewalls of the word line 40.

[0075] In some embodiments, the gate insulating layers 24 of transistors at the same location on different layers can be spaced apart along a direction perpendicular to the substrate 1. Figure 1A and Figure 1B The transistor structure shown is merely an example, and the embodiments disclosed herein are not limited thereto.

[0076] In some embodiments, the capacitor may further include a third dielectric layer 433 disposed at a first opening of the first sub-electrode 421 and connected to the first sub-electrode 421, the first capacitor electrode 41, the first dielectric layer 431, and the semiconductor layer 23. The third dielectric layer 433 can isolate the first sub-electrode 421 and the semiconductor layer 23.

[0077] In some embodiments, the semiconductor device includes a plurality of capacitor holes arrayed along the first direction X and the second direction Y. First sub-electrodes 421 in the plurality of capacitor holes in the same column along the second direction Y are connected to form an integral structure on the side of the stacked structure facing away from the substrate 1. Second sub-electrodes 422 in the plurality of capacitor holes in the same column are connected to form an integral structure on the side of the stacked structure facing away from the substrate 1. A second dielectric layer 432 in the plurality of capacitor holes in the same column is connected to form an integral structure on the side of the stacked structure facing away from the substrate 1. Furthermore, on the side of the stacked structure facing away from the substrate 1, the second dielectric layer 432 is disposed between the first sub-electrodes 421 and the second sub-electrodes 422, spaced apart.

[0078] Figure 1A and Figure 1BThe transistor structure shown is merely an example, and the embodiments disclosed herein are not limited thereto; the transistor can have other structures. The capacitor can be used in other memory cells, such as memory cells with a 2T1C structure, etc.

[0079] The technical solution of this embodiment is further illustrated below through the manufacturing process of the semiconductor device in this embodiment. In this embodiment, a film pattern is formed through patterning and photolithography processes. The "patterning process" includes film deposition, photoresist coating, mask exposure, development, etching, and photoresist stripping, which are mature manufacturing processes in related technologies. The "photolithography process" in this embodiment includes film coating, mask exposure, and development, which are mature manufacturing processes in related technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without specific limitations. In the description of this embodiment, it should be understood that "thin film" refers to a thin film made of a certain material on a substrate using a deposition or coating process. If the "thin film" does not require patterning or photolithography processes during the entire manufacturing process, it can also be called a "layer". If the "thin film" requires patterning or photolithography processes during the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning or photolithography process contains at least one "pattern".

[0080] In one exemplary embodiment, the manufacturing process of the semiconductor device may include:

[0081] 1) Forming a stacked structure;

[0082] A stacked structure is formed by sequentially depositing a first insulating film and a sacrificial layer film on substrate 1. Figure 2 This is a cross-sectional view along the BB' direction perpendicular to the substrate 1 after the stacked structure has been formed, as provided in some embodiments. Figure 2 As shown, the stacked structure may include a stack of alternating first insulating layers 11 and a stack of multiple sacrificial layers 10.

[0083] In some embodiments, substrate 1 may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0084] In some embodiments, the first insulating film may be a low-K dielectric layer, i.e., a dielectric layer with a dielectric constant not greater than 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2). The materials of the multiple first insulating layers 11 may be the same or different. The materials of the subsequent second to fourth insulating films are similar and will not be described in detail.

[0085] In some embodiments, the sacrificial layer film includes a film layer with a greater etching selectivity than the first insulating film, including but not limited to SiN (silicon nitride).

[0086] In some embodiments, the first insulating film and the sacrificial layer film can be deposited using a chemical vapor deposition method.

[0087] Figure 2 The number of stacked layers shown in the diagram is merely an example. In other embodiments, the stacked structure may include more or fewer alternating layers of a first insulating layer 11 and a sacrificial layer 10.

[0088] 2) The first hole K1 and the second hole K2 are formed simultaneously or sequentially;

[0089] The plurality of stacked structures are etched to form a plurality of first holes K1 and a plurality of second holes K2 penetrating the stacked structures. Subsequently, capacitors are formed in the first holes K1 and transistors are formed in the second holes K2, as shown below. Figure 3 As shown, Figure 3 This is a cross-sectional view along the BB' direction perpendicular to the substrate 1 after the formation of the first hole K1 and the second hole K2 in some embodiments. The first hole K1 extends in a direction perpendicular to the substrate 1, and the second hole K2 extends in a direction perpendicular to the substrate 1.

[0090] The first hole K1 and the second hole K2 are distributed at intervals along a first direction X. Multiple first holes K1 are distributed at intervals along a second direction Y, and multiple second holes K2 are distributed at intervals along a second direction Y. Two rows of second holes K2 may exist between two adjacent rows of first holes K1.

[0091] In some embodiments, the cross-sections of the first hole K1 and the second hole K2 in the direction parallel to the substrate 1 can be square, circular, or elliptical, etc.

[0092] In some embodiments, the stacked structure can be dry-etched to form a first hole K1 and a second hole K2.

[0093] In this embodiment, the first hole K1 and the second hole K2 can be formed simultaneously through a single patterning process, reducing process steps and lowering costs. However, this embodiment is not limited to this; the first hole K1 and the second hole K2 can be formed separately through multiple patterning processes. A single patterning process can be understood as using a single mask to simultaneously form the patterns of the first hole K1 and the second hole K2.

[0094] 3) Forming the second insulating layer 12 and the first dummy layer 61;

[0095] A second insulating film and a first dummy layer film are sequentially deposited, and then smoothed to form a second insulating layer 12 covering the bottom and sidewalls of the first hole K1 and the second hole K2. Finally, a first dummy layer 61 is filled into the first hole K1 and the second hole K2. Figure 4 As shown, Figure 4 A cross-sectional view along the BB' direction perpendicular to the substrate 1 after the formation of the second insulating layer 12 and the first dummy layer 61, provided for some embodiments.

[0096] In some embodiments, the first dummy layer film may be a material different from the first insulating film and the sacrificial layer film, such as polysilicon, silicon-oxygen-carbon ceramic (SiOC), etc.

[0097] 4) Form the first transverse groove A1;

[0098] A third insulating film is deposited to form a third insulating layer 13 covering the aforementioned structure;

[0099] The third insulating layer 13 is etched along a direction perpendicular to the substrate 1 to expose the second insulating layer 12 and the first dummy layer 61 in the first hole K1;

[0100] Etching removes the second insulating layer 12 and the first dummy layer 61 from the first hole K1, exposing the first hole K1;

[0101] Based on the first hole K1, the sacrificial layer 10 is laterally etched to a predetermined length to form a first transverse groove A1;

[0102] By slightly etching the first insulating layer 11 based on the first hole K1 and the first lateral groove A1, and increasing the dimension of the first lateral groove A1 along the direction perpendicular to the substrate 1, the first preset length can be increased. Furthermore, the aperture of the second sub-hole of the first hole K1 in the first insulating layer 11 can be increased; thus, the size of the capacitor can be increased. Figure 5 As shown, Figure 5 A cross-sectional view along the direction perpendicular to the substrate 1 after the formation of the first transverse groove A1, provided for some embodiments.

[0103] 5) Form the first sub-electrode 421, the first dielectric layer 431, and the first capacitor electrode 41;

[0104] A first conductive film, a first dielectric film, a second conductive film, and a second dummy layer film are sequentially deposited on the substrate 1 on which the aforementioned structure is formed. The first conductive film, the first dielectric film, the second conductive film, and the second dummy layer film sequentially cover the inner walls of the first hole K1 and the multiple first lateral grooves A1, but do not fill the first hole K1, forming a first sub-electrode 421, a first dielectric layer 431, a first capacitor electrode 41, and a second dummy layer.

[0105] The second dummy layer film, the second conductive film and the first dielectric film on the sidewall of the first hole K1 are removed by etching, while the first conductive film in the first hole K1 is retained, and the first conductive film, the first dielectric film, the second conductive film and the second dummy layer film in the plurality of first transverse grooves A1 are retained.

[0106] Etching removes the second dummy layer film from multiple first lateral grooves A1, such as Figure 6 As shown, Figure 6 A cross-sectional view along the BB' direction perpendicular to the substrate 1 after the formation of the first sub-electrode 421, the first dielectric layer 431, and the first capacitor electrode 41 in some embodiments.

[0107] In some embodiments, the second dummy layer thin film may be a low-K dielectric layer or polysilicon, etc.

[0108] In some embodiments, the first dielectric film may be a Low-K material, such as silicon oxide. Alternatively, it may be a High-K material, such as a dielectric material with a dielectric constant K ≥ 3.9. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplary examples include, but are not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials. The materials of the subsequent second and third dielectric films are similar to those of the first dielectric film and will not be described further.

[0109] In some embodiments, the first conductive film and the second conductive film may be one or more of the following different types of materials:

[0110] For example, it contains metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, and cobalt; it can be a metal alloy containing these metals.

[0111] Alternatively, it can be conductive metal oxides, metal nitrides, metal silicides, metal carbides, etc., such as conductive metal oxide materials like indium tin oxide (ITO), indium zinc oxide (IZO), and indium oxide (InO); or conductive metal nitride materials like titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), and titanium aluminum nitride (TiAlN).

[0112] Alternatively, it can be polycrystalline silicon, silicon, germanium, silicon-germanium, etc., which become conductive after doping. The materials for the subsequent third to fifth conductive films are similar and will not be described in detail.

[0113] 6) Form the second dielectric layer 432 and the second sub-electrode 422;

[0114] A second dielectric film and a third conductive film are sequentially deposited to form a second dielectric layer 432 and a second sub-electrode 422. The second dielectric layer 432 covers the inner walls of the first hole K1 and the plurality of first lateral grooves A1, and the second sub-electrode 422 fills the first hole K1 and the plurality of first lateral grooves A1. Figure 7 As shown, Figure 7 A cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the second dielectric layer 432 and the second sub-electrode 422, provided for some embodiments.

[0115] In some embodiments, the second sub-electrode 422 may include a first sub-layer 422a and a second sub-layer 422b. After forming the second dielectric layer 432, a first sub-conductive film may be deposited on the substrate 1 to form the first sub-layer 422a; then, a second sub-conductive film may be deposited to form the second sub-layer 422b, and the second sub-layer 422b fills the first hole K1 and a plurality of first lateral grooves A1. The first sub-layer 422a covers the second dielectric layer 432, and the second sub-layer 422b covers the first sub-layer 422a. The second sub-layer 422b is connected to the first sub-layer 422a. The first sub-layer 422a may be, for example, a film layer with good adhesion such as TiN, and the second sub-layer 422b may be, for example, a film layer with low resistivity such as polycrystalline silicon or tungsten. However, the embodiments disclosed herein are not limited to this; the second sub-electrode 422 may be a single-layer structure, such as polycrystalline silicon.

[0116] 7) Form the fourth insulating layer 14;

[0117] The second electronic electrode 422, the second dielectric layer 432 and the first sub-electrode 421 are etched to form a first trench T1 extending along the second direction Y. The bottom wall of the first trench T1 exposes the third insulating layer 13. The orthographic projection of the plurality of second holes K2 on the substrate 1 is located within the orthographic projection of the first trench on the substrate 1.

[0118] A fourth insulating film is deposited, which fills the first trench T1 and covers the aforementioned structure, forming a fourth insulating layer 14, as shown below. Figure 8 As shown, Figure 8 A cross-sectional view along the BB' direction perpendicular to the substrate 1 after the formation of the fourth insulating layer 14, provided for some embodiments.

[0119] 8) Form the second transverse groove A2;

[0120] The fourth insulating layer 14 and the third insulating layer 13 are etched along a direction perpendicular to the substrate 1, exposing the second insulating layer 12 and the first dummy layer 61 in the second hole K2;

[0121] Etching removes the second insulating layer 12 and the first dummy layer 61 from the second hole K2, exposing the second hole K2;

[0122] Based on the second hole K2, the sacrificial layer 10 is laterally etched to expose the first sub-electrode 421, forming a second lateral groove A2;

[0123] Based on the second hole K2 and the second lateral groove A2, the first insulating layer 11 is etched slightly, the size of the second lateral groove A2 along the direction perpendicular to the substrate 1 is increased (the second preset length is increased), and the aperture of the second hole K2 in the sub-hole of the first insulating layer 11 is increased; as shown Figure 9 As shown, Figure 9 A cross-sectional view along the direction perpendicular to the substrate 1 after the formation of the second transverse groove A2, as provided in some embodiments.

[0124] 9) Expose the first capacitor electrode 41;

[0125] The first sub-electrode 421 exposed in the second lateral groove A2 is etched to expose the first dielectric layer 431, and the first dielectric layer 431 is etched until the first capacitor electrode 41 is exposed; as shown Figure 10 As shown, Figure 10 This is a cross-sectional view along the BB' direction perpendicular to the substrate 1 after the first capacitor electrode 41 is exposed, as provided in some embodiments. At this time, the first sub-electrode 421 is disconnected in the second transverse groove A2 on the side facing the second hole K2, and the disconnection point of the first sub-electrode 421 is exposed in the second transverse groove A2.

[0126] 10) Formation of the third dielectric layer 433;

[0127] A third dielectric film is deposited, which covers the inner wall of the second hole K2 and the inner wall of the second transverse groove A2 to form a third dielectric layer 433;

[0128] The third dielectric layer 433 covering the sidewall of the first capacitor electrode 41 facing the second hole K2 is etched away, as well as the third dielectric layer 433 covering the sidewall of the first insulating layer 11, while retaining the third dielectric layer 433 covering the break in the first sub-electrode 421, to isolate the first sub-electrode 421 from the subsequently formed semiconductor layer 23, and to isolate the first sub-electrode 421 from the first capacitor electrode 41; Figure 11 As shown, Figure 11 A cross-sectional view along the direction perpendicular to the substrate 1 after the formation of the third dielectric layer 433 is provided for some embodiments. The third dielectric layer 433 is also distributed in the region between the first insulating layer 11 and the sacrificial layer 10 in the second lateral groove A2, that is, the region formed when the first insulating layer 11 is slightly etched based on the second hole K1 and the second lateral groove A2 to enlarge the size of the second lateral groove A2 along the direction perpendicular to the substrate 1.

[0129] 11) Forming a semiconductor layer 23, a gate insulating layer 24, and a word line 40;

[0130] A semiconductor thin film, a first gate insulating film, and a fourth conductive film are sequentially deposited on the substrate 1 on which the above structure is formed. The substrate is then polished to form a plurality of semiconductor layers 23, a first gate insulator layer 241, and a first portion 401 of a word line 40. The plurality of semiconductor layers 23 can cover the bottom wall and side wall of the second hole K2 and the second lateral groove A2. The first gate insulator layer 241 is disposed between the semiconductor layers 23 and the first portion 401 of the word line 40 to insulate the semiconductor layers 23 and the first portion 401 of the word line 40.

[0131] Etching removes the semiconductor film, the first gate insulating film, and the fourth conductive film from the second hole K2, causing a break between the semiconductor layers 23 at the same location on different layers; the semiconductor film, the first gate insulating film, and the fourth conductive film are retained in the second lateral groove A2; as shown Figure 12 As shown, Figure 12 A cross-sectional view along a direction perpendicular to the substrate 1 after forming the semiconductor layer 23, the first gate insulator layer 241 and the first portion 401 of the word line 40 in some embodiments.

[0132] A second gate insulating film is deposited, covering the inner wall of the second hole K2. The second gate insulating film is then etched to expose the first portion 401 of the word line 40, forming a second gate insulator layer 242. The second gate insulator layer 242 can prevent the semiconductor layer 23 from being connected to the second portion 402 of the subsequently formed word line 40. However, the embodiments of this disclosure are not limited to this. In some embodiments, the second gate insulating film may not be deposited. The first gate insulating layer sublayer 241 and the second gate insulating layer 242 together constitute the gate insulating layer 24.

[0133] A fifth conductive film is deposited, which fills the second hole K2 and the second lateral groove A2 to form the second portion 402 of the word line 40. The first portion 401 and the second portion 402 of the word line 40 together constitute the word line 40, as shown below. Figure 13 As shown, Figure 13 A cross-sectional view along a direction perpendicular to the substrate 1 after the formation of the second gate insulator layer 242 and the second portion 402 of the word line 40 in some embodiments.

[0134] In some embodiments, the semiconductor thin film, the first gate insulating film, the second gate insulating film, and the gate electrode film can be deposited by ALD.

[0135] In an exemplary embodiment of this disclosure, the material of the semiconductor layer 23 may be silicon or polycrystalline silicon with a band gap of less than 2 eV, or it may be a wide band gap material, such as a metal oxide material with a band gap of greater than 2 eV.

[0136] For example, the material of the metal oxide semiconductor layer or channel may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also contain compounds of other elements, such as nitrogen (N) and silicon (Si); it may also contain trace amounts of other doping elements.

[0137] In some embodiments, the material of the metal oxide semiconductor layer or channel may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), and indium tungsten oxide (InWO4). Materials such as IWO, titanium oxide (TiO), zinc oxynitride (ZnON), zinc magnesium oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), and zirconium zinc tin oxide (ZrZnSnO) can be used. As long as the leakage current of the transistor meets the requirements, it is acceptable. The specific requirements can be adjusted according to the actual situation.

[0138] These materials have wide band gaps and low leakage current. For example, when the metal oxide material is IGZO, the transistor leakage current is less than or equal to 10. -15 A. This can improve the performance of dynamic memory.

[0139] The above-mentioned materials for metal oxide semiconductor layers or channels only emphasize the element type of the material, without emphasizing the atomic ratio or the film quality of the material.

[0140] In exemplary embodiments of this disclosure, the material of the gate insulating layer 24 may comprise one or more high-K dielectric materials. In some embodiments, it may include one or more oxides of hafnium, aluminum, lanthanum, zirconium, etc. Exemplarily, for example, it may include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and other high-K materials.

[0141] In some embodiments, a bit line extending along the second direction Y can be formed on the side of the transistor opposite to the first hole K1. The bit line is connected to the semiconductor layer 23, and the semiconductor layer 23 of a row of transistors extending along the second direction Y is connected to the same bit line. The bit line can be fabricated before forming the capacitor.

[0142] This disclosure also provides an electronic device, including the semiconductor device described in any of the foregoing embodiments, or a semiconductor device formed by the manufacturing method of the semiconductor device described in any of the foregoing embodiments. The electronic device may be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a power bank, etc. The storage device may include memory in a computer, etc., and is not limited thereto.

[0143] While the embodiments disclosed in this invention are as described above, the content is merely for the purpose of facilitating understanding of the invention and is not intended to limit the invention. Any person skilled in the art to which this invention pertains may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this invention shall still be determined by the scope defined in the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A stacked structure disposed on a substrate includes a plurality of first insulating layers and a plurality of sacrificial layers alternately distributed along a direction perpendicular to the substrate, at least one capacitor aperture penetrating the stacked structure along a direction perpendicular to the substrate, and a plurality of capacitors distributed in the capacitor aperture along a direction perpendicular to the substrate. Each capacitor includes a first sub-electrode, a first dielectric layer, a first capacitor electrode, a second dielectric layer, and a second sub-electrode sequentially distributed from the outside to the inside in the capacitor aperture. The first capacitor electrodes of the plurality of capacitors in the same capacitor aperture are spaced apart along a direction perpendicular to the substrate. The plurality of first sub-electrodes of the plurality of capacitors in the same capacitor aperture are connected to form an integral structure extending along a direction perpendicular to the substrate, and the plurality of second sub-electrodes of the plurality of capacitors in the same capacitor aperture are connected to form an integral structure extending along a direction perpendicular to the substrate. The first capacitor electrode surrounds the second sub-electrode, and the first sub-electrode surrounds the first capacitor electrode.

2. The semiconductor device according to claim 1, characterized in that, The first dielectric layers of multiple capacitors in the same capacitor hole are spaced apart along a direction perpendicular to the substrate.

3. The semiconductor device according to claim 1, characterized in that, The second sub-electrode fills the capacitor hole.

4. The semiconductor device according to claim 1, characterized in that, The capacitor aperture includes a first sub-aperture located in the sacrificial layer and a second sub-aperture located in the first insulating layer. The first sub-aperture has a first transverse groove extending in a horizontal direction relative to the second sub-aperture. The first dielectric layer and the first capacitor electrode are sequentially distributed on the bottom wall and side wall of the first transverse groove.

5. The semiconductor device according to claim 4, characterized in that, Multiple capacitors in the same capacitor hole have multiple second dielectric layers connected to form an integral structure extending in a direction perpendicular to the substrate. The integral structure formed by the multiple second dielectric layers is distributed on the bottom wall and side wall of the capacitor hole, and the second dielectric layer is connected to the first dielectric layer distributed in the first transverse groove.

6. The semiconductor device according to claim 4, characterized in that, The semiconductor device further includes a plurality of transistors distributed along a direction perpendicular to the substrate and respectively connected to the plurality of capacitors, wherein the capacitors and the connected transistors are distributed along a first direction; The first sub-electrode extends continuously to the sidewall of the capacitor hole and has a first opening on the side facing the transistor to expose the first capacitor electrode; the first dielectric layer extends to the bottom wall and sidewall of the first transverse groove and has a second opening on the side facing the transistor to expose the first capacitor electrode; the transistor includes a semiconductor layer, and the semiconductor layer of the transistor is connected to the first capacitor electrode through the first opening of the first sub-electrode and the second opening of the first dielectric layer.

7. The semiconductor device according to claim 6, characterized in that, The capacitor further includes a third dielectric layer, which is disposed at the first opening of the first sub-electrode and connected to the first sub-electrode, the first capacitor electrode, the first dielectric layer, and the semiconductor layer.

8. The semiconductor device according to claim 6, characterized in that, The semiconductor device includes a plurality of capacitor holes arrayed along the first direction and the second direction, and the first sub-electrodes of the plurality of capacitor holes in the same column distributed along the second direction are connected to form an integral structure on the side of the stacked structure away from the substrate, and the second sub-electrodes of the plurality of capacitor holes in the same column are connected to form an integral structure on the side of the stacked structure away from the substrate; the second dielectric layer of the plurality of capacitor holes in the same column is connected to form an integral structure on the side of the stacked structure away from the substrate.

9. A method for manufacturing a semiconductor device, characterized in that, include: A stacked structure comprising alternating stacked first insulating layers and multiple sacrificial layers is formed on a substrate; Form at least one first hole through the stacked structure along a direction perpendicular to the substrate; Based on the first hole, the sacrificial layer is etched along a direction parallel to the substrate to form a first lateral groove; Within the first hole and the first transverse groove, a plurality of capacitors are sequentially formed, comprising a first sub-electrode, a first dielectric layer, a first capacitor electrode, a second dielectric layer, and a second capacitor electrode, distributed perpendicular to the substrate direction. The first capacitor electrodes of the plurality of capacitors in the same capacitor hole are spaced apart perpendicular to the substrate direction. The plurality of first sub-electrodes of the plurality of capacitors in the same capacitor hole are connected to form an integral structure extending perpendicular to the substrate direction. The plurality of second sub-electrodes of the plurality of capacitors in the same capacitor hole are connected to form an integral structure extending perpendicular to the substrate direction. The first capacitor electrode surrounds the second sub-electrode, and the first sub-electrode surrounds the first capacitor electrode.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The first sub-electrode, first dielectric layer, first capacitor electrode, second dielectric layer, and second capacitor electrode of a plurality of capacitors distributed perpendicular to the substrate direction are sequentially formed in the first hole and the first transverse groove, including: A first conductive film, a first dielectric film, and a second conductive film are sequentially deposited in the first hole and the first transverse groove, with the first conductive film, the first dielectric film, and the second conductive film sequentially covering the inner walls of the first hole and the first transverse groove; the second conductive film and the first dielectric film on the sidewall of the first hole are etched away, while the first conductive film in the first hole and the first transverse groove is retained, and the first dielectric film and the second conductive film in the first transverse groove are retained, forming the first sub-electrode, the first dielectric layer, and the first capacitor electrode; A second dielectric film and a third conductive film are deposited sequentially. The second dielectric film covers the inner wall of the first hole and the first lateral groove where the first sub-electrode, the first dielectric layer and the first capacitor electrode are formed. The third conductive film fills the first hole and the first lateral groove to form the second dielectric layer and the second sub-electrode.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, Before forming the first sub-electrode, first dielectric layer, first capacitor electrode, second dielectric layer and second capacitor electrode of a plurality of capacitors distributed in a direction perpendicular to the substrate in the first hole and the first lateral groove, the method further includes: etching the first insulating layer based on the first hole and the first lateral groove, such that the first lateral groove is expanded by a first preset length in the direction perpendicular to the substrate.

12. The method for manufacturing a semiconductor device according to claim 10, characterized in that, The method further includes: forming at least one second hole corresponding to the first hole in a direction perpendicular to the substrate and penetrating the stacked structure, wherein the first hole and the corresponding second hole are distributed along a first direction; After forming the second dielectric layer and the second sub-electrode, the method further includes: Based on the second hole, the sacrificial layer is etched along a direction parallel to the substrate to expose the first sub-electrode, forming a second lateral groove; Based on the second lateral groove, the first sub-electrode and the first dielectric layer are etched to expose the first capacitor electrode; A third dielectric film is deposited in the second hole and the second lateral groove. The third dielectric film covering the sidewall of the first capacitor electrode facing the second hole and the third dielectric film on the sidewall of the first insulating layer are etched away. The third dielectric film connected to the first sub-electrode, the first capacitor electrode and the first dielectric layer are retained to form the third dielectric layer.

13. The method for manufacturing a semiconductor device according to claim 12, characterized in that, Before etching the first sub-electrode and the first dielectric layer based on the second lateral groove to expose the first capacitor electrode, the method further includes: etching the first insulating layer based on the second hole and the second lateral groove, such that the second lateral groove is expanded to a second predetermined length along the dimension perpendicular to the substrate direction.

14. An electronic device, characterized in that, This includes the semiconductor device as described in any one of claims 1 to 8, or the semiconductor device formed by the manufacturing method of the semiconductor device as described in any one of claims 9 to 13.

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