A two-dimensional ring gate transistor and a preparation method thereof

Abstract

This invention belongs to the field of semiconductor technology and relates to a two-dimensional gate-ring transistor and its fabrication method, comprising: providing a substrate; forming source / drain regions on the substrate; forming source / drain electrodes in the source / drain regions; forming a first gate electrode region between the source / drain electrodes; forming a first gate electrode covered with a metal precursor in the first gate electrode region; oxidizing the metal precursor on the first gate electrode into a metal oxide to form a first oxide dielectric layer; transferring a two-dimensional material thin film onto the first oxide dielectric layer to form a two-dimensional semiconductor channel; forming a second oxide dielectric layer above the two-dimensional semiconductor channel and at the same position as the first oxide dielectric layer; forming a second gate electrode region on the second oxide dielectric layer; and forming a second gate electrode in the second gate electrode region. This invention utilizes the oxide layer resulting from the oxidation of the metal precursor as a dielectric layer to encapsulate a molybdenum disulfide channel between two oxide dielectric layers to achieve a gate-ring structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a two-dimensional gate-ring transistor and its fabrication method. Background Technology

[0002] As semiconductor process nodes continue to shrink to below 5 nanometers, the electrostatic control capability of the traditional FinFET's three-sided gate-surrounded structure is gradually becoming insufficient, leading to increased leakage current and power consumption. To achieve further transistor miniaturization, the gate-around transistor structure, where the dielectric layer completely surrounds the channel on all four sides, has become a core technology solution for 3-nanometer and below processes. This fully enclosed structure significantly enhances gate control capability, effectively suppresses leakage current, and achieves higher drive current at the same power consumption.

[0003] In recent years, the miniaturization of silicon-based gate-around transistors has reached its theoretical limit. Two-dimensional materials, such as molybdenum disulfide (MoS2), as a typical two-dimensional semiconductor material, possess atomic-level thickness and excellent tunability of electrical properties, and are considered one of the potential channel materials for continuing Moore's Law and further improving transistor integration density and performance. However, due to its low surface defect density and limited intrinsic mechanical strength, traditional dielectric layer fabrication processes, such as atomic layer deposition and magnetron sputtering, struggle to achieve uniform, high-quality dielectric film coverage on its surface.

[0004] Chinese patent CN111446288A discloses a two-dimensional material-based NS stacked transistor and its fabrication method. This patent uses two or more layers of two-dimensional material as the active layer and three or more layers of graphene or metal as the gate stack, increasing carrier transport paths and improving device performance through a multi-layer stacked structure. While this approach has some exploratory significance in the application of two-dimensional materials, its fabrication method does not involve the fabrication process of the dielectric layer, particularly failing to address the technical challenge of fabricating a high-quality dielectric layer on the surface of two-dimensional materials. Furthermore, the patterning of the dielectric layer in this approach typically requires direct etching, which may damage the dielectric layer, leading to a decrease in its quality and consequently affecting the reliability and stability of the device. Summary of the Invention

[0005] The purpose of this invention is to overcome the difficulties in growing dielectric layers on the surface of two-dimensional materials, and to propose a dielectric layer fabrication process compatible with two-dimensional channel materials, thereby enabling the construction of two-dimensional gate-around-the-ring (GOR) transistor devices based on this process. This transistor utilizes an oxide layer formed by the oxidation of a metal precursor as the dielectric layer, encapsulating a molybdenum disulfide channel between two oxide dielectric layers to achieve a GOR structure. This method first uses physical vapor deposition (PVD) to deposit a metal precursor film on the surface of the two-dimensional material. Subsequently, through the thermal oxidation reaction of the metal precursor in an oxygen atmosphere, the metal film is transformed into an oxide dielectric layer with a high dielectric constant. This process not only solves the problems of low reactivity and poor film quality on the surface of two-dimensional materials caused by traditional atomic layer deposition (ALD) techniques, but also achieves effective control over the dielectric layer pattern, providing a feasible technical path for the integration of two-dimensional electronic devices.

[0006] The objective of this invention can be achieved through the following technical solutions: One objective of this invention is to provide a method for fabricating a two-dimensional gate-ring transistor, comprising: Step 1: Provide a substrate, form source / drain regions on the substrate, and form source / drain electrodes in the source / drain regions; Step 2: A first gate electrode region is formed between the source / drain electrodes provided in step 1, and a first gate electrode covered with a metal precursor is formed in the first gate electrode region. Step 3: Oxidize the metal precursor on the first gate electrode obtained in Step 2 into an oxide dielectric to form a first oxide dielectric layer; Step 4: Transfer the two-dimensional material thin film onto the first oxide dielectric layer obtained in step 3 to form a two-dimensional semiconductor channel, while simultaneously forming an air gap between the two materials and the substrate. Step 5: Repeat steps 2 and 3 to form a second oxide dielectric layer above the two-dimensional semiconductor channel obtained in step 4 and at the same position as the first oxide dielectric layer; Step 6: Form a second gate electrode region on the second oxide dielectric layer obtained in step 5, and form a second gate electrode in the second gate electrode region.

[0007] Furthermore, the substrate is made of one or more of silicon, silicon oxide, and aluminum oxide; the substrate is preferably a silicon substrate, on which a silicon dioxide layer is formed. Furthermore, the thickness of the substrate is 500~1000μm, preferably 550μm.

[0008] In this invention, step 1 includes the following process: spin-coating photoresist on a substrate, exposing it by electron beam lithography, developing it by soaking it in a developer to form source / drain regions, depositing source / drain metals in a vacuum using an electron beam evaporator, and forming source / drain electrodes after soaking and peeling.

[0009] Furthermore, the photoresist is PMMA photoresist; Furthermore, the dose of the electron beam lithography exposure is 800-900 mJ / cm. 2 ; Furthermore, the developing solution is a mixed solution of methyl isobutyl ketone and isopropanol; the volume ratio of methyl isobutyl ketone to isopropanol is 3:1. Furthermore, the vacuum is defined as having a vacuum degree greater than 1 × 10⁻⁶. -8 Entrust; Furthermore, the soaking solvent in the soaking is acetone; Furthermore, the source / drain metal is a high work function metal, including one or more of gold, titanium, chromium, aluminum, and platinum, preferably gold; Furthermore, the thickness of the source / drain electrode is 20~100nm.

[0010] In this invention, step 2 includes the following process: spin-coating photoresist on a substrate, exposing it by electron beam lithography, developing it by soaking it in a developer to form a first gate electrode region, evaporating the first gate electrode metal and the metal precursor under vacuum using an electron beam evaporator, and then soaking and peeling it to form a first gate electrode covering the metal precursor.

[0011] The metal precursors include one or more of the following: molybdenum, tantalum, and aluminum. Furthermore, the photoresist is PMMA photoresist; Furthermore, the electron beam lithography exposure dose is 600~700 mJ / cm. 2 ; Furthermore, the developing solution is a mixed solution of methyl isobutyl ketone and isopropanol; the volume ratio of methyl isobutyl ketone to isopropanol is 3:1. Furthermore, the vacuum is defined as having a vacuum degree greater than 1 × 10⁻⁶. -8 Entrust; Furthermore, the soaking solvent in the soaking is acetone; Furthermore, the first gate electrode metal is a high work function metal, including one or more of gold, titanium, chromium, aluminum, and platinum; Furthermore, the thickness of the first gate electrode is 20~100nm; Furthermore, the thickness of the first gate electrode metal is 5~50nm; Furthermore, the thickness of the metal precursor is 5~10 nm.

[0012] In this invention, step 3 includes the following process: placing the substrate with the first gate electrode covered with the metal precursor obtained in step 2 in a tube furnace, heating and holding it in an oxygen atmosphere until the metal precursor of the gate is completely oxidized. In this invention, step 4 includes the following process: transferring a two-dimensional material thin film onto an oxide medium by a transfer method to form a two-dimensional semiconductor channel, while simultaneously forming an air gap between the two materials and the substrate.

[0013] Furthermore, the transfer method employs the PMMA stamping method, with the following specific steps: spin-coating a layer of PMMA onto the surface of the two-dimensional material film, curing it, then attaching a heat-release adhesive tape to the PMMA film, immersing it in water at room temperature until the two-dimensional material film naturally separates from the substrate, removing it, attaching it to the first oxide dielectric layer described in step 3, heating it to the release temperature of the heat-release adhesive, removing the heat-release adhesive tape, and then cleaning the PMMA with acetone.

[0014] The second objective of this invention is to provide a two-dimensional gate ring transistor, which is prepared using the method described above.

[0015] Compared with the prior art, the present invention has the following advantages: (1) This invention provides a method for fabricating a two-dimensional gate-ring transistor, which enables the construction of a two-dimensional gate-ring transistor device. This transistor uses a metal oxide as a dielectric layer, and a molybdenum disulfide channel is encapsulated between two oxide dielectric layers to achieve a gate-ring structure. The method first uses physical vapor deposition to deposit a metal precursor film on the surface of a two-dimensional material, and then transforms the metal film into an oxide dielectric layer with a high dielectric constant through the thermal oxidation reaction of the metal precursor in an oxygen atmosphere.

[0016] (2) This invention provides a method for fabricating a two-dimensional ring gate transistor. This method not only solves the problems of low reactivity and poor film quality on the surface of two-dimensional materials in traditional atomic layer deposition technology, but also realizes effective control of the dielectric layer pattern, providing a feasible technical path for the integration of two-dimensional electronic devices. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of a two-dimensional gate-ring transistor structure with an oxide layer formed by the oxidation of a metal precursor as the dielectric layer.

[0018] Figure 2 This is a schematic diagram of the structure prepared in step 1 of the fabrication method of the ring-gate two-dimensional transistor provided in the embodiment of the present invention; Figure 3 This is a schematic diagram of the structure prepared in steps 2 and 3 of the fabrication method of the ring-gate two-dimensional transistor provided in the embodiment of the present invention; Figure 4 This is a schematic diagram of the structure prepared in step 4 of the fabrication method of the ring-gate two-dimensional transistor provided in the embodiment of the present invention; Figure 5 This is a schematic diagram of the structure prepared in step 5 of the fabrication method of the ring-gate two-dimensional transistor provided in the embodiment of the present invention; Figure 6 This is a schematic diagram of the structure prepared in step 6 of the fabrication method of the ring-gate two-dimensional transistor provided in the embodiment of the present invention; Figure 7 A schematic cross-sectional view of the channel portion of a two-dimensional gate-ring transistor provided in an embodiment of the present invention; The numbers in the figure indicate: 1-Silicon substrate; 2-Silicon oxide barrier layer; 3-Source / drain electrode; 4-First gate electrode; 5-First oxide dielectric layer; 6-Two-dimensional material channel; 7-Second oxide dielectric layer; 8-Second gate electrode. Detailed Implementation

[0019] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments. These embodiments are implemented based on the technical solution of the present invention, providing detailed implementation methods and specific operating procedures. However, the scope of protection of the present invention is not limited to the following embodiments.

[0020] This invention provides a method for fabricating a two-dimensional gate-ring transistor, comprising: Step 1: Provide a substrate, form source / drain regions on the substrate, and form source / drain electrodes in the source / drain regions; Step 2: A first gate electrode region is formed between the source / drain electrodes provided in step 1, and a first gate electrode covered with a metal precursor is formed in the first gate electrode region. Step 3: Oxidize the metal precursor on the first gate electrode obtained in Step 2 into an oxide to form a first oxide dielectric layer; Step 4: Transfer the two-dimensional material thin film onto the first oxide dielectric layer obtained in step 3 to form a two-dimensional semiconductor channel, while simultaneously forming an air gap between the two materials and the substrate. Step 5: Repeat steps 2 and 3 to form a second oxide dielectric layer above the two-dimensional semiconductor channel obtained in step 4 and at the same position as the first oxide dielectric layer; Step 6: Form a second gate electrode region on the second molybdenum oxide dielectric layer obtained in step 5, and form a second gate electrode in the second gate electrode region.

[0021] In some embodiments of the present invention, the substrate is made of one or more of silicon, silicon oxide, and aluminum oxide; the substrate is preferably a silicon substrate, on which a silicon dioxide layer is formed; the thickness of the substrate is 500~1000μm, preferably 550μm.

[0022] In some embodiments of the present invention, step 1 includes the following process: spin-coating photoresist on a substrate, exposing it by electron beam lithography, developing it by soaking in a developer to form a source / drain region, depositing source / drain metals in a vacuum using an electron beam evaporator, and forming source / drain electrodes after soaking and stripping.

[0023] Optionally, the photoresist is a PMMA photoresist; Optionally, the electron beam lithography exposure dose is 800-900 mJ / cm. 2 ; Optionally, the developing solution is a mixed solution of methyl isobutyl ketone and isopropanol; the volume ratio of methyl isobutyl ketone to isopropanol is 3:1. Optionally, the vacuum is a vacuum degree greater than 1×10⁻⁶. -8 Entrust; Optionally, the soaking solvent in the soaking is acetone; Optionally, the source / drain metal is a high work function metal, including one or more of gold, titanium, chromium, aluminum, and platinum, preferably gold; Optionally, the thickness of the source / drain electrode is 20~100nm.

[0024] In some embodiments of the present invention, step 2 includes the following process: spin-coating photoresist on a substrate, exposing it by electron beam lithography, developing it by soaking it in a developer to form a first gate electrode region, evaporating the first gate electrode metal and the metal precursor under vacuum using an electron beam evaporator, and forming a first gate electrode covering the metal precursor after soaking and peeling.

[0025] Optionally, the photoresist is a PMMA photoresist; Optionally, the dose of the electron beam lithography exposure is 600~700mJ / cm. 2 ; Optionally, the developing solution is a mixed solution of methyl isobutyl ketone and isopropanol; the volume ratio of methyl isobutyl ketone to isopropanol is 3:1. Optionally, the vacuum is a vacuum degree greater than 1×10⁻⁶. -8 Entrust; Optionally, the soaking solvent in the soaking is acetone; Optionally, the first gate electrode metal is a high work function metal, including one or more of gold, titanium, chromium, aluminum, and platinum; Optionally, the thickness of the first gate electrode is 20~100nm; Optionally, the thickness of the first gate electrode metal is 5~50nm; Optionally, the thickness of the metal precursor is 5~10 nm.

[0026] In some embodiments of the present invention, step 3 includes the following process: placing the substrate with the first gate electrode covered with the metal precursor obtained in step 2 in a tube furnace, heating and holding it in an oxygen atmosphere until the metal precursor of the gate is completely oxidized. The metal precursors include one or more of the following: molybdenum, tantalum, and aluminum. In some embodiments of the present invention, step 4 includes the following process: transferring a two-dimensional material thin film onto an oxide medium by a transfer method to form a two-dimensional semiconductor channel, while simultaneously forming an air gap between the two materials and the substrate.

[0027] Optionally, the transfer method uses the PMMA stamping method, and the specific steps are as follows: spin-coating a layer of PMMA on the surface of the two-dimensional material film, curing it, attaching a heat-release adhesive tape to the PMMA film, immersing it in water at room temperature until the two-dimensional material film naturally separates from the substrate, removing it and attaching it to the first molybdenum oxide dielectric layer mentioned in step 3, heating it to the release temperature of the heat-release adhesive, removing the heat-release adhesive tape, and cleaning the PMMA with acetone.

[0028] Example like Figure 1 As shown, this embodiment provides a method for fabricating a two-dimensional gate-ring transistor, wherein the metal precursor and the oxidized dielectric are molybdenum metal and molybdenum oxide, respectively. The transistor structure includes, from bottom to top, a substrate, a source / drain electrode 3, a first gate electrode 4, a first molybdenum oxide dielectric layer 5, a two-dimensional material channel 6, a second molybdenum oxide dielectric layer 7, and a second gate electrode 8; The substrate includes a silicon substrate 1 and a silicon oxide barrier layer 2 disposed on the surface of the silicon substrate 1; the second molybdenum oxide dielectric layer 7 and the first molybdenum oxide dielectric layer 5 are in contact with and connected on the side of the two-dimensional semiconductor channel 6 to form a four-sided covered ring gate structure.

[0029] Before preparation, the raw material substrate is cleaned and treated, including the following steps: the substrate is ultrasonically cleaned in the order of acetone, isopropanol and deionized water, and then dried with a nitrogen gun for later use. The thickness of the substrate is 550 micrometers, and the thickness of the silicon surface oxide layer (i.e. silicon oxide barrier layer 2) is about 200-300 nm.

[0030] The fabrication method of a two-dimensional gate-ring transistor includes the following steps: Step 1: As Figure 2 As shown, source / drain regions are formed on silicon oxide isolation layer 2 by electron beam lithography, source / drain metals are deposited by ultra-high vacuum electron beam evaporation, and source / drain electrodes 3 are formed after resist removal. The thickness of source / drain electrodes 3 is 50nm. The specific process is as follows: Polymethyl methacrylate (PMMA) photoresist is spin-coated onto the outer surface of the silicon oxide barrier layer 2, and then exposed by electron beam lithography (dose of 850 mJ / cm). 2 The source / drain region is formed by soaking and developing the sample in a developer solution (a mixture of methyl isobutyl ketone and isopropanol, with a volume ratio of 3:1). The sample is then placed under vacuum (greater than 1x10⁻⁶). -8 The source / drain metal, which is gold, is deposited using an electron beam evaporator under the support. After being soaked and stripped with acetone, the source / drain electrode 3 is formed.

[0031] Step 2: As Figure 3 As shown, a gate region is formed in the middle of the source / drain electrode 3 by electron beam lithography. The first gate metal and a layer of molybdenum are deposited by ultra-high vacuum electron beam evaporation. After the resist is removed, the first gate electrode 4 is formed. The thickness of the first gate metal is 50 nm. The specific process is as follows: PMMA photoresist is spin-coated onto the outer surface of the silicon oxide barrier layer 2, and then exposed by electron beam lithography (dosage of 650 mJ / cm). 2 The gate region is formed by immersion and development in a developer solution (a mixture of methyl isobutyl ketone and isopropanol, with a volume ratio of 3:1). The gate region is then subjected to vacuum (greater than 1x10⁻⁶). -8 The first gate metal and a molybdenum layer are deposited using an electron beam evaporator under the conditions of ( ) and the first gate metal is gold. After being soaked and stripped with acetone, the first gate electrode 4 is formed.

[0032] Step 3: Place the substrate with electrodes in a tube furnace and heat it to 300°C at an oxygen flow rate of 300 sccm, with a heating rate of 10°C / min. Hold for 4 hours to convert metallic molybdenum into the first molybdenum oxide dielectric layer 5. This dielectric layer is prepared by three steps: photolithography (patterning), lift-off, and oxidation. The patterning of the molybdenum oxide dielectric layer is achieved by patterning the metallic molybdenum before oxidation. This dielectric layer is patterned through the photolithography process in step 2. Step 4: As Figure 4 As shown, a two-dimensional material thin film (commercially available, from Shenzhen Six Carbon Technology) prepared by chemical vapor deposition is transferred from a sapphire substrate to a first molybdenum oxide dielectric layer 5 using a transfer method. The material of the two-dimensional material thin film is a single layer of molybdenum disulfide, forming a two-dimensional material channel 6. The transfer method uses the PMMA stamping method. The specific steps are as follows: a layer of PMMA of about 200 nm is spin-coated on the surface of the two-dimensional material thin film, cured at 180°C for 2 min, and then a heat-release adhesive tape (commercially available product) is attached to the PMMA film. The above material is placed in water at room temperature until the two-dimensional material thin film naturally separates from the original substrate. After removal, it is attached to the first molybdenum oxide dielectric layer 5 mentioned in step 3, heated to the release temperature of the heat-release adhesive, and the PMMA is cleaned with acetone after removing the heat-release adhesive tape.

[0033] Step 5: As Figure 5As shown, the second molybdenum oxide dielectric layer region is formed by electron beam lithography at the same location as the first molybdenum oxide dielectric layer 5. A 10nm layer of metallic molybdenum is then deposited using an ultra-high vacuum electron beam evaporator. After resist removal, the layer is placed in a tube furnace and heated to 300℃ at an oxygen flow rate of 300sccm and a heating rate of 10℃ / min. It is held at this temperature for 4 hours to form the second molybdenum oxide dielectric layer 7. In this step, the photolithography process is completely identical to step 2, and the heating process is completely identical to step 3.

[0034] Step 6: Expose the second gate electrode region on the second molybdenum oxide dielectric layer 7 by electron beam lithography, and deposit the second gate metal (i.e., metallic gold) using an ultra-high vacuum electron beam evaporator. After removing the resist, the second gate electrode 8 is formed. The second gate electrode 8 is in contact with and connected to the first gate electrode 4 on the side of the molybdenum oxide dielectric layer.

[0035] The two-dimensional gate-ring transistor obtained by this invention utilizes molybdenum oxide as the dielectric layer, with a molybdenum disulfide channel sandwiched between two layers of molybdenum oxide dielectric to achieve the gate-ring structure. This invention first uses physical vapor deposition (PVD) to deposit a thin film of metallic molybdenum on the surface of a two-dimensional material. Then, through the thermal oxidation reaction of metallic molybdenum in an oxygen atmosphere, the metal film is transformed into a molybdenum oxide dielectric layer with a high dielectric constant. This process replaces the traditional atomic layer deposition (ALD) technique with a two-step process of metal deposition and oxidation. By patterning the oxidized metal instead of directly patterning the dielectric, effective control of the dielectric layer pattern is achieved. Furthermore, since direct metal deposition does not depend on the active reaction sites on the surface of the two-dimensional material, it fundamentally solves the problem of poor film quality in traditional ALD, providing a feasible technical path for the integration of two-dimensional electronic devices.

[0036] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any other way. Any person skilled in the art may make changes or modifications to the above-disclosed technical content to create equivalent embodiments. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A method for fabricating a two-dimensional gate-ring transistor, characterized in that, include: Step 1: Provide a substrate, form source / drain regions on the substrate, and form source / drain electrodes in the source / drain regions; Step 2: A first gate electrode region is formed between the source / drain electrodes provided in step 1, and a first gate electrode covered with a metal precursor is formed in the first gate electrode region. Step 3: Oxidize the metal precursor on the first gate electrode obtained in Step 2 into an oxide to form a first oxide dielectric layer; Step 4: Transfer the two-dimensional material thin film onto the first oxide dielectric layer obtained in step 3 to form a two-dimensional semiconductor channel, while simultaneously forming an air gap between the two materials and the substrate. Step 5: Repeat steps 2 and 3 to form a second oxide dielectric layer above the two-dimensional semiconductor channel obtained in step 4 and at the same position as the first oxide dielectric layer; Step 6: Form a second gate electrode region on the second oxide dielectric layer obtained in step 5, and form a second gate electrode in the second gate electrode region.

2. The method for fabricating a two-dimensional gate-ring transistor according to claim 1, characterized in that, The substrate is made of one or more of silicon, silicon oxide, and aluminum oxide; the substrate is preferably a silicon substrate, on which a silicon dioxide layer is formed. The thickness of the substrate is 500~1000μm.

3. The method for fabricating a two-dimensional gate-ring transistor according to claim 1, characterized in that, Step 1 includes the following processes: spin-coating photoresist on the substrate, exposing it by electron beam lithography, developing it by soaking in a developer to form source / drain regions, depositing source / drain metals in a vacuum using an electron beam evaporator, and forming source / drain electrodes after soaking and stripping.

4. The method for fabricating a two-dimensional gate-ring transistor according to claim 3, characterized in that, The photoresist is PMMA photoresist; The electron beam lithography exposure dose is 800-900 mJ / cm. 2 ; The developing solution is a mixture of methyl isobutyl ketone and isopropanol; the volume ratio of methyl isobutyl ketone to isopropanol is 3:

1. The vacuum is defined as a vacuum degree greater than 1 × 10⁻⁶. -8 Entrust; The soaking solvent used in the soaking process is acetone; The source / drain metal is a high work function metal, including one or more of gold, titanium, chromium, aluminum, and platinum, preferably gold; The thickness of the source / drain electrodes is 20~100nm.

5. The method for fabricating a two-dimensional gate-ring transistor according to claim 1, characterized in that, Step 2 includes the following processes: spin-coating photoresist on the substrate, exposing it by electron beam lithography, developing it by soaking it in a developer to form the first gate electrode region, evaporating the first gate electrode metal and the metal precursor under vacuum using an electron beam evaporator, and then soaking and peeling it to form the first gate electrode covering the metal precursor.

6. The method for fabricating a two-dimensional gate-ring transistor according to claim 5, characterized in that, The photoresist is PMMA photoresist; The electron beam lithography exposure dose is 600~700mJ / cm. 2 ; The developing solution is a mixture of methyl isobutyl ketone and isopropanol; the volume ratio of methyl isobutyl ketone to isopropanol is 3:

1. The vacuum is defined as a vacuum degree greater than 1 × 10⁻⁶. -8 Entrust; The soaking solvent used in the soaking process is acetone; The first gate electrode metal is a high work function metal, including one or more of gold, titanium, chromium, aluminum, and platinum; The thickness of the first gate electrode is 20~100nm; The thickness of the first gate electrode metal is 5~50nm; The thickness of the metal precursor is 5~10 nm.

7. The method for fabricating a two-dimensional gate-ring transistor according to claim 1, characterized in that, Step 3 includes the following process: the substrate with the first gate electrode covered with the metal precursor obtained in step 2 is placed in a tube furnace, heated and held in an oxygen atmosphere until the metal precursor of the gate is completely oxidized. The metal precursor comprises one or more of molybdenum, tantalum, and aluminum.

8. The method for fabricating a two-dimensional gate-ring transistor according to claim 1, characterized in that, Step 4 includes the following process: a two-dimensional material thin film is transferred onto molybdenum oxide by a transfer method to form a two-dimensional semiconductor channel, while an air gap is formed between the two materials and the substrate.

9. The method for fabricating a two-dimensional gate-ring transistor according to claim 8, characterized in that, The transfer method uses PMMA stamping, and the specific steps are as follows: spin-coating a layer of PMMA on the surface of the two-dimensional material film, curing it, attaching a heat-release adhesive tape to the PMMA film, immersing it in water at room temperature until the two-dimensional material film naturally separates from the substrate, removing it and attaching it to the first molybdenum oxide dielectric layer mentioned in step 3, heating it to the release temperature of the heat-release adhesive, removing the heat-release adhesive tape, and then cleaning the PMMA with acetone.

10. A two-dimensional gate-ring transistor, characterized in that, It is prepared by the method described in any one of claims 1-9.

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