High mobility low power consumption TeSeO thin film transistor and preparation method thereof
By employing a double-layer + dual-atmosphere annealing process, the problems of high off-state current and low mobility in TeSeO thin film transistors were solved, enabling the fabrication of high-mobility, low-power TeSeO thin film transistors.
CN122373392APending Publication Date: 2026-07-10NANJING UNIV OF POSTS & TELECOMM
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- NANJING UNIV OF POSTS & TELECOMM
- Filing Date
- 2026-04-10
- Publication Date
- 2026-07-10
AI Technical Summary
Technical Problem
TeSeO thin-film transistors suffer from high power consumption and low mobility due to high off-state current, which affects their application in low-power integrated circuits.
Method used
A double-layer + dual-atmosphere annealing process is adopted. First, the TeSeO-1 active layer is annealed in a vacuum environment to form oxygen vacancy traps. Then, the TeSeO-2 active layer is annealed in an O2/N2 mixed gas to fill the oxygen vacancy traps, thereby achieving excessive hole doping.
Benefits of technology
Significantly reducing off-state current and improving mobility, high-mobility, low-power TeSeO thin-film transistors were fabricated.
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Figure CN122373392A_ABST
Abstract
A high mobility and low power consumption TeSeO thin film transistor and a preparation method thereof, steps are as follows: obtaining a substrate; growing a gate electrode layer on the substrate; covering a gate dielectric layer on the gate electrode layer and the substrate; generating a TeSeO-1 active layer on the gate dielectric layer; performing first annealing treatment on the TeSeO-1 active layer in a vacuum environment; growing a TeSeO-2 active layer on the upper surface of the TeSeO-1 active layer; performing second annealing treatment on the TeSeO-2 active layer in an O2 / N2 mixed gas atmosphere; forming a source electrode layer and a drain electrode layer on both sides of the upper surface of the TeSeO-2 active layer at intervals, and the source electrode layer and the drain electrode layer are respectively overlapped with both sides of the gate electrode layer in the horizontal direction. Through the "double-layer + double-atmosphere annealing" process, the number of oxygen vacancy traps and hole carriers in different TeSeO film layers is controlled, and high hole mobility and low energy consumption of the device are realized.
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