A gate controlled transistor and a method of manufacturing the same

Abstract

This invention discloses a gate-controlled transistor (JFET) and its fabrication method. The JFET includes: a substrate; a first epitaxial layer located on the substrate, the first epitaxial layer including a first base region and a second base region spaced apart along a first direction, both the first base region and the second base region being close to the side of the first epitaxial layer away from the substrate; and a gate structure located on the side of the first epitaxial layer away from the substrate, the gate structure including a gate dielectric layer and a gate electrode, the gate electrode being located on the side of the gate dielectric layer away from the substrate, the gate dielectric layer contacting the first base region but not the second base region, and the gate electrode overlapping the first base region but not the second base region along a second direction. In this invention, the JFET is an asymmetric planar structure with a single-sided gate and a single-sided channel, placing the JFET region between the channel region and the non-channel region, enabling synergistic optimization of conduction characteristics and switching performance, and avoiding the problem of current accumulation in the central region of the JFET region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a gate-controlled transistor and its fabrication method. Background Technology

[0002] In a planar silicon carbide field-effect transistor (MOSFET), the part between the two body regions is called the junction field-effect region (JFET), which is the region through which current must flow when the silicon carbide field-effect transistor is in the on state.

[0003] Currently, when silicon carbide field-effect transistors are in the on state, current tends to accumulate in the center of the JFET region, forming a "current crowding effect" that affects the performance of silicon carbide MOSFETs. Summary of the Invention

[0004] This invention provides a gate-controlled transistor and its fabrication method to solve the problem of current accumulation in the JFET region of existing silicon carbide field-effect transistors.

[0005] According to one aspect of the present invention, a gate-controlled transistor is provided, comprising: Substrate; A first epitaxial layer is located on the substrate. The first epitaxial layer includes a first base region and a second base region arranged at intervals along a first direction. The first base region and the second base region are both close to the side of the first epitaxial layer away from the substrate. The first direction is parallel to the plane of the substrate. A gate structure is located on the side of the first epitaxial layer away from the substrate. The gate structure includes a gate dielectric layer and a gate electrode. The gate electrode is located on the side of the gate dielectric layer away from the substrate. The gate dielectric layer is in contact with the first base region but not with the second base region. Along a second direction, the gate electrode overlaps with the first base region but not with the second base region. The second direction is perpendicular to the plane of the substrate.

[0006] According to another aspect of the present invention, a method for fabricating a gate-controlled transistor is provided, for fabricating the gate-controlled transistor as described above, the method comprising: Provide the substrate; The first epitaxial layer is formed on one side of the substrate; The first base region and the second base region are formed in the first epitaxial layer; The gate dielectric layer and the gate electrode are sequentially formed on the side of the first epitaxial layer away from the substrate. The gate dielectric layer is in contact with the first base region but not with the second base region. The gate electrode overlaps with the first base region but not with the second base region along the second direction.

[0007] In this invention, the gate-controlled transistor is an asymmetric planar gate-controlled transistor, employing a cell layout structure design with a single-sided gate and a single-sided channel, which enables synergistic optimization of conduction characteristics and switching performance. On one hand, the single-sided gate and single-sided channel eliminate the need to reserve sufficient space for two channel regions, two gates, isolation dielectrics, and other components, thus reducing the size of the gate-controlled transistor. On the other hand, the single-sided gate and single-sided channel result in smaller overlap areas between the gate and source electrodes, and between the gate and drain electrodes. This reduces the gate-source capacitance and gate-drain capacitance, thereby lowering parasitic capacitance and ultimately reducing switching losses and drive power consumption, while increasing switching speed. This is beneficial for the application of gate-controlled transistors in high-frequency devices and high-frequency applications. On the other hand, the JFET region in a gate-controlled transistor is located between the channel region and the non-channel region. When the gate-controlled transistor is turned on, current is transmitted only through the inversion channel formed by the base region on one side. Therefore, the current will not accumulate in the central region of the JFET region of the gate-controlled transistor, and there is no "current crowding effect" in the JFET region. This can improve the effective channel utilization of the gate-controlled transistor, prevent the problem of local Joule heat concentration in the gate-controlled transistor, improve the on-resistance of the gate-controlled transistor, reduce the on-loss of the gate-controlled transistor, and improve the thermal reliability of the gate-controlled transistor, thereby improving the performance of the gate-controlled transistor and making it suitable for use in high-voltage, high-frequency, and high-efficiency power electronic equipment.

[0008] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0009] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 This is a schematic diagram of a gate-controlled transistor provided in an embodiment of the present invention; Figure 2This is a schematic diagram of another gate-controlled transistor provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of a method for fabricating a gate-controlled transistor according to an embodiment of the present invention; Figure 4 This is a schematic diagram of another method for fabricating a gate-controlled transistor provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the substrate and the first epitaxial layer provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of the first base region provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the second base region provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of the second injection region provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of the first injection region and the third injection region provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of the gate dielectric layer provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of the gate electrode and interlayer dielectric layer provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention. Detailed Implementation

[0011] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0012] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0013] Traditional planar silicon carbide (MOSFET) field-effect transistors employ a symmetrical layout, with channels and gates located on both the left and right sides, which improves channel density and current capability. However, this symmetrical structure places the junction field-effect region (JFET) between the two channels, causing current to tend to accumulate in the center of the JFET region when the transistor is on, resulting in a significant "current crowding effect." This not only limits the effective channel utilization of the silicon carbide MOSFET but may also cause localized Joule heat concentration, worsening on-resistance and thermal reliability, ultimately affecting the performance of the silicon carbide MOSFET.

[0014] Furthermore, traditional planar silicon carbide MOSFETs employ a symmetrical layout design, requiring the gate to cover both channels simultaneously. This inevitably increases the overlap area between the gate and source, as well as the overlap area between the gate and drain, resulting in a significant increase in gate-source capacitance and gate-drain capacitance. In other words, the symmetrical structure of traditional planar silicon carbide MOSFETs exhibits high parasitic capacitance, leading to high switching losses. This results in even greater switching losses and drive power consumption in high-frequency switching applications, severely limiting the performance potential of silicon carbide MOSFETs in high-frequency, high-efficiency scenarios.

[0015] To address the aforementioned technical problems, the present invention provides a gate-controlled transistor. Figure 1 This is a schematic diagram of a gate-controlled transistor provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of another gate-controlled transistor provided in an embodiment of the present invention, as shown below. Figure 1 and Figure 2 The gate-controlled transistor shown includes: a substrate 110; a first epitaxial layer 120 located on the substrate 110, the first epitaxial layer 120 including a first base region 130 and a second base region 140 arranged at intervals along a first direction X, the first base region 130 and the second base region 140 being close to the side of the first epitaxial layer 120 away from the substrate 110, the first direction X being parallel to the plane of the substrate 110; and a gate structure 150 located on the side of the first epitaxial layer 120 away from the substrate 110, the gate structure 150 including a gate dielectric layer 151 and a gate electrode 152, the gate electrode 152 being located on the side of the gate dielectric layer 151 away from the substrate 110, the gate dielectric layer 151 being in contact with the first base region 130 but not with the second base region 140, the gate electrode 152 overlapping the first base region 130 but not with the second base region 140 along a second direction Y, the second direction being perpendicular to the plane of the substrate.

[0016] The gate-controlled transistor provided by this invention can be a field-effect transistor or an insulated-gate bipolar transistor, and can be applied in power semiconductor devices. It is suitable for high-voltage, high-frequency, and high-efficiency power electronics applications, such as electric drive systems for new energy vehicles, smart grid converters, and industrial frequency converters, but is not limited thereto. For example, the gate-controlled transistor is a silicon carbide MOSFET, which is used in silicon carbide (SiC) devices and has high breakdown field strength, high saturated electron drift velocity, and excellent thermal stability.

[0017] In this embodiment, the gate-controlled transistor includes a substrate 110, which is a semiconductor substrate, such as a silicon substrate or a compound semiconductor substrate. The substrate of the gate-controlled transistor can be reasonably selected according to the product requirements. For example, if the gate-controlled transistor is a silicon carbide MOSFET, then a silicon carbide substrate is selected for substrate 110.

[0018] The gate-controlled transistor includes a first epitaxial layer 120, which is located on the substrate 110. In other words, the first epitaxial layer 120 is epitaxially grown on the upper surface of the substrate 110. For example, if the gate-controlled transistor is a silicon carbide MOSFET, then the first epitaxial layer 120 is selected as a silicon carbide epitaxial layer.

[0019] In this invention, different first conductivity types and second conductivity types are defined, wherein one of the first conductivity type and the second conductivity type is N-type and the other is P-type; for example, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type. The conductivity type of the film layer specifically refers to the conductivity type of the impurities implanted in the film layer, and the conductivity type of the region specifically refers to the conductivity type of the impurities implanted in the region; for example, the first epitaxial layer 120 having a first conductivity type means that impurities of the first conductivity type are implanted into the first epitaxial layer 120, and the first base region 130 having a second conductivity type means that impurities of the second conductivity type are implanted into the first base region 130, and so on.

[0020] Depending on the type of transistor, the conductivity type of the substrate 110 and the first epitaxial layer 120 can be reasonably designed. The conductivity types of the substrate 110 and the first epitaxial layer 120 can be the same or different. For example, if the gate-controlled transistor is a unipolar transistor, then the substrate 110 and the first epitaxial layer 120 in the unipolar transistor have the same conductivity type, for example, both the substrate 110 and the first epitaxial layer 120 may be P-type or both may be N-type. Alternatively, if the gate-controlled transistor is a bipolar transistor, then the substrate 110 and the first epitaxial layer 120 in the bipolar transistor have different conductivity types, for example, the substrate 110 may be N-type and the first epitaxial layer 120 may be P-type, or the substrate 110 may be P-type and the first epitaxial layer 120 may be N-type. In this embodiment, the first epitaxial layer 120 is used as the first conductivity type for illustration.

[0021] The first epitaxial layer 120 includes a first base region 130 and a second base region 140 arranged at intervals along a first direction X. Both the first base region 130 and the second base region 140 are located near the side of the first epitaxial layer 120 facing away from the substrate 110. The first base region 130 is located within the first epitaxial layer 120 and is located away from the substrate 110; therefore, the first base region 130 is located near the side of the first epitaxial layer 120 facing away from the substrate 110. Similarly, the second base region 140 is located within the first epitaxial layer 120 and is located away from the substrate 110; therefore, the second base region 140 is located near the side of the first epitaxial layer 120 facing away from the substrate 110. (See reference...) Figure 1 As shown, the first base region 130, the second base region 140, and the first epitaxial layer 120 are all flush with each other, with one side of the surface facing away from the substrate 110, the other side of the surface facing away from the substrate 110, and the other side of the surface facing away from the substrate 110.

[0022] Based on the structure of the gate-controlled transistor, a first direction X and a second direction Y are defined. The first direction X is parallel to the plane of the substrate 110 of the gate-controlled transistor, and the second direction Y is perpendicular to the plane of the substrate 110 of the gate-controlled transistor. The first direction X and the second direction Y are perpendicular to each other. Ion implantation is performed on a specific region of the first epitaxial layer 120 away from the upper surface of the substrate 110 to form a first base region 130. Similarly, ion implantation is performed on another specific region of the first epitaxial layer 120 away from the upper surface of the substrate 110 to form a second base region 140. A gap exists between the first base region 130 and the second base region 140, and the region between the first base region 130 and the second base region 140 is defined as the junction field-effect region (JFET region). It should be noted that along the first direction X, the first epitaxial layer 120 has two opposing sidewalls, which can be named the first sidewall and the second sidewall. The first base region 130 and the second base region 140 are located near opposite sides of the first epitaxial layer 120. Specifically, the first base region 130 is close to the first epitaxial layer 120 and away from the upper surface of the substrate 110, and the side of the first base region 130 is flush with one side wall (such as the first side wall) of the first epitaxial layer 120; similarly, the second base region 140 is close to the first epitaxial layer 120 and away from the upper surface of the substrate 110, and the side of the second base region 140 is flush with the other side wall (such as the second side wall) of the first epitaxial layer 120.

[0023] In the optional gate-controlled transistor, the first epitaxial layer 120 has a first conductivity type, the first base region 130 has a second conductivity type, and the second base region 140 has a second conductivity type; the gate-controlled transistor includes a unipolar transistor, in which the substrate 110 has a first conductivity type; or, the gate-controlled transistor includes a bipolar transistor, in which the substrate 110 has a second conductivity type.

[0024] If the gate-controlled transistor is a unipolar transistor (such as a MOSFET), then in the unipolar transistor, the substrate 110 has a first conductivity type, the first epitaxial layer 120 has a first conductivity type, the first base region 130 has a second conductivity type, and the second base region 140 has a second conductivity type. One of the first conductivity type and the second conductivity type is N-type and the other is P-type.

[0025] If the gate-controlled transistor is a bipolar transistor (such as an IGBT), then in the bipolar transistor, the substrate 110 has a second conductivity type, the first epitaxial layer 120 has a first conductivity type, the first base region 130 has a second conductivity type, and the second base region 140 has a second conductivity type. One of the first conductivity type and the second conductivity type is N-type and the other is P-type.

[0026] The gate-controlled transistor includes a gate structure 150 located on the side of the first epitaxial layer 120 away from the substrate 110. The gate structure 150 includes a gate dielectric layer 151 and a gate electrode 152, with the gate electrode 152 located on the side of the gate dielectric layer 151 away from the substrate 110. The gate structure 150 also includes an interlayer dielectric layer 153, where both the gate dielectric layer 151 and the interlayer dielectric layer 153 are insulating layers. Specifically, along the second direction Y, the gate dielectric layer 151, the gate electrode 152, and the interlayer dielectric layer 153 are sequentially stacked, with the gate electrode 152 located between the gate dielectric layer 151 and the interlayer dielectric layer 153. The gate dielectric layer 151 is close to the first epitaxial layer 120 and located on the side of the first epitaxial layer 120 away from the substrate 110, while the interlayer dielectric layer 153 is away from the first epitaxial layer 120. It should be noted that, along the second direction Y, the vertical projection of the gate dielectric layer 151 onto the substrate 110 and the vertical projection of the gate electrode 152 onto the substrate 110 can coincide; or, along the second direction Y, the vertical projection of the gate dielectric layer 151 onto the substrate 110 can cover the vertical projection of the gate electrode 152 onto the substrate 110. This ensures that the gate electrode 152 and the first epitaxial layer 120 are insulated from each other through the gate dielectric layer 151. The interlayer dielectric layer 153 is located outside the gate electrode 152 and covers both the gate electrode 152 and the gate dielectric layer 151. The interlayer dielectric layer 153 also covers a portion of the first base region 130, the JFET region, and a portion of the second base region 140. The interlayer dielectric layer 153 is in contact with the gate electrode 152, the gate dielectric layer 151, the first base region 130, the JFET region, and the second base region 140.

[0027] In this embodiment, the gate dielectric layer 151 is in contact with the first base region 130 but not with the second base region 140. Specifically, the gate dielectric layer 151 is partially in contact with the first base region 130 and also partially in contact with the JFET region. Correspondingly, a gate electrode 152 is formed on the side of the gate dielectric layer 151 facing away from the substrate 110. Along the second direction Y, the vertical projection of the gate electrode 152 on the first epitaxial layer 120 overlaps with the first base region 130, but the vertical projection of the gate electrode 152 on the first epitaxial layer 120 does not overlap with the second base region 140. Specifically, along the second direction Y, the vertical projection of the gate electrode 152 on the first epitaxial layer 120 only partially overlaps with the first base region 130, and the vertical projection of the gate electrode 152 on the first epitaxial layer 120 also only partially overlaps with the JFET region.

[0028] As described above, the gate dielectric layer 151 is in contact with the first base region 130 but not with the second base region 140, and the gate electrode 152 along the second direction Y overlaps with the first base region 130 but not with the second base region 140. Therefore, the gate-controlled transistor is not a symmetrical structure. The gate-controlled transistor provided in this embodiment is an asymmetrical structure. Here, the symmetry is judged based on the central axis A1-A2 extending along the second direction Y. Figure 1 and Figure 2 In this embodiment, the structure on the left side of the central axis A1-A2 differs from the structure on the right side. Most or all of the gate dielectric layer 151 is located in the structure on the left side of the central axis A1-A2, and most or all of the gate electrode 152 is also located in the structure on the left side of the central axis A1-A2. Therefore, the gate-controlled transistor has an asymmetric structure along the central axis A1-A2. Thus, the gate-controlled transistor provided in this embodiment is an asymmetric planar gate-controlled transistor.

[0029] In this embodiment, the gate-controlled transistor (GMT) has a gate electrode 152 only on the side where the first base region 130 is located, and no gate electrode 152 is provided on the side where the second base region 140 is located. Therefore, the GMT has a single-gate structure. Similarly, the GMT forms a channel only on the side where the first base region 130 is located, and no channel is formed on the side where the second base region 140 is located. Therefore, the GMT has a single-channel structure. The region where the first base region 130 of the GMT is located can be defined as the channel region, and the region where the second base region 140 of the GMT is located can be defined as the non-channel region. Obviously, the JFET region in the GMT is located between the channel region and the non-channel region. Therefore, the GMT provided in this embodiment is an asymmetric planar GMT, using a cell layout structure design with a single-gate and single-channel. Here, one cell can be understood as one GMT, and multiple cells can be understood as multiple GMTs.

[0030] As described above, with the gate electrode 152 positioned above the first base region 130 on one side, the gate-controlled transistor (JFET) transmits current only through the inversion conductive channel formed by the first base region 130 on one side when it is in the on state. It does not form a conductive channel in the second base region 140. Therefore, the width between the JFET region and the second base region 140 on the other side is significantly reduced, effectively decreasing the cell spacing. Simultaneously, the optimized current path through the JFET region when the single-sided channel is on significantly alleviates the current squeezing effect commonly found in existing double-sided channel structures, preventing deterioration of conduction characteristics due to reduced channel density. In other words, the gate-controlled transistor provided in this embodiment exhibits almost no current squeezing effect in the JFET region, improving conduction characteristics. Furthermore, the single-sided gate layout of the gate-controlled transistor in this embodiment significantly reduces the overlap area between the gate electrode 152 and the source, and between the gate electrode 152 and the drain, thereby reducing the gate-source capacitance and gate-drain capacitance, and consequently decreasing switching losses.

[0031] The gate-controlled transistor further includes a first electrode 160 and a second electrode 170. The first electrode 160 is located on the side of the gate structure 150 away from the substrate 110, and is in contact with the first base region 130 and the second base region 140. The first electrode 160 is insulated from the gate electrode 152. The second electrode 170 is located on the side of the substrate 110 away from the first epitaxial layer 120. The gate-controlled transistor includes a gate, a source, and a drain. Here, the gate electrode 152 is the gate of the gate-controlled transistor. Optionally, the first electrode 160 can be the source of the gate-controlled transistor, and the second electrode 170 can be the drain of the gate-controlled transistor; or, the first electrode 160 can be the drain of the gate-controlled transistor, and the second electrode 170 can be the source of the gate-controlled transistor. The first electrode 160 can be located outside the interlayer dielectric layer 153 to completely cover the interlayer dielectric layer 153; or, the first electrode 160 can be located on both sides of the interlayer dielectric layer 153 along the X direction. This ensures that the gate electrode 152 and the first electrode 160 are insulated from each other by the interlayer dielectric layer 153. The first electrode 160 is in contact with both the first base region 130 and the second base region 140.

[0032] In this invention, the gate-controlled transistor is an asymmetric planar gate-controlled transistor, employing a cell layout structure design with a single-sided gate and a single-sided channel, which enables synergistic optimization of conduction characteristics and switching performance. On one hand, the single-sided gate and single-sided channel eliminate the need to reserve sufficient space for two channel regions, two gates, isolation dielectrics, and other components, thus reducing the size of the gate-controlled transistor. On the other hand, the single-sided gate and single-sided channel result in smaller overlap areas between the gate and source electrodes, and between the gate and drain electrodes. This reduces the gate-source capacitance and gate-drain capacitance, thereby lowering parasitic capacitance and ultimately reducing switching losses and drive power consumption, while increasing switching speed. This is beneficial for the application of gate-controlled transistors in high-frequency devices and high-frequency applications. On the other hand, the JFET region in a gate-controlled transistor is located between the channel region and the non-channel region. When the gate-controlled transistor is turned on, current is transmitted only through the inversion channel formed by the base region on one side. Therefore, the current will not accumulate in the central region of the JFET region of the gate-controlled transistor, and there is no "current crowding effect" in the JFET region. This can improve the effective channel utilization of the gate-controlled transistor, prevent the problem of local Joule heat concentration in the gate-controlled transistor, improve the on-resistance of the gate-controlled transistor, reduce the on-loss of the gate-controlled transistor, and improve the thermal reliability of the gate-controlled transistor, thereby improving the performance of the gate-controlled transistor and making it suitable for use in high-voltage, high-frequency, and high-efficiency power electronic equipment.

[0033] refer to Figure 1 and Figure 2 As shown, the first base region 130 and the second base region 140 may be asymmetric base region structures. Optionally, along the first direction X, the width D1 of the first base region 130 may be less than or equal to the width D2 of the second base region 140. Optionally, along the second direction Y, the depth H1 of the first base region 130 may be less than or equal to the depth H2 of the second base region 140. Optionally, the second base region 140 may have a protruding structure 141 on the side near the first base region 130. Optionally, the second base region 140 may have a beak-like structure 141A on the side near the first base region 130.

[0034] In this embodiment, the gate-controlled transistor is an asymmetric planar gate-controlled transistor, specifically designed with a single-sided gate and a single-sided channel cell layout structure. The region containing the first base region 130 is the channel region, and the region containing the second base region 140 is the non-channel region. Based on this, the structural design of the first base region 130 and the second base region 140 can be optimized, resulting in an asymmetric base region structure for the gate-controlled transistor.

[0035] refer to Figure 1 and Figure 2As shown, the width D1 of the first base region 130 and the width D2 of the second base region 140 can be adjusted so that the width D1 of the first base region 130 is less than or equal to the width D2 of the second base region 140. Specifically, the width D1 of the first base region 130 can be less than the width D2 of the second base region 140. Here, the width D1 of the first base region 130 is the dimension of the first base region 130 along the first direction X, and the width D2 of the second base region 140 is the dimension of the second base region 140 along the first direction X. (Reference) Figure 1 and Figure 2 As shown, the depth H1 of the first base region 130 and the depth H2 of the second base region 140 can be adjusted so that the depth H1 of the first base region 130 is less than or equal to the depth H2 of the second base region 140. Specifically, the depth H1 of the first base region 130 can be less than the depth H2 of the second base region 140. Here, the depth H1 of the first base region 130 is the dimension of the first base region 130 along the second direction Y, and the depth H2 of the second base region 140 is the dimension of the second base region 140 along the second direction Y. (Reference) Figure 1 and Figure 2 As shown, the shape of the second base region 140 can be adjusted so that the shape of the first base region 130 is different from that of the second base region 140. Specifically, the second base region 140 may have a protruding structure 141 on the side near the first base region 130. This protruding structure 141 may be a beak-shaped structure 141A. It is not limited to this.

[0036] Based on the single-channel design of the gate-controlled transistor (GMT), the GMT can have an asymmetric base region structure. Therefore, during the manufacturing process of the GMT, the structures of the first base region 130 and the second base region 140 can be asymmetric. There is no need to precisely control the structures of the first base region 130 and the second base region 140, and correspondingly, there is no need to strictly require the structural symmetry of the first base region 130 and the second base region 140. For example, the width, depth, shape, and other structures of the first base region 130 and the second base region 140 can be different. There is also no need to strictly require the symmetry of the doping distribution of the first base region 130 and the second base region 140. The concentration and conductivity type of the impurities implanted into the first base region 130 can be reasonably selected according to the product requirements. Similarly, the concentration and conductivity type of the impurities implanted into the second base region 140 can be reasonably selected.

[0037] In this embodiment, a second base region 140 is formed in the first epitaxial layer 120. The second base region 140 includes a protrusion structure 141 or a beak-like structure 141A. The second base region 140 can have a specific doping distribution (such as impurity concentration gradient, junction depth) and specific geometric dimensional parameters (such as tip curvature radius, extension length, etc.) to match the current density distribution of the gate-controlled transistor in the on-state, avoiding influence on the current path. In the depletion state of the gate-controlled transistor, the second base region 140 with the beak-like structure 141A can form a space charge region through charge coupling effect, effectively protecting the gate dielectric layer 151 and reducing the maximum electric field strength of the gate dielectric layer 151. Junction depth can also be understood as the depth of the base region.

[0038] The first base region 130 and the second base region 140 adopt an asymmetric structure design. The first base region 130 can have a gradient doping distribution and a low surface doping concentration, which is conducive to inversion channel formation and has a shallow junction depth, which is beneficial for the uniform diffusion distribution of current after flowing through the JFET region. The second base region 140 can have a high concentration of uniform doping distribution and a deeper junction depth. The first base region 130 and the second base region 140 also differ in their lateral (X) width. This design can optimize the on-resistance and breakdown voltage characteristics of the gate transistor, which is beneficial to improving the on-resistance and breakdown voltage characteristics of the gate transistor.

[0039] Based on the single-side gate design of the gate-controlled transistor, the gate electrode 152 of the gate-controlled transistor does not require precise control of the gate alignment, nor does it require strict requirements on the position and height of the gate electrode 152. The gate electrode 152 is formed on the gate dielectric layer 151, and the size of the gate electrode 152 can be reasonably adjusted according to the product requirements.

[0040] As described above, based on the cell layout structure design of the gate-controlled transistor (GMT) with a single-sided channel, a single-sided gate, and an asymmetric base region, the manufacturing process complexity of the GMT in this embodiment is reduced. Specifically, the manufacturing process of the GMT does not have high requirements for photolithography overlay precision and ion implantation uniformity. Minor process deviations have little impact on the fluctuation of the electrical parameters of the GMT, and it can be manufactured using current mature processes without the need for complex self-aligned processes. This improves the manufacturing yield and consistency of the GMT, and is beneficial for achieving synergistic optimization of the GMT's conduction characteristics, switching speed, and reliability while maintaining low on-resistance.

[0041] Furthermore, since the gate electrode 152 is disposed above the first base region 130 on one side, the gate-controlled transistor transmits current only through the inversion channel formed by the first base region 130 when it is in the on state. On the other side, the second base region 140 is designed with a specific geometry and doping distribution. For example, the boundary between the second base region 140 and the JFET region is designed as a protruding structure 141 or a unique beak-shaped structure 141A. Based on this asymmetric base region design, the shape of the boundary between the second base region 140 and the JFET region matches the current density distribution of the gate-controlled transistor when it is in the on state. This allows the gate-controlled transistor to effectively protect the gate dielectric layer 151 through charge coupling effect when it is in the depletion state, reducing the peak electric field intensity of the gate dielectric layer 151 and improving the reliability of the gate dielectric layer 151. This can improve the on-resistance, switching speed, and reliability of the gate-controlled transistor while ensuring its high withstand voltage capability, achieving synergistic optimization of the gate-controlled transistor's conduction characteristics, switching characteristics, and gate oxide reliability.

[0042] Furthermore, the beak-shaped structure 141A at the junction of the second base region 140 and the JFET region simplifies the cell layout of the gate-controlled transistor, reduces the cell spacing, and alleviates current congestion in the JFET region of the gate-controlled transistor through current path reconfiguration. More importantly, under high-voltage blocking conditions, the beak-shaped structure 141A can "shield" the edge electric field of the gate dielectric layer 151 through charge coupling effect, avoiding the formation of high electric field concentration in the gate dielectric layer 151. This prevents the gate dielectric layer 151 from being locally broken down or degraded, without introducing additional process steps or sacrificing conduction performance. It can directly and fundamentally improve the gate oxide reliability and enhance the reliability of the gate-controlled transistor.

[0043] refer to Figure 1 and Figure 2 As shown, the optional first base region 130 includes a first injection region 131 and a second injection region 132, and the second base region 140 includes a third injection region 142. Along the first direction X, the first injection region 131 and the third injection region 142 are located on both sides of the second injection region 132. The first injection region 131 and the second injection region 132 are close to the side of the first base region 130 away from the second base region 140, and the third injection region 142 is close to the side of the second base region 140 away from the first base region 130. The first injection region 131 and the second injection region 132 have different conductivity types, and the first injection region 131 and the third injection region 142 have the same conductivity type. The gate dielectric layer 151 is in contact with the first sub-base region 133 in the first base region 130 and is in contact with the second injection region 132. The first sub-base region 133 is the base region region in the first base region 130 other than the first injection region 131 and the second injection region 132.

[0044] In this embodiment, ion implantation is performed on multiple specific regions of the first base region 130 to form a first implantation region 131 and a second implantation region 132 arranged along the first direction X. The first implantation region 131 and the second implantation region 132 can be in contact. The first implantation region 131 and the second implantation region 132 are located on the side of the first base region 130 away from the second base region 140, and the first implantation region 131 is located on the side of the second implantation region 132 away from the second base region 140. Ion implantation is then performed on a specific region of the second base region 140 to form a third implantation region 142, which is located on the side of the second base region 140 away from the first base region 130. That is, the first implantation region 131 and the third implantation region 142 are located on opposite sides of the second implantation region 132 along the first direction X. The first implantation region 131 and the second implantation region 132 have different conductivity types, while the first implantation region 131 and the third implantation region 142 have the same conductivity type.

[0045] As described above, the optional first epitaxial layer 120 has a first conductivity type, the first base region 130 has a second conductivity type, and the second base region 140 has a second conductivity type. Correspondingly, a first injection region 131 of the first conductivity type is embedded on the upper surface of the first base region 130, a second injection region 132 of the second conductivity type is also embedded on the upper surface of the first base region 130, and a third injection region 142 of the second conductivity type is embedded on the upper surface of the second base region 140. One of the first conductivity type and the second conductivity type is N-type and the other is P-type. The second injection region 132 can also be defined as a top injection region of the first conductivity type, and the first injection region 131 and the third injection region 142 can also be defined as short-circuit injection regions of the second conductivity type.

[0046] In this embodiment, the gate dielectric layer 151 is in contact with the first sub-base region 133 in the first base region 130 and also with the second implantation region 132. Along the Y direction, the gate electrode 152 overlaps with the first sub-base region 133 in the first base region 130 and partially overlaps with the second implantation region 132. In this embodiment, the first sub-base region 133 of the first base region 130 is neither the first implantation region 131 nor the second implantation region 132. Rather, the base region of the first base region 130 excluding the first implantation region 131 and the second implantation region 132 is the first sub-base region 133 of the first base region 130. Similarly, the base region of the second base region 140 excluding the third implantation region 142 is the second sub-base region 143 of the second base region 140.

[0047] The upper surface of the second injection region 132 and the upper surface of the first sub-base region 133 of the first base region 130 are flush. The gate dielectric layer 151 is in contact with the upper surface of the first sub-base region 133 in the first base region 130, and the gate dielectric layer 151 is also in contact with the upper surface of the second injection region 132. The upper surface of the film or region refers to the side of the film or region facing away from the substrate 110. Specifically, along the second direction Y, the gate dielectric layer 151 covers the first sub-base region 133 and partially covers the second injection region 132. That is, the width of the gate dielectric layer 151 along the X direction is greater than the width of the upper surface of the first sub-base region 133 along the X direction, and the width of the gate electrode 152 along the X direction is greater than the width of the upper surface of the first sub-base region 133 along the X direction. Therefore, the gate-controlled transistor in the on state will form a reverse conductive channel in the first base region 130, realizing the flow of current through the gate-controlled transistor.

[0048] Optionally, the first epitaxial layer 120 may further include a junction field-effect transistor (JFET) region located between the first base region 130 and the second base region 140; the gate dielectric layer 151 is in contact with the JFET region. Optionally, along the first direction X, the width D3 of the region where the gate dielectric layer 151 contacts the first base region 130 is greater than the width D4 of the region where the gate dielectric layer 151 contacts the JFET region.

[0049] In this embodiment, along the second direction Y, the gate dielectric layer 151 contacts the second implantation region 152, the first sub-base region 133, and the JFET region. The upper surfaces of the second implantation region 132, the first sub-base region 133, and the JFET region are flush. Along the Y direction, the gate electrode 152 overlaps with the second implantation region 152, the first sub-base region 133, and the JFET region. The width of the contact area between the gate dielectric layer 151 and the JFET region along the X direction is D4, and the width of the contact area between the gate dielectric layer 151 and the first base region 130 along the X direction is D3, where D3 is greater than D4. In other words, in the gate-controlled transistor, the width D4 of the contact area between the gate dielectric layer 151 and the JFET region is small, while the width D3 of the contact area between the gate dielectric layer 151 and the first base region 130 is large. This can reduce the overlap area between the gate electrode 152 and the drain in the gate-controlled transistor, thereby reducing parasitic capacitance and improving the conduction and switching performance of the gate-controlled transistor.

[0050] Based on the same inventive concept, embodiments of the present invention provide a method for fabricating a gate-controlled transistor, used to fabricate the gate-controlled transistor described in any embodiment of the present invention. Figure 3 This is a schematic diagram of a method for fabricating a gate-controlled transistor according to an embodiment of the present invention. Figure 4 This is a schematic diagram of another method for fabricating a gate-controlled transistor provided in an embodiment of the present invention, as shown below. Figure 3 and Figure 4 The fabrication method of the gate-controlled transistor shown includes: Step 210: Provide a substrate; Step 220: Form a first epitaxial layer on one side of the substrate; Step 230: Form a first base region and a second base region in the first epitaxial layer; Step 240: A gate dielectric layer and a gate electrode are sequentially formed on the side of the first epitaxial layer away from the substrate. The gate dielectric layer is in contact with the first base region but not with the second base region. The gate electrode overlaps with the first base region but not with the second base region along the second direction.

[0051] The optional step 230, which involves forming the first base region and the second base region in the first epitaxial layer, includes: Step 231: Implant a second type of conductivity impurity into the first epitaxial layer using an ion implantation process to form a first base region; Step 232: Using a beak-shaped mask, a second type of conductivity impurity is implanted into the first epitaxial layer through an ion implantation process to form a second base region. The side of the second base region closest to the first base region has a beak-shaped structure. The doping concentration of the first base region is different from that of the second base region.

[0052] The optional step 230, which involves forming the first base region and the second base region in the first epitaxial layer, includes: Step 233: Implant impurities of a first conductivity type into the first base region using an ion implantation process to form a second implantation region of the first base region; Step 234: Implant impurities of a second conductivity type into the first base region and the second base region respectively by ion implantation process to form a first implantation region of the first base region and a third implantation region of the second base region. The first implantation region and the third implantation region are located on both sides of the second implantation region along the first direction.

[0053] Option step 240, which involves sequentially forming a gate dielectric layer and a gate electrode on the side of the first epitaxial layer facing away from the substrate, includes: Step 241: Form a gate dielectric layer on the first sub-base region, the second injection region, and the junction field-effect region of the first base region. The junction field-effect region is located between the first base region and the second base region. The first sub-base region is the base region region in the first base region other than the first injection region and the second injection region. Step 242: Form a gate electrode on the gate dielectric layer.

[0054] Here Figure 2 The diagram shows a disassembled version of the gate-controlled transistor, illustrating the fabrication process.

[0055] Figure 5 This is a schematic diagram of the substrate and the first epitaxial layer provided in an embodiment of the present invention. Figure 5As shown, the gate-controlled transistor includes a substrate 110 and a first epitaxial layer 120 stacked along the Y direction. The conductivity type of the substrate 110 and the first epitaxial layer 120 is selected according to the type of the gate-controlled transistor. For unipolar transistors such as MOSFETs, a substrate of the first conductivity type (e.g., N-type) is selected; for bipolar transistors such as IGBTs, a substrate of the second conductivity type (e.g., P-type) is selected. The thickness and conductivity type of the substrate 110, as well as the impurity doping concentration, can be reasonably designed. For example, the thickness of the substrate 110 can range from 300 μm to 500 μm, and the doping concentration range can be 1 × 10⁻⁶. 18 cm -3 Up to 5×10 19 cm -3 The first epitaxial layer 120 is disposed on the upper surface of the substrate 110. The thickness, conductivity type, and impurity doping concentration of the first epitaxial layer 120 can be reasonably designed. For example, the thickness of the first epitaxial layer 120 can range from 5 μm to 300 μm, and the doping concentration of the first epitaxial layer 120 can range from 1 × 10⁻⁶. 14 cm -3 Up to 5×10 16 cm -3 Taking a silicon carbide MOSFET as an example, a silicon carbide epitaxial layer is grown on a silicon carbide substrate using a chemical vapor deposition (CVD) process. The optional process conditions are: a temperature range of 1500°C to 1600°C, a pressure range of 100 mbar to 300 mbar, a hydrogen atmosphere, and a doping gas of trimethylaluminum (TMA) or ammonia.

[0056] Figure 6 This is a schematic diagram of the first base region provided in an embodiment of the present invention. For example... Figure 6 As shown, the gate-controlled transistor includes a first base region 130, which is embedded in the upper surface of a first epitaxial layer 120. The first base region 130 is located in the first epitaxial layer 120 and is close to the side of the first epitaxial layer 120 facing away from the substrate 110. Gradient doping is achieved by performing multiple ion implantations on the first epitaxial layer 120, where aluminum ions can be used for ion implantation. During these multiple ion implantations, impurities of different conduction types with different energies can be implanted. The surface doping concentration of the first base region 130 is low, the junction depth H1 of the first base region 130 is shallow, and the lateral width D1 of the first base region 130 is smaller than the width D2 of the second base region 140. The thickness and conduction type impurity doping concentration of the first base region 130 can be reasonably designed. For example, the junction depth H1 of the first base region 130 along the Y direction can range from 0.5 μm to 1 μm, the width D1 of the first base region 130 along the X direction can range from 2 μm to 5 μm, and the surface doping concentration of the first base region 130 can range from 1 × 10⁻⁶. 15 cm -3 Up to 1×10 17 cm -3Taking a silicon carbide MOSFET as an example of a gate-controlled transistor, a second conductivity type impurity is implanted into a specific region of the silicon carbide epitaxial layer through a high-temperature ion implantation process to form a first base region with a certain doping concentration distribution. Optional process conditions include: aluminum ion implantation in 3 to 5 stages, an energy range of 50 keV to 600 keV, and a dose range of 1 × 10⁻⁶. 13 cm -2 Up to 5×10 13 cm -2 .

[0057] Figure 7 This is a schematic diagram of the second base region provided in an embodiment of the present invention. Figure 7 As shown, the gate-controlled transistor includes a second base region 140 with a beak-like structure 141A. The second base region 140 is embedded in the upper surface of the first epitaxial layer 120. The second base region 140 is located in the first epitaxial layer 120 and is close to the side of the first epitaxial layer 120 facing away from the substrate 110. Uniform doping is achieved by performing multiple ion implantations on the first epitaxial layer 120, where aluminum ions can be used for ion implantation. During these multiple ion implantations, impurities of different second conductivity types can be implanted. The doping concentration of the second base region 140 is basically the same, and the junction depth H2 is relatively deep. The thickness and conductivity type impurity doping concentration of the second base region 140 can be reasonably designed. For example, the junction depth H2 of the second base region 140 along the Y direction ranges from 1.5 μm to 2.5 μm, the width D2 of the second base region 140 along the X direction ranges from 4 μm to 10 μm, and the surface doping concentration of the second base region 140 ranges from 1 × 10⁻⁶. 17 cm -3 Up to 1×10 19 cm -3 Specifically, a specific shaped implantation mask, such as a beak-shaped mask 201, can be used to form a second base region 140 with a beak-like geometry, i.e., a beak-shaped structure 141A. The epitaxial layer region between the first base region 130 and the second base region 140 constitutes the JFET region. Taking a silicon carbide MOSFET as an example, a beak-shaped mask is formed using grayscale photolithography or multi-step exposure, and the tip curvature radius and extension length are controlled. The beak-shaped mask region corresponding to the beak-like structure is thicker, while the beak-shaped mask regions corresponding to other regions of the second base region are thinner. A second conductivity type impurity is implanted into a specific region of the silicon carbide epitaxial layer using a high-temperature ion implantation process to form a second base region with a certain doping concentration distribution. The second base region has a beak-like structure. The optional process conditions are: energy range of 100keV to 800keV, and dose range of 5×10⁻⁶. 13 cm -2 Up to 1×10 14 cm -2 .

[0058] Figure 8 This is a schematic diagram of the second injection region provided in an embodiment of the present invention. Figure 8 As shown, the first base region 130 in the gate-controlled transistor includes a second injection region 132, which is a top injection region. The second injection region 132 is embedded in the upper surface of the first base region 130 and is located in the first base region 130, near the side of the first base region 130 facing away from the substrate 110. A first conductivity type impurity is implanted into the upper surface of the first base region 130 to form the second injection region 132. The thickness and conductivity type impurity doping concentration of the second injection region 132 can be reasonably designed; for example, the depth of the second injection region 132 along the Y direction can range from 0.2 μm to 0.5 μm, and the doping concentration range of the second injection region 132 can be 1 × 10⁻⁶. 19 cm -3 Up to 1×10 22 cm -3 Taking a silicon carbide MOSFET as an example of a gate-controlled transistor, a first type of conductivity impurity is implanted into a specific region of the first base region through a high-temperature ion implantation process to form the top implantation region, i.e., the second implantation region.

[0059] Figure 9 This is a schematic diagram of the first injection region and the third injection region provided in an embodiment of the present invention. Figure 9 As shown, the first base region 130 in the gate-controlled transistor further includes a first injection region 131, and the second base region 140 includes a third injection region 142. Both the first injection region 131 and the third injection region 142 are short-circuited injection regions. The first injection region 131 is located on the side of the second injection region 132 away from the second base region 140. The first injection region 131 is embedded in the upper surface of the first base region 130 and is located in the first base region 130 and close to the side of the first base region 130 away from the substrate 110. The third injection region 142 is embedded in the upper surface of the second base region 140 and is located in the second base region 140 and close to the side of the second base region 140 away from the substrate 110. The third injection region 142 is located in the second base region 140 and close to the side of the second base region 140 away from the first base region 130. A second conductivity type impurity is implanted on the upper surface of the first base region 130 to form the first injection region 131. A second conductivity type impurity is implanted on the upper surface of the second base region 140 to form the third injection region 142. The thickness, conductivity type, and impurity doping concentration of either the first implantation region 131 or the third implantation region 142 can be reasonably designed. The depth of either the first implantation region 131 or the third implantation region 142 along the Y direction ranges from 0.2 μm to 0.5 μm, and its doping concentration ranges from 1 × 10⁻⁶. 19 cm -3 Up to 1×10 22 cm -3The first base region 130 also includes a first sub-base region 133, a portion of which is located near the side of the first base region 130 facing the second base region 140. The second base region 140 also includes a second sub-base region 143, a portion of which is located near the side of the second base region 140 facing the first base region 130. Taking a silicon carbide MOSFET as an example, a second type of impurity is implanted into specific regions of the first base region and specific regions of the second base region using a high-temperature ion implantation process to form a first implantation region and a third implantation region. Optional process conditions include high-temperature annealing in an argon atmosphere at a temperature range of 1600°C to 1800°C to activate impurity atoms and repair lattice damage.

[0060] Figure 10 This is a schematic diagram of the gate dielectric layer provided in an embodiment of the present invention. Figure 10 As shown, the gate structure 150 in the gate-controlled transistor includes a gate dielectric layer 151, which is formed on the upper surface of the first base region 130 by thermal oxidation or chemical vapor deposition. Along the X direction, the width of the gate dielectric layer 151 is greater than the width of the upper surface of the first sub-base region 133 in the first base region 130, so that the gate dielectric layer 151 can also cover the contact portion JFET region and the second implantation region 132. Specifically, the thickness of the gate dielectric layer 151 along the Y direction ranges from 10 nm to 300 nm, and the diameter (D4) ranges from 0.1 μm to 2 μm. Taking a silicon carbide MOSFET as an example, the gate dielectric layer is formed on the upper surface of the silicon carbide epitaxial layer by thermal oxidation or chemical vapor deposition. Optional thermal oxidation process conditions are: a temperature range of 1100°C to 1300°C, thermal oxidation in an O2 oxygen atmosphere, and the material of the gate dielectric layer can be SiO2 or Al2O3.

[0061] Figure 11 This is a schematic diagram of the gate electrode and interlayer dielectric layer provided in an embodiment of the present invention. Figure 11 As shown, the gate structure 150 in the gate-controlled transistor also includes a gate electrode 152 and an interlayer dielectric layer 153. The gate electrode 152 is disposed on the upper surface of the gate dielectric layer 151, and the thickness of the gate electrode 152 ranges from 0.1 μm to 1 μm. The interlayer dielectric layer 153 is disposed outside the gate electrode 152, covering the gate electrode 152 and part of the first epitaxial layer 120. The interlayer dielectric layer 153 is used to isolate the gate electrode 152 and the first electrode 160, and the thickness of the interlayer dielectric layer 153 ranges from 0.1 μm to 2 μm, thereby achieving surface passivation of the gate-controlled transistor. Taking a silicon carbide MOSFET as an example, a gate material is grown on the upper surface of the gate dielectric layer to form the gate electrode. The material of the gate electrode can be polysilicon or metallic Ni. An interlayer dielectric layer is grown outside the gate electrode. The material of the interlayer dielectric layer can be SiO2 or SiN. The interlayer dielectric layer is used to isolate the gate electrode from the first electrode, and the interlayer dielectric layer is patterned by photolithography.

[0062] refer to Figure 2 As shown, the gate-controlled transistor also includes a first electrode 160 and a second electrode 170. The first electrode 160 is disposed on the upper surface of the first epitaxial layer 120 and is in contact with the first implantation region 131, the second implantation region 132, and the third implantation region 142. The thickness of the first electrode 160 ranges from 1 μm to 5 μm. The second electrode 170 is disposed on the lower surface of the substrate 110, and the thickness of the second electrode 170 ranges from 1 μm to 5 μm. Taking a silicon carbide MOSFET as an example, an ohmic contact layer is grown on the outside of the interlayer dielectric layer and an ohmic contact layer is grown on the lower surface of the substrate. The ohmic contact layer can be a multilayer stacked structure of Ti / Al / Ni / Au. The ohmic contact is formed by heat treatment using an annealing process. An electrode layer is grown on the upper surface of the ohmic contact of the interlayer dielectric layer to form the first electrode. An electrode layer is grown on the surface of the ohmic contact of the substrate to form the second electrode. This results in an asymmetric planar silicon carbide gate-controlled transistor.

[0063] The fabrication method provided in the embodiments of the present invention can be used to fabricate the gate-controlled transistor provided in any embodiment of the present invention.

[0064] This invention also provides a semiconductor device comprising a plurality of cells, wherein the cells may be gate-controlled transistors as described in any embodiment of this invention. Figure 12 This is a schematic diagram of a semiconductor device provided in an embodiment of the present invention, such as... Figure 12 As shown, the semiconductor device includes three gate-controlled transistors 100. The gate-controlled transistors 100 share a substrate 110, a first epitaxial layer 120, a first electrode 160, and a second electrode 170. The first base region 130 and the second base region 140 of two adjacent gate-controlled transistors 100 are in contact, and the first injection region 131 and the third injection region 142 of two adjacent gate-controlled transistors 100 are in contact. For example, three gate transistors 100 are sequentially labeled as 100(1), 100(2), and 100(3) along the X direction. The second base region 140 of gate transistor 100(1) is in contact with the first base region 130 of gate transistor 100(2), the second base region 140 of gate transistor 100(2) is in contact with the first base region 130 of gate transistor 100(3), the third injection region 142 of gate transistor 100(1) is in contact with the first injection region 131 of gate transistor 100(2), and the third injection region 142 of gate transistor 100(2) is in contact with the first injection region 131 of gate transistor 100(3).

[0065] As described above, in semiconductor devices and their gate-controlled transistors, the gate-controlled transistors employ an asymmetric layout design with a single-sided gate and a single-sided channel. This reduces the cell spacing and the width of the JFET region and the second base region 140 within the cell. Consequently, both the JFET region and the second base region can utilize smaller width parameters. Simultaneously, it optimizes the current flow path through the JFET region, mitigating the current crowding effect and avoiding the deterioration of conduction characteristics caused by reduced channel density. Furthermore, the asymmetric layout design of the gate-controlled transistor eliminates the need for channel symmetry, reducing the precision requirements for processes such as photolithography alignment and ion implantation. Moreover, the single-sided gate layout of the gate-controlled transistor covers only one side of the active channel, reducing the overlap area between the gate and source, and between the gate and drain. This lowers the gate-source capacitance, gate-drain capacitance, and parasitic capacitance of the semiconductor device, thereby reducing switching losses. On the other hand, a beak-shaped structure is formed at the junction of the second base region and the JFET region in the gate-controlled transistor. In the depletion state of the semiconductor device, a space charge region is formed through charge coupling effect, which can effectively protect the exposed gate dielectric layer, reduce the peak electric field intensity of the gate dielectric layer, and significantly improve the reliability of the gate dielectric layer. In the conduction state of the semiconductor device, it matches the actual current density distribution of the semiconductor device, which can avoid the problem of deterioration of the conduction characteristics of the semiconductor device.

[0066] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0067] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate-controlled transistor, characterized in that, include: Substrate; A first epitaxial layer is located on the substrate. The first epitaxial layer includes a first base region and a second base region arranged at intervals along a first direction. The first base region and the second base region are both close to the side of the first epitaxial layer away from the substrate. The first direction is parallel to the plane of the substrate. A gate structure is located on the side of the first epitaxial layer away from the substrate. The gate structure includes a gate dielectric layer and a gate electrode. The gate electrode is located on the side of the gate dielectric layer away from the substrate. The gate dielectric layer is in contact with the first base region but not with the second base region. Along a second direction, the gate electrode overlaps with the first base region but not with the second base region. The second direction is perpendicular to the plane of the substrate.

2. The gate-controlled transistor according to claim 1, characterized in that, The first base region and the second base region are asymmetric base region structures.

3. The gate-controlled transistor according to claim 1, characterized in that, Along the first direction, the width of the first base region is less than or equal to the width of the second base region.

4. The gate-controlled transistor according to claim 1, characterized in that, Along the second direction, the depth of the first base region is less than or equal to the depth of the second base region.

5. The gate-controlled transistor according to claim 1, characterized in that, The second base region has a protruding structure on the side closest to the first base region.

6. The gate-controlled transistor according to claim 1, characterized in that, The second base region has a beak-like structure on the side closest to the first base region.

7. The gate-controlled transistor according to claim 1, characterized in that, The first base region includes a first injection region and a second injection region, and the second base region includes a third injection region. Along the first direction, the first injection region and the third injection region are located on both sides of the second injection region. The first injection region and the second injection region are close to the side of the first base region that is away from the second base region, and the third injection region is close to the side of the second base region that is away from the first base region. The first injection region and the second injection region have different conductivity types, and the first injection region and the third injection region have the same conductivity type. The gate dielectric layer is in contact with a first sub-base region in the first base region and with the second injection region. The first sub-base region is the base region in the first base region other than the first injection region and the second injection region.

8. The gate-controlled transistor according to claim 1, characterized in that, The first epitaxial layer further includes a junction field-effect region located between the first base region and the second base region; The gate dielectric layer is in contact with the junction field-effect region.

9. The gate-controlled transistor according to claim 8, characterized in that, Along the first direction, the width of the region where the gate dielectric layer contacts the first base region is greater than the width of the region where the gate dielectric layer contacts the junction field-effect region.

10. A method for fabricating a gate-controlled transistor, characterized in that, The method for fabricating a gate-controlled transistor as described in any one of claims 1 to 9 comprises: Provide the substrate; The first epitaxial layer is formed on one side of the substrate; The first base region and the second base region are formed in the first epitaxial layer; The gate dielectric layer and the gate electrode are sequentially formed on the side of the first epitaxial layer away from the substrate. The gate dielectric layer is in contact with the first base region but not with the second base region. The gate electrode overlaps with the first base region but not with the second base region along the second direction.

11. The preparation method according to claim 10, characterized in that, The first base region and the second base region are formed in the first epitaxial layer, including: The first base region is formed by implanting a second type of conductivity impurity into the first epitaxial layer using an ion implantation process. Using a beak-shaped mask, a second type of conductivity impurity is implanted into the first epitaxial layer through an ion implantation process to form the second base region. The side of the second base region closest to the first base region has a beak-shaped structure. The doping concentration of the first base region is different from that of the second base region.

12. The preparation method according to claim 10, characterized in that, The first base region and the second base region are formed in the first epitaxial layer, including: A first type of impurity is implanted into the first base region by ion implantation process to form a second implantation region of the first base region; Impurities of a second conductivity type are implanted into the first base region and the second base region respectively by ion implantation process to form a first implantation region of the first base region and a third implantation region of the second base region. The first implantation region and the third implantation region are located on both sides of the second implantation region along the first direction.

13. The preparation method according to claim 12, characterized in that, The gate dielectric layer and the gate electrode are sequentially formed on the side of the first epitaxial layer opposite to the substrate, including: The gate dielectric layer is formed on the first sub-base region, the second injection region, and the junction field-effect region of the first base region. The junction field-effect region is located between the first base region and the second base region. The first sub-base region is the base region region of the first base region other than the first injection region and the second injection region. The gate electrode is formed on the gate dielectric layer.

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