Semiconductor device fabrication method including dummy gate fabrication
By modifying and reducing the gate oxide layer, the damage to the gate oxide layer caused by wet etching was solved, ensuring the smooth progress of device electrical performance and film preparation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- HANGZHOU HFC SEMICONDUCTOR CO
- Filing Date
- 2026-04-16
- Publication Date
- 2026-07-10
AI Technical Summary
Wet etching can cause etching damage to the gate oxide layer when removing dummy gate patterns, resulting in uneven thickness and affecting the electrical performance of the device.
By modifying the hydrophilic surface of the gate oxide layer to a hydrophobic surface to form a pseudo-gate pattern, the hydrophobic surface is then reduced to a hydrophilic surface to prevent the etching solution from contacting and removing the pseudo-gate pattern, thus protecting the integrity of the gate oxide layer.
This effectively prevents etching damage to the gate oxide layer, ensures the electrical performance of the device, and facilitates the preparation of subsequent film layers.
Smart Images
Figure CN122373435A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for manufacturing a semiconductor device including dummy gate fabrication. Background Technology
[0002] In the fabrication process of semiconductor devices, when wet etching is used to remove the film layer on the gate oxide layer, the etching solution of the wet etching process will cause etching damage to the gate oxide layer, resulting in changes in the thickness of the gate oxide layer and uneven thickness of the gate oxide layer, which will affect the electrical performance of the device.
[0003] Figure 1 This is a top view of a corresponding step in a prior art method for fabricating a semiconductor device. Figure 2 and Figure 3 This is a cross-sectional schematic diagram of a corresponding step in a prior art method for fabricating a semiconductor device, wherein... Figure 2 for Figure 1 A schematic cross-sectional view along section line A1A2. Figure 1 To clearly display the shallow groove 20 below the pseudo-grid pattern 40, a certain degree of transparency is set for the pseudo-grid pattern 40 above the shallow groove 20, and the length of the shallow groove 20 is exemplarily made to exceed the length of the pseudo-grid pattern 40 to facilitate its display. Please refer to... Figure 1 and Figure 2 A substrate 10 is provided, in which shallow trenches 20 are formed, and the lower part of the shallow trenches 20 is filled with an isolation medium 22; a gate oxide layer 30 is formed on the surface of the substrate 10 and the upper sidewalls of the shallow trenches 20, and a plurality of dummy gate patterns 40 are formed and the gate oxide layer 30 exposes a plurality of locations, the plurality of locations being the openings 41 in the figure. Please refer to Figure 3 Epitaxial trenches 61 are formed in the substrate 10 at locations corresponding to the exposed gate oxide layer 30, and an epitaxial layer 62 is formed in the epitaxial trenches 61 to serve as the source / drain region of the device. An intermediate dielectric layer 52 and sidewalls 51 are formed above the substrate 10 at the locations corresponding to the source / drain regions. Then, wet etching is used to remove the dummy gate pattern 40. During wet etching to remove the dummy gate pattern 40, over-etching occurs, and the etching solution directly contacts the gate oxide layer 30, causing etching damage to the gate oxide layer 30 and resulting in changes in the thickness of the gate oxide layer 30 (e.g., ...). Figure 3 The thickness of the gate oxide layer 30 is thinner at the dotted frame, and the etching process results in uneven thickness (poor thickness uniformity). Damage to the gate oxide layer 30 will affect the electrical performance of the device. Summary of the Invention
[0004] The purpose of this invention is to provide a method for fabricating a semiconductor device including dummy gate fabrication, which prevents damage to the gate oxide layer and ensures the electrical performance of the device.
[0005] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device including dummy gate fabrication, comprising:
[0006] A substrate is provided in which a shallow trench isolation structure is formed;
[0007] A gate oxide layer is formed on the surface of the substrate;
[0008] The hydrophilic surface of the gate oxide layer is modified to become a hydrophobic surface;
[0009] Several pseudo-gate patterns are formed on the hydrophobic surface of the gate oxide layer, and the gate oxide layer is exposed at several locations;
[0010] The hydrophobic surface of the gate oxide layer exposed at several locations is reduced to a hydrophilic surface;
[0011] At the location corresponding to the gate oxide layer that has been converted to a hydrophilic surface, a source / drain region is formed in the substrate using an epitaxial method;
[0012] An intermediate dielectric layer is formed over the substrate corresponding to the source / drain region locations; and,
[0013] Remove the pseudo-gate pattern and perform a reduction process on the hydrophobic surface of the gate oxide layer corresponding to the pseudo-gate pattern to transform it into a hydrophilic surface.
[0014] Optionally, the hydrophilic surface of the gate oxide layer can be modified using a TMS solution.
[0015] Optionally, the concentration of the TMS solution is 0.5% to 5%, the temperature of the TMS solution is 25°C to 40°C, and the modification treatment time is 5 min to 10 min.
[0016] Optionally, the hydrophilic surface of the gate oxide layer has -OH groups, and the hydrophobic surface of the gate oxide layer has -Si(CH3)3 groups.
[0017] Optionally, the hydrophobic surface of the gate oxide layer at several exposed locations may be reduced using oxygen plasma, ozone solution, or SPM solution.
[0018] Optionally, the hydrophobic surface of the gate oxide layer at several exposed locations is bombarded with oxygen plasma in a plasma cleaner to perform a reduction treatment. The applied power of the plasma cleaner is 50W~500W, the applied pressure of the plasma cleaner is 0.1 Torr~1 Torr, and the reduction treatment time is 10s~5min.
[0019] Optionally, the concentration of the ozone solution is 20ppm to 30ppm, the temperature of the ozone solution is 20℃ to 30℃, and the reduction treatment time is 5min to 10min.
[0020] Optionally, the ratio of sulfuric acid to hydrogen peroxide in the SPM solution is 2:1 to 8:1, the temperature of the SPM solution is 120℃ to 200℃, and the reduction treatment time is greater than 10 minutes.
[0021] Optionally, the pseudo-gate pattern is removed by wet etching, wherein the etching solution used for wet etching includes ammonia or TMAH solution.
[0022] Optionally, the concentration of the ammonia water is 2% to 20%, and the concentration of the TMAH solution is 2% to 3%.
[0023] In the semiconductor device fabrication method including dummy gate fabrication provided by the present invention, the hydrophilic surface of the gate oxide layer is first modified to become a hydrophobic surface to form several dummy gate patterns and expose several positions of the gate oxide layer. Then, the hydrophobic surface of the exposed gate oxide layer is reduced to become a hydrophilic surface, which facilitates the formation of source / drain regions in the substrate at the positions of the gate oxide layer corresponding to the hydrophilic surface. Then, the dummy gate patterns are removed to expose the unreduced hydrophobic surface of the gate oxide layer. Since the gate oxide layer corresponding to the dummy gate pattern has a hydrophobic surface, the hydrophobic surface will repel the etching solution, making it difficult for the etching solution to stay on the hydrophobic surface. In the process of removing the dummy gate pattern, etching damage to the gate oxide layer can be prevented, thereby ensuring the electrical performance of the device. Furthermore, the reduction treatment of the hydrophobic surface of the gate oxide layer corresponding to the dummy gate pattern to become a hydrophilic surface is also beneficial to the subsequent film preparation. Attached Figure Description
[0024] Figure 1 This is a top view of a corresponding step in a method for fabricating a semiconductor device in the prior art.
[0025] Figure 2 and Figure 3 This is a cross-sectional schematic diagram of a corresponding step in a semiconductor device fabrication method in the prior art.
[0026] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor device including dummy gate fabrication, as provided in an embodiment of the present invention.
[0027] Figures 5-13 This is a cross-sectional schematic diagram of a corresponding step in a semiconductor device fabrication method including dummy gate fabrication, provided in an embodiment of the present invention.
[0028] in, Figures 1-3 The attached figures are labeled as follows:
[0029] 10-Substrate; 20-Shallow trench; 22-Isolation dielectric; 30-Gate oxide layer; 40-Dummy gate pattern; 41-Opening; 51-Sidewall; 52-Intermediate dielectric layer; 61-Epipolar groove; 62-Epipolar layer.
[0030] Figures 5-13 The attached figures are labeled as follows:
[0031] 100 - Substrate; 200 - Shallow trench; 220 - Isolation dielectric; 300 - Gate oxide layer; 400 - Pseudo-gate pattern; 410 - Opening; 510 - Sidewall; 520 - Intermediate dielectric layer; 610 - Epitaxial trench; 620 - Epitaxial layer. Detailed Implementation
[0032] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. The accompanying drawings are all in a very simplified form and are not drawn to scale, only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structures; in particular, different proportions are sometimes used because different drawings need to show different focuses.
[0033] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.
[0034] In the description of this application, it should be understood that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product is in use, or the orientation or positional relationship commonly understood by those skilled in the art. They are used only for the convenience of describing this application and simplifying the description, and are not intended to indicate or imply that the equipment or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.
[0035] Furthermore, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes said element. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.
[0036] Figure 4 This is a flowchart illustrating a semiconductor device fabrication method including dummy gate fabrication provided in this embodiment. Please refer to... Figure 4 This embodiment provides a method for fabricating a semiconductor device including dummy gate fabrication, comprising:
[0037] Step S1: Provide a substrate in which a shallow trench isolation structure is formed;
[0038] Step S2: Form a gate oxide layer on the surface of the substrate;
[0039] Step S3: Modify the hydrophilic surface of the gate oxide layer to transform it into a hydrophobic surface;
[0040] Step S4: Form several pseudo-gate patterns on the hydrophobic surface of the gate oxide layer and expose the gate oxide layer at several locations;
[0041] Step S5: Reduce the hydrophobic surface of the gate oxide layer at several exposed locations to transform it into a hydrophilic surface;
[0042] Step S6: At the location corresponding to the gate oxide layer that has been converted to a hydrophilic surface, a source / drain region is formed in the substrate using an epitaxial method;
[0043] Step S7: Form an intermediate dielectric layer on the substrate corresponding to the source / drain region location;
[0044] Step S8: Remove the pseudo-gate pattern and perform a reduction process on the hydrophobic surface of the gate oxide layer corresponding to the pseudo-gate pattern to transform it into a hydrophilic surface.
[0045] Figures 5-13 This is a cross-sectional schematic diagram of a corresponding step in the semiconductor device fabrication method including dummy gate fabrication provided in this embodiment. The following is in conjunction with... Figures 5-13 The method for fabricating a semiconductor device including the fabrication of a dummy gate provided in this embodiment will be described in detail.
[0046] Execution step S1: Please refer to Figure 5 A substrate 100 is provided, preferably a silicon substrate, and the substrate 100 includes an active region (not shown in the figure). A plurality of shallow trenches 200 are formed in the substrate 100 using a photolithography process (only one shallow trench 200 is shown in the figure); then, an isolation medium 220 is filled in the lower part of the shallow trenches 200 to form a shallow trench isolation structure.
[0047] Execution step S2: Please continue to refer to Figure 5 A gate oxide layer 300 is formed by oxidizing the surface of the substrate 100 and the upper sidewall of the shallow trench 200 using a thermal oxidation process. At this time, the gate oxide layer 300 has a hydrophilic surface, which refers to a surface with the property of attracting water molecules. Its molecular structure allows water molecules to adhere tightly to the surface, so the hydrophilic surface easily attracts the subsequent etching solution. The material of the gate oxide layer 300 can be silicon oxide, and the thickness of the gate oxide layer 300 can be 3nm~5nm, not limited to this thickness.
[0048] Execution step S3: Please refer to Figure 6 The hydrophilic surface of the gate oxide layer 300 is modified to transform it into a hydrophobic surface. To clearly illustrate this transformation in the figures, the darker areas on the gate oxide layer 300 represent its hydrophobic surface. In this embodiment, a TMS solution, specifically a trimethylsilyl ether solution, is used to modify the hydrophilic surface of the gate oxide layer 300. The concentration of the TMS solution can be 0.5% to 5%, the temperature can be 25°C to 40°C, and the immersion time of the hydrophilic surface of the gate oxide layer 300 in the TMS solution for modification can be 5 min to 10 min, but is not limited to these parameters.
[0049] Please refer to Figure 7 , Figure 7 This diagram illustrates the transformation of the hydrophilic surface of the gate oxide layer 300 into a hydrophobic surface. The hydrophilic surface of the gate oxide layer 300 contains hydrophilic -OH groups. After modification, the hydrophilic surface of the gate oxide layer 300 is transformed into a hydrophobic surface, containing hydrophobic -Si(CH3)3 groups. That is, the hydrophilic -OH groups on the surface of the gate oxide layer 300 are replaced by hydrophobic -Si(CH3)3 groups. During TMS solution treatment, ammonia gas is generated as a byproduct (which is removed). The hydrophobic surface repels water molecules, making it difficult for them to remain on it, thus repelling subsequent etching solutions. The contact angle of the gate oxide layer 300 surface treated with TMS solution can be increased from 24° to 90°, significantly increasing the hydrophobicity of the gate oxide layer 300 surface.
[0050] Execution step S4: Please refer to Figure 8 Several pseudo-gate patterns 400 are formed on the hydrophobic surface of the gate oxide layer 300. Specifically, some pseudo-gate patterns 400 are located above the shallow trench 200 and above the surface of the gate oxide layer 300 (in the figure, the pseudo-gate patterns 400 can also extend to the gate oxide layer 300 on the sidewall of the shallow trench 200). Some pseudo-gate patterns 400 are located on the gate oxide layer 300 and expose the gate oxide layer 300 at several locations. Several locations are the openings 410 in the figure. That is, there are openings 410 between adjacent pseudo-gate patterns 400 that expose part of the gate oxide layer 300. The gate oxide layer 300 exposed at the bottom of the opening 410 has a hydrophobic surface. The material of the pseudo-gate patterns 400 can be polycrystalline silicon.
[0051] Execution step S5: Please refer to Figure 9 Since the hydrophobic surface of the gate oxide layer 300 is not conducive to the deposition of the film, it is necessary to reduce the hydrophobic surface of the gate oxide layer 300 at some exposed locations (opening 410 locations) to transform it into a hydrophilic surface (as shown in the dashed box in the figure, the disappearance of the dark part of the gate oxide layer 300 surface indicates that it has been reduced to a hydrophilic surface).
[0052] In this embodiment, oxygen plasma, ozone solution or SPM solution is used to reduce the hydrophobic surface of the gate oxide layer 300 at several exposed locations (opening 410 locations). Among them, oxygen plasma utilizes high-energy active oxygen generated by plasma to bombard and break the Si-C bonds and CH bonds on the surface of the gate oxide layer 300, oxidizing them into volatile products (CO2, H2O), thereby removing the hydrophobic -Si(CH3)3 groups on the surface of the gate oxide layer 300 and regenerating hydrophilic -OH groups. In a plasma cleaner, oxygen plasma is used to bombard the hydrophobic surface of the gate oxide layer 300 at several exposed positions (opening 410 positions) for reduction treatment. High-purity oxygen (purity reaching or exceeding 99.99%) is used, and a small amount of chlorine can be added to enhance the physical bombardment effect. The applied power of the plasma cleaner can be 50W~500W, and the applied pressure can be 0.1 Torr~1 Torr, or atmospheric pressure. In the plasma cleaner, oxygen is ionized into oxygen plasma. Under the action of an electric field, the oxygen plasma bombards the hydrophobic surface for reduction. The reduction treatment time can be 10s~5min, and the reduction treatment temperature can be room temperature (indoor ambient temperature).
[0053] The highly reactive atomic oxygen in the ozone solution oxidizes and decomposes the hydrophobic -Si(CH3)3 groups on the surface of the gate oxide layer 300, and regenerates the hydrophilic -OH groups. The concentration of the ozone solution can be 20ppm~30ppm, the temperature can be 20℃~30℃, and the reduction treatment time can be 5min~10min, but is not limited to these values. The SPM solution is a mixture of sulfuric acid and hydrogen peroxide. The strong oxidizing property of the SPM solution can oxidize and decompose the hydrophobic -Si(CH3)3 groups on the surface of the gate oxide layer 300, and generate hydrophilic -OH groups. The ratio of sulfuric acid to hydrogen peroxide in the SPM solution can be 2:1~8:1, the temperature can be 120℃~200℃, and in order to completely reduce the hydrophilicity, the treatment time of the SPM solution is usually greater than 10min, but is not limited to these values.
[0054] Alternatively, ultraviolet radiation can be used. Short-wave ultraviolet light (100nm~280nm) decomposes oxygen to produce ozone and atomic oxygen. The highly reactive atomic oxygen oxidizes and decomposes the hydrophobic -Si(CH3)3 groups on the surface of the gate oxide layer 300, regenerating hydrophilic -OH groups. In an ultraviolet ozone cleaner, ultraviolet lamps are used to irradiate and reduce the hydrophobic surface of the gate oxide layer 300 at several exposed locations (opening 410). Low-pressure mercury lamps with short-wave ultraviolet light of 184nm or 254nm are used, and the process is conducted in an air or oxygen environment. The distance between the gate oxide layer 300 surface and the ultraviolet lamp can be 1mm~10mm, and the irradiation time can be 5min~30min. No additional heating is required during ultraviolet radiation; however, the ultraviolet lamp generates some heat, which can raise the temperature of the irradiated object to 40℃~80℃. This reduction treatment does not cause a change in the thickness of the gate oxide layer 300.
[0055] Please refer to Figure 10 , Figure 10 This is a schematic diagram of the transformation of the hydrophobic surface of the gate oxide layer 300 into a hydrophilic surface. The hydrophobic surface of the gate oxide layer 300 has hydrophobic -Si(CH3)3 groups. After reduction treatment, the hydrophobic surface of the gate oxide layer 300 is transformed into a hydrophilic surface, and the hydrophilic surface of the gate oxide layer 300 has hydrophilic -OH groups. That is, the hydrophobic -Si(CH3)3 groups on the surface of the gate oxide layer 300 are replaced by hydrophilic -OH groups. The hydrophilic surface is conducive to the deposition of the film layer, and the sidewalls and intermediate dielectric layers are subsequently prepared in the opening.
[0056] Execution step S6: Please refer to Figure 11At the location corresponding to the gate oxide layer 300 that has been converted to a hydrophilic surface, a source / drain region is formed in the substrate 100 using an epitaxial method. Specifically, a sidewall 510 is first formed at the location corresponding to the gate oxide layer 300 that has been converted to a hydrophilic surface (i.e., the sidewall of the opening 410). Then, the gate oxide layer 300 and the substrate 100 at the location corresponding to the gate oxide layer 300 that has been converted to a hydrophilic surface (i.e., below the opening 410) are etched to form an epitaxial trench 610. An epitaxial layer 620 is then grown in the epitaxial trench 610 using an epitaxial method. The epitaxial layer 620 serves as the source / drain region of the device, thereby realizing the formation of the source / drain region in the substrate 100 using an epitaxial method. The top surface of the epitaxial layer 620 is flush with the surface of the gate oxide layer 300.
[0057] Execution step S7: Please continue to refer to Figure 11 An intermediate dielectric layer 520 is formed above the substrate 100 corresponding to the source / drain region, that is, the intermediate dielectric layer 520 is formed by filling the opening 410. The sidewall 510 can be made of silicon nitride, silicon oxynitride or ONO stack, the intermediate dielectric layer 520 can be made of silicon oxide, and the epitaxial layer 620 can be made of germanium silicon, but is not limited to these.
[0058] Execution step S8: Please refer to Figure 12 Wet etching is used to remove the dummy gate pattern 400 to expose the hydrophobic surface of the gate oxide layer 300 corresponding to the dummy gate pattern 400 (the dark part of the gate oxide layer 300 surface in the figure represents the hydrophobic surface of the gate oxide layer 300 that has not been reduced).
[0059] In this embodiment, the etching solution for wet etching to remove the dummy gate pattern 400 includes ammonia or TMAH (tetramethylammonium hydroxide) solution, wherein the concentration of ammonia can be 2%~20%, and the concentration of TMAH solution can be 2%~3%, for example 2.38%, but is not limited thereto. Since the gate oxide layer 300 corresponding to the dummy gate pattern 400 has a hydrophobic surface, the hydrophobic surface repels the etching solution during wet etching, making it difficult for the etching solution to remain on the hydrophobic surface of the gate oxide layer 300, thus preventing etching damage to the gate oxide layer 300, ensuring the integrity of the gate oxide layer 300, and thereby ensuring the electrical performance of the device.
[0060] Please refer to Figure 13Since etching away the dummy gate pattern 400 exposes the hydrophobic surface of the gate oxide layer 300 corresponding to the dummy gate pattern 400, and this hydrophobic surface is not conducive to the deposition of subsequent film layers, it is necessary to perform a reduction treatment on the hydrophobic surface of the gate oxide layer 300 corresponding to the dummy gate pattern 400 to transform it into a hydrophilic surface (as shown by the dashed box in the figure, the disappearance of the dark part of the gate oxide layer 300 surface indicates that it has been reduced to a hydrophilic surface). The reduction treatment method in this step is the same as the reduction treatment method in step S5. Please refer to the description of step S5. The reduction treatment will not cause a change in the thickness of the gate oxide layer 300. After reducing the hydrophobic surface of the gate oxide layer 300 corresponding to the dummy gate pattern 400 to a hydrophilic surface, the subsequent steps include fabricating a metal oxide layer and a metal gate (not shown in the figure) on the hydrophilic surface of the gate oxide layer 300.
[0061] In summary, in the semiconductor device fabrication method including dummy gate fabrication provided by this invention, the hydrophilic surface of the gate oxide layer is first modified to become a hydrophobic surface to form several dummy gate patterns and expose several locations of the gate oxide layer. Then, the hydrophobic surface of the exposed gate oxide layer is reduced to become a hydrophilic surface, which facilitates the formation of source / drain regions in the substrate at the locations of the gate oxide layer that have been converted to hydrophilic surfaces. Subsequently, the dummy gate patterns are removed to expose the unreduced hydrophobic surface of the gate oxide layer. Since the gate oxide layer corresponding to the dummy gate pattern has a hydrophobic surface, the hydrophobic surface will repel the etching solution, making it difficult for the etching solution to remain on the hydrophobic surface. During the removal of the dummy gate pattern, etching damage to the gate oxide layer can be prevented, thereby ensuring the electrical performance of the device. Furthermore, the reduction treatment of the hydrophobic surface of the gate oxide layer corresponding to the dummy gate pattern to become a hydrophilic surface also facilitates the subsequent preparation of film layers.
[0062] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.
Claims
1. A method for fabricating a semiconductor device including dummy gate fabrication, characterized in that, include: A substrate is provided in which a shallow trench isolation structure is formed; A gate oxide layer is formed on the surface of the substrate; The hydrophilic surface of the gate oxide layer is modified to become a hydrophobic surface; Several pseudo-gate patterns are formed on the hydrophobic surface of the gate oxide layer, and the gate oxide layer is exposed at several locations; The hydrophobic surface of the gate oxide layer exposed at several locations is reduced to a hydrophilic surface; At the location corresponding to the gate oxide layer that has been converted to a hydrophilic surface, a source / drain region is formed in the substrate using an epitaxial method; An intermediate dielectric layer is formed above the substrate corresponding to the source / drain region location; as well as, Remove the pseudo-gate pattern and perform a reduction process on the hydrophobic surface of the gate oxide layer corresponding to the pseudo-gate pattern to transform it into a hydrophilic surface.
2. The method for fabricating a semiconductor device including dummy gate fabrication as described in claim 1, characterized in that, The hydrophilic surface of the gate oxide layer was modified using a TMS solution.
3. The method for fabricating a semiconductor device including dummy gate fabrication as described in claim 2, characterized in that, The concentration of the TMS solution is 0.5%~5%, the temperature of the TMS solution is 25℃~40℃, and the modification treatment time is 5min~10min.
4. The method for fabricating a semiconductor device including dummy gate fabrication as described in claim 1, characterized in that, The hydrophilic surface of the gate oxide layer has -OH groups, and the hydrophobic surface of the gate oxide layer has -Si(CH3)3 groups.
5. The method for fabricating a semiconductor device including dummy gate fabrication as described in claim 1, characterized in that, The hydrophobic surfaces of the gate oxide layer at several exposed locations are reduced using oxygen plasma, ozone solution, or SPM solution.
6. The method for fabricating a semiconductor device including dummy gate fabrication as described in claim 5, characterized in that, The hydrophobic surface of the gate oxide layer at several exposed locations is reduced by bombarding it with oxygen plasma in a plasma cleaner. The applied power of the plasma cleaner is 50W~500W, the applied pressure of the plasma cleaner is 0.1Torr~1Torr, and the reduction treatment time is 10s~5min.
7. The method for fabricating a semiconductor device including dummy gate fabrication as described in claim 5, characterized in that, The concentration of the ozone solution is 20ppm to 30ppm, the temperature of the ozone solution is 20℃ to 30℃, and the reduction treatment time is 5min to 10min.
8. The method for fabricating a semiconductor device including dummy gate fabrication as described in claim 5, characterized in that, The ratio of sulfuric acid to hydrogen peroxide in the SPM solution is 2:1 to 8:1, the temperature of the SPM solution is 120℃ to 200℃, and the reduction treatment time is greater than 10 minutes.
9. The method for fabricating a semiconductor device including dummy gate fabrication as described in claim 1, characterized in that, The dummy gate pattern is removed by wet etching, wherein the etching solution for wet etching includes ammonia or TMAH solution.
10. The method for fabricating a semiconductor device including dummy gate fabrication as described in claim 9, characterized in that, The concentration of the ammonia water is 2% to 20%, and the concentration of the TMAH solution is 2% to 3%.