Semiconductor device

Abstract

Embodiments relate to a semiconductor device. A semiconductor device of an embodiment includes an element region and a terminal region surrounding the element region, and includes: a first electrode; a second electrode; a semiconductor portion provided between the first electrode and the second electrode; a plurality of third electrodes provided at least in the semiconductor portion in the element region; a gate electrode between the plurality of third electrodes; and a wiring layer between the semiconductor portion and the second electrode, extending from the element region to the terminal region, connected to the plurality of third electrodes in the element region, and connected to the second electrode in the terminal region.

Description

[0001] Related applications

[0002] This application enjoys priority based on Japanese Patent Application No. 2025-001898 (filed on January 6, 2025). This application incorporates the entire contents of the basic application by reference to that basic application. Technical Field

[0003] The implementation relates to a semiconductor device. Background Technology

[0004] There are known semiconductor devices in which multiple field plate electrodes are arranged in a dot-like pattern when viewed from above. Summary of the Invention

[0005] According to an embodiment, a semiconductor device includes a component region and an end region surrounding the component region. The semiconductor device includes: a first electrode; a second electrode; a semiconductor portion disposed between the first electrode and the second electrode; a plurality of third electrodes disposed at least within the semiconductor portion of the component region; a gate electrode located between the plurality of third electrodes; and a wiring layer located between the semiconductor portion and the second electrode, extending from the component region to the end region, connected to the plurality of third electrodes in the component region, and connected to the second electrode in the end region.

[0006] According to the embodiments, a semiconductor device capable of reducing noise can be provided. Attached Figure Description

[0007] Figure 1 and Figure 2 This is a schematic top view of the semiconductor device according to the first embodiment.

[0008] Figure 3 yes Figure 2 AA section view in the image.

[0009] Figure 4 yes Figure 2 BB section view in the middle.

[0010] Figure 5 yes Figure 1 CC section view in the image.

[0011] Figure 6 This is a schematic cross-sectional view of the semiconductor device according to the second embodiment.

[0012] Figure 7 This is a schematic cross-sectional view of the semiconductor device according to the third embodiment.

[0013] Figure 8 and Figure 9This is a schematic cross-sectional view of the semiconductor device according to the fourth embodiment.

[0014] Figure 10 This is a schematic top view of the semiconductor device according to the fifth embodiment.

[0015] Figures 11-16 This is a schematic top view of a semiconductor device as a variation of the embodiment.

[0016] Explanation of reference numerals in the attached figures

[0017] 1-5… Semiconductor device, 10… Semiconductor section, 11… First semiconductor layer, 12… Second semiconductor layer, 13… Third semiconductor layer, 14… Fourth semiconductor layer, 15… Fifth semiconductor layer, 21… First electrode, 22… Second electrode, 22A… Main section, 22B… Extension section, 30… Gate electrode, 40… Third electrode, 51… First insulating film, 52… Second insulating film, 53… Third insulating film, 60… Wiring layer, 71… First connection section, 72… Second connection section, 73… Third connection section, 74… Fourth connection section, 80… Gate wiring, 100… Component area, 200… Terminal area Detailed Implementation

[0018] Hereinafter, the embodiments will be described with reference to the accompanying drawings. Furthermore, in each drawing, the same reference numerals are used to label the same components. In each drawing, the direction along the X-axis is designated as the first direction X, the direction along the Y-axis as the second direction Y, and the direction along the Z-axis as the third direction Z. The first direction X, the second direction Y, and the third direction Z are orthogonal to each other. For example, the arrow direction along the Z-axis is designated as relatively upward, and the opposite direction of the arrow along the Z-axis is designated as relatively downward.

[0019] [First Implementation Method]

[0020] Figure 1 This is a schematic top view showing the configuration of the main components in the semiconductor device 1 of the first embodiment.

[0021] Semiconductor device 1 has a component region 100 and an end region 200. For example, in a top view, the end region 200 surrounds the component region 100. The end region 200 is located on the side 1C of the component region 100 and the semiconductor device 1 in a first direction X and a second direction Y. Figure 5 (as shown) between.

[0022] Figure 2 This is a schematic top view of a portion of the element region 100 of the semiconductor device 1. Figure 3 yes Figure 2 AA section view in the image. Figure 4 yes Figure 2 BB section view in the middle.

[0023] like Figure 3 as well as Figure 4 As shown, the semiconductor device 1 includes a first electrode 21, a second electrode 22, and a semiconductor section 10. The first electrode 21 and the second electrode 22 are located at positions separated in the third direction Z. Furthermore, in Figure 2 The illustration of the second electrode 22 is omitted in the text.

[0024] The semiconductor section 10 is located between the first electrode 21 and the second electrode 22 in the third direction Z. The semiconductor section 10 has a first surface 10A and a second surface 10B. The first surface 10A is opposite to the first electrode 21 in the third direction Z. The second surface 10B is located on the opposite side of the second surface 10A in the third direction Z and is opposite to the second electrode 22.

[0025] Silicon can be used as the material for the semiconductor section 10, for example. Alternatively, silicon carbide, gallium nitride, etc., can also be used as the material for the semiconductor section 10. In this embodiment, the first conductivity type is described as n-type and the second conductivity type is described as p-type in the semiconductor section 10, but the first conductivity type can also be described as p-type and the second conductivity type as n-type.

[0026] The semiconductor section 10 includes an n-type first semiconductor layer 11, a p-type second semiconductor layer 12 disposed on the first semiconductor layer 11, an n-type third semiconductor layer 13 disposed on the second semiconductor layer 12, and a p-type fourth semiconductor layer 14 disposed on the second semiconductor layer 12. The n-type impurity concentration of the third semiconductor layer 13 is higher than that of the first semiconductor layer 11. The p-type impurity concentration of the fourth semiconductor layer 14 is higher than that of the second semiconductor layer 12. Additionally, the semiconductor section 10 includes a fifth semiconductor layer 15 disposed between the first electrode 21 and the first semiconductor layer 11.

[0027] The semiconductor device 1 in this embodiment, for example, has a vertically oriented MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) structure. In the MOSFET, the first electrode 21 functions as the drain electrode, the second electrode 22 functions as the source electrode, the first semiconductor layer 11 functions as the drift layer, the second semiconductor layer 12 functions as the base layer, the third semiconductor layer 13 functions as the source layer, and the fifth semiconductor layer 15 functions as an n-type drain layer with a higher n-type impurity concentration than the first semiconductor layer 11.

[0028] Alternatively, the semiconductor device in this embodiment may also have a vertical IGBT (Insulated Gate Bipolar Transistor) structure. In the IGBT, the first electrode 21 functions as the collector electrode, the second electrode 22 functions as the emitter electrode, the first semiconductor layer 11 functions as the drift layer, the second semiconductor layer 12 functions as the base layer, the third semiconductor layer 13 functions as the emitter layer, and the fifth semiconductor layer 15 functions as the p-type collector layer. In the IGBT, an n-type buffer layer with a higher n-type impurity concentration than the first semiconductor layer 11 may also be provided between the fifth semiconductor layer 15 (collector layer) and the first semiconductor layer 11 (drift layer).

[0029] The fourth semiconductor layer 14 can easily discharge carriers to the second electrode 22 when turned off, for example.

[0030] The first electrode 21 is connected to the first surface 10A of the semiconductor layer 10. In this embodiment, the first electrode 21 is connected to and electrically connected to the fifth semiconductor layer 15.

[0031] The second electrode 22 is disposed on the second surface 10B of the semiconductor section 10 through the third insulating film 53 described later.

[0032] The semiconductor device 1 of the embodiment further includes a gate electrode 30 and a first insulating film (gate insulating film) 51. The gate electrode 30 extends downward from the second surface 10B of the semiconductor portion 10 and is located within the semiconductor portion 10. The lower end of the gate electrode 30 is located within the first semiconductor layer 11, which is below the pn junction of the second semiconductor layer 12 and the first semiconductor layer 11. As a material for the gate electrode 30, conductive polysilicon can be used, for example.

[0033] like Figure 2 As shown, the gate electrode 30 extends, for example, in the first direction X and the second direction Y. Figure 3 As shown, the second semiconductor layer 12 is positioned opposite the side of the gate electrode 30 in the second direction Y. Figure 4 As shown, the second semiconductor layer 12 is opposite to the side of the gate electrode 30 in the first direction X.

[0034] The first insulating film 51 is disposed between the gate electrode 30 and the semiconductor portion 10. The side of the gate electrode 30 is opposed to the second semiconductor layer 12 through the first insulating film 51.

[0035] The semiconductor device 1 in the embodiment also includes a third electrode 40 and a second insulating film 52.

[0036] The third electrode 40 is formed as a column extending downward from the second surface 10B of the semiconductor section 10 and is located within the semiconductor section 10. For example... Figure 1 As shown, in top view, a plurality of third electrodes 40 are arranged in the first direction X and the second direction Y. For example, in top view, the plurality of third electrodes 40 are arranged in a square grid in the first direction X and the second direction Y. The shape of the third electrodes 40 in top view is, for example, circular. The plurality of third electrodes 40 are disposed at least in the element region 100. Figure 1 In the example shown, a third electrode 40 is also provided in the end region 200.

[0037] like Figure 3 and Figure 4 As shown, the third electrode 40 does not reach the fifth semiconductor layer 15. The lower end of the third electrode 40 is located within the first semiconductor layer 11. The shortest distance in the third direction Z between the lower end of the third electrode 40 and the first electrode 21 is shorter than the shortest distance in the third direction Z between the lower end of the gate electrode 30 and the first electrode 21. As a material for the third electrode 40, for example, conductive polycrystalline silicon can be used.

[0038] The second insulating film 52 is disposed between the third electrode 40 and the semiconductor portion 10.

[0039] like Figure 2 As shown, when viewed from above, the gate electrode 30 is located between a plurality of third electrodes 40 and extends in the first direction X and the second direction Y.

[0040] like Figure 3 and Figure 4 As shown, the semiconductor device 1 in this embodiment also includes a third insulating film 53. The third insulating film 53 is disposed between the second surface 10B of the semiconductor portion 10 and the second electrode 22, between the upper surface of the gate electrode 30 and the second electrode 22, and between the third electrode 40 and the second electrode 22.

[0041] The semiconductor device 1 in this embodiment further includes a conductive first connection portion 71. The first connection portion 71 extends through a third insulating film 53 between the second electrode 22 and the second surface 10B of the semiconductor portion 10, connecting the second electrode 22 to the third semiconductor layer 13 and also connecting the second electrode 22 to the fourth semiconductor layer 14. The first connection portion 71 is, for example, in contact with the upper surface of the third semiconductor layer 13 and the upper surface of the fourth semiconductor layer 14. The third semiconductor layer 13 and the fourth semiconductor layer 14 are electrically connected to the second electrode 22 via the first connection portion 71. For example, the second electrode 22 and the first connection portion 71 are integrally formed from the same metallic material. The second electrode 22 and the first connection portion 71, for example, contain aluminum.

[0042] like Figure 2As shown, in top view, a third electrode 40 and two first connection portions 71 are disposed, for example, in a region surrounded by the gate electrode 30. The two first connection portions 71 are located at positions separated from each other in the second direction Y. A third electrode 40 is located between the two first connection portions 71 at the separated positions in the second direction Y.

[0043] In a region surrounded by the gate electrode 30, a fourth semiconductor layer 14 continuously surrounds the third electrode 40. A third semiconductor layer 13 continuously surrounds the fourth semiconductor layer 14.

[0044] The semiconductor device 1 in this embodiment also includes a wiring layer 60 and a second connection portion 72. For example... Figure 4 As shown, the wiring layer 60 is located between the second surface 10B of the semiconductor portion 10 and the second electrode 22 in the third direction Z, and extends in the first direction X. A third insulating film 53 is provided between the wiring layer 60 and the second surface 10B of the semiconductor portion 10, and between the wiring layer 60 and the second electrode 22.

[0045] The second connection portion 72 passes through the third insulating film 53 between the wiring layer 60 and the third electrode 40, connecting the wiring layer 60 and the third electrode 40. The second connection portion 72 is in contact with the upper surface of the third electrode 40. A plurality of second connection portions 72 are correspondingly disposed on the third electrode 40. The third electrode 40 is electrically connected to the wiring layer 60 via the second connection portions 72. For example, the wiring layer 60 and the second connection portions 72 are integrally disposed of from the same material. For example, conductive polysilicon can be used as the material for the wiring layer 60 and the second connection portions 72.

[0046] exist Figure 1 In the example shown, when viewed from above, multiple wiring layers 60 are arranged in the second direction Y, and each wiring layer 60 extends from the component region 100 to the end region 200 in the first direction X. The second electrode 22 has a main portion 22A located in the component region 100 and multiple extension portions 22B extending from the main portion 22A to the end region 200 in the first direction X. When viewed from above, the main portion 22A continuously covers the multiple wiring layers 60 separated in the second direction Y and the multiple third electrodes 40 arranged in the first direction X and the second direction Y. The area of ​​the main portion 22A is larger than the area of ​​the extension portions 22B. The main portion 22A and the multiple extension portions 22B are integrally formed from the same material. In the end region 200, the extension portions 22B are located above the wiring layers 60. In addition, the third electrodes 40 are also disposed in the end region 200.

[0047] Figure 5 yes Figure 1 CC section view in the image.

[0048] The semiconductor device 1 of the embodiment further includes a third connection portion 73 located between the wiring layer 60 and the extension 22B of the second electrode 22 in the terminal region 200. The third connection portion 73 passes through a third insulating film 53 between the wiring layer 60 and the extension 22B of the second electrode 22, connecting the wiring layer 60 and the extension 22B of the second electrode 22. The third connection portion 73 is in contact with the upper surface of the wiring layer 60. The third connection portion 73 is conductive and, for example, is made of a metallic material.

[0049] A third connection portion 73 is provided between each of the plurality of wiring layers 60 extending along the first direction X and each of the plurality of extensions 22B of the second electrode 22 extending along the first direction X. Each wiring layer 60 is electrically connected to the second electrode 22 in the end region 200 via the third connection portion 73. The plurality of third electrodes 40 are electrically connected to the second electrode 22 via the second connection portion 72, the wiring layer 60 and the third connection portion 73 respectively.

[0050] In the component region 100, as described above, the semiconductor section 10 has a first semiconductor layer 11, a second semiconductor layer 12, a third semiconductor layer 13, a fourth semiconductor layer 14, and a fifth semiconductor layer 15. In the terminal region 200, the semiconductor section 10 has a first semiconductor layer 11 and a fifth semiconductor layer 15. In the terminal region 200, the third semiconductor layer 13 (source layer or emitter layer), which is connected to the second electrode 22 and forms part of the longitudinal main current path, is not disposed on the first semiconductor layer 11. In the terminal region 200, the second semiconductor layer 12 and the third semiconductor layer 13 may or may not be located on the first semiconductor layer 11. A p-type layer different from the second semiconductor layer 12 and the third semiconductor layer 13 may also be disposed on the first semiconductor layer 11 in the terminal region 200.

[0051] like Figure 1 As shown, a plurality of gate wirings 80 extending along a first direction X are provided in the end region 200. The gate wirings 80 are disposed separately from the second electrode 22 on the third insulating film 53. The gate wirings 80 extending along the first direction X are connected to each other and to gate pads (not shown). For example, the gate wirings 80 and the extensions 22B of the second electrode 22 are arranged alternately in the second direction Y.

[0052] In the element region 100, a portion of the gate electrode 30, for example formed by a grid pattern extending along the first direction X and the second direction Y, extends from the element region 100 toward the end region 200 along the first direction X. The gate electrode 30 of the end region 200 extends along the first direction X to a position overlapping below the gate wiring 80, and is electrically connected to the gate wiring 80 via a conductive fourth connection portion 74.

[0053] If a first potential (e.g., a positive potential) is applied to the first electrode 21, a second potential lower than the first potential (e.g., a ground potential) is applied to the second electrode 22, and a gate voltage above a threshold is applied to the gate electrode 30, an n-type channel is formed in the region of the second semiconductor layer 12 opposite to the side of the gate electrode 30. Current flows between the first electrode 21 and the second electrode 22 via the fifth semiconductor layer 15, the first semiconductor layer 11, the channel, and the third semiconductor layer 13, and the semiconductor device 1 becomes conductive.

[0054] In the off state of the semiconductor device 1, where the voltage applied to the gate electrode 30 is stopped above a threshold, the depletion layer extends from the pn junction of the second semiconductor layer 12 and the first semiconductor layer 11 and the boundary between the second insulating film 52 and the first semiconductor layer 11, maintaining the withstand voltage of the semiconductor device 1.

[0055] The third electrode 40, which is electrically connected to the second electrode 22, is a field plate electrode. In the off state of the semiconductor device 1, it makes the electric field distribution of the first semiconductor layer 11 (drift layer) smooth and increases the withstand voltage of the semiconductor device 1.

[0056] As in this embodiment, the configuration in which multiple third electrodes 40 (field plate electrodes) are arranged in a dotted pattern and the gate electrode 30 is formed in a grid pattern surrounding the third electrodes 40 can increase the channel and reduce the on-resistance compared to the configuration in which multiple third electrodes 40 and multiple gate electrodes 30 are formed in a stripe pattern.

[0057] As a comparative example, consider a configuration in which multiple third electrodes 40, arranged in a dot-like pattern, are connected to the second electrode 22 directly above each third electrode 40 without passing through the wiring layer 60. Compared to the embodiment where multiple third electrodes 40 are connected to the second electrode 22 via the wiring layer 60, the resistance of the third electrodes 40 in this comparative example is lower. Therefore, the resistance of the buffer circuit is also lower, potentially leading to increased noise (current ringing).

[0058] The buffer circuit is connected in parallel with the first electrode 21 and the second electrode 22 of the semiconductor device 1 to absorb the transient high voltage generated when the semiconductor device 1 is turned off. For example, an RC circuit including a resistor and a capacitor connected in series can be used as the buffer circuit. The buffer circuit is electrically connected to the third electrode 40 via the second electrode 22.

[0059] According to this embodiment, based on the connection of a plurality of third electrodes 40 disposed in the component region 100 to the wiring layer 60 in the component region 100, the wiring layer 60 extending from the component region 100 to the end region 200 is connected to the second electrode 22 in the end region 200. Therefore, compared to the comparative example, the resistance of the third electrodes 40 can be increased, the resistance of the buffer circuit can be increased, and noise can be reduced.

[0060] The resistivity of the wiring layer 60 is preferably higher than that of the second electrode 22. Furthermore, the resistivity of the wiring layer 60 is preferably higher than that of the third electrode 40.

[0061] The wiring layer 60 extends from the component region 100 to the end region 200, where it connects to the second electrode 22. The wiring layer 60 is not connected to the second electrode 22 within the component region 100. Therefore, it does not affect the arrangement of the components in the component region 100. Furthermore, since the wiring layer 60 is only connected to the second electrode 22 in the end region 200, it is easier to further increase the resistance of the third electrode 40. Alternatively, the wiring layer 60 may also be connected to the second electrode 22 within the component region 100.

[0062] The third semiconductor layer 13 (source layer or emitter layer) located directly below the wiring layer 60 is obstructed by the wiring layer 60 and cannot connect to the second electrode 22 located above the wiring layer 60. Figure 2 as well as Figure 4 As shown, by also providing a third semiconductor layer 13 directly below the wiring layer 60, the on-resistance can be reduced.

[0063] The following describes other embodiments. Regarding these other embodiments, the differences in configuration from the first embodiment described above will be primarily explained. Similar to the first embodiment, these other embodiments also reduce noise.

[0064] [Second Implementation]

[0065] Figure 6 This represents a cross-section (XZ section) of the semiconductor device 2 of the second embodiment, located at the position where the wiring layer 60 is formed, parallel to the first direction X extending from the wiring layer 60. Furthermore, in the semiconductor device 2 of the second embodiment, the cross-section (YZ section) of the element region 100 parallel to the second direction Y is also represented by this cross-section. Figure 3 same.

[0066] In the second embodiment, the third semiconductor layer 13 is not disposed directly below the wiring layer 60. Instead, a fourth semiconductor layer 14 is disposed on the second semiconductor layer 12 directly below the wiring layer 60 of the component region 100.

[0067] If the third semiconductor layer 13, which is not connected to the second electrode 22, is located directly below the wiring layer 60, there is a concern that the avalanche tolerance may decrease due to the operation of the parasitic NPN transistor. According to the second embodiment, the third semiconductor layer 13 is not located directly below the wiring layer 60, thus suppressing the decrease in avalanche tolerance.

[0068] [Third Implementation Method]

[0069] Figure 7 The XZ section is a cross section (XZ section) of the element region 100 of the semiconductor device 3 of the third embodiment, at the location where the wiring layer 60 is formed, which is parallel to the first direction X extending from the wiring layer 60.

[0070] Alternatively, as in the semiconductor device 3 of the third embodiment, the third semiconductor layer 13 and the fourth semiconductor layer 14 may not be disposed on the second semiconductor layer 12 directly below the wiring layer 60 of the element region 100. This can suppress the reduction in avalanche tolerance.

[0071] [Fourth Implementation Method]

[0072] Figure 8 The section (YZ section) represents the element region 100 of the semiconductor device 4 in the fourth embodiment, which is parallel to the second direction Y.

[0073] Figure 9 The XZ section is a cross section (XZ section) of the element region 100 of the semiconductor device 4 of the fourth embodiment, at the location where the wiring layer 60 is formed, which is parallel to the first direction X in which the wiring layer 60 extends.

[0074] like Figure 8 As shown, a fourth semiconductor layer 14 is disposed between the second semiconductor layer 12 and the third semiconductor layer 13. A first connecting portion 71, extending downward from the second electrode 22, penetrates the third semiconductor layer 13 and reaches the fourth semiconductor layer 14. The first connecting portion 71 is in contact with the side surface of the third semiconductor layer 13. Compared to a configuration where the first connecting portion 71 is only in contact with the upper surface of the third semiconductor layer 13, this configuration makes it easier to reduce the contact resistance between the first connecting portion 71 and the third semiconductor layer 13, and thus easier to reduce the on-resistance.

[0075] like Figure 9 As shown, the fourth semiconductor layer 14 is not disposed directly below the wiring layer 60. Directly below the wiring layer 60 of the component region 100, only the third semiconductor layer 13 is disposed on the second semiconductor layer 12. Furthermore, in the fourth embodiment, it is also possible to... Figure 7 As shown in the third embodiment, the third semiconductor layer 13 and the fourth semiconductor layer 14 are not disposed on the second semiconductor layer 12 directly below the wiring layer 60 of the component region 100.

[0076] [Fifth Implementation]

[0077] Figure 10 This is a schematic top view showing the configuration of the main components in the semiconductor device 5 of the fifth embodiment.

[0078] In the semiconductor device 5 of the fifth embodiment, when viewed from above, a plurality of wiring layers 60 are arranged in a first direction X, and each wiring layer 60 extends from the element region 100 to the end region 200 in a second direction Y. Furthermore, a plurality of extensions 22B of the second electrode 22 extend from the main portion 22A disposed in the element region 100 to the end region 200 along the second direction Y. A third connection portion 73 is provided between each of the plurality of wiring layers 60 extending along the second direction Y and each of the plurality of extensions 22B extending along the second direction Y. Each wiring layer 60 is electrically connected to the second electrode 22 via the third connection portion 73 at its end region 200, which is located on the outer side of the element region 100 in the second direction Y.

[0079] Furthermore, the third electrode 40, located in the end region 200 on the outer side of the component region 100 in the first direction X, can be directly connected to the extension 22B of the second electrode 22 without passing through the wiring layer 60.

[0080] Furthermore, in the semiconductor device 5 of the fifth embodiment, a plurality of gate wirings 80 extending in the second direction Y are provided in the end region 200 located on the outer side of the element region 100 in the second direction Y. The gate wirings 80 extending in the second direction Y are connected to each other and connected to gate pads (not shown).

[0081] The gate electrode 30 extends from the element region 100 to the end region 200 along the second direction Y. The gate electrode 30 of the end region 200 extends along the second direction Y to a position that overlaps with the lower part of the gate wiring 80, and is electrically connected to the gate wiring 80 via the fourth connection portion 74.

[0082] like Figure 11 As shown, in the component region 100, the plurality of wiring layers 60 may also be a grid pattern extending along the first direction X and the second direction Y. The end regions 200 of the wiring layers 60 in the first direction X and the end regions 200 in the second direction Y are connected to the extension 22B of the second electrode 22 via the third connection portion 73.

[0083] like Figure 12 As shown, it can also be a pattern in which multiple wiring layers 60 extend in the first direction X in the component region 100, and the wiring layers 60 extending in the first direction X are connected to each other by wiring layers 60 extending in a direction inclined relative to the first direction X and the second direction Y.

[0084] like Figure 13As shown, in a top view, multiple triangles (equilateral triangles in this example) arranged without gaps are imaginarily represented by double-dotted lines. Multiple third electrodes 40 can also be configured at the vertices of the triangles. Thus, the gate electrode 30 can be arranged in a honeycomb grid pattern between the multiple third electrodes 40 arranged in the densest possible configuration. This configuration reduces the on-resistance compared to a configuration where the gate electrode 30 is arranged in a lattice pattern between multiple third electrodes 40 arranged in a square grid.

[0085] When viewed from above, the gate electrode 30 is located among a plurality of third electrodes 40, with one third electrode 40 surrounded by a hexagonal (in this example, a regular hexagon) pattern. The planar pattern of the gate electrode 30 is a honeycomb grid pattern formed by repeating a plurality of hexagonal patterns.

[0086] In addition, Figure 13 In the example shown, the wiring layer 60 extends along the second direction Y above a plurality of third electrodes 40 arranged along the second direction Y. Figure 14 As shown, the wiring layer 60 can also extend in a direction inclined relative to the first direction X and the second direction Y.

[0087] like Figure 15 As shown, when viewed from above, the multiple third electrodes 40 can also be arranged in a zigzag pattern in the second direction Y. The centers of adjacent third electrodes 40 in the second direction Y are staggered from each other in the first direction X.

[0088] exist Figure 15 In the example shown, the wiring layer 60 extends along the first direction X above a plurality of third electrodes 40 arranged along the first direction X. Figure 16 As shown, the wiring layer 60 can also extend in a direction inclined relative to the first direction X and the second direction Y.

[0089] In addition, the centers of adjacent third electrodes 40 in the first direction X can also be offset from each other in the second direction Y.

[0090] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device comprising a component region and an end region surrounding the component region, characterized in that, have: First electrode; Second electrode; A semiconductor section is disposed between the first electrode and the second electrode; Multiple third electrodes are disposed at least within the semiconductor portion of the element region; A gate electrode is located between the plurality of third electrodes; as well as A wiring layer is located between the semiconductor portion and the second electrode, extends from the element region to the end region, is connected to the plurality of third electrodes in the element region, and is connected to the second electrode in the end region.

2. The semiconductor device according to claim 1, characterized in that, The resistivity of the wiring layer is higher than that of the second electrode.

3. The semiconductor device according to claim 1, characterized in that, The resistivity of the wiring layer is greater than the resistivity of the third electrode.

4. The semiconductor device according to claim 1, characterized in that, The semiconductor section has: A first semiconductor layer of a first conductivity type is disposed on the first electrode; A second semiconductor layer of a second conductivity type is disposed on the first semiconductor layer and is opposite to the gate electrode; as well as A third semiconductor layer of a first conductivity type is disposed on the second semiconductor layer and connected to the second electrode. The impurity concentration of the first conductivity type in the third semiconductor layer is higher than that in the first semiconductor layer.

5. The semiconductor device according to claim 4, characterized in that, The third semiconductor layer is not located directly below the wiring layer.

6. The semiconductor device according to claim 4, characterized in that, The semiconductor portion further comprises a fourth semiconductor layer of a second conductivity type, which is disposed on the second semiconductor layer and connected to the second electrode. The impurity concentration of the second conductivity type of the fourth semiconductor layer is higher than that of the second conductivity type of the second semiconductor layer.

7. The semiconductor device according to claim 6, characterized in that, The fourth semiconductor layer is not located directly below the wiring layer.

8. The semiconductor device according to claim 6, characterized in that, The third semiconductor layer and the fourth semiconductor layer are not located directly below the wiring layer.

9. The semiconductor device according to claim 1, characterized in that, The plurality of third electrodes are cylindrical in shape.

10. The semiconductor device according to claim 1, characterized in that, The plurality of third electrodes are arranged in a first direction and a second direction orthogonal to the first direction.

11. The semiconductor device according to claim 10, characterized in that, The plurality of wiring layers extend in the first direction and the second direction.

12. The semiconductor device according to claim 10, characterized in that, The gate electrode extends in the first direction and the second direction.

13. The semiconductor device according to claim 12, characterized in that, A third electrode is disposed in a region surrounded by the gate electrode extending along the first direction and the second direction.

14. The semiconductor device according to claim 1, characterized in that, The gate electrode surrounds one of the third electrodes in a hexagonal pattern.

15. The semiconductor device according to claim 4, characterized in that, The semiconductor portion further includes a fifth semiconductor layer disposed between the first electrode and the first semiconductor layer.

16. The semiconductor device according to claim 15, characterized in that, The fifth semiconductor layer is of the first conductivity type. The concentration of the first conductivity type impurity in the fifth semiconductor layer is higher than the concentration of the n-type impurity in the first semiconductor layer.

17. The semiconductor device according to claim 15, characterized in that, The fifth semiconductor layer is of the second conductivity type.

18. The semiconductor device according to claim 6, characterized in that, The plurality of third electrodes are arranged in a first direction and a second direction orthogonal to the first direction. The gate electrode extends in the first direction and the second direction. In a region surrounded by the gate electrode extending along the first and second directions, the fourth semiconductor layer continuously surrounds the third electrode, and the third semiconductor layer continuously surrounds the fourth semiconductor layer.

19. The semiconductor device according to claim 1, characterized in that, The wiring layer is not connected to the second electrode in the component region.

20. The semiconductor device according to claim 1, characterized in that, The wiring layer is formed of silicon.

Images