Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes a plurality of cells, a plurality of active regions, a plurality of gate regions, a plurality of sources and drains, and a plurality of power rails. The plurality of cells includes one or more taller cells, one or more shorter cells, and one or more over half height (OHH) cells. The shorter cells have a cell height that is smaller than the taller cells. The OHH cells have a cell height that is greater than the cell height of the taller cells. An active region is formed in each cell. A gate region extends across the active region. A source and a drain are formed in the active region on opposite sides of the gate region. The power rails include first and second power rails that define top and bottom boundaries of the cells, respectively. A method of fabricating the device is also disclosed.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Background Technology

[0002] In semiconductor design, a cell serves as the basic building block of a device, such as an integrated circuit (IC). Each cell is a circuit designed to perform a specific function, ranging from simple logic gates like AND and OR to more complex components like flip-flops and multiplexers. These cells can be categorized as standard cells, which are pre-designed, characterized, and stored in a standard cell library. These libraries are available for use by electronic design automation (EDA) tools, which leverage them to generate, optimize, and verify IC designs. IC designs are evaluated based on performance, power, and area (PPA), and design trade-offs are made between speed, energy efficiency, and physical footprint. Summary of the Invention

[0003] In one embodiment, a semiconductor device includes a plurality of cells, a plurality of active regions, a plurality of gate regions, a plurality of sources and drains, and a plurality of power rails. The cells are arranged in an array of columns and rows, including one or more taller cells, one or more shorter cells, and one or more one-half-height (OHH) cells. The shorter cells have a smaller cell height than the taller cells. The one-half-height cells have a larger cell height than the taller cells. An active region is formed in each cell. The active region includes a first conductivity type and a second conductivity type opposite to the first conductivity type. A gate region extends across the active region. Sources and drains are formed in the active regions on opposite sides of the gate region. The power rails include a first power rail and a second power rail that define the top and bottom boundaries of the cell, respectively.

[0004] In another embodiment, a semiconductor device includes a plurality of cells, a plurality of active regions, a plurality of gate regions, a plurality of source and drain electrodes, and a plurality of power rails. The cells are arranged in an array of columns and rows, including one or more average-height cells, a plurality of unit cells, and one or more half-height (OHH) cells. Higher cells have a greater cell height than average-height cells. Lower cells have a smaller cell height than average-height cells. Half-height cells have a greater cell height than higher cells. An active region is formed in each cell. The active region includes a first conductivity type and a second conductivity type opposite to the first conductivity type. A gate region extends across the active region. Sources and drains are formed in the active regions on opposite sides of the gate region. The power rails include a first power rail and a second power rail that define the top and bottom boundaries of the cell, respectively.

[0005] In another embodiment, a method of manufacturing a semiconductor device includes: fabricating a plurality of cells on a semiconductor substrate, arranged in an array of columns and rows, wherein fabricating the plurality of cells includes: fabricating a pair of first power rails defining a higher cell; fabricating a pair of second power rails defining a lower cell, wherein the lower cell has a smaller cell height than the higher cell; fabricating a pair of third power rails defining a half-height (OHH) cell, wherein the cell height of the OHH cell is substantially equal to the sum of the cell height of one of the higher cell and the lower cell and half the cell height of the other of the higher cell and the lower cell; patterning one or more active regions in each cell; forming a gate structure on the active regions; and doping the active regions to form source and drain regions on opposite sides of the gate structure. Attached Figure Description

[0006] The various aspects of this disclosure can be best understood from the following detailed description and accompanying drawings.

[0007] Figure 1 This is a schematic diagram illustrating exemplary layouts according to various embodiments disclosed herein.

[0008] Figure 2 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0009] Figure 3 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0010] Figure 4 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0011] Figure 5 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0012] Figure 6This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0013] Figure 7 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0014] Figure 8 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0015] Figure 9 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0016] Figure 10 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0017] Figure 11 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0018] Figure 12 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0019] Figure 13 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0020] Figure 14 This is a schematic diagram illustrating another exemplary layout based on various embodiments disclosed herein.

[0021] Figure 15 This is a flowchart of an exemplary method for manufacturing an apparatus according to various embodiments of the present disclosure.

[0022] Figure 16 This is a schematic block diagram of an exemplary electronic design automation (EDA) system according to various embodiments of the present disclosure.

[0023] Figure 17 This is a schematic block diagram of an example integrated circuit (IC) manufacturing system according to various embodiments of the present disclosure. Detailed Implementation

[0024] The following disclosure provides numerous different embodiments or examples to implement various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are in direct contact, or embodiments where an additional feature may be formed between the first and second features, such that the first and second features may not be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0025] In addition, spatial relative terms, such as “below,” “lower,” “lower part,” “above,” “upper,” “top,” “bottom,” etc., may be used herein to conveniently describe the relationship between one component or feature and another shown in the figures. These spatial relative terms are intended to cover different orientations of the structure in use or operation, other than those depicted in the figures. The apparatus may have different orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0026] In semiconductor design, cells of substantially the same cell height are read from one or more cell libraries and placed in the IC layout, for example, by electronic design automation (EDA) tools or systems. While uniform cell height devices simplify design and fabrication, they are less flexible in optimizing performance, power, and area (PPA). In some examples described herein, systems and methods include devices with varying cell heights. For example, a device includes: first and second unit cells, each with a different cell height; and a one-half-height (OHH) cell whose cell height is substantially equal to the sum of the cell height of the first unit cell and half the cell height of the second unit cell. This structure allows for design flexibility to optimize the balance between speed, energy efficiency, and physical footprint.

[0027] Figure 1 This is a schematic diagram of exemplary layouts according to various embodiments of this disclosure. Figure 1 In the example layout 100 (or the device associated therewith), multiple cells (C1, C2) are arranged in an array of rows (R1-R3) and columns (C1, C2). T1 C T2 C S C OHH1 C OHH2In some embodiments, each cell (C) T1 C T2 C S C OHH1 C OHH2 This includes one or more logic gates (e.g., AND gate, OR gate, any suitable logic gate, or a combination thereof), flip-flops, multiplexers, etc. Layout 100 may be generated by an EDA system, such as automated placement and routing (APR), and stored in a non-transitory computer-readable storage medium.

[0028] Each row (R1-R3) is defined by boundaries 110a-110d, each boundary extending along a first direction (x), and a row height (H) corresponding to the distance along a second direction (y) perpendicular to the first direction (y) between boundaries 110a-110d. T H S The first column (C1) includes multiple unit cells (e.g., a pair of higher cells (C) T1 C T2 ) and located in higher cells (C T1 C T2 The shorter cells (C) between ) S Unit cell (C) T1 C T2 C S ) can be arranged in order so that higher cells (C T1 The cell in the first row (R1) is followed by a shorter cell in the second row (R2), and then another taller cell (C) in the third row (R3). T2 Higher cell units (C) T1 C T2 ) has a height corresponding to its respective row height (H) T The height of the cell. The shorter cell (C) S ) has a corresponding row height (H) S The cell height (H) is the cell height. In this exemplary embodiment, the cell height (H) is... S ) smaller than cell height (H) T ).

[0029] Higher cell type (C T1The device includes first and second active regions 120a and 120b. The first active region 120a extends along a first direction (x) and has a first conductivity type (e.g., p-type). The second active region 120b is substantially parallel to the first active region 120a, spaced apart from the first active region 120a along a second direction (y), and has a second conductivity type (e.g., n-type) different from the first conductivity type. The p-type active region 120a is formed on the n-type well region, while the n-type active region 120b is formed on the p-type well region.

[0030] Dwarf cell type (C S The active regions include n-type and p-type active regions 130a and 130b. The n-type active region 130a extends along the first direction (x) and is formed on the p-type well region. The p-type active region 130b is substantially parallel to the n-type active region 130a, is separated from the n-type active region 130a along the second direction (y), and is formed on the n-type well region.

[0031] Higher cell type (C T2 The active regions include p-type and n-type active regions 140a and 140b. The p-type active region 140a extends along a first direction (x) and is formed on the n-type well region. The n-type active region 140b is substantially parallel to the p-type active region 140a, is separated from the p-type active region 140a along a second direction (y), and is formed on the p-type well region.

[0032] Active regions 120a-140a and 120b-140b are functional active regions, each contributing to the operation of the device. In addition to the active regions, layout 100 may also include multiple non-functional (or dummy) active regions 170a-170d, located between the first and second columns (C1, C2) and spanning the first to third rows (R1-R3). Dummy active regions may lack semiconductor components or contain semiconductor components not electrically connected to the device. They are incorporated into layout 100 to achieve manufacturing process uniformity, such as maintaining a consistent pattern density on the semiconductor die, or minimizing process-induced variations such as stress or load effects during manufacturing. Therefore, while these regions do not actively participate in the operation of the device, they play a supporting role in ensuring the structural and manufacturing integrity of layout 100.

[0033] The second column (C2) includes a pair of OHH cells (C OHH1 C OHH2 ), height of each cell (H) OHH The cell height (H) is approximately equal to the sum of the height of the first unit cell in a row and half the height of the second unit cell in the adjacent row. In some embodiments, the cell height (H) is... OHH It is basically equal to the cell height (H) T ) and half cell height (H S The sum of ) . In these embodiments, OHH cells (COHH1 The top edge of ) and the higher cell (C T1 The top edge of the cell is aligned with the bottom edge of the lower cell (C). S The center of the OHH cell is aligned. Similarly, the OHH cell (C OHH2 The bottom edge of the cell and the higher cell (C) T2 The bottom edge of the cell is aligned with the bottom edge of the lower cell (C). S Align the center of the ) with the center.

[0034] In other embodiments, cell height (H) OHH It is basically equal to the cell height (H) S ) and half cell height (H T The sum of ) . In these other embodiments, OHH cells (C OHH1 The bottom edge of ) and the shorter cell (C S The bottom edge of the cell is aligned with the top edge of the cell (C). T1 The center alignment of ) or OHH cell (C OHH1 The top edge of ) and the lower cell (C S The top edge of the cell is aligned with the bottom edge of the cell (C). T2 Align the center of the ) with the center.

[0035] In this example embodiment, the OHH cell (C OHH1 C OHH2 The cell height (H) is defined by boundaries 110a, 110d, and 110e. OHH This corresponds to the distance between boundaries 110a, 110d, and 110e.

[0036] Each OHH cell (C OHH1 C OHH2 This includes functional p-type and n-type active regions 150a, 150b, 160a, and 160b. The p-type active regions 150a and 160a extend in the first direction (y) and are formed above the n-type well region. The n-type active regions 150b and 150b are substantially parallel to the p-type active regions 150a and 160a, are spaced apart from the p-type active regions 150a and 160a along the second direction (y), and are formed above the p-type well region.

[0037] Layout 100 also includes gate regions, such as gate regions 180a and 180b, and source and drain regions formed in active regions 120a-160a and 120b-160b on either side of gate regions 180a and 180b. Gate regions 180a and 180b are functional gate structures (e.g., polysilicon or metal gates) electrically connected to the device. They are responsible for controlling the current flow between the source and drain regions based on the applied voltage. In this example embodiment, gate regions 180a and 180b extend from boundaries 110a and 110d to boundary 110e, cross boundaries 110b and 110c, and span the active regions 120a-160a and 120b-160b.

[0038] In addition to gate regions 180a and 180b, layout 100 also includes non-functional gate regions 190a-190d, also referred to as dummy gate regions. Dummy gate regions are not electrically connected to the device (or are not electrically active in the device). They are incorporated into the layout to ensure manufacturing uniformity and process optimization for purposes such as maintaining consistent lithography or etching conditions (pattern density) across the wafer, reducing mechanical stress variations that may affect the performance of nearby functional gates (stress management), providing a uniform surface during planarization to prevent the removal of non-uniform material (CMP or chemical mechanical polishing), and maintaining the electrical behavior of adjacent functional gates by mitigating physical asymmetries in the layout (isolation and symmetry). In this example embodiment, each gate region 190a-190d extends from boundary 110a to boundary 110d, crosses boundaries 110b, 110c, and 110e, and runs along the edges of active regions 120a-160a, 120b-160b, and 170a-170d.

[0039] Layout 100 also includes cut regions (CPOa-CPOe), each cut region being a different sibling (C... T1 C T2 C S C OHH1 C OHH2 This forms the gate region. For example, the cleaved region (CPOa) extends along the boundary 110a and divides the cell (C... T1 C OHH1 The gate regions 180a, 180b, 190a-190d of the cell are separated from the gate regions of one or more adjacent cells above.

[0040] Each cut region (CPOb) extends along boundary 110b and divides the cell (C T1 C SThe gate regions 180a, 190a, and 190b of the cells (CS, CT2) are separated from each other. A cleavage region (CPOc) extends along boundary 110c and separates the gate regions 180a, 190a, and 190b of the cells (CS, CT2) from each other. A cleavage region (CPOd) extends along boundary 110d and separates the gate regions 180a, 190a, and 190b of the cells (CS, CT2) from each other. T2 C OHH2 The gate regions 180a, 180b, and 190a-190d of the cell are separated from the gate regions of one or more adjacent cells below. The cleaved region (CPOe) extends along the boundary 110e and separates the cell (C... OHH1 C OHH2 The gate regions 180b, 190c, and 190d are separated from each other. In this example embodiment, the cut regions (CPOa-CPOe) include grooves formed in the device and dielectric material deposited in the grooves.

[0041] The layout 100 also includes multiple power rails (VDD, VSS), each carrying a supply voltage or reference voltage (e.g., ground or negative voltage). The power rails (VDD, VSS) each extend in a first direction (x) and alternate along a second direction (y). For example, each power rail (VSS) extends along its respective boundaries 110a, 110d and overlaps with its respective cut-out regions (CPOa, CPOd). Similarly, each power rail (VDD) extends along its respective boundaries 110b, 110d and overlaps with its respective cut-out regions (CPOb, CPOe).

[0042] As described above, because the layout (or associated device) integrates cells with varying cell heights, it enables design flexibility to optimize the balance between speed, energy efficiency, and physical footprint, commonly referred to as performance, power, and area (PPA). By adjusting cell heights according to specific functional requirements, layout 100 can allocate resources more efficiently. For example, larger cells can be used where higher performance or greater drive strength is required, while smaller cells can reduce power consumption and save area in less critical areas. This strategic variation in cell size contributes to achieving optimal overall PPA for layout 100.

[0043] Figure 2 This is a schematic diagram illustrating another exemplary layout based on various embodiments of the present disclosure. Figure 2 In the example layout 200, or its associated unit cell (e.g., cell C). T1 C T2 C SThe layout 200 includes a pair of active regions 210, 220, multiple gate regions 230-270, source and drain regions (S, D), a pair of cleaved regions (CPOa, CPOb), and a pair of power rails (VDD, VSS). The layout 200 is defined by top and bottom boundaries 280, 290, each extending in a first direction (x), and the cell height corresponding to the distance between the top and bottom boundaries 280, 290 along a second direction (y). The first active region 210 extends along the first direction (x) and has a first conductivity type (e.g., p-type). The second active region 220 is substantially parallel to the first active region 210, spaced apart from the first active region 210 along the second direction (y), and has a second conductivity type different from the first conductivity type (e.g., n-type). The p-type active region 210 is formed on the n-type well region, while the n-type active region 220 is formed on the p-type well region.

[0044] Gate regions 230-250 are functional gate structures (e.g., polysilicon or metal gates) electrically connected to the device. They are responsible for controlling the current flow between the source and drain regions (S, D) based on the applied voltage. In this exemplary embodiment, each gate region 230-250 extends from a top boundary 280 to a bottom boundary 290, spanning active regions 210, 220. Source and drain regions (S, D) are formed in the active regions 210, 220 on either side of the gate regions 230-250.

[0045] In addition to gate regions 230-250, layout 200 also includes non-functional gate regions 260, 270, which may also be referred to as dummy gate regions. Dummy gate regions are not electrically connected to the device (or are not electrically active in the device). In this exemplary embodiment, each gate region 260, 270 extends from the top boundary 280 along the edge of its respective active region 210, 220 to the bottom boundary 290.

[0046] Each cut region (CPOa, CPOb) forms a gate region of a different cell. For example, a cut region (CPOa) extends along the top boundary 280 and separates the gate regions 230-270 of the unit cell 200 from the gate regions of one or more adjacent cells above it. Similarly, a cut region (CPOb) extends along the bottom boundary 290 and separates the gate regions 230-270 of the unit cell 200 from the gate regions of one or more adjacent cells below it. In this exemplary embodiment, the cut regions (CPOa, CPOb) include a groove formed in the cell 200 and a dielectric material deposited in the groove.

[0047] Power rails (VDD, VSS) each extend in a first direction (x) and are spaced apart from each other in a second direction (y). Power rail (VDD) carries a supply voltage, while power rail (VSS) carries a reference voltage (e.g., ground or a negative voltage). Each power rail (VSS, VDD) extends along its respective boundaries 280, 290 and overlaps with its respective cut-off region (CPOa, CPOb).

[0048] From the above description, because layout 200 includes cut regions (CPOa, CPOb) and power rails (VSS, VDD), with each power rail overlapping its respective cut region (CPOa, CPOb), layout 200 corresponds to a unit cell (e.g., cell C). T1 C T2 C S However, it should be noted that layout 200 is not classified as a unit cell if there is an additional pair of power rails (VDD, VSS) between them.

[0049] Figure 3 This is a schematic diagram illustrating another exemplary layout according to various embodiments of the present disclosure. Figure 3 In the example layout 300, or its associated OHH cell (e.g., OHH cell C). OHH1 C OHH2 The layout 300 includes first and second active regions 310 and 320, multiple gate regions 330-370, source and drain regions (S, D), a pair of cleaved regions (CPOa, CPOb), and multiple power rails (VDD, VSS1, VSS2). The layout 300 is defined by top and bottom boundaries 380 and 390, each extending in a first direction (x), and the cell height corresponding to the distance between the top and bottom boundaries 280 and 290 along a second direction (y). The first active region 310 extends along the first direction (x) and has a first conductivity type (e.g., p-type). The second active region 320 is substantially parallel to the first active region 310, spaced apart from the first active region 310 along the second direction (y), and has a second conductivity type different from the first conductivity type (e.g., n-type). The p-type active region 310 is formed on the n-type well region, while the n-type active region 320 is formed on the p-type well region.

[0050] Gate regions 330-350 are functional gate structures (e.g., polysilicon or metal gates) electrically connected to the device. They are responsible for controlling the current flow between the source and drain regions (S, D) based on an applied voltage. In this exemplary embodiment, each gate region 330-350 extends from a top boundary 380 to a bottom boundary 390, spanning active regions 310, 320. Source and drain regions (S, D) are formed in active regions 310, 320, located on opposite sides of gate regions 330-350.

[0051] In addition to gate regions 330-350, layout 300 also includes non-functional (or dummy) gate regions 360, 370, also referred to as dummy gate regions. Dummy gate regions are not electrically connected to (or are not electrically active in) devices in one or more circuits. In this exemplary embodiment, each gate region 360, 370 extends from a top boundary 380 to a bottom boundary 390 along the edge of its respective active region 310, 320.

[0052] Each cut region (CPOa, CPOb) forms a gate region of a different cell. For example, a cut region (CPOa) extends along the top boundary 380 and separates the gate regions 330-370 of the OHH cell 300 from the gate regions of one or more adjacent cells above it. Similarly, a cut region (CPOb) extends along the bottom boundary 390 and separates the gate regions 330-370 of the unit cell 300 from the gate regions of one or more adjacent cells below it. In this exemplary embodiment, the cut regions (CPOa, CPOb) include a groove formed in the cell 300 and a dielectric material deposited in the groove.

[0053] Power rails (VDD, VSS1, VSS2) each extend in a first direction (x) and are spaced apart from each other in a second direction (y). Power rail (VDD) carries a supply voltage, while power rails (VSS1, VSS2) carry a reference voltage (e.g., ground or a negative voltage). In some embodiments, power rail (VSS1) extends along boundary 380 and overlaps with a cut region (CPOa). Power rail (VDD) is disposed between power rails (VSS1, VSS2) and spans gate regions 330-370. The cut region (CPOb) is disposed between power rails (VDD, VSS2).

[0054] From the above description, because layout 300 includes a cut area (CPOa), power rails (VSS1) overlapping with the cut area (CPOa), power rails (VDD, VSS2), and a cut area (CPOb) between the power rails (VDD, VSS2), layout 300 corresponds to an OHH cell (e.g., OHH cell C). OHH1 C OHH2 However, it should be noted that layout 300 is not classified as an OHH cell if there is an additional pair of power rails (VDD, VSS1, VSS2).

[0055] Figure 4 This is a schematic diagram illustrating another exemplary layout according to various embodiments of this disclosure. Figure 4 In the example layout 400 (or the device associated therewith), multiple units with different heights (H) are included. T H SThe unit cells (C1, C2) are arranged in an array of rows (R1, R2, R1', R2') and columns (C1, C2). T C S Each row (R1, R2) is defined by boundaries 410a-410c, each boundary extending along a first direction (x), and the row height (H) corresponding to the distance between boundaries 410a-410c along a second direction (y). T H S Unit cell (C) T (For example) a higher cell, located in the first row (R1), and having a height corresponding to the row height (H) T The height of a unit cell (C). S (For example) a shorter cell, located in the second row (R2), and having a height corresponding to the row height (H) S The cell height (H) is the cell height. In this exemplary embodiment, the cell height (H) is... S ) smaller than cell height (H) T ).

[0056] Higher cell type (C T The device includes first and second active regions 420a and 420b. The first active region 420a extends along a first direction (x) and has a first conductivity type (e.g., p-type). The second active region 420b is substantially flat with the first active region 420a, spaced apart from the first active region 420a along a second direction (y), and has a second conductivity type (e.g., n-type) different from the first conductivity type. The p-type active region 420a is formed on the n-type well region, while the n-type active region 420b is formed on the p-type well region.

[0057] Dwarf cell type (C S The active regions include n-type and p-type active regions 430a and 430b. The n-type active region 430a extends along the first direction (x) and is formed on the p-type well region. The p-type active region 430b is substantially parallel to the n-type active region 430a, is spaced apart from the n-type active region 430a along the second direction (y), and is formed on the n-type well region.

[0058] In this exemplary embodiment, the width (W) of the active regions 430a and 430b S The width (W) of the active regions 420a and 420b is smaller than that of the active regions. T For example, width (W) T ) and width (W) S The ratio ranges from about 1.5 to about 2. In some embodiments, the distance (S) between active regions 430a and 430b is substantially the same as the distance (S) between active regions 420a and 420b.

[0059] The layout 400 also includes a gate region 440 and source and drain regions formed in active regions 420a, 420b, 430a, 430b on opposite sides of the gate region 440. The gate regions 440 are functional gate structures (e.g., polysilicon or metal gates) electrically connected to the device. They are responsible for controlling the current flow between the source and drain regions based on the applied voltage. In this exemplary embodiment, the gate region 440 extends from boundary 410a to boundary 410c, crosses boundary 410b, and spans the active regions 420a, 420b, 430a, 430b.

[0060] Layout 400 also includes cut regions (CPOa-CPOc), each cut region being a unique sibling (C... T C S This forms the gate region. For example, the cleaved region (CPOa) extends along boundary 410a and connects the higher cells (C... T The gate region 440 of the cell is separated from the gate regions of one or more adjacent cells above it.

[0061] The cut region (CPOb) extends along boundary 410b and divides the unit cell (C T C S The gate regions 440 of the ) are separated from each other. The cleavage region (CPOc) extends along the boundary 410c and separates the shorter cells (C S The gate region 440 of the cell is separated from the gate regions of one or more adjacent cells below it.

[0062] Layout 400 also includes multiple cells (C H1 C H2 C M These cells are arranged in an array of rows (R1', R2') and columns (C1, C2). Each row (R1', R2') is defined by boundaries 450a-450c, each boundary extending along a first direction (x), and a row height (H) corresponding to the distance between boundaries 450a-450c along a second direction (y). The average height cell (C1, C2) H1 The cell is located in the first row (R1') and has a cell height corresponding to the row height (H). The average height cell (C) H2 The cell (C) is located in the second row (R2') and has a cell height corresponding to the row height (H). In this exemplary embodiment, the average height cell (C) is... H1 C H2 They have essentially the same cell height (H).

[0063] Average height cell (C H1The device includes first and second active regions 460a and 460b. The first active region 460a extends along a first direction (x) and has a first conductivity type (e.g., p-type). The second active region 460b is substantially parallel to the first active region 460a, spaced apart from the first active region 460a along a second direction (y), and has a second conductivity type different from the first conductivity type (e.g., n-type). The p-type active region 460a is formed on the n-type well region, while the n-type active region 460b is formed on the p-type well region. In this exemplary embodiment, the distance (S) between active regions 460a and 460b is substantially equal to the distance (S) between active regions 420a, 420b, 430a, and 430b.

[0064] Average height cell (C H2 The active regions 470a and 470b are n-type and p-type. The n-type active region 470a extends along a first direction (x) and is formed on the p-type well region. The p-type active region 470b is substantially parallel to the n-type active region 470a, spaced apart from the n-type active region 470a along a second direction (y), and is formed on the n-type well region. In this exemplary embodiment, the width (W) of the active regions 470a and 470b is... S The widths (W) of the active regions 470a and 470b S They are basically equal and within the range 0.3W ≤ W S ≤ 0.8W (1) In this exemplary embodiment, the width (W) T Within the range 1.2W ≤ W T ≤ 2W (2) Merged cell (C M () spans the first and second rows (R1', R2'). For example, merge cells (C M ) has a similar height to the cell (C H1 The top edge of the cell is aligned with the top edge of the cell, and with the average height cell (C). H2 The bottom edge of the cell is aligned with the bottom edge of the cell. In this exemplary embodiment, the cell (C) is merged. M The cell height is greater than (for example) essentially twice the cell height (H).

[0065] Combined cell (C MThe active region 480a-480c includes active regions 480a-480c. The first active region 480a extends along a first direction (x) and has a first conductivity type (e.g., p-type). The second active region 480b is substantially parallel to the first active region 480a, spaced apart from the first active region 480a along a second direction (y), and has a second conductivity type different from the first conductivity type (e.g., n-type). The third active region 480c is substantially parallel to the second active region 480b, spaced apart from the second active region 480a along the second direction (y), and has a first conductivity type. In this exemplary embodiment, the width (W) of the active regions 480a-480c is... M Within the range 1W ≤ W M ≤ 4W (3) In some embodiments, OHH cells (e.g., OHH cell C) OHH1 C OHH2 Width (W) OHH Within the range 0.4W ≤ W OHH ≤ 4W (4) Figure 5 This is a schematic diagram illustrating another example layout according to various embodiments of this disclosure. Figure 5 In the example layout 500 (or the device associated with it), there are units with different heights (H). T H S H OHH Multiple cells 510-530 are arranged in an array of rows (R1, R2) and columns (C1, C2). Each row (R1, R2) is defined by boundaries 540-560, each boundary extending along a first direction (x), and a row height (H) corresponding to the distance between boundaries 540-560 along a second direction (y). T H S The first column (C1) comprises a pair of unit cells. Unit cell 510 (e.g., the higher cell) is located in the first row (R1) and has a height corresponding to the row height (H). T The cell height is 520. A shorter cell, located in the second row (R2), has a height corresponding to the row height (H). S The cell height (H) is the cell height. In this exemplary embodiment, the cell height (H) is... S ) smaller than cell height (H) T ).

[0066] The second column (C2) includes OHH cells 530 spanning the first and second rows (R1, R2), with a cell height (H). OHH The cell height (H) is greater than that of the higher cell 510. TIn some embodiments, the OHH cell 530 has a top edge aligned with the top edge of the taller cell 510 and a bottom edge aligned with the center of the shorter cell 520. In these embodiments, the cell height (H) of the OHH cell 450 is... OHH It is basically equal to the cell height (H) T ) and half cell height (H S The sum of ) . In other embodiments, the OHH cell 530 has a bottom edge aligned with the bottom edge of the shorter cell 520 and a top edge aligned with the center of the taller cell 510. In these other embodiments, the cell height (H) of the OHH cell 530 OHH It is basically equal to the cell height (H) S ) and half cell height (H T The sum of ).

[0067] Figure 6 This is a schematic diagram illustrating another example layout according to various embodiments of this disclosure. Figure 6 In the example layout 600 (or associated device), multiple unit cells 610a-610b, 620a-620c, 630a, 630b, 640a-640c, and 650a-650d with different heights are arranged in an array of columns and rows. In at least one embodiment, layout 600 includes multiple cell structures (CS1-CS5), each including multiple unit cells. For example, the unit cells of cell structure (CS1) include a taller cell 610a in one row and a shorter cell 610b in an adjacent row. The unit cells of cell structure (CS2) include a pair of taller cells 620a and 620b in the first two rows, respectively, and a shorter cell 620c in the third row. The unit cells of cell structure (CS3) include three taller cells 630a-630c in the first three rows, respectively, and a shorter cell 630d in the next row. The unit cell in the cell structure (C4) includes the taller cell 640a in the first row (R1) and a pair of shorter cells 640b and 640c in the next two rows. The unit cell in the cell structure (CS5) includes the taller cell in the first row (R1) and three shorter cells in the next three rows.

[0068] Cell structures with a higher number of taller cells than shorter cells (e.g., cell structures CS2, CS3) are configured for performance-oriented purposes, such as speed, while cell structures with a higher number of shorter cells than taller cells (e.g., cell structures CS4, CS5) are configured for power and area-oriented purposes. For example, the number of taller and shorter cells determines the suitability of a cell structure for improving performance or power and area. In some embodiments, this suitability is represented by the equivalent cell height (HE) of the cell structure. For example, the equivalent cell height (H... E The determination of ) is as follows: (5) (6) In one example, for the cell structure (CS3), R MIX = 3 and H E =(3H T +H S ) / 4. In another example, for the cell structure (CS5), R MIX = 1 / 3 and H E =(H T +3H S ) / 4. That is to say, each R MIX and H E Increases towards cell unit structure (CS3) and decreases towards cell unit structure (CS5). Cell unit structure (CS1) has R MIX = 1 and H E =(H T +H S ) / 2. In at least one embodiment, H T +H S = 2H, resulting in the cell structure (CS1) having H E = H. This indicates that cell structures with the same height (H) have similar performance and power / area ratios compared to those with varying heights (H). T H S The cell columns of cells are equivalent. For example, when H E When the height is greater than H, the cell structures (CS2, CS3) offer a better performance improvement than cell structures with the same height. Therefore, cell structures (CS2, CS3) are suitable for velocity-oriented applications. Between cell structures (CS2, CS3), cell structure (CS2) offers a smaller performance improvement but has better power and area parameters than cell structure (CS3).

[0069] On the other hand, when H EWhen the height is less than H, the cell structures (CS4, CS5) offer better power and area improvements than cell structures with the same height. Between cell structures (CS4, CS5), cell structure (C4) offers smaller power and area improvements, but better performance (i.e., higher speed) than cell structure (CS5).

[0070] In some embodiments, an OHH cell is defined as a cell whose height is substantially equal to the sum of the height of one unit cell and half the height of another unit cell in an adjacent row. In one example, Figure 7 This is a schematic diagram illustrating another example layout according to various embodiments of this disclosure. For example... Figure 7 As shown, example layout 700 (or the device associated therewith) includes multiple units with different heights (H, H). OHH Cells 710-730 are arranged in an array of rows (R1, R2) and columns (C1, C2). Rows (R1, R2) are defined by boundaries 740-760, each extending along a first direction (x), and the row height (H) corresponds to the distance along a second direction (y) between boundaries 740-760. The first column (C1) comprises a pair of average height cells 710, 720. Each average height cell 710, 720 has a cell height corresponding to the row height (H).

[0071] The second column (C2) includes a cell height (H) that spans the first and second rows (R1, R2) and has a height greater than the cell height (H). OHH The OHH cell 730. In at least one embodiment, the OHH cell 730 has a bottom edge aligned with the bottom edge of the average height cell 720 and a top edge aligned with the center of the average height cell 710. In such at least one embodiment, the cell height (H) of the OHH cell 730 is... OHH Essentially, it is equal to the sum of the cell height (H) of the average height cell 720 and half the cell height (H) of the average height cell 710.

[0072] In another example, Figure 8 This is a schematic diagram illustrating another example layout according to various embodiments of this disclosure. For example... Figure 8 As shown, example layout 800 (or the device associated therewith) includes multiple units with different heights (H). T H S H OHH Cells 810-830 are arranged in rows (R1, R2) and columns (C1, C2) of an array. Rows (R1, R2) are defined by boundaries 840-860, each extending along a first direction (x), and the row height (H) is... S H TThe distance ( ) corresponds to the distance between boundaries 840 and 850 along the second direction (y). The first column (C1) comprises a pair of unit cells, namely the shorter cell 810 in the first row (R1) and the taller cell 820 in the second row (R2). Each unit cell 810, 820 has a height (H) corresponding to its respective row height. S H T The cell height (H) is the cell height in this example embodiment. S ) smaller than cell height (H) T ).

[0073] The second column (C2) includes a cell that spans the first and second rows (R1, R2) and has a cell height (H). T Larger cell height (H) OHH The OHH cell 830. In at least one embodiment, the OHH cell 830 has a bottom edge aligned with the bottom edge of the higher cell 820 and a top edge aligned with the center of the shorter cell 810. In such at least one embodiment, the cell height (H) of the OHH cell 830 is... OHH Essentially equal to cell height (H) T ) and half cell height (H S The sum of ).

[0074] In another example, Figure 9 This is a schematic diagram illustrating another example layout according to various embodiments of this disclosure. For example... Figure 9 As shown, example layout 900 (or the device associated therewith) includes multiple units with different heights (H). T H S H OHH The unit cells 910-930 are arranged in an array of rows (R1, R2) and columns (C1, C2). Rows (R1, R2) are defined by boundaries 940-960, each extending along a first direction (x), and the row height (H) is... S H T The distance ( ) corresponds to the distance along the second direction (y) between the boundaries 940-960. The first column (C1) comprises a pair of unit cells, namely the taller cell 910 and the shorter cell 920. Each unit cell 910, 920 has a height (H) corresponding to its respective row height. T H S The cell height (H) is the cell height in this example embodiment. S ) smaller than cell height (H) T ).

[0075] The second column (C2) includes a cell that spans the first and second rows (R1, R2) and has a cell height (H). T Larger cell height (H) OHHThe OHH cell 930. In at least one embodiment, the OHH cell 930 has a bottom edge aligned with the bottom edge of the shorter cell 920 and a top edge aligned with the center of the taller cell 910. In such at least one embodiment, the cell height (H) of the OHH cell 930 is... OHH Essentially equal to cell height (H) S ) and half cell height (H T The sum of ).

[0076] In another example, Figure 10 This is a schematic diagram illustrating another example layout according to various embodiments of this disclosure. For example... Figure 10 As shown, example layout 1000 (or the device associated therewith) includes multiple units with different heights (H). T H OHH Cells 1010-1030 are arranged in rows (R1, R2) and columns (C1, C2) of an array. Rows (R1, R2) are defined by boundaries 1040-1060, each boundary extending along a first direction (x), and the row height (H) is... T This corresponds to the distance along the second direction (y) between the boundary 1040 and 1060. The first column (C1) includes a pair of unit cells 1010 and 1020 (e.g., two higher cells). Each unit cell 1010 and 1020 has a value corresponding to the row height (H). T The cell height.

[0077] The second column (C2) includes a column that extends between the first and second rows (R1, R2) and has a cell height (H). T Larger cell height (H) OHH The OHH cell 1030. In at least one embodiment, the OHH cell 1030 has a bottom edge aligned with the bottom edge of the higher cell 1020 and a top edge aligned with the center of the higher cell 1010. In such at least one embodiment, the cell height (H) of the OHH cell 1030 is... OHH This is essentially equal to the cell height (H) of the higher cell 1020. T ) and half the cell height of the higher cell 1010 (H) T The sum of ).

[0078] In another example, Figure 11 This is a schematic diagram illustrating another example layout according to various embodiments of this disclosure. For example... Figure 11 As shown, example layout 1100 (or the device associated therewith) includes multiple units with different heights (H). S H OHHCells 1110-1130 are arranged in rows (R1, R2) and columns (C1, C2) of an array. Rows (R1, R2) are defined by boundaries 1140-1160, each boundary extending along a first direction (x), and the row height (H) is... S This corresponds to the distance along the second direction (y) between the boundaries 1140 and 1160. The first column (C1) comprises a pair of unit cells 1110 and 1120, for example, two shorter cells. Each unit cell 1110 and 1120 has a distance corresponding to the row height (H). S The cell height.

[0079] The second column (C2) includes a column that extends between the first and second rows (R1, R2) and has a cell height (H). S Larger cell height (H) OHH The OHH cell 1130. In at least one embodiment, the OHH cell 1130 has a bottom edge aligned with the bottom edge of the shorter cell 1120 and a top edge aligned with the center of the shorter cell 1110. In such at least one embodiment, the cell height (H) of the OHH cell 1130 is... OHH This is essentially equal to the cell height (H) of the shorter cell 1120. S ) and half the cell height of the shorter cell 1110 (H) S The sum of ).

[0080] Figure 12 This is a schematic diagram illustrating another example layout according to various embodiments of the present disclosure. Figure 12 In the example layout 1300 (or the device associated therewith), multiple units with different heights (H) are included. T H S H OHH1 H OHH2 Cells (C1-C4) arranged in rows (R1-R6) and columns (C1-C4) array. T C S C OHH1 C OHH2 The first column (C1) includes multiple unit cells, for example, taller and shorter cells (C...). T C S In some embodiments, taller and shorter cells (C) T C S The cells are arranged alternately in rows (R1-R6). In this example embodiment, the higher cells (C...) T ) has cell height (H) T ), while the dwarf cell (C S ) has a higher cell height (H) T Small cell height (H) S ).

[0081] The second column (C2) includes a pair of OHH cells (C OHH1 ) and a pair of OHH cells (C OHH2 Each OHH cell (C OHH1 C OHH2 () spans a pair of adjacent rows. For example, the first OHH cell (C OHH1 ) has a higher cell (C) in the first row (R1) T The top edge of the cell is aligned with the top edge of the cell in the second row (R2), and with the lower cell in the second row (C). S The center of the cell is aligned with the bottom edge. The second OHH cell (C OHH1 ) has a higher cell (C) in the third row (R3) T The bottom edge of the cell is aligned with the bottom edge of the cell in the second row (R2), and with the lower cell in the second row (C). S The center of the cell is aligned with the top edge. In this example embodiment, the OHH cell (C OHH1 C OHH2 Cell height (H) OHH1 It has a value substantially equal to the cell height (H) T ) and half cell height (H S The sum of ) . In this example embodiment, OHH cells (C OHH1 Cell height (H) OHH1 Essentially equal to cell height (H) T ) and half cell height (H S The sum of ).

[0082] Similarly, the first OHH cell unit (C OHH2 ) has the same characteristics as the shorter cells (C) in the fourth row (R4). S The top edge of the cell is aligned with the top edge of the cell in the fifth row (R5), and with the higher cell in the fifth row (C). T The center of the cell is aligned with the top edge. The second OHH cell (C OHH2 ) has the same lower cell (C) as the sixth row (R6) S The bottom edge of the cell is aligned with the bottom edge of the cell in the fifth row (R5), and with the higher cell in the fifth row (C). T The center of the cell is aligned with the top edge. In some embodiments, the OHH cell (C OHH2 Cell height (H) OHH2 Essentially equal to cell height (H) S ) and half cell height (H T The sum of ) . In some of these embodiments, the cell height (H OHH2 ) smaller than cell height (H) OHH1 ).

[0083] The third column (C3) includes a pair of OHH cells (C OHH1 Each OHH cell (C OHH1 It spans a pair of adjacent rows and has a height greater than the cell height (H). T Cell height (H) OHH1 For example, the first OHH cell unit (C OHH1 ) has a higher cell (C) in the third row (R3) T The top edge of the cell is aligned with the top edge of the cell in the fourth row (R2), and with the lower cell in the fourth row (R2). S The center of the cell is aligned with the bottom edge. The second OHH cell (C OHH1 ) has a higher cell (C) in the fifth row (R5) T The bottom edge of the cell is aligned with the bottom edge of the cell in the fourth row (R4), and with the lower cell in the fourth row (R4). S The center of the cell is aligned with the top edge. In this example embodiment, the OHH cell (C OHH1 Cell height (H) OHH1 Essentially equal to cell height (H) T ) and half cell height (H S The sum of ).

[0084] The fourth column (C4) includes multiple unit cells, such as taller and shorter cells (C... T C S In some embodiments, taller and shorter cells (C) T C S The cells are arranged alternately between rows (R3-R6). In this example embodiment, the higher cells (C...) T ) has cell height (H) T ), while the dwarf cell (C S ) has a height smaller than the cell height (H) T Cell height (H) S ).

[0085] Figure 13 This is a schematic diagram illustrating another example layout according to various embodiments of the present disclosure. Figure 13 In the example layout 1300 (or the device associated therewith), multiple units with different heights (H) are included. T H S H OHH1 H OHH2 H OHH3 H OHH4 ) cell unit (C T C S C OHH1 C OHH2 C OHH3 COHH4 These cells are arranged in an array of rows (R1-R12) and columns (C1, C2). The first column (C1) includes multiple unit cells (e.g., taller and shorter cells (C1, C2)). T C S In some embodiments, adjacent taller and shorter cells (C) T C S The pairs are arranged alternately between rows (R1-R6). In this example embodiment, the higher cells (C...) T ) has cell height (H) T ), while the dwarf cell (C S ) has a height smaller than the cell height (H) T Cell height (H) S ).

[0086] The second column (C2) includes a pair of OHH cells (C OHH1 ), a pair of OHH cells (C OHH2 ), a pair of OHH cells (C OHH3 ), a pair of OHH cells (C OHH4 Each OHH cell (C OHH1 C OHH2 C OHH3 C OHH4 () spans a pair of adjacent rows. For example, the first OHH cell (C OHH1 ) has the same characteristics as the shorter cells (C) in the first row (R1). S The top edge of the cell is aligned with the top edge of the cell in the second row (R2), and with the lower cell in the second row (C). S The center of the cell is aligned with the bottom edge. The first OHH cell (C OHH2 ) has a higher cell (C) in the third row (R3) T The bottom edge of the cell is aligned with the bottom edge of the cell in the second row (R2), and with the lower cell in the second row (C). S The center of the top edge is aligned with the center of the top edge.

[0087] Second OHH cell line (C OHH2 ) has a higher cell (C) in the fourth row (R4) T The top edge of the cell is aligned with the top edge of the cell in the fifth row (R5), and with the lower cell in the fifth row (C). S The center of the cell is aligned with the bottom edge. The second OHH cell (C OHH1 ) has the same lower cell (C) as the sixth row (R6) S The bottom edge of the cell is aligned with the bottom edge of the cell in the fifth row (R5), and with the lower cell in the fifth row (R5). S The center of the top edge is aligned with the center of the top edge.

[0088] Similarly, the first OHH cell unit (C OHH3 ) has a higher cell (C) in the seventh row (R7) T The top edge of the cell is aligned with the top edge of the cell in the eighth row (R8), and with the higher cell in the eighth row (C). T The center of the cell is aligned with the bottom edge. The first OHH cell (C OHH4 ) has the same lower cell (C) as the ninth row (R9) S The bottom edge of the cell is aligned with the bottom edge of the cell in the eighth row (R8), and with the higher cell in the eighth row (C). T The center of the top edge is aligned with the center of the top edge.

[0089] Second OHH cell line (C OHH4 ) has the same lower cell (C) as the tenth row (R10) S The top edge of the cell is aligned with the top edge of the cell in row eleven (R11), and with the higher cell (C) in row eleven (R11). T The center of the cell is aligned with the bottom edge. The second OHH cell (C OHH3 ) has a higher cell (C) in the twelfth row (R12). T The bottom edge of the cell is aligned with the bottom edge of the cell in row eleven (R11), and with the higher cell (C) in row eleven (R11). T The center of the top edge is aligned with the center of the top edge.

[0090] In some embodiments, OHH cells (C OHH1 Cell height (H) OHH1 Essentially equal to cell height (H) S ) and half cell height (H S The sum of OHH cells (C OHH2 Cell height (H) OHH2 Essentially equal to cell height (H) T ) and half cell height (H S The sum of OHH cells (C OHH3 Cell height (H) OHH3 Essentially equal to cell height (H) T ) and half cell height (H T The sum of OHH cells (C OHH4 Cell height (H) OHH4 Essentially equal to cell height (H) S ) and half cell height (H T The sum of ).

[0091] In these specific embodiments, the following relationship is satisfied: H S < H T < H OHH1 < HOHH4 < H OHH2 < H OHH3 (7) Figure 14 This is a schematic diagram illustrating another example layout according to various embodiments of the present disclosure. Figure 14 In the example layout 1400 (or the device associated therewith), there are cells with different cell heights (H). T H S H OHH Multiple cells (C1, C2) arranged in an array of rows (R1-R3) and columns (C1, C2) T1 C T2 C S C OHH1 C OHH2 The first column (C1) includes multiple unit cells (e.g., a pair of higher cells (C) T1 C T2 ) and located in higher cells (C T1 C T2 The shorter cells (C) between ) S In this example embodiment, the higher cell (C) T1 C T2 ) has cell height (H) T ), while the dwarf cell (C S ) has a height smaller than the cell height (H) T Cell height (H) S ).

[0092] The second column (C2) includes a pair of OHH cells (C OHH1 C OHH1 Each of these cells overlaps with a pair of adjacent rows. For example, the OHH cell (C OHH1 ) has higher cell type (C T1 The top edge of the cell is aligned with the top edge of the cell, and with the lower cell (C). S The center of the cell is aligned with the bottom edge. Similarly, the OHH cell (C OHH2 ) has higher cell type (C T2 The bottom edge of the cell is aligned with the bottom edge of the lower cell (C). S The center of the cell is aligned with the bottom edge. In this example embodiment, the OHH cell (C OHH1 C OHH2 Cell height (H) OHH Essentially equal to cell height (H) T ) and half cell height (H S The sum of ).

[0093] The layout also includes multiple metal layers (M0) located in the cell (C).T1 C T2 C S C OHH1 C OHH2 Between the power rails (e.g., power rails VDD, VSS) and the metal layer (M0). The metal layer (M0) may correspond to the first metal layer in the metal stack. In at least one embodiment, the metal layer (M0) includes large, medium, and small width metal lines (M... H M T M S Metal wire (M) H Connect cells of the same height in a column (e.g., average height cells 710, 720) to power rails (VDD, VSS) and facilitate signal routing between average height cells 710, 720. Metal wire (M) T Connecting unit cells (e.g., higher cell C) T1 C T2 ) to power rails (VDD, VSS) and promote higher cells (C T1 C T2 Signal wiring between (M) wires. S Connecting unit cells (e.g., the shorter cell C) S ) to power rails (VDD, VSS) and promote the lower dwarf cells (C S Signal wiring between (M). In this example embodiment, the metal wire (M) H The width of the wire is smaller than that of the metal wire (M). T The width of the wire is greater than that of the metal wire (M). S The width of the metal lines in the metal layer (M0). This strategic variation in the width of the metal lines also contributes to achieving the overall optimal PPA of the device disclosed herein.

[0094] Figure 15 This is a flowchart of an example method for manufacturing an apparatus according to various embodiments of the present disclosure. For ease of understanding, reference will now be made to... Figure 1-14 Example method 1500 is described further. It can be understood that method 1500 is applicable to... Figure 1-14 Structures other than those shown. Furthermore, it is understood that additional operations may be provided before, during, and after method 1500, and in alternative embodiments of method 1500, some of the operations described below may be replaced or eliminated.

[0095] In operation 1510, the device manufacturing system places multiple unit cells in the first column (C1) rows (R1-R3) in the layout. The unit cells include the higher cells (C1, R1, R3) in the first row (R1). T1 The shorter cells (C) in the second row (R2) S ), and another higher cell (C) in the third row (R3). T2In operation 1520, the device manufacturing system places one or more OHH cells (C) in the layout. OHH1 C OHH2 ) in the second column. For example, the first OHH cell (C OHH1 ) spans the first and second rows (R1, R2), while the first OHH cell (C OHH2 () Spanning the second and third rows (R2, R3). In operation 1530, the device manufacturing system places multiple active regions in the layout within each cell (C). T1 C T2 C S C OHH1 C OHH2 In operation 1540, the device fabrication system places a gate region in a layout, the gate region spanning the active region. In operation 1540, the device fabrication system places source and drain regions in a layout, the source and drain regions being on opposite sides of the gate region in the active region. In operation 1540, the device fabrication system uses a layout fabrication apparatus.

[0096] Figure 16 This is a schematic block diagram of an example electronic design automation (EDA) system 1600 according to various embodiments of the present disclosure. Figure 16 In this example, EDA system 1600 includes an automated placement and routing (APR) system. The design layout diagrams described herein represent methods of arranging wire wiring, which, according to one or more embodiments, can be implemented, for example, using EDA system 1600.

[0097] In at least one embodiment, the EDA system 1600 is a general-purpose computing device including a hardware processor 1610 and a non-transitory computer-readable storage medium 1620. The computer-readable storage medium 1620, among other things, is encoded (i.e. stores) computer program code 1630, a set of executable instructions. The instructions 1630, executed by the hardware processor 1610, represent (at least partially) an EDA tool that implements part or all of the methods described herein (hereinafter referred to as the process and / or method) according to one or more embodiments.

[0098] Processor 1610 is electrically coupled to computer-readable storage medium 1620 via bus 1640. Processor 1610 is also electrically coupled to I / O interface 1650 via bus 1640. Network interface 1660 is also electrically connected to processor 1610 via bus 1640. Network interface 1660 is connected to network 1670, enabling processor 1610 and computer-readable storage medium 1620 to be connected to external components via network 1670. Processor 1610 is configured to execute computer program code 1630 encoded in computer-readable storage medium 1620 to make system 1600 available for performing part or all of the process and / or method. In one or more embodiments, processor 1610 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or a suitable processing unit.

[0099] In at least one embodiment, the computer-readable storage medium 1620 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1620 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In some embodiments using optical disk, the computer-readable storage medium 1620 includes a compact disk-read-only memory (CD-ROM), an optical disc read / write (CD-R / W), and / or a digital video disc (DVD).

[0100] In this example embodiment, computer-readable storage medium 1620 stores computer program code 1630 configured to enable system 1600 (where such execution representation, at least partially, an EDA tool) to perform part or all of the process and / or method. In one embodiment, computer-readable storage medium 1620 also stores information that facilitates the execution of part or all of the process and / or method. In such an embodiment, computer-readable storage medium 1620 stores a standard cell library 1680, including the standard cells disclosed herein.

[0101] I / O interface 1650 is coupled to external circuitry. In some embodiments, I / O interface 1650 includes a keyboard, keypad, mouse, trackball, trackpad, touchscreen, and / or cursor arrow keys for conveying information and commands to processor 1610.

[0102] Network interface 1660 is coupled to processor 1610. Network interface 1660 allows system 1600 to communicate with network 1670, to which one or more other computer systems are connected. Network interface 1660 includes a wireless network interface such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, part or all of the process and / or method is implemented in two or more systems 1600.

[0103] System 1600 is configured to receive information via I / O interface 1650. The information received via I / O interface 1650 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters processed by processor 1302. The information is transmitted to processor 1610 via bus 1640. EDA system 1600 is configured to receive UI-related information via I / O interface 1650. This information is stored as a user interface (UI) 1690 in computer-readable storage medium 1620.

[0104] In some embodiments, part or all of the process and / or method is implemented as a standalone software application executed by a processor. In other embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In one embodiment, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In one or more embodiments, part or all of the process and / or method is implemented as a software application used by the EDA system 1600. In at least one embodiment, a layout diagram including standard cells is generated using a tool such as VIRTUOSO®, available from CADENCE DESIGN SYSTEMS, or other suitable layout generation tools.

[0105] In one embodiment, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage or memory units, such as one or more optical discs, like DVDs; magnetic disks, such as hard disks; semiconductor memories, such as ROM, RAM, memory cards, etc.

[0106] Figure 17This is a schematic block diagram of an exemplary integrated circuit (IC) manufacturing system 1700 according to various embodiments. In at least one embodiment, based on a layout diagram, the manufacturing system 1700 is used to manufacture at least one component of one or more semiconductor masks or at least one layer of a semiconductor integrated circuit. Figure 14 In this example, the IC manufacturing system 1700 includes entities such as a design studio 1710, a mask manufacturing terminal 1720, and an IC wafer fab / manufacturer (or wafer foundry) 1730, which interact with each other in design, development, and manufacturing cycles and / or services related to the manufacture of IC devices 1740. The entities in system 1700 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as intranets and the internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of the design studio 1710, mask manufacturing terminal 1720, and IC wafer fab 1730 are owned by a single, larger company. In other embodiments, two or more of the design studio 1710, mask manufacturing terminal 1720, and IC wafer fab 1730 coexist in a shared facility and use shared resources.

[0107] Design studio (or design team) 1710 generates IC design layout 1710'. IC design layout 1710' includes various geometric patterns designed for IC device 1740. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute various components of the IC device 1740 to be manufactured. Various layer combinations form various IC features. For example, a portion of IC design layout 1710' includes various IC features such as active regions, gate electrodes, source and drain electrodes, metal lines or vias for interlayer interconnects, and openings for bonding pads, which will be formed in a semiconductor substrate (such as a silicon wafer), and various material layers will be disposed on the semiconductor substrate. Design studio 1710 implements appropriate design procedures to form IC design layout 1710'. Design procedures include one or more of logic design, physical design, or placement and routing operations. IC design layout 1710 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1710' can be expressed in GDSII file format or DFII file format.

[0108] Mask manufacturing end 1720 includes data preparation 1750 and mask manufacturing 1760. Mask manufacturing end 1720 uses an IC design layout 1710' to manufacture one or more masks 1760' for manufacturing various layers of an IC device 1740 according to the IC design layout 1710'. Mask manufacturing end 1720 performs mask data preparation 1750, where the IC design layout 1710' is translated into a representative data file (RDF). Mask data preparation 1750 provides the RDF for mask manufacturing 1760. Mask manufacturing 1760 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a mask (photomask) 1760' or a semiconductor wafer 1770'. The design layout 1710' is manipulated by mask data preparation 1750 to conform to the specific characteristics of the mask writer and / or the requirements of the IC wafer fab 1730. Figure 17 In this embodiment, mask data preparation 1750 and mask manufacturing 1760 are shown as separate components. In some embodiments, mask data preparation 1750 and mask manufacturing 1760 may be collectively referred to as mask data preparation.

[0109] In some embodiments, mask data preparation 1750 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout (Figure 1710'). In at least one embodiment, mask data preparation 1750 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution auxiliary features, phase-transfer masks, other suitable techniques, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0110] In some embodiments, mask data preparation 1750 includes a mask rule checker (MRC) that examines the IC design layout 1710' processed in the OPC using a set of mask creation rules that include certain geometric and / or connectivity constraints to ensure sufficient margins, taking into account variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1710' to compensate for constraints during mask fabrication 1760, which may undo some modifications performed by the OPC to conform to the mask creation rules.

[0111] In one or more embodiments, mask preparation 1750 includes lithography process checking (LPC), a simulation of a process performed by IC wafer fab 1730 to manufacture IC device 1740. The LPC simulates this process based on IC design layout 1710' to create a simulated manufactured device, such as IC device 1740. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture IC device 1740, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, and combinations thereof. In some embodiments, after the LPC has created the simulated manufactured device, if the simulated device is not close enough in shape to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1710'.

[0112] It should be understood that, for clarity, the above description of mask data preparation 1750 has been simplified. In some embodiments, data preparation 1750 includes additional features, such as logic operations (LOPs), to modify the IC design layout 1710' according to manufacturing rules. Furthermore, the processes applied to the IC design layout 1710' during data preparation 1750 can be performed in various different sequences.

[0113] After mask data preparation 1750 and during mask fabrication 1760, a mask 1760' or a set of masks 1760' is fabricated based on the modified IC design layout 1710'. In some embodiments, mask fabrication 1760 includes performing one or more photolithographic exposures based on the IC design layout 1710'. In other embodiments, a mechanism of electron beam (e-beam) or multiple electron beams is used to form a pattern on the mask (photomask or photomask) 1760' based on the modified IC design layout 1710'. The mask 1760' can be formed using various techniques. In one embodiment, a binary technique is used to form the mask 1760'. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam, such as an ultraviolet (UV) beam, used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer is blocked by the opaque areas and travels through the transparent areas. In one example, the binary mask version of mask 1760' comprises a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, mask 1760' is formed using a phase shift mask (PSM) technique. In the phase shift mask (PSM) version of mask 1760', various features in the pattern formed on the phase shift mask are configured to have appropriate phase differences to enhance resolution and imaging quality. In various examples, the phase shift mask can be attenuated PSM or alternating PSM. The mask generated by mask fabrication 1760 is used in a variety of processes. For example, such a mask is used in ion implantation processes to form various doped regions in semiconductor wafer 1770', in etching processes to form various etched regions in semiconductor wafer 1770', and / or in other suitable processes.

[0114] IC wafer fab 1730 is an IC manufacturing business that includes one or more manufacturing facilities for manufacturing various IC products. In some embodiments, IC wafer fab 1730 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing (front-end-of-line (FEOL) manufacturing) of multiple IC products, a second manufacturing facility that can provide back-end manufacturing (back-end-of-line (BEOL) manufacturing) for interconnection and packaging of IC products, and a third manufacturing facility that can provide other services for the foundry business.

[0115] IC wafer fab 1730 includes manufacturing tools 1770 configured to perform various manufacturing operations on semiconductor wafers 1770', such that IC devices 1740 are manufactured according to a mask (e.g., mask 1760'). In various embodiments, manufacturing tools 1770 include one or more wafer steppers, ion implanters, photoresist coaters, process chambers (e.g., CVD chambers or LPCVD furnaces), CMP systems, plasma etching systems, wafer cleaning systems, or other manufacturing equipment capable of performing one or more suitable manufacturing processes as described herein.

[0116] IC wafer fab 1730 uses a mask 1760' manufactured by mask fabrication end 1720 to manufacture IC device 1740. Therefore, IC wafer fab 1730 uses IC design layout 1710' at least indirectly to manufacture IC device 1740. In some embodiments, semiconductor wafer 1770' is manufactured by IC wafer fab 1730 using mask 1760' to form IC device 1740. In some embodiments, IC manufacturing includes performing one or more photolithographic exposures at least indirectly based on IC design layout 1710'. Semiconductor wafer 1770' includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1770' further includes one or more various doped regions, dielectric features, multilayer interconnects, etc. (formed in subsequent manufacturing steps).

[0117] In one embodiment, a semiconductor device includes a plurality of cells, a plurality of active regions, a plurality of gate regions, a plurality of source and drain electrodes, and a plurality of power rails. The cells are arranged in an array of columns and rows, including one or more taller cells, one or more shorter cells, and one or more half-height (OHH) cells. The shorter cells have a smaller cell height than the taller cells. The half-height cells have a larger cell height than the taller cells. An active region is formed in each cell. The active region includes a first conductivity type and a second conductivity type opposite to the first conductivity type. A gate region extends across the active region. Sources and drains are formed in the active regions on opposite sides of the gate region. The power rails include a first power rail and a second power rail that define the top and bottom boundaries of the cell, respectively.

[0118] In one embodiment, the taller cell is located in a first column; the shorter cell is located in a second column; and the OHH cell spans the first and second columns, wherein the OHH cell has a top edge aligned with the top edge of the taller cell and a bottom edge aligned with the center of the shorter cell. In one embodiment, a tall cell is located in the first column; a shorter cell is located in the second column; and an OHH cell is located in both the first and second columns, wherein the OHH cell has a bottom edge aligned with the bottom edge of the shorter cell and a top edge aligned with the center of the taller cell. In one embodiment, the cell height of the OHH cell is substantially equal to the cell height of the taller cell plus half the cell height of the shorter cell. In one embodiment, the cell height of the OHH cell is substantially equal to the cell height of the shorter cell plus half the cell height of the taller cell. In one embodiment, one or more average height cells are included, having an average cell height greater than the cell height of the shorter cell and less than the cell height of the taller cell. In one embodiment, a first average height cell is located in a first column; a second average height cell is located in a second column; and an OHH cell spans the first column and the second column, wherein the OHH cell has a top edge aligned with the top edge of the first average height cell and a bottom edge aligned with the center of the second average height cell.

[0119] In another embodiment, a semiconductor device includes a plurality of cells, a plurality of active regions, a plurality of gate regions, a plurality of source and drain electrodes, and a plurality of power rails. The cells are arranged in an array of columns and rows, including one or more average-height cells, a plurality of unit cells, and one or more half-height (OHH) cells. Higher cells have a greater cell height than average-height cells. Lower cells have a smaller cell height than average-height cells. Half-height cells have a greater cell height than higher cells. An active region is formed in each cell. The active region includes a first conductivity type and a second conductivity type opposite to the first conductivity type. A gate region extends across the active region. Sources and drains are formed in the active regions on opposite sides of the gate region. The power rails include a first power rail and a second power rail that define the top and bottom boundaries of the cell, respectively.

[0120] In another embodiment, the taller cell is located in a first column; the shorter cell is located in a second column; and the OHH cell spans the first and second columns, wherein the OHH cell has a top edge aligned with the top edge of the taller cell and a bottom edge aligned with the center of the shorter cell. In another embodiment, the shorter cell is located in a first column; the taller cell is located in a second column; and the OHH cell spans the first and second columns, wherein the OHH cell has a top edge aligned with the top edge of the shorter cell and a bottom edge aligned with the center of the taller cell. In another embodiment, a first average height cell is located in a first column; a second average height cell is located in a second column; and the OHH cell spans the first and second columns, wherein the OHH cell has a top edge aligned with the top edge of the first average height cell and a bottom edge aligned with the center of the second average height cell. In another embodiment, it further includes: a first taller cell located in a first column; a second taller cell located in a second column; and an OHH cell spanning the first and second columns, having a cell height substantially equal to the sum of the cell height of the first taller cell and half the cell height of the second taller cell. In another embodiment, it further includes: a first shorter cell located in a first column; a second shorter cell located in a second column; and an OHH cell spanning the first and second columns, having a cell height substantially equal to the sum of the cell height of the first shorter cell and half the cell height of the second shorter cell. In another embodiment, it further includes merged cells spanning the first and second columns. In another embodiment, it further includes a plurality of taller cells and a plurality of shorter cells arranged alternately across multiple columns. In another embodiment, it further includes adjacent pairs of taller and shorter cells arranged alternately across multiple columns.

[0121] In another embodiment, a method of manufacturing a semiconductor device includes: fabricating a plurality of cells on a semiconductor substrate, arranged in an array of columns and rows, wherein fabricating the plurality of cells includes: fabricating a pair of first power rails defining a higher cell; fabricating a pair of second power rails defining a lower cell, wherein the lower cell has a smaller cell height than the higher cell; fabricating a pair of third power rails defining a half-height (OHH) cell, wherein the cell height of the OHH cell is substantially equal to the sum of the cell height of one of the higher cell and the lower cell and half the cell height of the other of the higher cell and the lower cell; patterning one or more active regions in each cell; forming a gate structure on the active regions; and doping the active regions to form source and drain regions on opposite sides of the gate structure.

[0122] In another embodiment, the method further includes: placing the taller and shorter cells in a first row, spanning a first and a second column of the layout; and placing the OHH cells in a second row such that the OHH cells span the first and second columns. In another embodiment, the method further includes: forming the unit cell by placing a pair of cut sections on the top and bottom edges of the taller or shorter cell, respectively; and placing a pair of power rails on the cut sections, respectively. In another embodiment, the method further includes: forming the OHH cell by placing a pair of cut sections on the top and bottom edges of the OHH cell, respectively; placing a first power rail on the cut section at the top edge of the OHH cell; placing a second power rail between the cut sections; and placing a third power rail such that the cut section at the bottom edge of the OHH cell is positioned between the second and third power rails.

[0123] In another embodiment, a method of manufacturing a semiconductor device includes: fabricating a plurality of cells arranged in an array of columns and rows on a semiconductor substrate, including: forming an active region in each cell; forming a gate region through the active region; and forming source and drain regions in the active region opposite to the gate region. The cell includes one or more taller cells, one or more shorter cells, and one or more half-height (OHH) cells. The shorter cells have a smaller cell height than the taller cells. The half-height cell has a cell height substantially equal to the sum of the cell height of one of the taller and shorter cells and half the cell height of the other taller or shorter cell. The active region includes a first conductivity type and a second conductivity type opposite to the first conductivity type.

[0124] The foregoing has outlined the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions should not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Multiple cells are arranged in an array of columns and rows, wherein the multiple cells include: One or more higher cells; One or more shorter cells having a smaller cell height than the taller cells; and One or more half-height (OHH) cells have a cell height greater than that of the higher cell; Multiple active regions are formed in each cell, wherein the active regions include a first conductivity type and a second conductivity type opposite to the first conductivity type; Multiple gate regions, each extending across the active region; Multiple source and drain electrodes are formed in the active region, located on opposite sides of the gate region; and Multiple power rails, including a first power rail and a second power rail, define the top and bottom boundaries of a cell, respectively.

2. The semiconductor device according to claim 1, characterized in that: The higher cell is located in the first row; The shorter cell is located in the second row; and The OHH cell spans the first row and the second row, wherein the OHH cell has a top edge aligned with the top edge of the taller cell and a bottom edge aligned with the center of the shorter cell.

3. The semiconductor device according to claim 1, characterized in that, The cell height of the OHH cell is substantially equal to the cell height of the higher cell plus half the cell height of the lower cell.

4. The semiconductor device according to claim 1, characterized in that, The cell height of the OHH cell is substantially equal to the cell height of the shorter cell plus half the cell height of the taller cell.

5. The semiconductor device according to claim 1, characterized in that, It also includes one or more average height cells having an average cell height greater than the cell height of the shorter cell and less than the cell height of the taller cell.

6. The semiconductor device according to claim 1, characterized in that: The first average height cell is located in the first row; A second average height cell, located in the second row; and An OHH cell spans the first row and the second row, wherein the OHH cell has a top edge aligned with the top edge of the first average height cell and a bottom edge aligned with the center of the second average height cell.

7. A semiconductor device, characterized in that, include: Multiple cells arranged in an array of columns and rows, wherein the multiple cells include: One or more average height cells; Multiple unit cells, including: A higher-height cell has a cell height greater than that of the average-height cell; A shorter cell, having a cell height smaller than that of the average height cell; and One or more half-height (OHH) cells have a cell height greater than that of the higher cell; Multiple active regions are formed in each cell, wherein the active regions include a first conductivity type and a second conductivity type opposite to the first conductivity type; Multiple gate regions, each extending across the active region; Multiple source and drain electrodes are formed in the active region, located on opposite sides of the gate region; and Multiple power rails, including a first power rail and a second power rail, define the top and bottom boundaries of a cell, respectively.

8. The semiconductor device according to claim 7, characterized in that: The higher cell is located in the first row; The shorter cell is located in the second row; and The OHH cell spans the first and second rows, wherein the OHH cell has a top edge aligned with the top edge of the taller cell and a bottom edge aligned with the center of the shorter cell.

9. The semiconductor device according to claim 7, characterized in that: The first average height cell is located in the first row; A second average height cell, located in the second row; and The OHH cell spans the first row and the second row, wherein the OHH cell has a top edge aligned with the top edge of the first average height cell and a bottom edge aligned with the center of the second average height cell.

10. A method for manufacturing a semiconductor device, characterized in that, include: Fabricating multiple cells on a semiconductor substrate, arranged in an array of columns and rows, wherein fabricating said multiple cells includes: Create a pair of first power rails that define a higher cell; Manufacture a pair of second power rails defining a shorter cell, wherein the shorter cell has a smaller cell height than the taller cell; Manufacture a pair of third power rails defining half-height (OHH) cells, wherein the cell height of the OHH cell is substantially equal to the sum of the cell height of one of the higher cell and the lower cell and half the cell height of the other of the higher cell and the lower cell; Pattern one or more active regions in each cell; A gate structure is formed on the active region; and The active region is doped to form source and drain regions on opposite sides of the gate structure.

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