Display panel and electronic device

Abstract

An embodiment of the present invention discloses a display panel and an electronic device. The display panel includes: a first pixel electrode and a second pixel electrode spaced apart from each other; a barrier layer including a first opening corresponding to the first pixel electrode and a second opening corresponding to the second pixel electrode; a counter electrode disposed on the barrier layer and overlapping the first pixel electrode and the second pixel electrode; a first intermediate layer sandwiched between the first pixel electrode and the counter electrode, wherein the first intermediate layer includes a first sub-stack body overlapping the first pixel electrode and including a first sub-emitting layer emitting light of a first color, and a second sub-stack body disposed on the first sub-stack body and including a second sub-emitting layer emitting light of the same color as the first sub-emitting layer; the display panel further includes: a second intermediate layer sandwiched between the second pixel electrode and the counter electrode, overlapping the second pixel electrode, and including a second emitting layer emitting light of a second color different from the first color.

Description

Technical Field

[0001] Embodiments of the present invention provide a display panel and an electronic device including the display panel. Background Technology

[0002] Recently, display panels have been used in electronic devices for various purposes. As the application of display panels becomes more widespread, the demand for high-resolution display panels and display panels of various shapes is increasing, and research on space utilization of display panels is ongoing in order to achieve high-resolution display panels. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel with a long lifespan and high-quality image output, and an electronic device including the display panel. However, these technical problems are exemplary, and the scope of the present invention is not limited thereto.

[0004] An embodiment of the present invention discloses a display panel, the display panel comprising: a first pixel electrode and a second pixel electrode spaced apart from each other; a dam layer including a first opening corresponding to the first pixel electrode and a second opening corresponding to the second pixel electrode; a counter electrode disposed on the dam layer and overlapping the first pixel electrode and the second pixel electrode; a first intermediate layer sandwiched between the first pixel electrode and the counter electrode, and including a first sub-stack body overlapping the first pixel electrode and including a first sub-emitting layer emitting light of a first color, and a second sub-stack body disposed on the first sub-stack body and including a second sub-emitting layer emitting light of the same color as the first sub-emitting layer; and a second intermediate layer sandwiched between the second pixel electrode and the counter electrode, overlapping the second pixel electrode, and including a second emitting layer emitting light of a second color different from the first color, wherein a portion of the second intermediate layer is sandwiched between the first sub-stack body and the second sub-stack body on a first portion of the dam layer between the first pixel electrode and the second pixel electrode.

[0005] The display panel may further include a hole injection layer, wherein the hole injection layer overlaps with the first pixel electrode, the first portion of the dam layer and the second pixel electrode, and is sandwiched between the first pixel electrode and the first intermediate layer and between the second pixel electrode and the second intermediate layer.

[0006] The first intermediate layer may include: a charge generation layer sandwiched between the first sub-light-emitting layer and the second sub-light-emitting layer, and includes an electron generation layer and a hole generation layer, wherein the electron generation layer may be a sub-layer of the first sub-stack, and the hole generation layer may be a sub-layer of the second sub-stack.

[0007] The first sub-stack may include: a first sub-light-emitting layer; a first sub-hole transport layer located between the first pixel electrode and the first sub-light-emitting layer; an electron-generating layer located on the opposite side of the first sub-hole transport layer, separated from the first sub-light-emitting layer; and a first sub-electron transport layer located between the first sub-light-emitting layer and the electron-generating layer.

[0008] The second sub-stack may include: a second sub-light-emitting layer; a hole-generating layer located between the first sub-stack and the second sub-light-emitting layer; and a second sub-hole-transporting layer located between the hole-generating layer and the second sub-light-emitting layer.

[0009] The width of each of the electron generation layer and the first sub-electron transport layer of the first sub-stack may be smaller than the width of the second sub-hole transport layer.

[0010] The display panel may further include an electron transport layer sandwiched between the opposing electrode and the second sub-stack of the first intermediate layer.

[0011] The electron transport layer may extend in a manner sandwiched between the opposing electrode and the second intermediate layer, and overlap with the second sub-stack of the first intermediate layer, the second intermediate layer, and the first portion of the dam layer.

[0012] The first color can be blue, and the second color can be red or green.

[0013] The display panel may further include: a third pixel electrode, spaced apart from the first pixel electrode; and a third intermediate layer, sandwiched between the third pixel electrode and the opposing electrode, overlapping the third pixel electrode, and including a third light-emitting layer that emits light of a third color different from the first color and the second color, wherein a portion of the third intermediate layer may be sandwiched between the first sub-stack and the second sub-stack on a second portion of the dam layer between the first pixel electrode and the third pixel electrode.

[0014] An embodiment of the present invention discloses an electronic device comprising a display panel including a first pixel, a second pixel, and a third pixel. The display panel includes: a first pixel electrode corresponding to the first pixel; a second pixel electrode corresponding to the second pixel and spaced apart from the first pixel electrode; a diaphragm layer including a first opening corresponding to the first pixel electrode and a second opening corresponding to the second pixel electrode; a counter electrode disposed on the diaphragm layer and overlapping the first pixel electrode and the second pixel electrode; and a first intermediate layer sandwiched between the first pixel electrode and the counter electrode, and including a first [unclear - possibly a first color] layer overlapping the first pixel electrode and containing light emitting a first color. The first sub-stack of a sub-emitting layer and a second sub-stack disposed on the first sub-stack and including a second sub-emitting layer emitting light of the same color as the first sub-emitting layer; and a second intermediate layer sandwiched between the second pixel electrode and the opposing electrode, overlapping the second pixel electrode, and including a second emitting layer emitting light of a second color different from the first color, wherein the first sub-stack includes an electron generating layer, and the second sub-stack includes a hole generating layer, and a portion of the second intermediate layer is sandwiched between the electron generating layer and the hole generating layer on a first portion of the dam layer between the first pixel electrode and the second pixel electrode.

[0015] The display panel may further include a hole injection layer, wherein the hole injection layer may overlap with the first pixel electrode, the first portion of the dam layer and the second pixel electrode, and may be sandwiched between the first pixel electrode and the first intermediate layer and between the second pixel electrode and the second intermediate layer.

[0016] The first sub-stack may include: a first sub-light-emitting layer; a first sub-hole transport layer located between the first pixel electrode and the first sub-light-emitting layer; an electron-generating layer located on the opposite side of the first sub-hole transport layer, separated from the first sub-light-emitting layer; and a first sub-electron transport layer located between the first sub-light-emitting layer and the electron-generating layer.

[0017] The second sub-stack may include: a second sub-light-emitting layer; a hole-generating layer located between the first sub-stack and the second sub-light-emitting layer; and a second sub-hole-transporting layer located between the hole-generating layer and the second sub-light-emitting layer.

[0018] The width of each of the electron generation layer and the first sub-electron transport layer of the first sub-stack may be smaller than the width of the second sub-hole transport layer.

[0019] The display panel may further include an electron transport layer sandwiched between the opposing electrode and the second sub-stack of the first intermediate layer.

[0020] The electron transport layer may extend in a manner sandwiched between the opposing electrode and the second intermediate layer, and may overlap with the second sub-stack of the first intermediate layer, the second intermediate layer, and the first portion of the dam layer.

[0021] The first color can be blue, and the second color can be red or green.

[0022] The display panel may further include: a third pixel electrode, corresponding to the third pixel and spaced apart from the first pixel electrode; and a third intermediate layer, sandwiched between the third pixel electrode and the opposing electrode, overlapping the third pixel electrode, and including a third light-emitting layer that emits light of a third color different from the first color and the second color, wherein a portion of the third intermediate layer is sandwiched between the first sub-stack and the second sub-stack on a second portion of the dam layer between the first pixel electrode and the third pixel electrode.

[0023] According to some embodiments of the present invention, a display panel and electronic device can be provided that improves display quality and lifespan through a relatively simple structure. The above effects are exemplary, and the effects of the present invention are not limited to those described above. Attached Figure Description

[0024] Figure 1a This is a block diagram of an electronic device according to an embodiment.

[0025] Figure 1b These are schematic diagrams of electronic devices according to various embodiments.

[0026] Figure 2 This is a schematic plan view of a display panel according to an embodiment of the present invention.

[0027] Figure 3 This is a schematic cross-sectional view of a display panel according to an embodiment of the present invention.

[0028] Figure 4 As a cross-sectional view that selects and enlarges the portion corresponding to the first pixel and the second pixel of the display panel according to an embodiment of the present invention, it is an enlarged view. Figure 3 A cross-sectional view of section IV.

[0029] Figure 5 As a cross-sectional view that selects and enlarges the portions corresponding to the first and third pixels of the display panel according to an embodiment of the present invention, it is an enlarged view. Figure 3 A cross-sectional view of the V-section.

[0030] Figure 6 This is a schematic diagram illustrating the pixel-by-pixel stacking structure of a display panel according to an embodiment of the present invention.

[0031] Figure 7 As a cross-sectional view that selects and enlarges the portion corresponding to the first pixel of the display panel according to an embodiment of the present invention, it can be compared with... Figure 3 It corresponds to part VII.

[0032] Explanation of reference numerals in the attached figures Detailed Implementation

[0033] This invention can be subjected to various modifications and can have multiple embodiments, specific embodiments of which are exemplarily illustrated in the accompanying drawings and described in detail below. The effects and features of the invention, as well as methods for implementing them, will become clear with reference to the embodiments described in detail below in conjunction with the accompanying drawings. However, the invention is not limited to the embodiments disclosed below, but can be implemented in various forms.

[0034] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. When describing with reference to the accompanying drawings, the same or corresponding constituent elements will be given the same reference numerals, and repeated descriptions thereon will be omitted.

[0035] In the following embodiments, the terms "first" and "second" are not restrictive in meaning, but are used to distinguish one constituent element from another.

[0036] In the following embodiments, the singular expression includes the plural expression unless otherwise explicitly stated in the context.

[0037] In the following embodiments, terms such as "comprising" or "having" indicate the presence of the features or constituent elements described in the specification, without pre-excluding the possibility of adding more than one other feature or constituent element.

[0038] In the following embodiments, when referring to a portion of a membrane, region, constituent element, etc., located above or on other portions, it includes not only the case where it is directly located on other portions, but also the case where other membranes, regions, constituent elements, etc. are sandwiched in between.

[0039] In the accompanying drawings, the sizes of the constituent elements may be enlarged or reduced for ease of explanation. For example, the sizes and thicknesses of the various components shown in the drawings are arbitrarily illustrated for ease of explanation; therefore, the present invention is not limited to the sizes and thicknesses shown in the drawings.

[0040] Where an embodiment can be implemented in different ways, the specific process sequence may also be performed differently from the described sequence. For example, two processes described consecutively may be performed substantially simultaneously, or they may be performed in the reverse order of the described sequence.

[0041] In the following embodiments, when referring to the connection of membranes, regions, constituent elements, etc., it includes cases where the membranes, regions, constituent elements are directly connected, and / or cases where they are indirectly connected by other membranes, regions, constituent elements, etc. sandwiched between them. For example, in this specification, when referring to the electrical connection of membranes, regions, constituent elements, etc., it indicates cases where the membranes, regions, constituent elements, etc. are directly electrically connected and / or cases where they are indirectly electrically connected by other membranes, regions, constituent elements, etc. sandwiched between them.

[0042] Figure 1a This is a block diagram of an electronic device 1 according to an embodiment. Figure 1b These are schematic diagrams of electronic devices according to various embodiments.

[0043] Reference Figure 1a An electronic device 1 according to one embodiment may include a display module 11, a processor 12, a memory 13, and a power module 14. The display module 11 may include a display panel 10 according to an embodiment of the present invention. Figure 2 In some embodiments, the display module 11 may include a display panel 10. Figure 2 ), gate driver (not shown), and data driver (not shown). In one embodiment, the display panel 10 ( Figure 2 Gate drivers (not shown) and / or data drivers (not shown) may be used to form the display panel 10. Figure 2 The gate driver (not shown) and / or data driver (not shown) may be arranged together in the display panel 10 during the manufacturing process. Figure 2 On, and can be coupled to display panel 10 ( ) through a bonding structure Figure 2 Electrical connection.

[0044] The processor 12 may include at least one of a central processing unit (CPU), an application processor (AP), a graphics processing unit (GPU), a communication processor (CP), an image signal processor (ISP), and a controller.

[0045] The memory 13 may store data information required for the operation of the processor 12 or the display module 11. If the processor 12 runs an application stored in the memory 13, image data signals and / or input control signals may be transmitted to the display module 11, and the display module 11 may process the received signals and output image information through the display screen.

[0046] The power module 14 may include a power supply module such as a power adapter or battery device and a power conversion module that converts the power supplied by the power supply module to generate the power required for the operation of the electronic device 1.

[0047] At least one of the various components of the electronic device 1 described above can be included within a display device that includes the display module 11. Furthermore, a portion of a single module that is functionally included in one module can be included within the display device, while another portion is disposed separately from the display device. For example, the display device may include the display module 11, and the processor 12, memory 13, and power module 14 can be disposed in the form of other devices within the electronic device 1 besides the display device.

[0048] Reference Figure 1b Includes a display panel 10 according to an embodiment ( Figure 2 The electronic devices can include not only image display electronic devices such as smartphones 1a, tablet PCs 1b, laptop computers 1c, televisions (TVs) 1d, and desktop monitors 1e, but also wearable electronic devices including display modules such as smart glasses 1f, head-mounted displays 1g, and smartwatches 1h, and vehicle electronic devices including display modules such as car dashboards, central dashboards, central information displays (CID) arranged on dashboards, and room mirror displays.

[0049] Figure 2 This is a schematic plan view of a display panel 10 according to an embodiment of the present invention.

[0050] Reference Figure 2 The display panel 10 may include a display area DA and a non-display area NDA located outside the display area DA. The display area DA can display images by means of pixels P arranged in the display area DA. Each pixel P may include display elements such as light-emitting elements. For example, each pixel P may emit red, green, blue or white light.

[0051] The non-display area NDA, located outside the display area DA and not displaying any image, can completely surround the display area DA. Drivers or similar devices for providing electrical signals or power to the display area DA can be arranged within the non-display area NDA. Pads can also be arranged within the non-display area NDA to serve as areas for electrically connecting electronic components or printed circuit boards.

[0052] As an example, Figure 2 The illustration shows a polygon (e.g., a quadrilateral) whose length in the first direction (e.g., the x-direction) of the display area DA is less than the length in the second direction (e.g., the y-direction). However, as another embodiment, the polygon (e.g., a quadrilateral) whose length in the second direction (e.g., the y-direction) of the display area DA is less than the length in the first direction (e.g., the x-direction) may also be a polygon (e.g., a quadrilateral). Figure 2 The illustration shows a roughly quadrilateral display area DA, but the invention is not limited thereto. As another embodiment, the display area DA can have various shapes, such as an N-sided polygon (N is a natural number of 3 or 5 or greater), a circle, or an ellipse. Figure 2 As shown, the display area DA can be a polygon with rounded corners, but as another embodiment, the corners of the display area DA can be shaped to include vertices where straight lines intersect.

[0053] As a display element included in the display panel 10, the light-emitting diode (LED) can be an organic light-emitting diode (OLED) including an organic light-emitting layer. The LED can also be an inorganic light-emitting diode including an inorganic light-emitting layer. The size of the LED can be on the micrometer or nanometer scale. For example, the LED can be a micro LED. Alternatively, the LED can be a quantum dot light-emitting diode (QD) including a quantum dot light-emitting layer.

[0054] Figure 3 This is a schematic cross-sectional view of a display panel 10 according to an embodiment of the present invention. The display panel 10 according to one embodiment may include light-emitting diodes (e.g., a first light-emitting diode LED1, a second light-emitting diode LED2, and a third light-emitting diode LED3) disposed on a substrate 100.

[0055] The substrate 100 may comprise glass, metal, or a polymer resin. The substrate 100 may comprise a polymer resin when at least a portion of the display device is bent or when the display device has flexible properties. The substrate 100 may comprise a polymer resin such as polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. In one embodiment, the substrate 100 may have a multilayer structure comprising at least two base layers, each comprising a polymer resin as described above, and an inorganic layer sandwiched between the base layers.

[0056] A buffer layer 201 may be disposed on the substrate 100. The buffer layer 201 may include inorganic materials such as silicon oxide, silicon nitride, and / or silicon oxynitride. The buffer layer 201 may improve the smoothness of the upper surface of the substrate 100, or may prevent or minimize the penetration of impurities from the substrate 100 direction into the semiconductor layer ACT of the transistor TFT.

[0057] The transistor TFT can be disposed on the buffer layer 201. The transistor TFT may include a semiconductor layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0058] The semiconductor layer ACT can be disposed on the buffer layer 201. The semiconductor layer ACT may include amorphous silicon or polycrystalline silicon. The semiconductor layer ACT may include an oxide semiconductor material. The oxide semiconductor material of the semiconductor layer ACT includes oxides of one or more substances selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), and zinc (Zn). The semiconductor layer ACT may include an organic semiconductor material. The semiconductor layer ACT may include a channel region, a source region, and a drain region.

[0059] The gate electrode GE can include metals, alloys, conductive metal oxides, or transparent conductive materials. For example, the gate electrode GE can include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). The gate electrode GE can have a single-layer or multi-layer structure containing the above materials.

[0060] Each of the source electrode SE and drain electrode DE may include a metal, alloy, conductive metal oxide, or transparent conductive material. For example, each of the source electrode SE and drain electrode DE may include silver (Ag), silver-containing alloys, molybdenum (Mo), molybdenum-containing alloys, aluminum (Al), aluminum-containing alloys, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), nickel (Ni), chromium (Cr), chromium nitride (CrN), titanium (Ti), tantalum (Ta), platinum (Pt), scandium (Sc), indium tin oxide (ITO), or indium zinc oxide (IZO). Each of the source electrode SE and drain electrode DE may have a single-layer structure or a multi-layer structure containing the above-mentioned materials. For example, each of the source electrode SE and drain electrode DE may have a Ti / Al bilayer structure or a Ti / Al / Ti trilayer structure.

[0061] The gate insulating layer 203 may be sandwiched between the semiconductor layer ACT and the gate electrode GE. The gate insulating layer 203 may include inorganic insulators such as silicon oxide, silicon nitride, and / or silicon oxynitride.

[0062] Interlayer insulating layer 205 may be disposed on the gate electrode GE. Source electrode SE and drain electrode DE may be disposed on interlayer insulating layer 205. Interlayer insulating layer 205 may include inorganic insulators such as silicon oxide, silicon nitride and / or silicon oxynitride.

[0063] although Figure 3 The illustration shows a transistor TFT having both a source electrode SE and a drain electrode DE, but the invention is not limited thereto. In one embodiment, a pixel circuit electrically connected to each of the first light-emitting diode LED1, the second light-emitting diode LED2, and the third light-emitting diode LED3 may include multiple transistors, wherein the drain region of the first transistor of one of the multiple transistors may be electrically connected to the source region of the second transistor of another. In this case, the drain region of the first transistor and the source region of the second transistor may be integrated, the first transistor may not have a drain electrode DE, and the second transistor may not have a source electrode SE.

[0064] Planarization layer 207 can be disposed on the transistor TFT. Planarization layer 207 can provide a flat upper surface. Planarization layer 207 may include an organic insulating material. Although Figure 3 The illustration shows a single-layer planarization layer 207, but the invention is not limited thereto. In another embodiment, the planarization layer 207 may have a multi-layer structure.

[0065] A first light-emitting diode (LED1), a second light-emitting diode (LED2), and a third light-emitting diode (LED3) can be disposed on a planarization layer 207. The first light-emitting diode (LED1) may include a first pixel electrode 310, a counter electrode 500, and a first intermediate layer 410 between the first pixel electrode 310 and the counter electrode 500. The second light-emitting diode (LED2) may include a second pixel electrode 320, a counter electrode 500, and a second intermediate layer 420 between the second pixel electrode 320 and the counter electrode 500. The third light-emitting diode (LED3) may include a third pixel electrode 330, a counter electrode 500, and a third intermediate layer 430 between the third pixel electrode 330 and the counter electrode 500.

[0066] The first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330 can be arranged spaced apart from each other. The opposing electrode 500 can be shared among the first light-emitting diode LED1, the second light-emitting diode LED2, and the third light-emitting diode LED3. The opposing electrode 500 can be formed on the substrate 100 in a manner that overlaps with the first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330.

[0067] In one embodiment, the first functional layer 405 and the second functional layer 450 can be shared among the first light-emitting diode LED1, the second light-emitting diode LED2, and the third light-emitting diode LED3. The first functional layer 405, as a common layer, can be disposed between each of the first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330 and the opposing electrode 500. For example, the first functional layer 405 can be sandwiched between the first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330 and the first intermediate layer 410, the second intermediate layer 420, and the third intermediate layer 430, respectively. The first functional layer 405 can be a hole injection layer (HIL). For example, the first functional layer 405 can be a p-hole injection layer (p-HIL) containing p-type impurities. The second functional layer 450, as a common layer, can be disposed between each of the first intermediate layer 410, the second intermediate layer 420, and the third intermediate layer 430 and the opposing electrode 500. In one embodiment, the second functional layer 450 may include an electron transfer layer (ETL). In another embodiment, the second functional layer 450 may include an electron transfer layer (ETL) and an electron injection layer (EIL).

[0068] Each of the first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330 may be a (semi-)transparent electrode or a reflective electrode. Each of the first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330 may include a reflective layer comprising silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and compounds thereof, as well as a transparent or semi-transparent electrode layer located on the reflective layer. The transparent or semi-transparent electrode layer may include one or more selected from the group consisting of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). Each of the first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330 may have a three-layer structure of ITO / Ag / ITO.

[0069] The dam layer 209 can cover the edges of each of the first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330. The dam layer 209 can increase the distance between the edges of each of the first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330 and the opposing electrode 500. Therefore, the dam layer 209 can prevent electric arcing or the like from occurring at the edges of each of the first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330.

[0070] Layer 209 may include an insulating material. In one embodiment, layer 209 may include one or more organic insulating materials selected from the group consisting of polyimide resins, polyamide resins, acrylic resins, benzocyclobutene resins, and phenolic resins. In one embodiment, layer 209 may have a colored material. For example, layer 209 may have a colored pigment (e.g., a pigment of a predetermined color such as white or black). In one embodiment, layer 209 may be black. For example, layer 209 may include a polyimide (PI) adhesive and a mixture of red, green, and blue pigments. Alternatively, layer 209 may include a Cardo adhesive resin and a mixture of lactam black pigment and blue pigment. Alternatively, layer 209 may include carbon black.

[0071] The dam layer 209 may include a first opening OP1, a second opening OP2, and a third opening OP3 that overlap with the first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330, respectively. The first opening OP1, the second opening OP2, and the third opening OP3 of the dam layer 209 may expose a portion of the first pixel electrode 310, the second pixel electrode 320, and the third pixel electrode 330, respectively. The first opening OP1, the second opening OP2, and the third opening OP3 of the dam layer 209 may correspond to the light-emitting areas of the first light-emitting diode LED1, the second light-emitting diode LED2, and the third light-emitting diode LED3, respectively. The light-emitting areas of the first light-emitting diode LED1, the second light-emitting diode LED2, and the third light-emitting diode LED3 may correspond to the light-emitting areas of the first pixel P1, the second pixel P2, and the third pixel P3 (or, the pixel areas of the first pixel P1, the second pixel P2, and the third pixel P3), respectively.

[0072] The first intermediate layer 410 may be sandwiched between the first pixel electrode 310 and the opposing electrode 500, and may overlap with the first pixel electrode 310 and the opposing electrode 500. The first intermediate layer 410 may have a width (or size) larger than the width (or size) of the first opening OP1 of the embankment layer 209, and the edge of the first intermediate layer 410 may be located on the upper surface of the embankment layer 209.

[0073] The first intermediate layer 410 may include multiple sub-layers, and the sub-layers may include multiple light-emitting layers (hereinafter referred to as "sub-light-emitting layers") that emit light of a first color. Relatedly, Figure 3 The illustration shows a first intermediate layer 410 comprising a first sub-stack 4110 containing a first sub-light-emitting layer and a second sub-stack 4120 containing a second sub-light-emitting layer.

[0074] The first sub-stacking body 4110 may overlap with the first pixel electrode 310 and extend onto the embankment layer 209. The edge of the first sub-stacking body 4110 may be located on the upper surface of the embankment layer 209. A surface of the first sub-stacking body 4110 facing the first pixel electrode 310 (e.g., the lower surface) may be in direct contact with the first functional layer 405. For example, the entire surface of the first sub-stacking body 4110 facing the first pixel electrode 310 (e.g., the lower surface) may be in direct contact with the first functional layer 405. The first sub-stacking body 4110 may include multiple sub-layers containing multiple first sub-light-emitting layers. Specific structures for the first sub-stacking body 4110 will be described with reference to... Figure 4 This will be discussed later.

[0075] The second sub-stack 4120 may overlap with the first pixel electrode 310 on the first sub-stack 4110 and extend onto the embankment 209. The edge of the second sub-stack 4120 may be located on the upper surface of the embankment 209.

[0076] A portion of the second sub-stacking body 4120 (e.g., the inner region of the second sub-stacking body 4120) may be in direct contact with the first sub-stacking body 4110. The edge of the second sub-stacking body 4120 is spaced apart from the edge of the first sub-stacking body 4110. The outer region of the second sub-stacking body 4120, which includes the edge of the second sub-stacking body 4120, is spaced apart from the outer region of the first sub-stacking body 4110, which includes the edge of the first sub-stacking body 4110. For example, a portion of a second intermediate layer 420 (e.g., the outer region of the second intermediate layer 420) or a portion of a third intermediate layer 430 (e.g., the outer region of the third intermediate layer 430) may be sandwiched between the outer region of the second sub-stacking body 4120 and the outer region of the first sub-stacking body 4110. The outer region of the second sub-stacking body 4120 is not in direct contact with the outer region of the first sub-stacking body 4110 disposed on the embankment 209. The second sub-stack 4120 may include multiple sub-layers containing the second sub-light-emitting layer, and the specific structure of the second sub-stack 4120 will be referred to Figure 4 This will be discussed later.

[0077] The second intermediate layer 420 may include multiple sublayers. The second intermediate layer 420 may include a light-emitting layer that emits light of a second color. The process of forming the second intermediate layer 420 may be performed between the process of forming the first sub-stack 4110 of the first intermediate layer 410 and the process of forming the second sub-stack 4120, so a portion of the second intermediate layer 420 may be sandwiched on the embankment 209 between the first sub-stack 4110 and the second sub-stack 4120.

[0078] The third intermediate layer 430 may include multiple sublayers. The third intermediate layer 430 may include a light-emitting layer that emits light of a third color. The process of forming the third intermediate layer 430 may be performed between the process of forming the first sub-stack 4110 of the first intermediate layer 410 and the process of forming the second sub-stack 4120. Therefore, a portion of the third intermediate layer 430 may be sandwiched on the embankment 209 between the first sub-stack 4110 and the second sub-stack 4120.

[0079] Each of the first intermediate layer 410, the second intermediate layer 420, and the third intermediate layer 430 includes a light-emitting layer that can emit light of different colors from each other. For example, the first color of light emitted from the first and second sub-light-emitting layers included in the first sub-staple 4110 and the second sub-staple 4120 of the first intermediate layer 410 can be blue light. The second color of light emitted from the light-emitting layer included in the second intermediate layer 420 can be green (or red) light, or the third color of light emitted from the light-emitting layer included in the third intermediate layer 430 can be red (or green) light. For the first intermediate layer 410 that emits blue light, as a series structure including the first sub-staple 4110 and the second sub-staple 4120, light efficiency and lifetime can be improved.

[0080] Figure 4 As a cross-sectional view that selects and enlarges the portion corresponding to the first pixel P1 and the second pixel P2 of the display panel 10 according to an embodiment of the present invention, it is an enlarged cross-sectional view. Figure 3 A cross-sectional view of section IV. Figure 5 As a cross-sectional view that selects and enlarges the portions corresponding to the first pixel P1 and the third pixel P3 of the display panel 10 according to an embodiment of the present invention, it is an enlarged cross-sectional view. Figure 3 A cross-sectional view of the V-section. Figure 6 This is a schematic diagram illustrating the pixel-by-pixel stacking structure of a display panel 10 according to an embodiment of the present invention.

[0081] Reference Figure 4 The dam layer 209 can be disposed on the first pixel electrode 310 and the second pixel electrode 320, and the first functional layer 405 can be disposed on the dam layer 209. The first functional layer 405 can overlap with the first pixel electrode 310, the second pixel electrode 320 and the dam layer 209, and can be sandwiched between the first pixel electrode 310 and the first intermediate layer 410 and between the second pixel electrode 320 and the second intermediate layer 420. The first functional layer 405 may include a hole injection layer (e.g., p-HIL), or may include a hole injection layer (e.g., p-HIL) and a hole transport layer.

[0082] The first functional layer 405 can directly contact the first pixel electrode 310 through the first opening OP1, and can directly contact the second pixel electrode 320 through the second opening OP2. The first functional layer 405 can directly contact the upper surface of the embankment layer 209. Relatedly, Figure 4 This illustrates a situation where a portion of the dike layer 209 (hereinafter referred to as "first portion 209A") between the first functional layer 405 and the first pixel electrode 310 and the second pixel electrode 320 is in direct contact.

[0083] The first intermediate layer 410 may include a first sub-light-emitting layer 4113 and a second sub-light-emitting layer 4124. The first intermediate layer 410 may include a charge-generating layer between the first sub-light-emitting layer 4113 and the second sub-light-emitting layer 4124. Relatedly... Figure 4 An electron generation layer 4115, which serves as a negative charge generation layer between a first sub-emitting layer 4113 and a second sub-emitting layer 4124, and a hole generation layer 4121, which serves as a positive charge generation layer, are shown.

[0084] The electron generation layer 4115 can be an n-type charge generation layer. The electron generation layer 4115 can supply electrons. The electron generation layer 4115 can include an n-type host material and an n-type dopant material. The n-type dopant material can be a metal from Group 1 or Group 2 of the periodic table, an organic material capable of injecting electrons, or a mixture thereof. For example, the n-type dopant material can be one of an alkali metal or an alkaline earth metal. The electron generation layer 4115 can be composed of an organic layer doped with an alkali metal such as lithium (Li), sodium (Na), potassium (K), or cesium (Cs), or an alkaline earth metal such as magnesium (Mg), strontium (Sr), barium (Ba), or radium (Ra), but the invention is not limited thereto. The n-type host material can include an organic material capable of transporting electrons. For example, the n-type host substance can be tris(8-hydroxyquinolinato)aluminum (Alq3), lithium 8-hydroxyquinolinatolithium (Liq), 2-(4-biphenyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole (tBu-PBD), 3-(biphenyl-4-yl)-5-(4-tert-butylphenyl)-4-phenyl-4H-1,2,4-triazole (TAZ), spiropeptide (PBD) The invention may consist of one or more of the following: spiro-PBD, bis(2-methyl-8-hydroxyquinoline-N1,O8)-(1,1'-biphenyl-4-hydroxy)aluminum (BAlq: Bis(2-methyl-8-quinolinolato-N1,O8)-(1,1'-Biphenyl-4-olato)aluminum), SAlq, 1,3,5-tris(1-phenyl-1H-benzimidazole-2-yl)benzene (TPBi: 2,2',2''-(1,3,5-benzinetriyl)-tris(1-phenyl-1-H-benzimidazole)), oxadiazole, triazole, phenanthroline, benzoxazole, and benzthiazole, but is not limited thereto.

[0085] Hole generation layer 4121 can be a p-type charge generation layer. Hole generation layer 4121 can supply holes. Hole generation layer 4121 can include a p-type host material and a p-type dopant material. The p-type dopant material can be an organic compound such as a metal oxide, 2,3,5,6-tetrafluoro-7,7',8,8'-tetracyanoquino-dimethane (F4-TCNQ), or hexaazatriphenylene-hexacarbonitrile (HAT-CN), or vanadium pentoxide (V2O5), molybdenum oxide (MoO2). x The p-type host material can be composed of metallic substances such as tungsten trioxide (WO3), but is not limited to these. The p-type host material can also be composed of organic substances capable of transporting holes (e.g., containing N,N'-dinaphthyl-N,N'-diphenylbenzidine (NPD: N,N-dinaphthyl-N,N'-diphenylbenzidine)). The invention comprises one or more of the following substances: benzidine, N,N'-bis(naphthalene-1-yl)-N,N'-bis(phenyl)-2,2'-dimethylbenzidine (α-NPD: N,N'-bis(naphthalene-1-yl)-N,N'-bis(phenyl)-2,2'-dimethylbenzidine), N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine (TPD: N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1-biphenyl]-4,4'-diamine), and 4,4',4''-tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine (4,4',4''-Tris(N-3-methylphenyl-N-phenyl-amino)-triphenylamine), but is not limited thereto.

[0086] The electron generation layer 4115 and the hole generation layer 4121 can be in direct contact with each other in the region corresponding to the first opening OP1 (e.g., the region corresponding to the first pixel P1). The electron generation layer 4115 and the hole generation layer 4121 can be separated from each other in the non-pixel region NP. The electron generation layer 4115 is a sub-layer of the first sub-stack 4110, and the hole generation layer 4121 is a sub-layer of the second sub-stack 4120. The outer regions of the electron generation layer 4115, which includes the edge of the electron generation layer 4115, and the outer regions of the hole generation layer 4121, which includes the edge of the hole generation layer 4121, can be separated from each other along the stacking direction (e.g., the z-direction) of the electron generation layer 4115 and the hole generation layer 4121 without direct contact.

[0087] The first sub-stack 4110 of the first intermediate layer 410 may include a first sub-light-emitting layer 4113 that emits light of a first color (e.g., blue), a first sub-hole transport layer 4111 serving as a hole transport layer (HTL) between the first pixel electrode 310 and the first sub-light-emitting layer 4113, an electron-generating layer 4115 located on the opposite side of the first sub-hole transport layer 4111 separated from the first sub-light-emitting layer 4113, and a first sub-electron transport layer 4114 between the first sub-light-emitting layer 4113 and the electron-generating layer 4115.

[0088] In one embodiment, the first sub-stack 4110 may include a first auxiliary layer 4112 between the first sub-hole transport layer 4111 and the first sub-emitting layer 4113. The first auxiliary layer 4112 may adjust the hole charge balance to improve the light generation efficiency of the first sub-emitting layer 4113. The first auxiliary layer 4112 may have a thickness determined according to the resonant period of the light emitted from the first sub-emitting layer 4113 and may improve the color purity of the light emitted from the first sub-emitting layer 4113.

[0089] The second sub-stack 4120 of the first intermediate layer 410 may include a second sub-emitting layer 4124 that emits light of a first color, a hole generation layer 4121 between the first sub-stack 4110 and the second sub-emitting layer 4124, and a second sub-hole transport layer 4122 serving as a hole transport layer (HTL) between the hole generation layer 4121 and the second sub-emitting layer 4124.

[0090] In one embodiment, the second sub-stack 4120 may include a second auxiliary layer 4123 between the second sub-hole transport layer 4122 and the second sub-light-emitting layer 4124. The second auxiliary layer 4123 may adjust the hole charge balance to improve the light generation efficiency of the second sub-light-emitting layer 4124.

[0091] The second functional layer 450 (e.g., an electron transport layer) may be sandwiched between the second sub-stack 4120 and the counter electrode 500, and may overlap with the second sub-stack 4120. The second functional layer 450 (e.g., an electron transport layer), as a common layer, may extend to the second intermediate layer 420 located in the second pixel P2, and may overlap with the second intermediate layer 420 and the first portion 209A of the dike layer 209 between the first pixel P1 and the second pixel P2.

[0092] The second intermediate layer 420 may include a second light-emitting layer 4204 that emits light of a second color (e.g., green), a second hole transport layer 4201 between the second pixel electrode 320 and the second light-emitting layer 4204, and a first resonant auxiliary layer 4202 between the second hole transport layer 4201 and the second light-emitting layer 4204. The first resonant auxiliary layer 4202, as a layer for matching the resonant distance of the second color, may be an auxiliary hole transport layer.

[0093] The second intermediate layer 420 may include a fourth auxiliary layer 4203 between the first resonant auxiliary layer 4202 and the second light-emitting layer 4204. The fourth auxiliary layer 4203 can adjust the hole charge balance to improve the light generation efficiency of the second light-emitting layer 4204. It can also improve the color purity of the light emitted from the second light-emitting layer 4204.

[0094] Reference Figure 5 The dam layer 209 can be disposed on the first pixel electrode 310 and the third pixel electrode 330, and the first functional layer 405 can be disposed on the dam layer 209. The first functional layer 405 can overlap with the first pixel electrode 310, the third pixel electrode 330 and the dam layer 209, and can be sandwiched between the first pixel electrode 310 and the first intermediate layer 410 and between the third pixel electrode 330 and the third intermediate layer 430.

[0095] The first functional layer 405 can directly contact the first pixel electrode 310 through the first opening OP1, and can directly contact the third pixel electrode 330 through the third opening OP3. The first functional layer 405 can directly contact the upper surface of the embankment layer 209. Relatedly, Figure 5 This illustrates a situation where a portion of the dam 209 (hereinafter referred to as "second portion 209B") between the first functional layer 405 and the first pixel electrode 310 and the third pixel electrode 330 is in direct contact. Figure 5 The specific structure of the first intermediate layer 410 shown is the same as that described above. Figure 4 The descriptions are the same.

[0096] The third intermediate layer 430 may include a third light-emitting layer 4304 that emits light of a third color (e.g., red), a third hole transport layer 4301 between the third pixel electrode 330 and the third light-emitting layer 4304, and a second resonant auxiliary layer 4302 between the third hole transport layer 4301 and the third light-emitting layer 4304. The second resonant auxiliary layer 4302, as a layer for matching the resonant distance of the third color, may be an auxiliary hole transport layer.

[0097] The third intermediate layer 430 may include a third auxiliary layer 4303 between the second resonant auxiliary layer 4302 and the third light-emitting layer 4304. The third auxiliary layer 4303 can adjust the hole charge balance to improve the light generation efficiency of the third light-emitting layer 4304.

[0098] Reference Figure 4 , Figure 5 and Figure 6 In the non-pixel region NP, a portion of each of the second intermediate layer 420 and the third intermediate layer 430 may be sandwiched between the first sub-stack 4110 and the second sub-stack 4120.

[0099] like Figure 4 and Figure 6 As shown, on the first portion 209A of the embankment layer 209 corresponding to the non-pixel region NP, a portion of the second intermediate layer 420 may be sandwiched between the first sub-stack 4110 and the second sub-stack 4120. For example, a portion of each of the sub-layers of the second intermediate layer 420 (e.g., the second hole transport layer 4201, the first resonant auxiliary layer 4202, the fourth auxiliary layer 4203, and the second light-emitting layer 4204) may be sandwiched between the electron generation layer 4115 of the first sub-stack 4110 and the hole generation layer 4121 of the second sub-stack 4120.

[0100] like Figure 5 and Figure 6 As shown, on the second portion 209B of the embankment layer 209 corresponding to the non-pixel region NP, a portion of the third intermediate layer 430 may be sandwiched between the first sub-stack 4110 and the second sub-stack 4120. For example, a portion of each of the sub-layers of the third intermediate layer 430 (e.g., the third hole transport layer 4301, the second resonant auxiliary layer 4302, the third auxiliary layer 4303, and the third light-emitting layer 4304) may be sandwiched between the electron generation layer 4115 of the first sub-stack 4110 and the hole generation layer 4121 of the second sub-stack 4120.

[0101] In some embodiments, the structure in which each of the second intermediate layer 420 and the third intermediate layer 430 is sandwiched between the first sub-stack 4110 and the second sub-stack 4120 can prevent unintended light from emitting from a portion of the display panel 10.

[0102] As a comparative example of the present invention, the following situation will be described: the second sub-stack 4120 is disposed below the second intermediate layer 420 and the third intermediate layer 430, and the first light-emitting diode LED1 is turned on (ON) while the second light-emitting diode LED2 and the third light-emitting diode LED3 are turned off (OFF). In this case, a portion of the holes in the first pixel electrode 310 moves toward the second pixel P2 and the third pixel P3 through the first functional layer 405, and a portion of the holes generated from the hole generation layer 4121 of the second sub-stack 4120 moves to the second intermediate layer 420 and the third intermediate layer 430 through the second sub-stack 4120, and may emit unexpected light in the region corresponding to the second pixel P2 and the third pixel P3 and / or the non-pixel region NP.

[0103] As another comparative example of the present invention, the following situation will be described: a first sub-stack 4110 is disposed above the second intermediate layer 420 and the third intermediate layer 430, and the first light-emitting diode LED1 is turned on (ON) while the second light-emitting diode LED2 and the third light-emitting diode LED3 are turned off (OFF). In this case, some electrons that have not formed excitons in the first sub-light-emitting layer 4113 of the first sub-stack 4110 can move along the -z direction and flow into the second intermediate layer 420 and the third intermediate layer 430, and some holes in the first pixel electrode 310 can move to the non-pixel region NP through the first functional layer 405. In this case, light corresponding to the second or third color may be unexpectedly emitted in the non-pixel region NP. The above phenomenon may be significant at low gray levels.

[0104] However, according to embodiments of the present invention, by referring to Figures 3 to 5 The structure described above can prevent the emission of unintended light as described above.

[0105] For example, such as Figure 6As shown, when the first light-emitting diode LED1 is turned on (ON) and the second light-emitting diode LED2 and the third light-emitting diode LED3 are turned off (OFF), electrons in the electron generation layer 4115 of the first sub-stacking body 4110 corresponding to the first light-emitting diode LED1 can move along the -z direction, and holes in the hole generation layer 4121 of the second sub-stacking body 4120 can move along the z direction. Therefore, even if the first sub-stacking body 4110 and the second sub-stacking body 4120 overlap with the second intermediate layer 420 and the third intermediate layer 430 in the non-pixel region NP, it can prevent the unexpected emission of light corresponding to the second color and the third color in the non-pixel region NP.

[0106] like Figure 6 As shown, when the first light-emitting diode LED1 is ON and the second light-emitting diodes LED2 and LED3 are OFF, a portion of the holes in the first pixel electrode 310 can move through the first functional layer 405, across the non-pixel region NP, and toward the second pixel P2 and the third pixel P3. However, in the non-pixel region NP, the movement of these holes can be prevented by the first sub-stacking layer 4110 on the first functional layer 405. For example, electrons that have not formed excitons in the first sub-light-emitting layer 4113 of the first sub-stacking layer 4110 can accumulate below the first sub-light-emitting layer 4113 (e.g., in the -z direction), and these electrons can trap the holes moving toward the second pixel P2 and the third pixel P3 through the first functional layer 405. In other words, the path of the holes moving toward the second pixel P2 and the third pixel P3 through the first functional layer 405 can be blocked. Therefore, even when the second light-emitting diode LED2 and the third light-emitting diode LED3 are turned off, it is possible to prevent the second pixel P2 and the third pixel P3 from faintly illuminating the second color light and / or the third color light.

[0107] Figure 7 As a cross-sectional view that selects and enlarges the portion corresponding to the first pixel P1 of the display panel 10 according to an embodiment of the present invention, it can be compared with... Figure 3 It corresponds to part VII.

[0108] Reference Figure 7 The first intermediate layer 410 may include a first sub-stack 4110 and a second sub-stack 4120, and in the non-pixel region NP, a second intermediate layer 420 or a third intermediate layer 430 may be sandwiched between the first sub-stack 4110 and the second sub-stack 4120. The specific configurations of the first intermediate layer 410, the second intermediate layer 420, and the third intermediate layer 430 are as described above. Figures 4 to 6 The content described is the same, and the following explanation will focus on the differences.

[0109] In one embodiment, the widths W4115 and W4114 of the electron generation layer 4115 and / or the first sub-electron transport layer 4114 of the first intermediate layer 410 may be smaller than the width of the hole transport layer of the first intermediate layer 410. For example, the widths W4115 and W4114 of the electron generation layer 4115 and the first sub-electron transport layer 4114 may be smaller than the width W4122 of the second sub-hole transport layer 4122. The width W4111 of the first sub-hole transport layer 4111 may be relatively larger than the widths W4115 and W4114 of the electron generation layer 4115 and the first sub-electron transport layer 4114.

[0110] For reference Figure 6 When the first pixel P1 is ON and the second pixel P2 and the third pixel P3 are OFF, electrons that have not formed excitons in the second sub-light-emitting layer 4124 can travel towards the second sub-hole transport layer 4122 among the electrons moving from the opposing electrode 500 toward the first intermediate layer 410. As a comparative example, if the width W4115 of the electron generating layer 4115 and the width W4114 of the first sub-electron transport layer 4114 are greater than the width of the second sub-light-emitting layer 4124, the second sub-hole transport layer 4122 may come into contact with the electron generating layer 4115 and / or the first sub-electron transport layer 4114 due to manufacturing errors. In this case, the light emitted from the first sub-stack 4110 may deviate from the expected brightness range or affect surrounding layers (e.g., the second intermediate layer 420 and the third intermediate layer 430). However, with the above-described structure, this situation can be prevented.

[0111] The present invention has been described above with reference to an embodiment shown in the accompanying drawings. However, this is merely illustrative, and those skilled in the art will understand that various modifications and variations of the embodiments are possible. Therefore, the true scope of protection of the present invention should be determined by the technical concept of the appended claims.

Claims

1. A display panel, comprising: The first pixel electrode and the second pixel electrode are separated from each other; The dam layer includes a first opening corresponding to the first pixel electrode and a second opening corresponding to the second pixel electrode; Opposing electrodes are arranged on the embankment and overlap with the first pixel electrode and the second pixel electrode; A first intermediate layer is sandwiched between the first pixel electrode and the opposing electrode, and includes a first sub-stack that overlaps with the first pixel electrode and includes a first sub-emitting layer that emits light of a first color, and a second sub-stack that is disposed on the first sub-stack and includes a second sub-emitting layer that emits light of the same color as the first sub-emitting layer. as well as The second intermediate layer is sandwiched between the second pixel electrode and the opposing electrode, overlaps with the second pixel electrode, and includes a second light-emitting layer that emits light of a second color different from the first color. Wherein, a portion of the second intermediate layer is sandwiched between the first sub-stack and the second sub-stack on the first portion of the dam layer between the first pixel electrode and the second pixel electrode.

2. The display panel according to claim 1, further comprising: Hole injection layer, The hole injection layer overlaps with the first pixel electrode, the first portion of the dam layer and the second pixel electrode, and is sandwiched between the first pixel electrode and the first intermediate layer and between the second pixel electrode and the second intermediate layer.

3. The display panel according to claim 1, wherein, The first intermediate layer includes: A charge generation layer is sandwiched between the first sub-light-emitting layer and the second sub-light-emitting layer, and includes an electron generation layer and a hole generation layer. Wherein, the electron generation layer is a sublayer of the first sub-stack, and the hole generation layer is a sublayer of the second sub-stack.

4. The display panel according to claim 3, wherein, The first sub-stack includes: The first sub-light-emitting layer; The first sub-hole transport layer is located between the first pixel electrode and the first sub-light emission layer; The electron generation layer is located on the opposite side of the first sub-hole transport layer, separated from the first sub-light-emitting layer; and The first sub-electron transport layer is located between the first sub-luminescent layer and the electron generation layer.

5. The display panel according to claim 4, wherein, The second sub-stack includes: The second sub-light-emitting layer; The hole generation layer is located between the first sub-stack and the second sub-light-emitting layer; and The second sub-hole transport layer is located between the hole generation layer and the second sub-emissive layer.

6. The display panel according to claim 5, wherein, The width of each of the electron generation layer and the first sub-electron transport layer of the first sub-stack is smaller than the width of the second sub-hole transport layer.

7. The display panel according to claim 5, further comprising: An electron transport layer is sandwiched between the opposing electrode and the second sub-stack of the first intermediate layer.

8. The display panel according to claim 7, wherein, The electron transport layer extends between the opposing electrode and the second intermediate layer, and overlaps with the second sub-stack of the first intermediate layer, the second intermediate layer, and the first portion of the dam layer.

9. The display panel according to claim 1, wherein, The first color is blue, and the second color is either red or green.

10. The display panel according to claim 1, further comprising: The third pixel electrode is separated from the first pixel electrode; as well as A third intermediate layer is sandwiched between the third pixel electrode and the opposing electrode, overlaps with the third pixel electrode, and includes a third light-emitting layer that emits light of a third color different from the first color and the second color. Wherein, a portion of the third intermediate layer is sandwiched between the first sub-stack and the second sub-stack on the second portion of the dam layer between the first pixel electrode and the third pixel electrode.

11. An electronic device comprising a display panel including a first pixel, a second pixel, and a third pixel, said display panel comprising: The first pixel electrode corresponds to the first pixel; The second pixel electrode corresponds to the second pixel and is spaced apart from the first pixel electrode; The dam layer includes a first opening corresponding to the first pixel electrode and a second opening corresponding to the second pixel electrode; Opposing electrodes are arranged on the embankment and overlap with the first pixel electrode and the second pixel electrode; A first intermediate layer is sandwiched between the first pixel electrode and the opposing electrode, and includes a first sub-stack that overlaps with the first pixel electrode and includes a first sub-emitting layer that emits light of a first color, and a second sub-stack that is disposed on the first sub-stack and includes a second sub-emitting layer that emits light of the same color as the first sub-emitting layer. as well as The second intermediate layer is sandwiched between the second pixel electrode and the opposing electrode, overlaps with the second pixel electrode, and includes a second light-emitting layer that emits light of a second color different from the first color. The first sub-stack includes an electron generation layer, and the second sub-stack includes a hole generation layer. A portion of the second intermediate layer is sandwiched between the electron generation layer and the hole generation layer on the first portion of the dam layer between the first pixel electrode and the second pixel electrode.

12. The electronic device according to claim 11, wherein, The display panel also includes a hole injection layer. The hole injection layer overlaps with the first pixel electrode, the first portion of the dam layer and the second pixel electrode, and is sandwiched between the first pixel electrode and the first intermediate layer and between the second pixel electrode and the second intermediate layer.

13. The electronic device according to claim 11, wherein, The first sub-stack includes: The first sub-light-emitting layer; The first sub-hole transport layer is located between the first pixel electrode and the first sub-light emission layer; The electron generation layer is located on the opposite side of the first sub-hole transport layer, separated from the first sub-light-emitting layer; and The first sub-electron transport layer is located between the first sub-luminescent layer and the electron generation layer.

14. The electronic device according to claim 13, wherein, The second sub-stack includes: The second sub-light-emitting layer; The hole generation layer is located between the first sub-stack and the second sub-light-emitting layer; and The second sub-hole transport layer is located between the hole generation layer and the second sub-emissive layer.

15. The electronic device according to claim 14, wherein, The width of each of the electron generation layer and the first sub-electron transport layer of the first sub-stack is smaller than the width of the second sub-hole transport layer.

16. The electronic device according to claim 11, wherein, The display panel also includes: An electron transport layer is sandwiched between the opposing electrode and the second sub-stack of the first intermediate layer.

17. The electronic device according to claim 16, wherein, The electron transport layer extends between the opposing electrode and the second intermediate layer, and overlaps with the second sub-stack of the first intermediate layer, the second intermediate layer, and the first portion of the dam layer.

18. The electronic device according to claim 11, wherein, The first color is blue, and the second color is either red or green.

19. The electronic device according to claim 11, wherein, The display panel also includes: A third pixel electrode, corresponding to the third pixel and spaced apart from the first pixel electrode; and A third intermediate layer is sandwiched between the third pixel electrode and the opposing electrode, overlaps with the third pixel electrode, and includes a third light-emitting layer that emits light of a third color different from the first color and the second color. Wherein, a portion of the third intermediate layer is sandwiched between the first sub-stack and the second sub-stack on the second portion of the dam layer between the first pixel electrode and the third pixel electrode.

Images