Display device, method of manufacturing the same, and electronic device including the same

Abstract

This invention discloses a display device, a method for manufacturing the same, and an electronic device including the display device. The display device includes: a substrate; a first type transistor including a second active pattern, a third gate electrode, and at least one of a plurality of first metal patterns, wherein the second active pattern is disposed on the substrate and doped with an N-type dopant, the third gate electrode overlaps with the second active pattern, and at least one of the plurality of first metal patterns is disposed on the third gate electrode and connected to the second active pattern through a contact hole; a light-emitting element disposed on the plurality of first metal patterns and including a first electrode, wherein a pixel opening is defined by a pixel defining layer; and a second metal pattern disposed between the plurality of first metal patterns and the first electrode and covering the third gate electrode in a plan view, wherein a gap is defined in the second metal pattern to overlap with the pixel opening in a plan view.

Description

Technical Field

[0001] This disclosure relates to a display device, a method of manufacturing a display device, and an electronic device including a display device. More specifically, this disclosure relates to a display device including an N-channel metal-oxide-semiconductor (“NMOS”) transistor, a method of manufacturing a display device, and an electronic device including a display device. Background Technology

[0002] Users may view an image from in front of the display screen, but they may also view it from different angles. Therefore, a technique is desired that minimizes color coordinate distortion caused by viewing angle to improve image quality when viewed from various angles. Summary of the Invention

[0003] The embodiments provide a display device with improved color symmetry without increasing the thickness of the insulating layer.

[0004] Other embodiments provide a method for manufacturing a display device.

[0005] Other embodiments provide electronic devices including a display device.

[0006] The display device according to an embodiment includes: a substrate; a first type transistor including a second active pattern, a third gate electrode, and at least one of a plurality of first metal patterns, the second active pattern being disposed on the substrate and doped with an N-type dopant, the third gate electrode overlapping the second active pattern, and at least one of the plurality of first metal patterns being disposed on the third gate electrode and connected to the second active pattern through a contact hole; a light-emitting element disposed on the plurality of first metal patterns and including a first electrode, wherein a pixel opening is defined by a pixel defining layer; and a second metal pattern disposed between the plurality of first metal patterns and the first electrode and covering the third gate electrode in a plan view, wherein a gap is defined in the second metal pattern to overlap with the pixel opening in a plan view.

[0007] In an embodiment, in a plan view, a pixel opening may include a first point, a second point that is furthest from the first point in a first direction, a third point, and a fourth point that is furthest from the third point in a second direction intersecting the first direction, wherein the third point is located in the direction in which the first point intersects the first and second directions. The minimum distance in the first direction between the first point of the pixel opening and the nearest boundary line of the nearest first point in the gap and the minimum distance in the first direction between the second point and the nearest boundary line of the nearest second point in the gap may be equal to each other. Furthermore, the minimum distance in the second direction between the third point of the pixel opening and the nearest boundary line of the nearest third point in the gap and the minimum distance in the second direction between the fourth point and the nearest boundary line of the nearest fourth point in the gap may be equal to each other.

[0008] In an embodiment, in a plan view, the slits of the second metal pattern defined at the location overlapping with the pixel opening can be provided as a plurality.

[0009] In an embodiment, in a cross-sectional view, the first electrode may include a first end and a second end spaced apart from the first end in a first direction, and the second metal pattern may be spaced apart from both the first end and the second end in the first direction.

[0010] In an embodiment, in a cross-sectional view, within a pixel opening, the second metal pattern and at least one of a plurality of first metal patterns may be spaced apart from each other in a first direction.

[0011] In an embodiment, the display device may further include: a second type of transistor, at least a portion of which is located between the substrate and the first type of transistor, and the second type of transistor may include a first active pattern doped with a P-type dopant.

[0012] In an embodiment, the second active pattern may include an oxide semiconductor, and the first active pattern may include a silicon semiconductor.

[0013] In an embodiment, the pixel opening may include a first opening of a pixel emitting a first color light, a second opening of a pixel emitting a second color light different from the first color light, and a third opening of a pixel emitting a third color light different from both the first and second color lights, wherein the second color light may be green light, and the gap may be defined to at least partially overlap with the second opening in a planar view.

[0014] In an embodiment, the light-emitting element may further include: an intermediate layer disposed in a pixel opening defined by a pixel defining layer and on a first electrode; and a second electrode disposed on the intermediate layer.

[0015] In an embodiment, the display device may further include an insulating layer disposed between the second metal pattern and the first electrode, and the insulating layer may include an organic material.

[0016] A method for manufacturing a display device according to an embodiment of the present disclosure includes: forming a first type transistor on a substrate, wherein the first type transistor includes: a second active pattern disposed on the substrate and doped with an N-type dopant; a third gate electrode overlapping the second active pattern; and at least one of a plurality of first metal patterns disposed on the third gate electrode and connected to the second active pattern through a contact hole; forming a second metal pattern on the plurality of first metal patterns to cover the third gate electrode in a planar view, wherein a gap is formed through the second metal pattern to overlap with a pixel opening in the planar view; and forming a light-emitting element on the second metal pattern, wherein the light-emitting element includes a first electrode and the pixel opening is defined by a pixel defining layer.

[0017] In one embodiment, forming the second metal pattern may include: forming a second preliminary metal layer on a first via insulating layer covering a plurality of first metal patterns; and removing a portion of the second preliminary metal layer by using photoresist to define a gap.

[0018] In an embodiment, in a cross-sectional view, the first electrode may include a first end and a second end spaced apart from the first end in a first direction, and in the removal of this portion of the second preliminary metal layer, the second preliminary metal layer may be removed at a location overlapping the first end and the second end of the first electrode.

[0019] In an embodiment, during the removal of this portion of the second preliminary metal layer, the second preliminary metal layer may be removed at locations where it overlaps with a plurality of first metal patterns.

[0020] An electronic device according to an embodiment of the present disclosure includes: a processor that outputs image data signals and inputs control signals; and a display device that operates based on the image data signals and the input control signals, wherein the display device includes: a substrate; a first type transistor including a second active pattern, a third gate electrode, and at least one of a plurality of first metal patterns, the second active pattern being disposed on the substrate and doped with an N-type dopant, the third gate electrode overlapping the second active pattern, and at least one of the plurality of first metal patterns being disposed on the third gate electrode and connected to the second active pattern through a contact hole; a light-emitting element disposed on the plurality of first metal patterns and including a first electrode, wherein a pixel opening is defined by a pixel defining layer; and a second metal pattern disposed between the plurality of first metal patterns and the first electrode and covering the third gate electrode in a plan view, wherein a gap is defined in the second metal pattern to overlap with the pixel opening in a plan view.

[0021] In an embodiment, in a plan view, a pixel opening may include a first point, a second point that is furthest from the first point in a first direction, a third point, and a fourth point that is furthest from the third point in a second direction intersecting the first direction, wherein the third point is located in the direction in which the first point intersects the first and second directions. The minimum distance in the first direction between the first point of the pixel opening and the nearest boundary line of the nearest first point in the gap and the minimum distance in the first direction between the second point and the nearest boundary line of the nearest second point in the gap may be equal to each other. Furthermore, the minimum distance in the second direction between the third point of the pixel opening and the nearest boundary line of the nearest third point in the gap and the minimum distance in the second direction between the fourth point and the nearest boundary line of the nearest fourth point in the gap may be equal to each other.

[0022] In an embodiment, in a cross-sectional view, the first electrode may include a first end and a second end spaced apart from the first end in a first direction, and the second metal pattern may be spaced apart from both the first end and the second end in the first direction.

[0023] In an embodiment, in a cross-sectional view, within a pixel opening, the second metal pattern and at least one of the plurality of first metal patterns may not overlap with each other.

[0024] In an embodiment, the electronic device may further include: a second type transistor, at least a portion of which is located between a substrate and a first type transistor, and the second type transistor includes a first active pattern doped with a P-type dopant, the second active pattern comprising an oxide semiconductor, and the first active pattern comprising a silicon semiconductor.

[0025] In an embodiment, the pixel opening may include a first opening of a pixel emitting a first color light, a second opening of a pixel emitting a second color light different from the first color light, and a third opening of a pixel emitting a third color light different from both the first and second color lights, wherein the second color light may be green light, and the gap may be defined to at least partially overlap with the second opening in a planar view.

[0026] In the display device and electronic device according to embodiments of the present disclosure, a gap is formed in the second metal pattern so as not to overlap with the end of the first electrode. Accordingly, the effects caused by the tapered shape of the second metal pattern can be minimized.

[0027] Furthermore, the display device and electronic device according to embodiments of this disclosure may include a second metal pattern with slits that are symmetrical in the second metal pattern. Accordingly, color symmetry can be improved.

[0028] Furthermore, the display device and electronic device according to embodiments of this disclosure may include a second metal pattern configured not to overlap with the first metal pattern. Accordingly, the effects caused by the tapered shape of the first metal pattern can be minimized.

[0029] Furthermore, the display device and electronic device according to embodiments of this disclosure may include a second metal pattern having a gap defined therein to prevent overlap with the first type of transistor. The second metal pattern can shield the first type of transistor and effectively prevent changes in device characteristics. Attached Figure Description

[0030] The above and other features of the embodiments of this disclosure will become more apparent from the accompanying drawings, which describe the embodiments of this disclosure in more detail.

[0031] Figure 1 This is a block diagram illustrating an electronic device according to an embodiment.

[0032] Figure 2 These are schematic diagrams of electronic devices according to various embodiments.

[0033] Figure 3 This is a view illustrating an electronic device according to an embodiment.

[0034] Figure 4 It is a diagram. Figure 3 A plan view of the display device.

[0035] Figure 5 It is a diagram. Figure 3 A block diagram of the display device.

[0036] Figure 6 It is a diagram. Figure 4 and Figure 5 The circuit diagram of the pixels.

[0037] Figure 7 It is a diagram. Figure 6 A cross-sectional view of an example transistor.

[0038] Figure 8 The illustration includes Figure 1 A cross-sectional view of the second metal pattern in an electronic device.

[0039] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 It is a diagram. Figure 8 A plan view of the first and second metal patterns.

[0040] Figure 15 It is a diagram. Figure 9, Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 An enlarged view of an embodiment of part A.

[0041] Figure 16 It is a diagram. Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 A view of another embodiment of part A.

[0042] Figure 17 This is a diagram illustrating pixel positions and surface flatness according to embodiments and comparative embodiments of the present disclosure.

[0043] Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 This is a view illustrating a display device and a method of manufacturing an electronic device including the display device according to embodiments of the present disclosure. Detailed Implementation

[0044] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals refer to the same elements throughout.

[0045] It will be understood that when an element is referred to as being "on" another element, it can be directly on that other element, or there can be an intervening element between them. Conversely, when an element is referred to as being "directly on" another element, there is no intervening element.

[0046] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, the first element, component, region, layer, or part discussed below may be referred to as the second element, component, region, layer, or part without departing from the teachings of this document.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “the,” and “at least one” do not indicate a limitation of quantity and are intended to include both singular and plural. Thus, a reference to an element “a” in the claims (followed by a reference to the element “said”) includes one such element and multiple such elements. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” should not be construed as a limiting “a.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that when the terms “comprising” or “including” are used in this specification, they indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0048] Furthermore, relative terms such as “down” or “bottom” and “up” or “top” may be used herein to describe the relationship between one element and another as illustrated in the accompanying drawings. It will be understood that relative terms are intended to encompass different orientations of the device beyond those depicted in the drawings. For example, if a device in one of the drawings is flipped, the element described as being “down” to the other element will be oriented “up” to the other element. Thus, depending on the specific orientation of the figure, the term “down” can encompass both “down” and “up” orientations. Similarly, if a device in one of the drawings is flipped, the element described as being “below” or “under” the other element will be oriented “above” the other element. Thus, the term “below” or “under” can encompass both “up” and “down” orientations.

[0049] Given the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), the terms “approximately” or “about” as used herein include the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art. For example, “approximately” may mean within one or more standard deviations of the stated value, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0050] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms (e.g., those defined in common dictionaries) shall be interpreted as having the meaning consistent with their meaning in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense unless expressly defined herein.

[0051] The embodiments described herein are illustrated with cross-sectional views that are schematic illustrations of idealized embodiments. Therefore, variations in the shape of the illustrated areas are expected, for example, due to manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes of the areas illustrated in the figures, but should include deviations in shape due to, for example, manufacturing processes. For instance, areas illustrated or described as flat may generally have rough and / or non-linear characteristics. Additionally, sharp corners in the illustrations may be rounded. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to depict the precise shapes of the illustrated areas, nor are they intended to limit the scope of the present claims.

[0052] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. The same reference numerals will be used for the same parts in the drawings, and any repeated detailed descriptions of the same parts will be omitted or simplified.

[0053] The display device according to the embodiments can be applied to various electronic devices. The electronic device according to the embodiments includes the aforementioned display device, and may also include modules or devices with other additional functions in addition to the display device.

[0054] Figure 1 This is a block diagram illustrating an electronic device according to an embodiment.

[0055] refer to Figure 1 According to an embodiment, the electronic device EA may include a display module DM, a processor PC, a memory ME, and a power module PM.

[0056] The processor PC may include a central processing unit (“CPU”), an application processor (“AP”), a graphics processing unit (“GPU”), a communication processor (“CP”), an image signal processor (“ISP”), and / or a controller.

[0057] Data information used for the operation of the processor PC or display module DM can be stored in the memory ME. When the processor PC executes the application stored in the memory ME, image data signals (e.g., Figure 5 Input image data (IDAT) and / or input control signals (e.g., Figure 5 The control signal (CTRL) is transmitted to the display module DM, and the display module DM can process the received signal and output image information through the display screen.

[0058] The power module PM may include a power supply module such as a power adapter and / or battery device, and a power conversion module that converts the power supplied by the power supply module to generate power for the operation of the electronic device EA.

[0059] At least one of the components of the aforementioned electronic device EA can be included in the display device according to the above embodiments. Additionally, some individual modules that are functionally included in a single module can be included in the display device, and other individual modules can be provided separately from the display device. In embodiments, for example, the display device may include a display module DM, and the processor PC, memory ME, and power module PM may be provided as other devices in the electronic device EA besides the display device. In embodiments, the display device can operate based on image data signals and input control signals.

[0060] Figure 2 These are schematic diagrams of electronic devices according to various embodiments.

[0061] refer to Figure 2 The one or more suitable electronic devices applied to the display device according to the embodiments may include not only electronic devices for image display such as smartphones 10_1a, tablet PCs 10_1b, laptop computers 10_1c, televisions (TVs) 10_1d and / or desktop monitors 10_1e, but also wearable electronic devices including display modules such as smart glasses 10_2a, head-mounted displays 10_2b and / or smartwatches 10_2c, and vehicle electronic devices 10_3 including display modules such as interior mirror displays and / or central information displays (“CIDs”) located on the instrument panel, central dashboard and / or instrument panel of a vehicle.

[0062] Figure 3 This is a view illustrating an electronic device according to an embodiment.

[0063] refer to Figure 3 An electronic device according to an embodiment (e.g., 10_1a) may include a display device DD, a heat sink PHP, and a housing that houses the display device DD and the heat sink PHP.

[0064] exist Figure 3 In this context, the first direction DR1, the second direction DR2, and the third direction DR3 can intersect each other. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other.

[0065] For example, the plane can be defined by a first direction DR1 and a second direction DR2. For example, the normal direction of the plane (e.g., the direction of the thickness of the display device DD) can be a third direction DR3. The third direction DR3 can be the thickness direction of the electronic device.

[0066] Here, "top," "upper," and "upper surface" can refer to the direction in which the second substrate 120 is positioned relative to the first substrate 110 of the display device DD (i.e., the third direction DR3). Here, "bottom," "ground," "base," and "lower surface" can refer to the direction in which the heat sink PHP is positioned relative to the first substrate 110 of the display device DD (i.e., the direction opposite to the third direction DR3). Furthermore, "left," "right," "upper," and "lower" can refer to the orientation of the display device DD in a plan view. For example, "right" can mean the first direction DR1, "left" can mean the direction opposite to the first direction DR1, "upper" can mean the second direction DR2, and "lower" can mean the direction opposite to the second direction DR2.

[0067] In an embodiment, for example, the housing may include an upper cover TC disposed on the upper part of the display device DD and a lower cover BC disposed on the lower part of the display device DD.

[0068] The top cover TC can be positioned to cover the edge of the upper surface of the display device DD. The display device DD may include a display area in which a plurality of pixels are disposed. The display area may be surrounded by a peripheral area. In an embodiment, for example, the top cover TC may cover the display area.

[0069] The lower cover BC can be positioned to cover the entire lower surface of the display device DD. The display device DD can be connected to the driver chip DC. In an embodiment, for example, the driver chip DC may include a driver circuit 210 and a flexible film 220. The flexible film 220 can be bent such that the driver circuit 210 can be adjacent to the rear surface of the display device DD. In an embodiment, for example, the surface on which light emitted from multiple pixels is displayed as an image can be the front surface, and the surface on the third-direction DR3 facing the front surface can be the rear surface. The front surface of the display device DD can be adjacent to the upper cover TC, and the rear surface of the display device DD can be adjacent to the lower cover BC.

[0070] The mounting recess can be defined within a housing. The object to be protected can be accommodated within the space defined by the mounting recess. In one embodiment, for example, the object to be protected can be a display device DD. In another embodiment, for example, the object to be protected can be various electronic devices including the display device DD. Figure 3 An embodiment of an electronic device including a display device DD, namely a smartphone 10_1a, is shown as an example; however, this disclosure is not limited thereto. As described above, the electronic device EA can be implemented in various forms.

[0071] Figure 4 It is a diagram. Figure 3 A plan view of the display device. Figure 5 It is a diagram. Figure 3 A block diagram of the display device.

[0072] refer to Figure 3 , Figure 4 and Figure 5 An embodiment of the display device DD may include a display area DA and a non-display area NDA (i.e., the peripheral area).

[0073] The display area DA can be an area for displaying images. Multiple pixels PX can be set in the display area DA. Because the pixels PX emit light, the display area DA can display images.

[0074] The non-display area NDA can be an area where no image is displayed. The non-display area NDA can surround at least a portion of the display area DA. In an embodiment, for example, the non-display area NDA can completely surround the display area DA. A driver that provides signals or voltages to the pixel PX can be located in the non-display area NDA. In an embodiment, for example, the driver can include a gate driver GDV, a light-emitting driver EDV, a data driver DDV, and a controller CON.

[0075] Each pixel PX can be electrically connected to the gate driver GDV, the light-emitting driver EDV, and the data driver DDV. In an embodiment, each pixel PX can be connected to the gate driver GDV via a gate line GL, to the light-emitting driver EDV via a light-emitting line EL, and to the data driver DDV via a data line DL. Accordingly, each pixel PX can receive the gate signal GS, the light-emitting signal EM, and the data voltage DATA.

[0076] The gate driver GDV can receive the gate control signal GCTRL from the controller CON. The gate driver GDV can generate the gate signal GS based on the gate control signal GCTRL. The gate signal GS can be provided to each of the pixels PX through the gate line GL.

[0077] The EDV (Emitting Driver) can receive the ECTRL (Emitting Control Signal) from the CON (Controller). The EDV can then generate an EM (Emitting Signal) based on the ECTRL. The EM can be provided to each pixel PX via the EL (Emitting Line).

[0078] The data driver DDV can receive the data control signal DCTRL and output image data ODAT from the controller CON. The data driver DDV can generate a data voltage DATA based on the data control signal DCTRL and the output image data ODAT. The data voltage DATA can be supplied to each pixel PX via the data line DL.

[0079] The controller CON can receive control signals CTRL and input image data IDAT from an external device (e.g., a GPU). Based on the control signals CTRL and IDAT, the controller CON can generate gate control signals GCTRL, emission control signals ECTRL, data control signals DCTRL, and output image data ODAT. The controller CON can control the gate driver GDV, the emission driver EDV, and the data driver DDV.

[0080] Figure 6 It is a diagram. Figure 4 and Figure 5 The circuit diagram of the pixels.

[0081] refer to Figure 4 , Figure 5 and Figure 6 An embodiment of a pixel PX may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a storage capacitor CST, and a light-emitting element ED.

[0082] The first terminal of the first transistor T1 can be connected to the data line DL via the second transistor T2. In an embodiment, for example, the first transistor T1 can receive the data voltage DATA from the data line DL through its first terminal and generate a drive current corresponding to the data voltage DATA.

[0083] The second terminal of the first transistor T1 can be connected to the light-emitting element ED via the sixth transistor T6. In an embodiment, for example, the first transistor T1 can apply a drive current to the light-emitting element ED. The gate terminal of the first transistor T1 can be connected to the storage capacitor CST.

[0084] The first terminal of the second transistor T2 can be connected to the data line DL. The second terminal of the second transistor T2 can be connected to the first terminal of the first transistor T1. The gate write signal GW can be applied to the gate terminal of the second transistor T2.

[0085] Accordingly, the second transistor T2 can be turned on by the gate write signal GW. During the interval when the second transistor T2 is turned on (i.e., during the on-time of the second transistor T2), the second transistor T2 can apply the data voltage DATA to the first transistor T1.

[0086] The first terminal of the third transistor T3 can be connected to the second terminal of the first transistor T1. The second terminal of the third transistor T3 can be connected to the gate terminal of the first transistor T1. The gate compensation signal GC can be applied to the gate terminal of the third transistor T3.

[0087] Accordingly, the third transistor T3 can be turned on by the gate compensation signal GC. During the interval when the third transistor T3 is turned on, since the third transistor T3 is diode connected to the first transistor T1, the third transistor T3 can compensate for the threshold voltage.

[0088] A first initialization voltage VINT can be applied to the first terminal of the fourth transistor T4. The second terminal of the fourth transistor T4 can be connected to the gate terminal of the first transistor T1. A first gate initialization signal GI can be applied to the gate terminal of the fourth transistor T4.

[0089] Accordingly, the fourth transistor T4 can be turned on by the first gate initialization signal GI. During the interval when the fourth transistor T4 is turned on, the fourth transistor T4 can apply the first initialization voltage VINT to the gate terminal of the first transistor T1.

[0090] A first electrical voltage, ELVDD, can be applied to the first terminal of the fifth transistor T5. The second terminal of the fifth transistor T5 can be connected to the first terminal of the first transistor T1. A light emission signal, EM, can be applied to the gate terminal of the fifth transistor T5.

[0091] Accordingly, the fifth transistor T5 can be turned on by the light-emitting signal EM. During the interval when the fifth transistor T5 is turned on, the fifth transistor T5 can apply the first power voltage ELVDD to the first transistor T1.

[0092] In this embodiment, the first power voltage ELVDD and the second power voltage ELVSS applied to the light-emitting element ED can be constant voltages. The first power voltage ELVDD and the second power voltage ELVSS can have different voltage levels than each other.

[0093] The first terminal of the sixth transistor T6 can be connected to the second terminal of the first transistor T1. The second terminal of the sixth transistor T6 can be connected to the light-emitting element ED. The light-emitting signal EM can be applied to the gate terminal of the sixth transistor T6.

[0094] Accordingly, the sixth transistor T6 can be turned on by the light-emitting signal EM. During the interval when the sixth transistor T6 is turned on, the sixth transistor T6 can apply a drive current to the light-emitting element ED.

[0095] The second initialization voltage VAINT can be applied to the first terminal of the seventh transistor T7. The second terminal of the seventh transistor T7 can be connected to the light-emitting element ED. The second gate initialization signal GB can be applied to the gate terminal of the seventh transistor T7.

[0096] Accordingly, the seventh transistor T7 can be turned on by the second gate initialization signal GB. During the interval when the seventh transistor T7 is turned on, the seventh transistor T7 can apply the second initialization voltage VAINT to the light-emitting element ED.

[0097] A bias voltage VBIAS can be applied to the first terminal of the eighth transistor T8. The second terminal of the eighth transistor T8 can be connected to the first terminal of the first transistor T1. A second gate initialization signal GB can be applied to the gate terminal of the eighth transistor T8.

[0098] Accordingly, the eighth transistor T8 can be turned on by the second gate initialization signal GB. During the interval when the eighth transistor T8 is turned on, the eighth transistor T8 can apply a bias voltage VBIAS to the first transistor T1.

[0099] The first terminal of the storage capacitor CST can be connected to the gate terminal of the first transistor T1. A first electrical voltage ELVDD can be applied to the second terminal of the storage capacitor CST opposite to the first terminal.

[0100] The storage capacitor CST can be used to maintain the voltage level of the gate electrode of the gate terminal of the first transistor T1 during the invalid interval of the gate write signal GW.

[0101] In an embodiment, for example, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-channel metal-oxide-semiconductor (“PMOS”) transistors, and the third transistor T3 and the fourth transistor T4 may be N-channel metal-oxide-semiconductor (“NMOS”) transistors.

[0102] NMOS transistors use electrons as the primary charge carriers. When a positive voltage is applied to the gate electrode, the NMOS transistor can be turned on. NMOS transistors can exhibit relatively high current density and fast switching speeds, therefore they are commonly used in high-speed, high-performance electronic devices.

[0103] On the other hand, PMOS transistors can use holes as the primary charge carriers. When a negative voltage is applied to the gate electrode, the PMOS transistor can be turned on. PMOS transistors can have relatively low switching speeds but low power consumption, making them suitable for portable electronic devices where reduced power consumption is required.

[0104] However, Figures 1 to 6The embodiments shown are merely examples, and this disclosure is not limited thereto. In another embodiment, for example, the transistor type of each of the first to eighth transistors T1, T2, T3, T4, T5, T6, T7, T8 is not limited thereto.

[0105] Figure 7 It is a diagram. Figure 6 A cross-sectional view of an example transistor. Figure 8 The illustration includes Figure 1 A cross-sectional view of the second metal pattern in an electronic device.

[0106] For example, Figure 8 From Figure 7 A cross-sectional view taken starting from the top of the second interlayer insulation layer (ILD2). For ease of illustration and description, [the following text is missing]. Figure 8 In this diagram, the components below the second interlayer insulating layer ILD2, namely the components from the substrate SUB to the third gate insulating layer GI3, are omitted.

[0107] refer to Figure 6 , Figure 7 and Figure 8 An embodiment of the display device DD may include a substrate SUB, a buffer layer BFR, a first active pattern AP1, a first gate insulating layer GI1, a first gate electrode GE1, a second gate insulating layer GI2, a second gate electrode GE2, a second-second gate electrode GE22, a first interlayer insulating layer ILD1, a second active pattern AP2, a third gate insulating layer GI3, a first third gate electrode GE31, a second third gate electrode GE32, a second interlayer insulating layer ILD2, a first metal pattern ME1, and a first via insulating layer VIA1. In an embodiment, for example, the first metal pattern ME1 may include or define a first source electrode EP13, a first drain electrode EP14, a second source electrode EP11, and a second drain electrode EP12.

[0108] The substrate SUB can be made of transparent or opaque materials. The substrate SUB can include glass, quartz, or plastic, etc. These can be used individually or in combination.

[0109] A buffer layer (BFR) can be disposed on the substrate SUB. The buffer layer BFR prevents metal atoms or impurities from diffusing from the substrate SUB to the transistor. Additionally, when the surface of the substrate SUB is uneven, the buffer layer BFR can improve the surface flatness of the substrate SUB. The buffer layer BFR can include materials such as silicon oxide (SiO2). x Silicon nitride (SiN) x ), silicon carbide (SiC) x ), silicon oxynitride (SiO) x N y ) or silicon dioxide (SiO) x Cy Inorganic materials such as ( ). These can be used alone or in combination with each other.

[0110] A first active pattern AP1 may be disposed on a buffer layer BFR. The first active pattern AP1 may include a source region SA1, a drain region DA1, and a channel region CA1 located between the source region SA1 and the drain region DA1. In an embodiment, the first active pattern AP1 may include a silicon semiconductor material. In an embodiment, for example, the first active pattern AP1 may include amorphous silicon or polycrystalline silicon, etc. These can be used individually or in combination with each other.

[0111] In an embodiment, the first active pattern AP1 may include a P-type impurity. For example, the P-type impurity may include boron (B) ions. The P-type impurity may be doped into the source region SA1 and drain region DA1 of the first active pattern AP1. For example, in an embodiment, the source region SA1 and drain region DA1 of the first active pattern AP1 may correspond to the first and second terminals of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8, respectively.

[0112] The first gate insulating layer GI1 may be disposed on the buffer layer BFR and may cover the first active pattern AP1. The first gate insulating layer GI1 may comprise inorganic materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon carbide. These may be used individually or in combination with each other.

[0113] The first gate electrode GE1 can be disposed on the first gate insulating layer GI1. The first gate electrode GE1 can overlap with the channel region CA1 of the first active pattern AP1 in the third direction DR3 (or the thickness direction of the substrate SUB). The first gate electrode GE1 can include a metal, alloy, conductive metal oxide, or conductive metal nitride, etc. Examples of metals can include silver (Ag), molybdenum (Mo), aluminum (Al), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), titanium (Ti), tantalum (Ta), platinum (Pt), or scandium (Sc), etc. In embodiments, for example, the conductive metal oxide can include indium tin oxide or indium zinc oxide, etc. In embodiments, for example, the conductive metal nitride can include aluminum nitride (AlN), etc. x ), Tungsten nitride (WN) x ) or chromium nitride (CrN) x These can be used individually or in combination with each other. In an embodiment, for example, the first gate electrode GE1 may correspond to the gate terminals of the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8.

[0114] A second gate insulating layer GI2 may be disposed on the first gate insulating layer GI1 and may cover the first gate electrode GE1. In embodiments, for example, the second gate insulating layer GI2 may comprise an inorganic material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon carbide. These may be used individually or in combination with each other.

[0115] The second gate electrode GE2 and the second-second gate electrode GE22 may be disposed on the second gate insulating layer GI2. The second gate electrode GE2 and the second-second gate electrode GE22 may be disposed in the same layer as each other (or directly disposed on the same layer as each other). In embodiments, for example, the second gate electrode GE2 and the second-second gate electrode GE22 may comprise the same material or be formed of the same material.

[0116] The second gate electrode GE2 and the second-second gate electrode GE22 may include metals, alloys, conductive metal oxides, or conductive metal nitrides, etc. These can be used individually or in combination with each other.

[0117] The second gate electrode GE2 may overlap with the first gate electrode GE1 on the third-direction DR3. In an embodiment, for example, the first gate electrode GE1, the second gate electrode GE2, and the second gate insulating layer GI2 therebetween may constitute... Figure 6 Storage capacitor CST.

[0118] In an embodiment, for example, the second-second gate electrode GE22 can be with Figure 6 The lower gate terminals of the third transistor T3 and the fourth transistor T4 correspond to each other.

[0119] The first interlayer insulating layer ILD1 can be disposed on the second gate insulating layer GI2 and can cover the second gate electrode GE2 and the second gate electrode GE22. In embodiments, for example, the first interlayer insulating layer ILD1 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon carbide. These can be used individually or in combination with each other.

[0120] A second active pattern AP2 may be disposed on the first interlayer insulating layer ILD1. The second active pattern AP2 may include a material different from that of the first active pattern AP1. In an embodiment, the second active pattern AP2 may include an oxide semiconductor material. For example, in an embodiment, the second active pattern AP2 may include indium gallium zinc oxide or indium tin zinc oxide, etc. These may be used individually or in combination with each other.

[0121] The second active pattern AP2 may include a source region SA2, a drain region DA2, and a channel region CA2 located between the source region SA2 and the drain region DA2. In an embodiment, the second active pattern AP2 may include an N-type impurity. In an embodiment, for example, the N-type impurity may include phosphorus (P) ions. The N-type impurity may be doped into the source region SA2 and the drain region DA2 of the second active pattern AP2. In an embodiment, for example, the source region SA2 and the drain region DA2 of the second active pattern AP2 may be respectively doped with Figure 6 The first and second terminals of the third transistor T3 and the fourth transistor T4 correspond to each other.

[0122] The third gate insulating layer GI3 can be disposed on the first interlayer insulating layer ILD1 and can cover the second active pattern AP2. The third gate insulating layer GI3 may include inorganic materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon carbide. These can be used alone or in combination with each other.

[0123] The first and second gate electrodes GE31 and GE32 can be disposed on the third gate insulating layer GI3. The first and second gate electrodes GE31 and GE32 can be disposed in the same layer as each other (or directly disposed on the same layer as each other). In an embodiment, for example, the first and second gate electrodes GE31 and GE32 can be formed using the same material and the same process.

[0124] The first and third gate electrodes GE31 and the second and third gate electrodes GE32 may include metals, alloys, conductive metal oxides, or conductive metal nitrides. These may be used individually or in combination with each other.

[0125] The first and third gate electrodes GE31 may overlap with the channel region CA2 of the second active pattern AP2 on the third-direction DR3. In an embodiment, for example, the first and third gate electrodes GE31 may be with Figure 6 The upper gate terminals of the third transistor T3 and the fourth transistor T4 correspond to each other.

[0126] The second and third gate electrodes GE32 can be electrically connected to the second gate electrode GE22 through a contact hole CNT that penetrates the third gate insulating layer GI3 and the first interlayer insulating layer ILD1 (i.e., defined or formed through the third gate insulating layer GI3 and the first interlayer insulating layer ILD1). In an embodiment, for example, the second and third gate electrodes GE32 can be connected to the second gate electrode GE22. Figure 6 The upper gate terminals of the third transistor T3 and the fourth transistor T4 correspond to each other.

[0127] The second interlayer insulating layer ILD2 can be disposed on the third gate insulating layer GI3 and can cover the first third gate electrode GE31 and the second third gate electrode GE32. In embodiments, for example, the second interlayer insulating layer ILD2 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon carbide. These can be used individually or in combination with each other.

[0128] A first metal pattern ME1 (e.g., a first source electrode EP13, a first drain electrode EP14, a second source electrode EP11, and a second drain electrode EP12) can be disposed on a second interlayer insulating layer ILD2. The first source electrode EP13, the first drain electrode EP14, the second source electrode EP11, and the second drain electrode EP12 can be formed using the same material and the same process.

[0129] The first source electrode EP13, the first drain electrode EP14, the second source electrode EP11, and the second drain electrode EP12 may include metals, alloys, conductive metal oxides, or conductive metal nitrides, etc. These can be used individually or in combination with each other.

[0130] The first source electrode EP13 can contact the source region SA1 of the first active pattern AP1 through a contact hole that penetrates a portion of the first gate insulating layer GI1, the second gate insulating layer GI2 and the third gate insulating layer GI3, as well as portions of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 (through said portions).

[0131] The first drain electrode EP14 can contact the drain region DA1 of the first active pattern AP1 through a contact hole that penetrates a portion of the first gate insulating layer GI1, the second gate insulating layer GI2 and the third gate insulating layer GI3, as well as portions of the first interlayer insulating layer ILD1 and the second interlayer insulating layer ILD2 (through said portions).

[0132] The second source electrode EP11 can contact the source region SA2 of the second active pattern AP2 through a contact hole (e.g., CNT) that penetrates a portion of the third gate insulating layer GI3 and the second interlayer insulating layer ILD2 (through the portion defined by said portion).

[0133] The second drain electrode EP12 can contact the drain region DA2 of the second active pattern AP2 through a contact hole that penetrates a portion of the third gate insulating layer GI3 and the second interlayer insulating layer ILD2 (through the portion defined by said portion).

[0134] Accordingly, a second type transistor PTR2, including some of the first metal pattern ME1 (e.g., the first source electrode EP13 and the first drain electrode EP14), the first active pattern AP1, and the first gate electrode GE1, can be disposed on the substrate SUB.

[0135] Additionally, a first-type transistor PTR1, including some of the first metal pattern ME1 (e.g., the second source electrode EP11 and the second drain electrode EP12), the second-second gate electrode GE22, the second active pattern AP2, the first third gate electrode GE31, and the second third gate electrode GE32, can be disposed on the second gate insulating layer GI2. In other words, in the embodiment, at least a portion of the second-type transistor PTR2 can be disposed between the substrate SUB and the first-type transistor PTR1.

[0136] A first via insulating layer VIA1 can be disposed on the second interlayer insulating layer ILD2 and can cover the first source electrode EP13, the first drain electrode EP14, the second source electrode EP11, and the second drain electrode EP12. The first via insulating layer VIA1 can include organic materials. In embodiments, for example, the first via insulating layer VIA1 can include phenolic resin, acrylic resin, polyimide resin, polyamide resin, silicone resin, or epoxy resin, etc. These can be used individually or in combination with each other.

[0137] In an embodiment, for example, the light-emitting element ED can be coupled to a third-party DR3. Figure 7 The first type transistor PTR1 and the second type transistor PTR2 overlap. Figure 8 For ease of illustration and description, the first type of transistor PTR1 can be mainly depicted.

[0138] A second through-hole insulating layer VIA2 may be disposed on the first through-hole insulating layer VIA1. The second through-hole insulating layer VIA2 may cover the second metallic pattern ME2. In embodiments, the second through-hole insulating layer VIA2 may include an organic material. For example, the second through-hole insulating layer VIA2 may include polyimide resin, polyamide resin, silicone resin, or epoxy resin, etc. These may be used individually or in combination with each other.

[0139] In this embodiment, the light-emitting element ED can be disposed on the second through-hole insulating layer VIA2. The light-emitting element ED may include a first electrode E1, an intermediate layer ML, and a second electrode E2.

[0140] The first electrode E1 can be disposed on the second via insulating layer VIA2. The first electrode E1 can be connected to the second drain electrode EP14 through a contact hole (not shown) that penetrates the second via insulating layer VIA2 (defined by the second via insulating layer VIA2). The first electrode E1 may include metal, alloy, conductive metal oxide, conductive metal nitride, or transparent conductive material, etc. These can be used alone or in combination with each other. In an embodiment, for example, the first electrode E1 may include silver (Ag) and indium tin oxide (“ITO”).

[0141] A pixel defining layer (PDL) may be disposed on the second via insulating layer (VIA2). In an embodiment, the pixel defining layer (PDL) may partially cover the first electrode E1. In an embodiment, for example, the pixel defining layer (PDL) may cover the first terminal EN1 and the second terminal EN2 of the first electrode E1.

[0142] In an embodiment, a pixel opening may be defined in a pixel defining layer (PDL) to expose at least a portion of the first electrode E1. In an embodiment, for example, the pixel opening in the PDL may expose a central portion of the first electrode E1, and the PDL may cover two opposite ends of the first electrode E1 (e.g., the first end EN1 and the second end EN2).

[0143] The pixel defining layer (PDL) may comprise inorganic or organic materials. In embodiments, for example, the pixel defining layer (PDL) may comprise epoxy resin or silicone resin, etc. These may be used alone or in combination with each other. However, this disclosure is not limited thereto. In embodiments, for example, the pixel defining layer (PDL) may further comprise a light-shielding material comprising black pigment or black dye, etc.

[0144] An intermediate layer ML may be disposed on the pixel defining layer PDL. The intermediate layer ML may be disposed on a first electrode E1 exposed by a pixel opening in the pixel defining layer PDL. The intermediate layer ML may include an organic light-emitting material. In embodiments, for example, the intermediate layer ML may include a low molecular weight organic compound or a high molecular weight organic compound. However, this disclosure is not limited thereto. In embodiments, for example, the intermediate layer ML may include a material such as a quantum dot.

[0145] The second electrode E2 can be disposed on the intermediate layer ML. The second electrode E2 can include metals, alloys, conductive metal oxides, conductive metal nitrides, or transparent conductive materials, etc. In embodiments, for example, the second electrode E2 can include aluminum (Al), platinum (Pt), silver (Ag), magnesium (Mg), gold (Au), chromium (Cr), tungsten (W), or titanium (Ti), etc. These can be used individually or in combination with each other.

[0146] In one embodiment, the second metal pattern ME2 may be disposed between the first metal pattern ME1 and the first electrode E1. In another embodiment, for example, the second metal pattern ME2 may be disposed on the first through-hole insulating layer VIA1. In yet another embodiment, for example, the second metal pattern ME2 may include a connecting electrode and a shielding pattern.

[0147] For example, the connection electrode can be connected to the first drain electrode EP14 through a contact hole (not shown) that penetrates the first through-hole insulating layer VIA1 (defined by the first through-hole insulating layer VIA1). Accordingly, the connection electrode can electrically connect the second type transistor PTR2 and the light-emitting element ED. In embodiments, the connection electrode may, for example, include metals, alloys, conductive metal nitrides, conductive metal oxides, or transparent conductive materials, etc. These can be used individually or in combination with each other.

[0148] In an embodiment, the shielding pattern (e.g., Figure 8 EP21 can cover the first and third gate electrodes GE31. In the case of NMOS transistors, there is a problem of electron movement due to external light. In embodiments, for example, when light of a specific wavelength is incident on an NMOS transistor, the device characteristics of the channel may change due to the movement of electrons. This may change the performance of the NMOS transistor, resulting in a brightness difference different from the design. In embodiments, a shielding pattern can be disposed on the light-emitting portion (e.g., the portion overlapping the pixel opening defined by the pixel defining layer PDL, described below) to effectively prevent light incident on this light-emitting portion from altering the device characteristics. The shielding pattern can shield the underlying NMOS transistor from the influence of external light.

[0149] In an embodiment, at the location where the slit overlaps with the pixel opening along the third direction DR3, the gap can be defined within the second metal pattern ME2. In an embodiment, for example, as... Figure 8 As shown, in the cross-sectional view (which may be defined by a first direction DR1 and a third direction DR3), the second metal pattern ME2 may include a first portion EP21 and a second portion EP22, with the gap defined between the first portion EP21 and the second portion EP22.

[0150] In the case of the display device and electronic device according to the comparative embodiments, the shielding pattern can be formed by deposition over a large area. For example, Figure 8 The second metal pattern ME2 is shown as including a first part EP21 and a second part EP22, but in the case of a display device according to a comparative embodiment and an electronic device including a display device, the first part EP21 and the second part EP22 may have a continuous form.

[0151] Deposition can be performed using sputtering facilities. Due to the limitations of sputtering facilities, the top surface of the shielding pattern may not be flat. After deposition over a large area, the ends of the shielding pattern may be tapered.

[0152] If the pixel opening is formed at the tapered end of the shielding pattern, unevenness in the luminescent portion may occur. Depending on the size of the cone angle, positional coverage distortion may occur. Consequently, the viewing angle characteristics may deteriorate.

[0153] To effectively prevent degradation of viewing angle characteristics due to unevenness in the light-emitting portion, the display device and the electronic device including the display device according to the comparative embodiment may include a relatively thick insulating layer (e.g., a second through-hole insulating layer VIA2). For example, the thickness of the second through-hole insulating layer VIA2 may be relatively thick compared to other insulating layers. Alternatively, an additional insulating layer may be formed on the second through-hole insulating layer VIA2. As described above, the insulating layer comprising an organic material (e.g., the second through-hole insulating layer VIA2) may have a flat top surface. Accordingly, in this case, the effects due to the tapered shape can be minimized.

[0154] However, as the thickness of the insulating layer, including organic materials, increases, manufacturing costs and time may also increase. Furthermore, the thickness of the display device and the electronic device including it may also increase. Additionally, a relatively thick insulating layer may lead to new problems such as pixel shrinkage.

[0155] On the other hand, when a user views a display screen, they may view it from various angles in front of them (e.g., from the bottom to the top of the screen or from the side to the center). For example, they may view it from... Figure 3 and Figure 4 The DC section of the driver chip can be used to view the display screen in the second direction DR2, or it can be viewed in the opposite direction of the first direction DR1 or tilted on the first direction DR1.

[0156] In this regard, wide-angle distortion (“WAD”) is becoming increasingly important. WAD refers to the property that color and brightness change depending on the viewing angle. For example, as the viewing angle widens, color and brightness may change inconsistently (i.e., color asymmetry).

[0157] In the case of the display device and the electronic device including the display device according to the comparative embodiment, when the shielding pattern is deposited over a large area, it may be uneven (flatness difference) in the left-right direction (e.g., in the opposite direction of the first direction DR1 or on the first direction DR1) or in the up-down direction (e.g., in the opposite direction of the second direction DR2 or on the second direction DR2). In this case, color asymmetry may occur.

[0158] In the display device and electronic device including the display device according to embodiments of the present disclosure, the gap can be defined in the second metal pattern ME2. By means of the gap, the second metal pattern ME2 can be formed to be small in size and simultaneously symmetrical. Accordingly, a thinner display device (without increasing the thickness of the insulating layer) and an electronic device including the display device with improved display quality (viewing angle characteristics) can be provided.

[0159] In an embodiment, in a cross-sectional view, the second metal pattern ME2 may be separated from the first end EN1 and the second end EN2 of the first electrode E1 in a first direction DR1. In another embodiment, for example, the second metal pattern ME2 may not overlap with both the first end EN1 and the second end EN2 of the first electrode E1 in a third direction DR3 in the region corresponding to the pixel opening.

[0160] If the second metal pattern ME2 overlaps with the end of the first electrode E1 (e.g., the first end EN1 and / or the second end EN2) on the third direction DR3, the first electrode E1 may be bent due to the tapered shape of the second metal pattern ME2. For example, if the second metal pattern ME2 only overlaps with the first end EN1 on the third direction DR3, the first end EN1 may be at a higher horizontal level than the second end EN2. In this case, the color coordinate difference may lead to a decrease in display quality (e.g., unintended coloring).

[0161] However, in the display device (and electronic device including the display device) according to embodiments of the present disclosure, the second metal pattern ME2 may not overlap with the ends (e.g., the first end EN1 and the second end EN2) of the first electrode E1 in the third direction DR3 in the region corresponding to the pixel opening. Accordingly, a decrease in display quality due to color coordinate differences can be effectively prevented.

[0162] In an embodiment, in a cross-sectional view, the second metal pattern ME2 may be spaced apart from the first metal pattern ME1. In another embodiment, for example, the second metal pattern ME2 may not overlap with the first metal pattern ME1 in the third-direction DR3 region corresponding to the pixel opening.

[0163] When the second metal pattern ME2 overlaps with the first metal pattern ME1 on the third-direction DR3, the first electrode E1 may be bent due to the tapered shape of the first metal pattern ME1. In an embodiment, for example, in the region where both the first metal pattern ME1 and the second metal pattern ME2 are formed, the first electrode E1 may be formed at a higher horizontal height due to the combined height of the first metal pattern ME1 and the second metal pattern ME2, compared to a region where neither the first metal pattern ME1 nor the second metal pattern ME2 exists. In this case, the color coordinate difference may degrade the display quality (e.g., displaying in unexpected colors).

[0164] However, in a display device (and an electronic device including the display device) according to embodiments of the present disclosure, the second metal pattern ME2 may not overlap with the first metal pattern ME1 in the third direction DR3 in the region corresponding to the pixel opening. In such an embodiment, since the bending formation of the first electrode E1 due to the tapered shape of the first metal pattern ME1 is effectively prevented, the degradation of display quality caused by color coordinate difference can also be effectively prevented.

[0165] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 It is a diagram. Figure 8 A plan view of the first and second metal patterns.

[0166] For example, Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 The main illustration shows the region of the pixel opening POP through which light of the first color to the third color is emitted.

[0167] refer to Figure 9 In an embodiment, the pixel aperture POP may include a first aperture POP1 of a pixel that emits a first color light, a second aperture POP2 of a pixel that emits a second color light that is different from the first color light, and a third aperture POP3 of a pixel that emits a third color light that is different from the first color light and the second color light.

[0168] In one embodiment, the first color light can be red light, the second color light can be green light, and the third color light can be blue light. However, this disclosure is not limited thereto. In another embodiment, for example, the first to third color lights can be light-emitting colors other than red, green, and blue. In yet another embodiment, for example, the first to third color lights can emit light of the same color as each other.

[0169] refer to Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14In an embodiment, the second metal pattern ME2 may be disposed on the first metal pattern ME1. Here, as shown in section A, in a plan view (or when viewed on a third-party DR3), the gap may be defined at a location overlapping the pixel opening POP. However, this disclosure is not limited thereto. In an embodiment, for example, the gap may also be defined at a location not overlapping the pixel opening POP (see reference). Figure 13 At the lower part of part A, to minimize the effect caused by the cone shape of the second metal pattern ME2. Accordingly, the second metal pattern ME2 can be minimized.

[0170] like Figure 13 As shown, in one embodiment, the gap may be defined to overlap with at least a portion of the second opening POP2. In one embodiment, for example, in the case of including RGB pixels (pixels emitting red, green, and blue light respectively), the viewing angle characteristics may be most sensitive to the pixels emitting green light. Accordingly, the gap may be defined to overlap with at least a portion of the second opening POP2. However, this disclosure is not limited thereto. In another embodiment, for example, the gap may be formed to overlap with the first opening POP1 and the third opening POP3, such that the second metallic pattern ME2 can have a further reduced area.

[0171] For example, in Figure 10 In part A, the NMOS transistor can be located in the symmetrical part. For example... Figure 12 As shown, the gap can be defined within a second metal pattern ME2. The gap may not overlap with an NMOS transistor (e.g., a channel). In other words, the NMOS transistor can be shielded by the second metal pattern ME2. Accordingly, the display device and the electronic device including the display device can be thinned and effectively prevent changes in component characteristics due to external light, thereby improving color symmetry.

[0172] Figure 15 It is a diagram. Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 An enlarged view of an embodiment of part A. Figure 16 It is a diagram. Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 and Figure 14 A view of another embodiment A' of part A.

[0173] refer to Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 In an embodiment, in a planar view, the second metallic pattern ME2 may have multiple slits SL defined at the location overlapping with the pixel opening POP. In an embodiment, for example, a first slit SL1 and a second slit SL2 may be defined at the location overlapping with the second opening POP2. As the number of slits SL in the second metallic pattern ME2 increases, the second metallic pattern ME2 can undergo further area reduction and can further improve color symmetry.

[0174] In an embodiment, a pixel opening (e.g., a second opening POP2) may include a first point PO1, a second point PO2, a third point PO3, and a fourth point PO4. The second point PO2 may be the position furthest from the first point PO1 (i.e., the furthest separated from the first point PO1) along the first direction DR1. The third point PO3 may be located in the direction intersecting the first direction DR1 and the second direction DR2. The fourth point PO4 may be the position furthest from the third point PO3 (i.e., the furthest separated from the third point PO3) along the second direction DR2.

[0175] In an embodiment, the first gap G1 and the second gap G2 may be the same as (or equal to) each other. The first gap G1 may be defined as the minimum distance in the first direction DR1 between a first point PO1 of a pixel opening (e.g., a second opening POP2) and the nearest boundary line in the gap SL to the first point PO1 (e.g., a first side of the second gap SL2). The second gap G2 may be defined as the minimum distance in the first direction DR1 between a second point PO2 and the nearest boundary line in the gap SL to the second point PO2 (e.g., a second side of the first gap SL1).

[0176] In such an embodiment, the third gap G3 and the fourth gap G4 may be identical (or equal). The third gap G3 may be defined as the minimum distance in the second direction DR2 between the third point PO3 of the pixel opening (e.g., the second opening POP2) and the boundary line in the gap SL that is closest to the third point PO3 (e.g., the third side intersecting the first side of the second gap SL2). The fourth gap G4 may be defined as the minimum distance in the second direction DR2 between the fourth point PO4 and the boundary line in the gap SL that is closest to the fourth point PO4 (e.g., the fourth side of the first gap SL1 that intersects the second side).

[0177] refer to Figure 16 In an embodiment, in a planar view, the slits SL defining the second metal pattern ME2 at the location overlapping the pixel opening can be multiple. In an embodiment, for example, in... Figure 15In this embodiment, the slits SL (e.g., a first slit SL1 and a second slit SL2) can be formed parallel to the boundary of the pixel opening. In another embodiment, such as Figure 16 As shown, the difference in the formation of multiple slits is that the boundaries of the pixel openings are not considered.

[0178] In an embodiment, such as Figure 15 As shown, the boundaries of the pixel openings and the second metal pattern ME2 overlap each other. In another embodiment, as... Figure 16 As shown, a portion of the boundary of the pixel opening and the second metal pattern ME2 do not overlap. In other words, depending on the location defining the gap SL, as... Figure 15 As shown, the boundary of the pixel opening can overlap with the second metal pattern ME2, or as... Figure 16 As shown, it may include the boundary of the pixel opening and the portion of the second metal pattern ME2 that does not overlap.

[0179] In an embodiment, a pixel opening (e.g., a second opening POP2) may include a first point PO1', a second point PO2', a third point PO3', and a fourth point PO4'. The second point PO2' may be the position furthest from the first point PO1' in the first direction DR1. The third point PO3' may be located in the direction where the first point PO1' intersects with the first direction DR1 and the second direction DR2. The fourth point PO4' may be the position furthest from the third point PO3' in the second direction DR2.

[0180] In an embodiment, such as Figure 16 As shown, the first gap G1' and the second gap G2' can be the same as each other (or equal). The first gap G1' can be defined as the minimum distance in the first direction DR1 between a first point PO1' of a pixel opening (e.g., a second opening POP2) and the nearest boundary line in the gap to the first point PO1'. The second gap G2' can be defined as the minimum distance in the first direction DR1 between a second point PO2' and the nearest boundary line in the gap to the second point PO2'.

[0181] In such an embodiment, the third gap G3' and the fourth gap G4' can be the same (or equal). The third gap G3' can be defined as the minimum distance in the second direction DR2 between the third point PO3' of the pixel opening (e.g., the second opening POP2) and the nearest boundary line in the gap to the third point PO3'. The fourth gap G4' can be defined as the minimum distance in the second direction DR2 between the fourth point PO4' and the nearest boundary line in the gap to the fourth point PO4'.

[0182] The second metallic pattern ME2, with slits defined therein, can be observed under a microscope at the location where it overlaps with the pixel opening. Because the slits of the second metallic pattern ME2 have a symmetrical structure, the effects caused by the tapering can be minimized. Accordingly, viewing characteristics (color asymmetry) can be further improved.

[0183] In the embodiments, the first gap G1 (or the second gap G2) and the third gap G3 (or the fourth gap G4) may be the same as each other or may be different from each other. Here, as the length of the gaps (e.g., the first gap to the fourth gaps G1, G2, G3, G4) increases, the cone angle can be reduced to further improve the viewing angle characteristics (color asymmetry).

[0184] Figure 17 This is a diagram illustrating pixel positions and surface flatness according to embodiments and comparative embodiments of the present disclosure.

[0185] exist Figure 17 In the diagram, the horizontal axis represents the pixel position, and the vertical axis represents the surface flatness.

[0186] refer to Figure 9 and Figure 17 For example, X1 represents the lowest position of the third opening POP3, and XN represents the highest position of the third opening POP3 (e.g., in...). Figure 9 In this context, XN represents a location at a second distance from X1 along the second direction DR2. For example, Y1 represents the lowest position of the second opening POP2, and YN represents the highest position of the second opening POP2 (e.g., in...). Figure 9 In this context, YN represents the position located on the second direction DR2, separated from Y1.

[0187] As described above, in the case of the electronic device according to the comparative embodiment, a large-area shielding pattern may be included. In other words, the gap may not be limited to the shielding pattern included in the display device and the electronic device including the display device according to the comparative embodiment. In this case, the insulating layer overlapping with the third opening POP3 (e.g., Figure 8 Measurements of the horizontal height of the top surface of the second through-hole insulating layer (VIA2) showed that the insulating layer varied between approximately 7.05 micrometers and approximately 7.22 micrometers. Measurements of the top surface of the insulating layer overlapping the second opening POP2 in the case of the electronic device according to the comparative embodiment showed that the insulating layer varied between approximately 7.1 micrometers and approximately 7.22 micrometers (see the dashed REF).

[0188] In the case of a display device and an electronic device including the display device according to embodiments of the present disclosure, a shielding pattern having slits defined therein may be included (e.g., Figure 8The second metal pattern ME2). The gap can be defined as symmetrical about the corresponding opening (e.g., refer to...). Figure 15 and Figure 16 In this case, the insulating layer overlapping with the third opening POP3 (e.g., Figure 8 Measurements of the horizontal height of the top surface of the second through-hole insulating layer (VIA2) indicate that the insulating layer varies between approximately 7.03 micrometers and approximately 7.05 micrometers. Measurements of the top surface of the insulating layer overlapping the second opening POP2 in the case of a display device and an electronic device including the display device according to embodiments of the present disclosure indicate that the insulating layer varies between approximately 7.04 micrometers and approximately 7.08 micrometers (see solid line DD).

[0189] In the case of the display device and the electronic device including the display device according to embodiments of the present disclosure, it can be confirmed that, due to the shielding pattern having symmetrical slits defined therein, the flatness difference of the light-emitting portion is reduced from approximately 0.18 to approximately 0.04. Accordingly, the flatness difference of the light-emitting portion can be improved without increasing the thickness of the insulating layer. In addition, positional coverage deformation can be prevented more effectively, and viewing angle characteristics (e.g., color asymmetry, etc.) can be further improved. As a result, a thinner display device (and an electronic device including the display device) with improved display quality can be provided.

[0190] Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 This is a view illustrating a display device and a method of manufacturing an electronic device including the display device according to embodiments of the present disclosure.

[0191] In the following text, Figure 18 , Figure 19 , Figure 20 , Figure 21 , Figure 22 , Figure 23 and Figure 24 In the description of the display device and the method of manufacturing the electronic device including the display device shown herein, the references above will be omitted or simplified. Figures 1 to 17 The components described are the same as or similar to the components.

[0192] refer to Figure 7 , Figure 18 and Figure 19The second active pattern AP2 with N-type dopant, the first third gate electrode GE31 overlapping the second active pattern AP2, and some (or at least one) first metal pattern ME1 disposed on the first third gate electrode GE31 and connected to the second active pattern AP2 through contact holes can be formed on the substrate SUB (step S100).

[0193] In an embodiment, for example, a second active pattern AP2 may be formed on a first interlayer insulating layer ILD1. A third gate insulating layer GI3 may be formed to cover the second active pattern AP2. A first third gate electrode GE31 may be formed on the third gate insulating layer GI3. A second interlayer insulating layer ILD2 may be formed to cover the first third gate electrode GE31. A first metal pattern ME1 may be formed in a contact hole (e.g., CNT) formed through the second interlayer insulating layer ILD2 and the third gate insulating layer GI3. The first metal pattern ME1 may be formed in the same layer as each other (or directly on the same layer as each other). In an embodiment, for example, a first source electrode EP13, a second source electrode EP11, a first drain electrode EP14, and a second drain electrode EP12 may be formed in the same layer. A first via insulating layer VIA1 may be formed to cover the first metal pattern ME1.

[0194] refer to Figure 19 , Figure 20 , Figure 21 , Figure 22 and Figure 23 The second metal pattern ME2 is formed to cover the first and third gate electrodes GE31 on the first metal pattern ME1, and the gap (e.g., Figure 15 The gap SL) is along the third direction DR3 and the pixel opening (e.g., Figure 9 The POPs are formed in the second metal pattern ME2 at the overlapping position (steps S210, S220, S230 and S240). The second metal pattern ME2 can shield the NMOS transistor located under the second metal pattern ME2 from the influence of external light.

[0195] A second preliminary metal layer ME2' can be formed on the first via insulating layer VIA1 (step S210). A portion of the second preliminary metal layer ME2' can be removed using photoresist PR (e.g., patterned using dry etching) to form a gap. In embodiments, for example, as... Figure 21 and Figure 22As shown, the second preliminary metal layer ME2' at the location where the photoresist PR is set is removed, but this disclosure is not limited thereto. In an embodiment, for example, the second preliminary metal layer ME2' at the location where the photoresist PR is not set can be removed. Accordingly, a second metal pattern ME2 can be formed (steps S220, S230). A second via insulating layer VIA2 can be formed on the second metal pattern ME2 (step S240).

[0196] By forming gaps in the second metal pattern ME2, the degradation of viewing angle characteristics due to unevenness in the light-emitting portion can be effectively prevented without increasing the thickness of the insulating layer. In other words, a thinner display device with improved display quality and an electronic device including the display device can be provided.

[0197] refer to Figure 24 The light-emitting element ED, including the first electrode E1, can be formed on the first metal pattern ME1, and the first electrode E1 is exposed by a pixel opening defined by the pixel defining layer PDL (step S300).

[0198] In the cross-sectional view or as Figure 24 As shown, the first electrode E1 may include a first end EN1 and a second end EN2 spaced apart from the first end EN1 in a first direction DR1. In an embodiment, for example, the cross-section may be defined by the first direction DR1 and the third direction DR3. (See reference...) Figure 21 and Figure 22 When removing a portion of the second preliminary metal layer ME2', the portion of the second preliminary metal layer ME2' that overlaps with the ends of the first electrode E1 (e.g., the first end EN1 and the second end EN2) can be removed. Accordingly, the leveling error of the light-emitting portion caused by the second metal pattern ME2 can be reduced. In other words, color asymmetry can be minimized.

[0199] Additionally, the portion of the second preliminary metal layer ME2' that overlaps with the first metal pattern ME1 can be removed. Correspondingly, the flatness difference in the light-emitting portion caused by the first metal pattern ME1 can be reduced. In other words, color asymmetry can be further minimized.

[0200] The display device and electronic device including the display device according to the embodiments can be applied to computers (e.g., laptop computers), mobile phones, smartphones, smart tablets, portable media players (“PMPs”), personal digital assistants (“PDAs”), or MP3 players, etc.

[0201] This invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0202] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, comprising: substrate; Type I transistors include: A second active pattern is disposed on the substrate and doped with an N-type dopant. The third gate electrode overlaps with the second active pattern; and At least one of the plurality of first metal patterns is disposed on the third gate electrode and connected to the second active pattern through a contact hole; A light-emitting element, disposed on the plurality of first metal patterns and including a first electrode, wherein a pixel opening is defined by a pixel defining layer; and A second metal pattern is disposed between the plurality of first metal patterns and the first electrode and covers the third gate electrode in a plan view, wherein a gap is defined in the second metal pattern to overlap with the pixel opening in the plan view.

2. The display device according to claim 1, wherein, In the plan view, The pixel opening includes a first point, a second point furthest from the first point in a first direction, a third point, and a fourth point furthest from the third point in a second direction intersecting the first direction, wherein the third point is located in the direction in which the first point intersects the first and second directions. The minimum distance in the first direction between the first point of the pixel opening and the nearest boundary line in the gap to the first point, and the minimum distance in the first direction between the second point and the nearest boundary line in the gap to the second point, are equal to each other, and The minimum distance in the second direction between the third point of the pixel opening and the nearest boundary line in the gap to the third point is equal to the minimum distance in the second direction between the fourth point and the nearest boundary line in the gap to the fourth point.

3. The display device according to claim 1, wherein, In the plan view, the second metal pattern is provided as a plurality of slits at locations overlapping with the pixel openings.

4. The display device according to claim 1, wherein, In the cross-sectional view, The first electrode includes a first end and a second end spaced apart from the first end in a first direction, and The second metal pattern is spaced apart from both the first end and the second end in the first direction.

5. The display device according to claim 1, wherein, In the cross-sectional view, in the pixel opening, the second metal pattern and at least one of the plurality of first metal patterns are spaced apart from each other in a first direction.

6. The display device according to claim 1, further comprising: A second type of transistor, at least a portion of which is located between the substrate and the first type of transistor, and The second type of transistor includes a first active pattern doped with a P-type dopant.

7. The display device according to claim 6, wherein, The second active pattern includes an oxide semiconductor, and The first active pattern includes a silicon semiconductor.

8. The display device according to claim 1, wherein, The pixel aperture includes a first aperture for a pixel emitting a first color light, a second aperture for a pixel emitting a second color light different from the first color light, and a third aperture for a pixel emitting a third color light different from both the first color light and the second color light. The second color light is green light, and The gap is defined to at least partially overlap with the second opening in the plan view.

9. The display device according to claim 1, wherein, The light-emitting element further includes: An intermediate layer is disposed within the pixel opening defined by the pixel defining layer and on the first electrode; and The second electrode is disposed on the intermediate layer.

10. The display device according to claim 1, further comprising: An insulating layer is disposed between the second metal pattern and the first electrode, and The insulating layer comprises organic materials.

11. A method for manufacturing a display device, the method comprising: A first type of transistor is formed on a substrate, wherein the first type of transistor includes: a second active pattern disposed on the substrate and doped with an N-type dopant; a third gate electrode overlapping the second active pattern; and at least one of a plurality of first metal patterns disposed on the third gate electrode and connected to the second active pattern through a contact hole; A second metal pattern is formed on the plurality of first metal patterns to cover the third gate electrode in a planar view, wherein a gap is formed through the second metal pattern to overlap with a pixel opening in the planar view; and A light-emitting element is formed on the second metal pattern, wherein the light-emitting element includes a first electrode, and the pixel opening is defined by a pixel defining layer.

12. The manufacturing method according to claim 11, wherein, The formation of the second metal pattern includes: A second preliminary metal layer is formed on the first through-hole insulating layer covering the plurality of first metal patterns; and The gap is defined by removing a portion of the second preliminary metal layer using photoresist.

13. The manufacturing method according to claim 12, wherein, In the cross-sectional view, the first electrode includes a first end and a second end spaced apart from the first end in a first direction, and In the removal of the portion of the second preliminary metal layer, the second preliminary metal layer is removed at a location overlapping the first end and the second end of the first electrode.

14. The manufacturing method according to claim 12, wherein, In the removal of said portion of the second preliminary metal layer, the second preliminary metal layer is removed at locations where it overlaps with the plurality of first metal patterns.

15. An electronic device comprising: The processor outputs image data signals and inputs control signals; as well as The display device according to any one of claims 1 to 10 operates based on the image data signal and the input control signal.

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