A double-sided symmetric piezoelectric insulator substrate and a method of manufacturing the same

Abstract

This invention provides a double-sided symmetrical piezoelectric insulator substrate and its fabrication method, belonging to the technical fields of semiconductor materials and radio frequency microelectronic devices. It comprises a five-layer symmetrical structure, sequentially including a first piezoelectric functional layer, a first silicon dioxide layer, a support layer, a second silicon dioxide layer, and a second piezoelectric functional layer along the thickness direction. The first piezoelectric functional layer, the first silicon dioxide layer, the support layer, the second silicon dioxide layer, and the second piezoelectric functional layer are sequentially bonded together to form a symmetrical stacked structure. The second silicon dioxide layer is symmetrically arranged with the first silicon dioxide layer. This invention overcomes the limitation of existing single-sided POI substrates, which can only utilize a single surface to fabricate filters, enabling simultaneous integration of filter functions on both sides of a single substrate, thereby saving chip area, reducing packaging costs, and improving integration density.

Description

Technical Field

[0001] This invention relates to the fields of semiconductor materials and radio frequency microelectronic devices, and in particular to a double-sided symmetrical piezoelectric insulator substrate and its preparation method. Background Technology

[0002] Piezoelectric on Insulator (POI) substrates are the core substrate material for high-performance surface acoustic wave (IHP SAW) filters. A typical POI substrate adopts a three-layer structure of silicon / silicon dioxide / lithium tantalate (Si / SiO2 / LT). This structure utilizes the high-velocity silicon substrate to confine the acoustic wave energy to the surface of the piezoelectric layer, while the SiO2 layer provides temperature compensation, which can significantly improve the Q value and frequency temperature stability of the device. It has become the mainstream substrate solution for high-frequency SAW filters in fields such as 5G communication.

[0003] In existing technologies, research on POI substrates mainly focuses on single-sided structure optimization and fabrication process improvement. For example, some patents improve the transfer quality of piezoelectric layers by releasing thermal stress through openings in the bonding surface of the piezoelectric film layer; other patents use polycrystalline silicon layers and double-layer SiO2 homogeneous bonding to enhance bonding strength. In addition, some studies have deposited additional oxide layers and hypersonic layers on top of traditional POI substrates to form so-called "double-layer POI structures," but in essence, this still adds a functional layer above the electrodes of a single-sided substrate and does not change the single-sided utilization characteristics of the substrate.

[0004] However, existing POI substrates are all single-sided structures, meaning that the piezoelectric functional layer is fabricated only on one surface of the substrate. In RF front-end module design, to achieve multi-band or multi-channel filtering functions, multiple filter chips are usually placed side-by-side or stacked in a package. These solutions either occupy a large substrate area or have complex and costly packaging processes. As wireless communication devices increasingly demand miniaturization and high integration, how to integrate more filter functions within a limited chip area has become a pressing technical challenge in this field. Summary of the Invention

[0005] To address the aforementioned shortcomings in the prior art, this invention provides a double-sided symmetrical piezoelectric insulator substrate and its fabrication method, overcoming the limitation that existing single-sided POI substrates can only utilize a single surface to fabricate filters. This enables the simultaneous integration of filter functions on both sides of a single substrate, thereby saving chip area, reducing packaging costs, and improving integration.

[0006] To achieve the above objectives, the technical solution adopted by the present invention is as follows: a double-sided symmetrical piezoelectric insulator substrate, comprising a five-layer symmetrical structure, which includes, along the thickness direction, a first piezoelectric functional layer, a first silicon dioxide layer, a support layer, a second silicon dioxide layer, and a second piezoelectric functional layer; the first piezoelectric functional layer, the first silicon dioxide layer, the support layer, the second silicon dioxide layer, and the second piezoelectric functional layer are sequentially bonded together to form a symmetrical stacked structure; the second silicon dioxide layer is symmetrically disposed with respect to the first silicon dioxide layer; The first piezoelectric functional layer is used as a surface acoustic wave excitation layer on the front side of the substrate; Both the first silicon dioxide layer and the second silicon dioxide layer are used to provide temperature compensation. The support layer serves as both a mechanical support and an acoustic wave confinement layer. The second piezoelectric functional layer is used as a surface acoustic wave excitation layer on the back side of the substrate.

[0007] The beneficial effects of this invention are: achieving bifacial symmetrical acoustic wave excitation and functional decoupling: by symmetrically setting a first piezoelectric functional layer and a second piezoelectric functional layer on both sides of the support layer, surface acoustic waves can be independently excited and propagated on both sides of the substrate, providing a physical basis for integrating filters with different functions on both sides of the same substrate. The symmetrical structural design helps to balance the stress and acoustic wave energy distribution on both sides, avoiding warping or acoustic wave leakage caused by structural asymmetry.

[0008] Significantly improves the temperature stability of the filter: Introducing silicon dioxide layers (first silicon dioxide layer and second silicon dioxide layer) between the piezoelectric functional layer and the support layer, utilizing the positive temperature coefficient of sound velocity of silicon dioxide (opposite to the negative temperature coefficient of piezoelectric materials), can effectively compensate for the frequency drift of surface acoustic waves caused by changes in ambient temperature. Symmetrical placement of the silicon dioxide layers on both sides ensures consistent temperature compensation on both sides, thereby significantly reducing the temperature drift coefficient of the double-sided device and improving the frequency stability of the device over a wide temperature range.

[0009] Enhancing acoustic wave energy confinement and reducing loss: The support layer acts as both a mechanical support and an acoustic wave confinement layer. By selecting materials and thicknesses with appropriate acoustic impedance, and combining them with symmetrical silicon dioxide and piezoelectric functional layers, surface acoustic wave energy can be effectively confined near the substrate surface, reducing the radiation leakage of acoustic wave energy into the substrate interior. The symmetrical structure further suppresses the excitation of asymmetric clutter modes, thereby reducing the filter's insertion loss and improving the quality factor (Q value).

[0010] It provides excellent mechanical support and process compatibility: The intermediate support layer has sufficient thickness and mechanical strength to provide stable mechanical support for the entire double-sided substrate, facilitating the maintenance of substrate flatness and fragmentation resistance in subsequent wafer-level double-sided processing, photolithography, packaging, and other processes. Simultaneously, the layers are bonded together, avoiding lattice mismatches and defects that may occur during epitaxial growth, ensuring the high quality of each material layer (especially the piezoelectric single crystal layer), and exhibiting high compatibility with existing semiconductor bonding and thinning processes.

[0011] Achieving compact 3D integration and high-performance RF front-end modules: This substrate allows the functionality that previously required two separate filter chips to be integrated into a single double-sided chip, significantly reducing the projected area of ​​the RF front-end module. Symmetrical temperature compensation and acoustic wave confinement design ensure that the double-sided integrated filter maintains or even surpasses the key performance indicators of traditional single-sided devices (such as low insertion loss, high rejection, and high temperature stability), providing a core material solution for high-density, multi-band, and high-performance RF front-ends in 5G / 6G communications.

[0012] Furthermore, the second silicon dioxide layer has the same thickness as the first silicon dioxide layer.

[0013] The beneficial effects of the above-mentioned further solution are: achieving strictly symmetrical temperature compensation on both sides: since the first silicon dioxide layer and the second silicon dioxide layer have the same thickness, they provide completely consistent temperature compensation effects on both sides. This ensures that when the ambient temperature changes, the frequency drift generated by the first piezoelectric functional layer and the second piezoelectric functional layer is basically the same, thereby ensuring that the center frequency stability of the bifacial integrated filter remains consistent during operation, avoiding channel mismatch or signal distortion caused by inconsistent temperature drift on both sides.

[0014] Eliminating substrate warpage caused by thermal stress: There may be a certain difference in the coefficient of thermal expansion between the silicon dioxide layer and the piezoelectric functional layer and support layer. When the thickness of the silicon dioxide layer on both sides is equal, the thermal stress generated on both sides during the manufacturing process (such as high-temperature bonding) or when the operating environment temperature changes, is symmetrically distributed and cancels each other out, thereby significantly reducing the macroscopic warpage or bending of the substrate. A flat substrate is beneficial to improving the process accuracy and yield of subsequent double-sided photolithography, thin film deposition, and wafer-level packaging.

[0015] Ensuring the symmetry and purity of acoustic modes: Equal-thickness silica layers help maintain the acoustic symmetry of the entire five-layer structure. This symmetry suppresses the excitation of asymmetric clutter modes (such as flexural waves and antisymmetric Lamb waves), ensuring high consistency between the surface acoustic wave modes excited on both sides, reducing parasitic responses, and improving the filter's out-of-band rejection capability and signal-to-noise ratio.

[0016] Simplified process design and control: During the fabrication process, the same deposition, polishing, or bonding process parameters and control targets can be used for both the first and second silicon dioxide layers, reducing the complexity of process development and monitoring costs. Furthermore, equal thickness facilitates in-situ comparison and verification using optical or mechanical measurement methods, improving the convenience and reliability of quality control.

[0017] Enhancing the predictability and reusability of device design: Since the silicon dioxide layers on both sides are of the same thickness, engineers can reuse the same set of temperature compensation models and acoustic wave propagation simulation parameters when designing filters on both sides, reducing the additional simulation and debugging workload caused by the differences in the two-sided structure and accelerating the product development cycle.

[0018] This invention also provides a method for preparing a double-sided symmetrical piezoelectric insulator substrate, comprising the following steps: S1. Provide a first piezoelectric material layer and form a first silicon dioxide layer on its surface; S2. Provide a second piezoelectric material layer, and form a second silicon dioxide layer on its surface; S3. Provide a support layer and bond the surface of the first silicon dioxide layer to the first surface of the support layer; S4. Bond the surface of the second silicon dioxide layer to the second surface of the support layer; S5. Thinning the first piezoelectric material layer and the second piezoelectric material layer to form a first piezoelectric functional layer and a second piezoelectric functional layer of predetermined thickness, thus completing the preparation of the double-sided symmetrical piezoelectric insulator substrate.

[0019] The beneficial effects of this invention are: achieving symmetrical integration of high-quality heterogeneous materials: by separately preparing "piezoelectric material layer + silicon dioxide layer" units and then sequentially bonding them to both sides of the support layer, the process conflicts and material quality problems that may arise from simultaneously depositing or growing piezoelectric materials on both sides of the support layer are avoided. This method allows the first and second piezoelectric material layers to be made of the same or different high-quality piezoelectric single crystals (such as lithium tantalate or lithium niobate), ensuring that both sides have excellent surface acoustic wave excitation performance.

[0020] Precise control of each layer thickness ensures symmetry and consistency: By independently thinning the first and second piezoelectric material layers, the final thicknesses of the first and second piezoelectric functional layers can be precisely controlled to target values ​​(e.g., several wavelength depths), and the thicknesses on both sides can be made equal or different as needed. Simultaneously, the silicon dioxide layer thickness is independently formed and controllable before bonding, which facilitates achieving equal silicon dioxide layer thicknesses on both sides, thereby ensuring the overall structural symmetry and acoustic performance consistency of the substrate.

[0021] Reduced process complexity and improved bonding quality: The complex five-layer structure is broken down into two independent bonding steps (bonding the first surface first, then the second surface). Each time, only the alignment and bonding of three layers need to be handled, reducing the difficulty of aligning multiple heterogeneous materials at once. The support layer, acting as an intermediate mechanical support, provides a stable substrate after the first bonding, facilitating operation and uniform pressure application during the second bonding, thereby improving the bonding strength and void-free rate at the bonding interface.

[0022] Excellent process compatibility and scalability: The bonding, thinning, and polishing processes employed in this method are all mature technologies in the semiconductor and MEMS fields (such as plasma-activated bonding, chemical mechanical polishing, and smart lift-off), which are easy to implement on existing production lines. Furthermore, the support layer material (such as silicon, glass, sapphire, or quartz) and thickness can be flexibly adjusted according to different application requirements, adapting to filter designs with different frequencies and mechanical strength requirements.

[0023] Reduce material waste and lower costs: By thinning the piezoelectric material layer, the high-quality piezoelectric material stripped off can be recycled (for example, the excess piezoelectric layer can be transferred to other carriers for reuse through smart stripping technology), which greatly reduces the consumption of expensive piezoelectric single crystal substrates and helps to reduce the manufacturing cost of double-sided integrated surface acoustic wave filters.

[0024] Ensuring substrate flatness facilitates subsequent double-sided processing: The substrate after double-sided thinning and polishing has high flatness and low warpage, providing an ideal base plane for subsequent double-sided processes such as high-precision photolithography, metal deposition and etching on the first and second piezoelectric functional layers, which helps to improve the yield and performance consistency of the final double-sided integrated filter.

[0025] Furthermore, hydrogen ion implantation is performed on the first piezoelectric material layer and the second piezoelectric material layer before bonding to form a peeling interface.

[0026] The beneficial effects of the above-mentioned further solutions are: controllable thinning and transfer of high-quality piezoelectric functional layers: heat treatment following hydrogen ion implantation and bonding (such as smart exfoliation technology) can precisely exfoliate uniformly thick piezoelectric single-crystal films at a predetermined depth. This enables the first and second piezoelectric functional layers to obtain high-quality single-crystal thin layers with intact lattices and extremely low defect density. Their piezoelectric properties and electromechanical coupling coefficient are close to those of bulk materials, far superior to polycrystalline or amorphous piezoelectric films prepared by deposition or thinning and polishing methods.

[0027] Significantly reducing the consumption cost of expensive piezoelectric substrates: Traditional grinding and thinning processes remove and consume most of the piezoelectric material, resulting in a huge waste of expensive piezoelectric single crystal substrates (especially large-size lithium tantalate and lithium niobate wafers). Using hydrogen ion implantation and stripping, the implantation depth is typically only a few micrometers to tens of micrometers. The remaining piezoelectric material substrate after stripping can be reused for the next implantation and bonding after surface regeneration treatment, allowing for multiple recycling and significantly reducing the material cost per device.

[0028] Achieving ultrathin, uniform, and precisely controllable piezoelectric functional layers: By precisely controlling the energy and dosage of hydrogen ion implantation, the target depth of the peeling interface within the piezoelectric material layer can be set, thereby obtaining piezoelectric functional layers with thicknesses down to the submicron level. Combined with low-temperature annealing peeling technology after bonding, thermal damage to the silicon dioxide layer or support layer caused by high-temperature processes can be avoided, making it particularly suitable for heterogeneous material bonding systems with significant differences in thermal expansion coefficients.

[0029] Reduced burden on subsequent thinning processes and improved process efficiency: Since the stripping process has essentially removed most of the excess piezoelectric material, only light chemical mechanical polishing (CMP) is required to improve surface roughness and thickness uniformity, eliminating the need for time-consuming and damage-inducing long-term grinding. This significantly shortens the processing cycle and reduces the risk of edge chipping, scratches, or subsurface damage caused by mechanical thinning.

[0030] Maintaining the symmetry and independence of the two-sided piezoelectric functional layers: The injection energy and dosage of the first and second piezoelectric material layers can be controlled independently, thereby obtaining piezoelectric functional layers of the same or different thicknesses on both sides. If a completely symmetrical filter design is required on both sides, the same injection parameters can be used to ensure that the thickness of the piezoelectric layers on both sides is strictly equal, maintaining the overall acoustic and mechanical symmetry of the substrate.

[0031] Compatible with wafer-level mass production and increased capacity: The hydrogen ion implantation process can process an entire wafer in one go on a standard ion implanter, and the stripping process can also be completed in batches at the wafer level, making it highly compatible with existing semiconductor foundry processes. This enables low-cost, high-efficiency mass production of biaxially symmetrical piezoelectric insulator substrates, meeting the demand for high-performance piezoelectric substrates in RF front-end modules.

[0032] The present invention has at least the following significant beneficial effects: First, it enables double-sided utilization of the substrate. By symmetrically setting piezoelectric functional layers on both sides of the support layer, a single substrate has two active surfaces that can be used to fabricate devices independently, breaking through the limitation of traditional POI substrates that can only be used on one side.

[0033] Second, chip area utilization is doubled. With the same substrate area, the number of filters that can be integrated doubles, significantly improving chip area efficiency and reducing the substrate cost for single-function filters.

[0034] Third, thermal stress self-balancing. Due to the use of a top-to-bottom symmetrical LT / SiO2 / Si / SiO2 / LT structure, the thermal stress inside the substrate is symmetrically distributed, resulting in small warping deformation when the temperature changes, which is beneficial to improving the accuracy and yield of subsequent photolithography and bonding processes.

[0035] Fourth, it has excellent process compatibility. The substrate of this invention can be prepared using existing mature processes and equipment for POI substrates, without the need to develop additional dedicated equipment, and has good prospects for industrial implementation.

[0036] Fifth, it offers high design flexibility. Filters with different frequency bands and bandwidths can be designed on both sides to meet the needs of multi-frequency, multi-mode RF front-ends; devices on both sides can be vertically interconnected through technologies such as through-silicon vias, further expanding the design space. Attached Figure Description

[0037] Figure 1 This is a flowchart of the preparation method of the present invention.

[0038] Figure 2 This is a schematic diagram of the structure of the double-sided symmetrical piezoelectric insulator substrate provided in Embodiment 3 of the present invention.

[0039] Figure 3 This is a process flow diagram for Embodiment 3 of the present invention.

[0040] Figure 4 This is a process route diagram for Embodiment 4 of the present invention.

[0041] Among them, 1-first piezoelectric functional layer, 2-first silicon dioxide layer, 3-support layer, 4-second silicon dioxide layer, 5-second piezoelectric functional layer. Detailed Implementation

[0042] The specific embodiments of the present invention are described below to enable those skilled in the art to understand the present invention. However, it should be understood that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the present invention as defined and determined by the appended claims. All inventions utilizing the concept of the present invention are protected.

[0043] Example 1 This invention provides a double-sided symmetrical piezoelectric insulator substrate, comprising a five-layer symmetrical structure, sequentially including a first piezoelectric functional layer 1, a first silicon dioxide layer 2, a support layer 3, a second silicon dioxide layer 4, and a second piezoelectric functional layer 5 along the thickness direction; the first piezoelectric functional layer 1, the first silicon dioxide layer 2, the support layer 3, the second silicon dioxide layer 4, and the second piezoelectric functional layer 5 are sequentially bonded together to form a symmetrical stacked structure; the second silicon dioxide layer 4 is symmetrically disposed with respect to the first silicon dioxide layer 2; the first piezoelectric functional layer 1 serves as a surface acoustic wave (SAW) excitation layer on the front side of the substrate; both the first silicon dioxide layer 2 and the second silicon dioxide layer 4 provide temperature compensation; the support layer 3 serves as a mechanical support and acoustic wave confinement layer; and the second piezoelectric functional layer 5 serves as a SAW excitation layer on the back side of the substrate. The second silicon dioxide layer 4 has the same thickness as the first silicon dioxide layer 2.

[0044] In this embodiment, the double-sided symmetrical piezoelectric insulator substrate has a symmetrical five-layer structure, which includes, sequentially along the thickness direction: The first piezoelectric functional layer 1, made of piezoelectric single crystal material, serves as the surface acoustic wave excitation layer on the front side of the substrate. The first silicon dioxide layer 2 covers the first piezoelectric functional layer 1 and provides temperature compensation. The support layer 3, made of high-velocity acoustic material, is located in the middle of the substrate and serves as a mechanical support and acoustic wave confinement layer. The second silicon dioxide layer 4 covers the support layer 3 and is symmetrically arranged with the first silicon dioxide layer 2. The second piezoelectric functional layer 5, made of piezoelectric single crystal material, serves as the surface acoustic wave excitation layer on the back side of the substrate. The first piezoelectric functional layer 1, the first silicon dioxide layer 2, the support layer 3, the second silicon dioxide layer 4, and the second piezoelectric functional layer 5 are sequentially bonded together to form a symmetrical stacked structure.

[0045] Preferably, the support layer 3 is made of high-resistivity silicon material with a resistivity ≥3000 Ω·cm to ensure good RF characteristics and low loss. The piezoelectric functional layer material is lithium tantalate (LiTaO3) or lithium niobate (LiNbO3), and the appropriate tangent can be selected according to the specific application. The first silicon dioxide layer 2 and the second silicon dioxide layer 4 have equal thickness to ensure that the internal thermal stress of the substrate is symmetrically distributed, resulting in small warping deformation when the temperature changes, which is beneficial to improving the accuracy of subsequent photolithography and bonding processes.

[0046] Example 2 like Figure 1 As shown, the present invention also provides a method for preparing a double-sided symmetrical piezoelectric insulator substrate, comprising the following steps: S1. Provide a first piezoelectric material layer and form a first silicon dioxide layer 2 on its surface; S2. Provide a second piezoelectric material layer, and form a second silicon dioxide layer 4 on its surface; S3. Provide a support layer and bond the surface of the first silicon dioxide layer 2 to the first surface of the support layer; S4. Bond the surface of the second silicon dioxide layer 4 to the second surface of the support layer 3; S5. Thinning treatment is performed on the first piezoelectric material layer and the second piezoelectric material layer to form a first piezoelectric functional layer 1 and a second piezoelectric functional layer 5 of predetermined thickness, thus completing the preparation of the double-sided symmetrical piezoelectric insulator substrate.

[0047] In this embodiment, the thinning process can be performed using ion implantation lift-off (Smart Cut) or a combination of mechanical grinding and chemical mechanical polishing. When using ion implantation lift-off, hydrogen ions can be implanted into the first and second piezoelectric material layers respectively before bonding to form a lift-off interface. After bonding, heat treatment is used to achieve the transfer and thinning of the piezoelectric layer.

[0048] Example 3 like Figure 3 As shown, this embodiment provides a double-sided symmetrical piezoelectric insulator substrate with an LT / SiO2 / Si / SiO2 / LT structure. The specific fabrication steps are as follows: (1) Provide the first piezoelectric material layer: a lithium tantalate single crystal wafer with a thickness of 500 μm with a 42° YX tangent is used, and the surface is cleaned and polished.

[0049] (2) Forming the first silicon dioxide layer: A SiO2 thin film with a thickness of 0.6 μm is deposited on the surface of the first piezoelectric material layer using plasma enhanced chemical vapor deposition (PECVD) process.

[0050] (3) Provide a second piezoelectric material layer: Use the same 42°YX tangential lithium tantalate single crystal wafer as the first piezoelectric material layer, and deposit a SiO2 thin film with a thickness of 0.6μm on its surface.

[0051] (4) Provide support layer 3: Use a high resistivity silicon wafer with a resistivity of 4000Ω·cm and a thickness of 500μm, and clean and activate the front and back sides.

[0052] (5) First bonding: The SiO2 surface on the first piezoelectric material layer is hydrophilically bonded to the first surface of the silicon support layer, and the bonding strength is enhanced by annealing after bonding.

[0053] (6) First thinning: The first piezoelectric material layer is thinned to 0.5 μm by a combination of mechanical grinding and chemical mechanical polishing to form the first piezoelectric functional layer 1.

[0054] (7) Second bonding: Bond the SiO2 surface on the second piezoelectric material layer to the second surface of the silicon support layer.

[0055] (8) Second thinning: The second piezoelectric material layer is thinned to 0.5 μm using the same process to form the second piezoelectric functional layer 5.

[0056] Finally, a bi-faceted symmetrical POI substrate with LT(0.5μm) / SiO2(0.6μm) / Si(500μm) / SiO2(0.6μm) / LT(0.5μm) was obtained.

[0057] Example 4 The difference between this embodiment and Embodiment 3 is that an ion implantation lift-off process is used to thin the piezoelectric layer. The specific steps are as follows: (1) Provide a first piezoelectric material layer and a second piezoelectric material layer: both are lithium niobate single crystal wafers with a 128° YX tangent.

[0058] (2) Ion implantation: Hydrogen ion implantation is performed on the two piezoelectric material layers respectively. The implantation energy and dose are set according to the target peel thickness. In this embodiment, the target thickness is 0.8 μm.

[0059] (3) Formation of silicon dioxide layer: 0.2 μm SiO2 thin film is deposited on the surface of the two piezoelectric material layers after ion implantation.

[0060] (4) Provide support layer 3: a high-resistivity silicon wafer with a thickness of 500μm.

[0061] (5) First bonding and peeling: The SiO2 surface of the first piezoelectric material layer is bonded to the first surface of the silicon support layer, and then heat treatment is performed to peel the first piezoelectric material layer along the injection interface, leaving a 0.8 μm piezoelectric layer.

[0062] (6) Second bonding and peeling: Using the same process, the second piezoelectric material layer is bonded to the second surface of the silicon support layer and then peeled off.

[0063] (7) Surface smoothing: The surfaces of the two piezoelectric layers after peeling are lightly chemically and mechanically polished to reduce surface roughness.

[0064] The performance of the double-sided symmetrical POI substrates prepared in Examples 3 and 4 was tested, and the results are shown in Table 1. Table 1 is the performance test result table.

[0065] Table 1

[0066] Test results show that the double-sided symmetrical POI substrate of this invention, due to its symmetrical structure, exhibits good thermal stress balance and superior warpage compared to traditional single-sided structures. The piezoelectric layers on both sides are of uniform quality, and the bonding interface quality is high, meeting the requirements for fabricating high-performance surface acoustic wave devices.

[0067] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A double-sided symmetrical piezoelectric insulator substrate, characterized in that, It includes a five-layer symmetrical structure, which includes, along the thickness direction, a first piezoelectric functional layer (1), a first silicon dioxide layer (2), a support layer (3), a second silicon dioxide layer (4), and a second piezoelectric functional layer (5); the first piezoelectric functional layer (1), the first silicon dioxide layer (2), the support layer (3), the second silicon dioxide layer (4), and the second piezoelectric functional layer (5) are bonded together in sequence to form a symmetrical stacked structure; the second silicon dioxide layer (4) is symmetrically arranged with the first silicon dioxide layer (2); The first piezoelectric functional layer (1) is used as a surface acoustic wave excitation layer on the front side of the substrate; The first silicon dioxide layer (2) and the second silicon dioxide layer (4) are both used to provide temperature compensation function; The support layer (3) is used as a mechanical support and an acoustic wave confinement layer; The second piezoelectric functional layer (5) is used as a surface acoustic wave excitation layer on the back side of the substrate.

2. The double-sided symmetrical piezoelectric insulator substrate according to claim 1, characterized in that, The second silicon dioxide layer (4) has the same thickness as the first silicon dioxide layer (2).

3. A method for preparing a double-sided symmetrical piezoelectric insulator substrate, characterized in that, Includes the following steps: S1. Provide a first piezoelectric material layer and form a first silicon dioxide layer on its surface (2). S2. Provide a second piezoelectric material layer and form a second silicon dioxide layer on its surface (4). S3. Provide a support layer (3) and bond the surface of the first silicon dioxide layer (2) to the first surface of the support layer (3); S4. Bond the surface of the second silicon dioxide layer (4) to the second surface of the support layer (3); S5. Thinning treatment is performed on the first piezoelectric material layer and the second piezoelectric material layer to form a first piezoelectric functional layer (1) and a second piezoelectric functional layer (5) of predetermined thickness, thus completing the preparation of the double-sided symmetrical piezoelectric insulator substrate.

4. The method for preparing a double-sided symmetrical piezoelectric insulator substrate according to claim 3, characterized in that, Before bonding, hydrogen ion implantation is performed on the first piezoelectric material layer and the second piezoelectric material layer to form a peeling interface.

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