An etching method and application for reducing wafer warpage

Abstract

This application belongs to the field of semiconductor manufacturing technology and discloses an etching method and application for reducing wafer warpage. The method includes the following steps: defining a stress relief pattern on the wafer dicing track, wherein the stress relief pattern is entirely located within the dicing track; and performing multiple etching operations on the dicing track according to the stress relief pattern, with the multiple etching operations occurring at intervals during the wafer manufacturing process. This application achieves precise stress dispersion throughout the entire wafer manufacturing process by adapting the stress relief pattern to the wafer dicing track and performing multiple etching operations at process intervals, significantly improving the wafer warpage problem and meeting the stringent requirements for wafer flatness in high-precision chip manufacturing.

Description

Technical Field

[0001] This application belongs to the field of semiconductor manufacturing technology, and specifically relates to an etching method and application for reducing wafer warpage. Background Technology

[0002] In semiconductor manufacturing, wafer processing involves multiple core processes such as etching, oxidation, and high temperatures. During this process, the wafer repeatedly undergoes material modification, local phase transitions, and thermal cycling, leading to the continuous accumulation of internal stress. This causes macroscopic warping deformation of the wafer, which can even result in microcracks and product failure in severe cases. Wafer warping has a series of adverse effects on subsequent processes, directly causing problems such as misalignment in lithography, uneven thin film growth, device performance drift, and decreased bonding yield. It seriously affects the precision, consistency, and yield of chip manufacturing, and in extreme cases, it can even cause equipment vacuum failure, making subsequent processes impossible. In particular, various high-precision lithography equipment has extremely stringent requirements for the overall warping and local flatness of the wafer. The warping degree of the wafer must be controlled within the limited depth of focus of the equipment and the dynamic compensation capability of the leveling system. Otherwise, it will directly cause problems such as out-of-focus exposure patterns, loss of control of critical dimensions, and misalignment. Therefore, in the wafer manufacturing process, effectively adjusting the accumulated stress and reducing the degree of wafer warping is a key link in improving the quality of chip manufacturing.

[0003] Currently, the industry mainly uses two methods to adjust wafer stress to improve warpage. One method is to fabricate a reactive stress film on the back of the wafer to balance the overall stress of the wafer. This method is mainly used for stress improvement of the wafer before the process, but it has many technical defects. When the back coating process is carried out, the front of the wafer is difficult to protect effectively, which makes it impossible to improve stress during the wafer fabrication process. As a result, the wafer will continue to accumulate stress in subsequent processes such as coating and electrode metallization, and the warpage will continue to increase. This makes it difficult to meet the process requirements of high-precision lithography equipment. At the same time, the integrity of the back film layer will directly affect the stability of the overall process. If the film layer is damaged during the process, it will directly lead to the interruption of the process. Moreover, for wafers with high warpage, it is often necessary to prepare thin films with extremely high performance requirements. The actual preparation of such thin films is difficult and it is difficult to achieve large-scale application. Another approach is to cut trench arrays on the wafer. This method can be used to improve wafer stress before and during the manufacturing process. However, the cutting operation will cause hard and thermal damage to the wafer itself. Hard damage is easily manifested as edge microcracks and edge chipping, while thermal damage will result in problems such as sidewall recasting layers and material deformation. These damages will extend to the adjacent chip pattern area, which will not only interfere with the electrical performance of the device, but also damage the precision structure of the chip, directly affecting the yield and reliability of the final product. At the same time, this solution cannot be adapted to wafers with different design combinations, has high process complexity, and will increase production costs, resulting in poor universality. Moreover, the control of wafer stress by this method is irreversible. If the design or process parameters are not appropriate, overcompensation is very likely to occur, leading to reverse warping of the wafer or the generation of new stress unevenness problems. More importantly, the stress improvement effect of this solution is not repeatable, and it is difficult to effectively disperse the stress of the wafer that has accumulated stress during the manufacturing process through multiple processes. Summary of the Invention

[0004] This application aims to improve at least one technical problem in the background art.

[0005] This application provides an etching method for reducing wafer warpage. The wafer has dicing channels formed on it. The etching method for reducing wafer warpage includes the following steps: Define a stress relief pattern on the cutting track, with the entire stress relief pattern located within the cutting track; The wafer is etched multiple times along the dicing path according to the stress relief pattern, with these multiple etching operations occurring at intervals during the wafer fabrication process.

[0006] In some specific implementations, the stress relief pattern is set in the central region of the cutting track, and the difference between each critical dimension of the stress relief pattern and the corresponding critical dimension of the cutting track is 1μm-10μm.

[0007] In some specific implementations, grooves are formed through multiple etching processes, with a depth-to-width ratio of 0.075-0.5.

[0008] In some specific implementations, etching includes the following steps: The wafer is coated with resist, exposed, and developed, then subjected to ICP dry etching, resist removal, cleaning, and drying to complete the etching process.

[0009] In some specific implementations, ICP dry etching is performed using a mixed gas, which includes Cl2, BCl3 and Ar in a volume ratio of 4:1:1.

[0010] In some specific implementations, the power of ICP dry etching is 400W-600W, and the pressure is 0.2Pa-2Pa.

[0011] In some specific implementations, the mixed gas also includes a first gas, which is N2 or O2, and the volume percentage of the first gas in the mixed gas is 10%-13%.

[0012] In some specific implementations, adhesive removal is performed using organic solvents or plasma.

[0013] In some specific implementation scenarios, the cleaning process involves first using an alkaline solution, followed by rinsing with water.

[0014] In some specific implementations, the etching process is carried out no more than three times.

[0015] This application also provides the application of the above-described etching method for reducing wafer warpage in semiconductor manufacturing.

[0016] The beneficial effects of this application are as follows: The etching method for reducing wafer warpage provided in this application effectively solves the technical deficiencies of existing wafer stress adjustment schemes in terms of process adaptability, process repeatability, wafer protection, and universality. By adapting the design of stress release patterns on the wafer dicing track and performing multiple etching operations at process intervals, it achieves precise stress dispersion throughout the entire wafer manufacturing process, significantly improving the wafer warpage problem and meeting the stringent requirements for wafer flatness in high-precision chip manufacturing. This method offers high process flexibility, allowing etching operations to be performed as needed at each node before, during, and after the wafer manufacturing process. Furthermore, the process improvement effect exhibits good repeatability, gradually releasing stress based on the accumulated stress on the wafer, ensuring the precision and consistency of chip manufacturing. Simultaneously, this method performs etching operations only in the dicing track area, avoiding hard and thermal damage to the wafer at the process level, effectively protecting the wafer device structure and product pattern area, and improving chip manufacturing yield and product reliability. Furthermore, this method features a simple process design, requires no additional complex equipment, is compatible with different wafer materials and manufacturing equipment, allows for flexible selection of etching methods, significantly reduces the difficulty of process implementation and production costs, and is both practical and universal. It can be integrated into various semiconductor chip manufacturing process systems, providing reliable process support for high-precision and large-scale chip manufacturing. Detailed Implementation

[0017] The present application is further described below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the application. Furthermore, it should be understood that after reading the contents of this application, those skilled in the art can make various alterations or modifications to this application, and these equivalent forms also fall within the scope defined by the appended claims.

[0018] This application provides an etching method for reducing wafer warpage. The wafer has dicing channels formed on it. The etching method for reducing wafer warpage includes the following steps: Define a stress relief pattern on the cutting track, with the entire stress relief pattern located within the cutting track; The wafer is etched multiple times along the dicing path according to the stress relief pattern, with these multiple etching operations occurring at intervals during the wafer fabrication process.

[0019] The etching method for reducing wafer warpage provided in this application addresses the technical problem of wafer warpage caused by the continuous accumulation of stress during the manufacturing process. First, a stress relief pattern (which can be rectangular or other long strips) is defined (designed) on the wafer's dicing track. The stress relief pattern is entirely located within the dicing track. This design allows the stress relief pattern to adapt to the layout of the dicing track, preventing the pattern from extending into the product pattern area and interfering with the device structure on the wafer. Subsequently, when performing etching operations on the dicing track according to this stress relief pattern, multiple etching operations are used, with these operations spaced apart during the wafer's manufacturing process. This allows for timely stress relief of the wafer after it experiences stress from different process steps, effectively dispersing the stress that gradually accumulates during the manufacturing process. This solves the technical problems of existing technologies where back-side reactive film fabrication cannot improve wafer stress during the manufacturing process, and where trench array cutting is difficult to disperse accumulated stress through multiple processes. By performing multiple etching operations at intervals between process nodes (the etching is not performed continuously and occurs between different wafer process nodes, which generally include metal electrode / thin film deposition, wafer front-side electroplating, electrode alloying, etc.), stress can be gradually released according to the stress accumulation of the wafer, improving the effectiveness of wafer stress release and thus effectively reducing wafer warpage. At the same time, this etching method only operates in the dicing area and will not cause hard or thermal damage to the wafer, ensuring the integrity of the device structure on the wafer. It also eliminates the need to combine multiple processes to achieve stress improvement at different process nodes, greatly improving process flexibility, simplifying the process flow, and controlling process costs.

[0020] In some specific implementations, the stress relief pattern is positioned in the center region of the dicing trace. The difference between each critical dimension (CD) of the stress relief pattern and the corresponding critical dimension of the dicing trace is 1μm-10μm. Appropriate width margins are reserved on both sides of the stress relief pattern. This ensures that the pattern does not become too close to the chip's functional area due to insufficient margin, effectively avoiding the risk of accidental damage during etching. Conversely, excessive margins do not overly compress the effective width of the stress relief pattern, ensuring sufficient stress relief space to achieve the desired wafer warpage reduction. Furthermore, this unilateral dimension difference design keeps the relative position of the stress relief pattern and the dicing trace regular, resulting in uniform distribution of the etched trenches within the dicing trace and improving the overall uniformity of stress relief on the wafer.

[0021] In some specific implementations, trenches are formed through multiple etching processes, with an aspect ratio of 0.075-0.5. After multiple etching processes according to the stress relief pattern, corresponding trenches are formed on the wafer dicing track. Controlling the aspect ratio of these trenches within the range of 0.075-0.5 is a reasonable design that balances stress relief effect with the structural stability within the dicing track. If the aspect ratio of the trenches is lower than this range, the depth of the etched trenches is insufficient, failing to create enough stress relief space and effectively dispersing the stress accumulated on the wafer during the process, thus failing to achieve the desired effect of reducing wafer warpage. If the aspect ratio of the trenches is higher than this range, it will significantly weaken the structural strength of the dicing track itself, making it prone to structural problems such as trench sidewall collapse in subsequent wafer fabrication processes. It may also indirectly affect the structural stability of the surrounding area of ​​the dicing track, increasing the risk of wafer fabrication. This aspect ratio range allows the trenches to achieve effective stress relief while maintaining the structural integrity of the dicing track, adapting to various process operations in wafer fabrication, and ensuring the stability of the wafer structure after multiple etching processes.

[0022] In some specific implementations, etching includes the following steps: The wafer is coated with resist, exposed, and developed, then subjected to ICP dry etching, resist removal, cleaning, and drying to complete the etching process.

[0023] The etching process begins with coating, exposure, and development of the wafer. This series of operations precisely defines the etching area on the wafer surface that matches the stress relief pattern, ensuring the accuracy of subsequent etching operations and ensuring that the pattern formed on the dicing path matches the designed stress relief pattern. Subsequently, ICP dry etching is used to carry out the etching operation. This etching method can achieve low-damage etching and avoid hard or thermal damage to the wafer. After etching, the photoresist is removed, cleaned, and dried in sequence. This effectively removes residual photoresist and impurities generated during the etching process from the wafer surface, ensuring the cleanliness of the wafer surface after etching and preventing various residual substances from adversely affecting subsequent wafer manufacturing processes. At the same time, the entire operation process is compatible with conventional wafer manufacturing processes, without the need for additional special equipment, which greatly improves the operability and adaptability of the process.

[0024] In some specific implementations, ICP dry etching uses a mixed gas, comprising Cl2, BCl3, and Ar in a volume ratio of 4:1:1. This specific gas composition is tailored to the etching requirements of the wafer dicing area. Cl2 and BCl3 serve as the core etching gases, enabling effective etching of the wafer material and ensuring etching rate and effect. Ar, as an auxiliary gas, effectively enhances plasma density, allowing the etching plasma to be evenly distributed in the etching area and improving etching uniformity. This specific volume ratio of mixed gas allows the etching process to be both efficient and uniform, accurately forming the designed stress relief pattern on the dicing track without over-etching the wafer, effectively protecting the wafer structure around the dicing track.

[0025] In some specific implementations, the power of ICP dry etching is 400W-600W, and the pressure is 0.2Pa-2Pa. This specific power and pressure range is a reasonable choice that balances etching effect, etching efficiency, and wafer protection. Power control within this range ensures the plasma has appropriate energy, achieving effective etching of the wafer, guaranteeing etching depth and precision, without excessive heat generation leading to thermal damage, or insufficient etching efficiency and depth due to insufficient power, thus failing to create effective stress release space. Pressure control within this range ensures a stable plasma distribution within the etching chamber, further guaranteeing etching uniformity, maintaining consistent trench size on the dicing path, and improving the overall uniformity of wafer stress release. This power and pressure combination makes the ICP dry etching process stable and controllable, fully adaptable to the process requirements of multiple etching steps in this method.

[0026] In some specific implementations, the mixed gas also includes a first gas, which is N2 or O2, and the volume percentage of the first gas in the mixed gas is 10%-13%. Adding this specific volume percentage of N2 or O2 to the etching mixed gas can form a passivation layer on the sidewalls of the etched trenches. This passivation layer can effectively suppress lateral etching during the etching process, keeping the trench sidewalls steep and ensuring the forming accuracy of the stress relief pattern. At the same time, the limitation of this volume percentage is particularly reasonable. If the volume percentage of N2 or O2 is too low, it will not be able to form an effective passivation layer on the trench sidewalls, making it difficult to suppress lateral etching. If the percentage is too high, it will dilute the concentration of the core etching gas, reduce the etching rate and etching effect, and may even form excess reaction products on the wafer surface, affecting subsequent processes. This volume percentage range can balance the forming effect of the passivation layer and the efficiency of the etching process, so that the etched trenches meet the design requirements of stress relief and ensure structural regularity.

[0027] In some specific implementations, resist removal is performed using organic solvents (such as N-methylpyrrolidone or acetone) or plasma. Both methods efficiently remove the photoresist coated on the wafer surface and are suitable for the etching process requirements of the dicing area in this etching method. They do not damage the trench structure formed by etching, nor do they affect the device structure in the patterned area of ​​the wafer product. Furthermore, the two removal methods can be flexibly selected according to the wafer's process requirements and the actual production equipment. Organic solvent removal is suitable for conventional wet processing operations, while plasma removal enables non-contact removal, improving the uniformity of resist removal. This wide range of process options further enhances the adaptability of this etching method, allowing it to be integrated into different wafer manufacturing process systems.

[0028] In some specific implementations, cleaning involves first using an alkaline solution (e.g., ammonia solution, with a volume ratio of ammonia to deionized water of 1:(5-10)) followed by rinsing with water (deionized water). This step-by-step cleaning design first uses the alkaline solution to react with residual impurities, etching products, and resist stripping on the wafer surface, effectively removing and cleaning various stubborn residues. It also effectively cleans impurities that easily remain in the etched trenches. Subsequent rinsing with water thoroughly removes the alkaline solution and any remaining residue, preventing corrosion from prolonged contact with the wafer and avoiding residues that could affect subsequent drying and wafer fabrication processes. This step-by-step cleaning approach balances cleaning effectiveness with wafer protection, keeping the wafer surface and trenches clean after cleaning, providing a good surface foundation for subsequent drying and wafer fabrication processes.

[0029] In some specific implementations, the number of etching operations does not exceed three. This limit is designed in conjunction with the stress accumulation patterns of the wafer during the manufacturing process, while also considering both process operability and production economics. The stress generated at each core process node before, during, and after the wafer fabrication process can be gradually and fully released through a maximum of three interval etching operations. Combined with the design of performing etching at intervals during the process using this etching method, three or fewer etching operations can precisely match the main stress-generating nodes in the wafer fabrication process, effectively dispersing the accumulated stress at each stage. This is sufficient to control the wafer warpage within the range that meets the requirements of high-precision processes, achieving the ideal stress improvement effect. If the number of etching operations is too high, it will not only increase the overall process steps of the wafer, prolong the production cycle, and increase process operation and time costs, but may also increase the potential risk of secondary impact on the wafer surface due to repeated etching processes, which is detrimental to the overall stability of the wafer structure. Limiting the number of etching cycles to no more than three simplifies the process, controls production costs, and avoids the potential risks associated with multiple processes, all while ensuring adequate stress relief. This makes the etching method more operable and practical in industrial wafer manufacturing.

[0030] Example 1 The etching method described above for reducing wafer warpage reduces the warpage of a 5000μm × 5000μm GaAs wafer, comprising the following steps: A stress relief pattern is defined on the dicing track of the wafer. The stress relief pattern is set in the center region of the dicing track. The difference between each critical dimension of the stress relief pattern and the critical dimension of the dicing track is 5μm (in some other specific implementations, the difference between each critical dimension of the stress relief pattern and the critical dimension of the dicing track can be any value in the range of 1μm-10μm, such as 1μm, 2μm, 4μm, 8μm, 10μm). The aspect ratio of the trench formed after etching is designed to be 0.5 (in some other specific implementations, the aspect ratio of the trench can be any value in the range of 0.075-0.5). The etching depth (depth of the trench) is designed to be 15μm. The wafer is etched twice according to the stress relief pattern. The first etching is performed before the electroplating process on the front side of the wafer, and the second etching is performed after all processes on the front side of the wafer are completed.

[0031] The first etching process includes the following steps: The wafer is coated with resist, exposed, and developed, then subjected to ICP dry etching, immersed in acetone to remove resist, cleaned with an alkaline solution (ammonia solution, the volume ratio of ammonia to deionized water is 1:10, in some other specific implementations, the volume ratio of ammonia to deionized water can be any value in the range of 1:(5-10)) for 30 seconds, then rinsed with water (deionized water) for 2 minutes, and then spun dry to complete the etching.

[0032] The ICP dry etching process employs a mixed gas, comprising Cl2, BCl3, and Ar in a volume ratio of 4:1:1. The mixed gas also includes a first gas, N2 (or O2 in some other embodiments), comprising 10% of the mixed gas by volume (or any value within the range of 10%-13%, such as 11%, 12%, or 13% in some other embodiments). The ICP dry etching power is 500W (or any value within the range of 400W-600W in some other embodiments, such as 400W, 450W, or 600W), the pressure is 1Pa (or any value within the range of 0.2Pa-2Pa in some other embodiments, such as 0.2Pa, 0.5Pa, 0.8Pa, 1.5Pa, or 2Pa), and the time is 10 minutes, resulting in an etching depth of 5μm.

[0033] The second etching took 20 minutes (the etching depth was 10 μm at this time, and the total etching depth was 15 μm), and other steps or parameters were the same as the first etching.

[0034] In Example 1, the first etching is performed before the electroplating process on the front side of the wafer. That is, the initial etching is performed before the deposition of a relatively thick electroplated gold layer. This helps to release the stress accumulated on the wafer in the previous process, improves flatness, and provides a better alignment basis for subsequent high-precision electroplating and photolithography. The second etching is performed after all processes on the front side of the wafer are completed. That is, the final deep etching is performed after all high-temperature processes (such as electrode alloying) are completed, which can avoid damage to the sidewalls of sensitive structures at high temperatures.

[0035] Example 2 The etching method described above for reducing wafer warpage reduces the warpage of a 5000μm × 5000μm GaAs wafer, differing from Example 1 in that the designed etching depth is 5μm. Everything else is the same as in Example 1.

[0036] Example 3 The etching method described above for reducing wafer warpage reduces the warpage of a 5000μm × 5000μm GaAs wafer, differing from Example 1 in that the designed etching depth is 10μm. Everything else is the same as in Example 1.

[0037] Example 4 The etching method described above for reducing wafer warpage reduces the warpage of a 5000μm × 5000μm GaAs wafer, differing from Example 1 in that the designed etching depth is 20μm. Everything else is the same as in Example 1.

[0038] The effects of different etching depths on wafer warpage (bow value) in Examples 1-4 are shown in Table 1.

[0039] Table 1 Referring to the data in Table 1, the analysis of the detection data on the reduction of wafer bow value at different etching depths shows that the effect of etching depth on wafer stress relief and warpage improvement exhibits a clear law of diminishing marginal benefits. As the etching depth gradually increases from 5μm to 20μm, although the reduction of wafer bow value continues to increase, the rate of increase gradually slows down, and the gain effect of stress relief continuously weakens. An etching depth of 5 μm is sufficient to initially release residual stress in the wafer surface film, achieving a significant improvement in wafer warpage. When the etching depth is increased to 10 μm, stress in the wafer's intermediate layer material begins to be released, further enhancing the warpage improvement effect. However, the rate of increase in bow value reduction begins to slow down. When the etching depth reaches 15 μm, most of the film stress on the wafer has been released. At this point, further etching mainly improves the bow value by fine-tuning the substrate stress, and the marginal benefit decreases significantly. When the etching depth is further increased to 20 μm, the main source of wafer stress release is essentially complete, and the rate of increase in bow value reduction continues to narrow, approaching the limit of warpage improvement. Further etching has very limited contribution to improving the overall wafer warpage.

[0040] In the description of this specification, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature.

[0041] The above description is only a preferred embodiment of this application. It should be noted that those skilled in the art can make several improvements and additions without departing from the method of this application, and these improvements and additions should also be considered within the scope of protection of this application.

Claims

1. An etching method for reducing wafer warpage, characterized in that, The wafer has dicing channels formed on it, and the etching method for reducing wafer warpage includes the following steps: A stress relief pattern is defined on the cutting track, and the stress relief pattern is entirely located within the cutting track. The stress relief pattern is etched multiple times on the dicing surface, with these multiple etchings occurring at intervals during the wafer fabrication process.

2. The etching method for reducing wafer warpage according to claim 1, characterized in that, The stress relief pattern is correspondingly set in the central region of the cutting channel, and the difference between each critical dimension of the stress relief pattern and the critical dimension corresponding to the cutting channel is 1μm-10μm.

3. The etching method for reducing wafer warpage according to claim 1, characterized in that, The grooves are formed by repeated etching, and the aspect ratio of the grooves is 0.075-0.

5.

4. The etching method for reducing wafer warpage according to claim 1, characterized in that, The etching process includes the following steps: The wafer is coated with resist, exposed, and developed, then subjected to ICP dry etching, resist removal, cleaning, and drying to complete the etching process.

5. The etching method for reducing wafer warpage according to claim 4, characterized in that, The ICP dry etching is performed using a mixed gas, which includes Cl2, BCl3 and Ar in a volume ratio of 4:1:

1.

6. The etching method for reducing wafer warpage according to claim 5, characterized in that, The power of the ICP dry etching is 400W-600W, and the pressure is 0.2Pa-2Pa.

7. The etching method for reducing wafer warpage according to claim 5, characterized in that, The mixed gas also includes a first gas, which is N2 or O2, and the volume percentage of the first gas in the mixed gas is 10%-13%.

8. The etching method for reducing wafer warpage according to claim 4, characterized in that, The adhesive removal is performed using organic solvents or plasma. And / or, the cleaning process involves first cleaning with an alkaline solution, followed by rinsing with water.

9. The etching method for reducing wafer warpage according to claim 1, characterized in that, The etching process is performed no more than three times.

10. The application of the etching method for reducing wafer warpage as described in any one of claims 1-9 in semiconductor manufacturing.

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